[linux-2.6-block.git] / drivers / gpu / ipu-v3 / ipu-dp.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
 */
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/err.h>

#include <video/imx-ipu-v3.h>
#include "ipu-prv.h"

#define DP_SYNC 0
#define DP_ASYNC0 0x60
#define DP_ASYNC1 0xBC

#define DP_COM_CONF		0x0
#define DP_GRAPH_WIND_CTRL	0x0004
#define DP_FG_POS		0x0008
#define DP_CSC_A_0		0x0044
#define DP_CSC_A_1		0x0048
#define DP_CSC_A_2		0x004C
#define DP_CSC_A_3		0x0050
#define DP_CSC_0		0x0054
#define DP_CSC_1		0x0058

#define DP_COM_CONF_FG_EN		(1 << 0)
#define DP_COM_CONF_GWSEL		(1 << 1)
#define DP_COM_CONF_GWAM		(1 << 2)
#define DP_COM_CONF_GWCKE		(1 << 3)
#define DP_COM_CONF_CSC_DEF_MASK	(3 << 8)
#define DP_COM_CONF_CSC_DEF_OFFSET	8
#define DP_COM_CONF_CSC_DEF_FG		(3 << 8)
#define DP_COM_CONF_CSC_DEF_BG		(2 << 8)
#define DP_COM_CONF_CSC_DEF_BOTH	(1 << 8)

#define IPUV3_NUM_FLOWS		3

struct ipu_dp_priv;

struct ipu_dp {
	u32 flow;
	bool in_use;
	bool foreground;
	enum ipu_color_space in_cs;
};

struct ipu_flow {
	struct ipu_dp foreground;
	struct ipu_dp background;
	enum ipu_color_space out_cs;
	void __iomem *base;
	struct ipu_dp_priv *priv;
};

struct ipu_dp_priv {
	struct ipu_soc *ipu;
	struct device *dev;
	void __iomem *base;
	struct ipu_flow flow[IPUV3_NUM_FLOWS];
	struct mutex mutex;
	int use_count;
};

static u32 ipu_dp_flow_base[] = {DP_SYNC, DP_ASYNC0, DP_ASYNC1};

static inline struct ipu_flow *to_flow(struct ipu_dp *dp)
{
	if (dp->foreground)
		return container_of(dp, struct ipu_flow, foreground);
	else
		return container_of(dp, struct ipu_flow, background);
}

int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable,
		u8 alpha, bool bg_chan)
{
	struct ipu_flow *flow = to_flow(dp);
	struct ipu_dp_priv *priv = flow->priv;
	u32 reg;

	mutex_lock(&priv->mutex);

	reg = readl(flow->base + DP_COM_CONF);
	if (bg_chan)
		reg &= ~DP_COM_CONF_GWSEL;
	else
		reg |= DP_COM_CONF_GWSEL;
	writel(reg, flow->base + DP_COM_CONF);

	if (enable) {
		reg = readl(flow->base + DP_GRAPH_WIND_CTRL) & 0x00FFFFFFL;
		writel(reg | ((u32) alpha << 24),
			     flow->base + DP_GRAPH_WIND_CTRL);

		reg = readl(flow->base + DP_COM_CONF);
		writel(reg | DP_COM_CONF_GWAM, flow->base + DP_COM_CONF);
	} else {
		reg = readl(flow->base + DP_COM_CONF);
		writel(reg & ~DP_COM_CONF_GWAM, flow->base + DP_COM_CONF);
	}

	ipu_srm_dp_update(priv->ipu, true);

	mutex_unlock(&priv->mutex);

	return 0;
}
EXPORT_SYMBOL_GPL(ipu_dp_set_global_alpha);

int ipu_dp_set_window_pos(struct ipu_dp *dp, u16 x_pos, u16 y_pos)
{
	struct ipu_flow *flow = to_flow(dp);
	struct ipu_dp_priv *priv = flow->priv;

	writel((x_pos << 16) | y_pos, flow->base + DP_FG_POS);

	ipu_srm_dp_update(priv->ipu, true);

	return 0;
}
EXPORT_SYMBOL_GPL(ipu_dp_set_window_pos);

static void ipu_dp_csc_init(struct ipu_flow *flow,
		enum ipu_color_space in,
		enum ipu_color_space out,
		u32 place)
{
	u32 reg;

	reg = readl(flow->base + DP_COM_CONF);
	reg &= ~DP_COM_CONF_CSC_DEF_MASK;

	if (in == out) {
		writel(reg, flow->base + DP_COM_CONF);
		return;
	}

	if (in == IPUV3_COLORSPACE_RGB && out == IPUV3_COLORSPACE_YUV) {
		writel(0x099 | (0x12d << 16), flow->base + DP_CSC_A_0);
		writel(0x03a | (0x3a9 << 16), flow->base + DP_CSC_A_1);
		writel(0x356 | (0x100 << 16), flow->base + DP_CSC_A_2);
		writel(0x100 | (0x329 << 16), flow->base + DP_CSC_A_3);
		writel(0x3d6 | (0x0000 << 16) | (2 << 30),
				flow->base + DP_CSC_0);
		writel(0x200 | (2 << 14) | (0x200 << 16) | (2 << 30),
				flow->base + DP_CSC_1);
	} else {
		writel(0x095 | (0x000 << 16), flow->base + DP_CSC_A_0);
		writel(0x0cc | (0x095 << 16), flow->base + DP_CSC_A_1);
		writel(0x3ce | (0x398 << 16), flow->base + DP_CSC_A_2);
		writel(0x095 | (0x0ff << 16), flow->base + DP_CSC_A_3);
		writel(0x000 | (0x3e42 << 16) | (1 << 30),
				flow->base + DP_CSC_0);
		writel(0x10a | (1 << 14) | (0x3dd6 << 16) | (1 << 30),
				flow->base + DP_CSC_1);
	}

	reg |= place;

	writel(reg, flow->base + DP_COM_CONF);
}

int ipu_dp_setup_channel(struct ipu_dp *dp,
		enum ipu_color_space in,
		enum ipu_color_space out)
{
	struct ipu_flow *flow = to_flow(dp);
	struct ipu_dp_priv *priv = flow->priv;

	mutex_lock(&priv->mutex);

	dp->in_cs = in;

	if (!dp->foreground)
		flow->out_cs = out;

	if (flow->foreground.in_cs == flow->background.in_cs) {
		/*
		 * foreground and background are of same colorspace, put
		 * colorspace converter after combining unit.
		 */
		ipu_dp_csc_init(flow, flow->foreground.in_cs, flow->out_cs,
				DP_COM_CONF_CSC_DEF_BOTH);
	} else {
		if (flow->foreground.in_cs == IPUV3_COLORSPACE_UNKNOWN ||
		    flow->foreground.in_cs == flow->out_cs)
			/*
			 * foreground identical to output, apply color
			 * conversion on background
			 */
			ipu_dp_csc_init(flow, flow->background.in_cs,
					flow->out_cs, DP_COM_CONF_CSC_DEF_BG);
		else
			ipu_dp_csc_init(flow, flow->foreground.in_cs,
					flow->out_cs, DP_COM_CONF_CSC_DEF_FG);
	}

	ipu_srm_dp_update(priv->ipu, true);

	mutex_unlock(&priv->mutex);

	return 0;
}
EXPORT_SYMBOL_GPL(ipu_dp_setup_channel);

int ipu_dp_enable(struct ipu_soc *ipu)
{
	struct ipu_dp_priv *priv = ipu->dp_priv;

	mutex_lock(&priv->mutex);

	if (!priv->use_count)
		ipu_module_enable(priv->ipu, IPU_CONF_DP_EN);

	priv->use_count++;

	mutex_unlock(&priv->mutex);

	return 0;
}
EXPORT_SYMBOL_GPL(ipu_dp_enable);

int ipu_dp_enable_channel(struct ipu_dp *dp)
{
	struct ipu_flow *flow = to_flow(dp);
	struct ipu_dp_priv *priv = flow->priv;
	u32 reg;

	if (!dp->foreground)
		return 0;

	mutex_lock(&priv->mutex);

	reg = readl(flow->base + DP_COM_CONF);
	reg |= DP_COM_CONF_FG_EN;
	writel(reg, flow->base + DP_COM_CONF);

	ipu_srm_dp_update(priv->ipu, true);

	mutex_unlock(&priv->mutex);

	return 0;
}
EXPORT_SYMBOL_GPL(ipu_dp_enable_channel);

void ipu_dp_disable_channel(struct ipu_dp *dp, bool sync)
{
	struct ipu_flow *flow = to_flow(dp);
	struct ipu_dp_priv *priv = flow->priv;
	u32 reg, csc;

	dp->in_cs = IPUV3_COLORSPACE_UNKNOWN;

	if (!dp->foreground)
		return;

	mutex_lock(&priv->mutex);

	reg = readl(flow->base + DP_COM_CONF);
	csc = reg & DP_COM_CONF_CSC_DEF_MASK;
	reg &= ~DP_COM_CONF_CSC_DEF_MASK;
	if (csc == DP_COM_CONF_CSC_DEF_BOTH || csc == DP_COM_CONF_CSC_DEF_BG)
		reg |= DP_COM_CONF_CSC_DEF_BG;

	reg &= ~DP_COM_CONF_FG_EN;
	writel(reg, flow->base + DP_COM_CONF);

	writel(0, flow->base + DP_FG_POS);
	ipu_srm_dp_update(priv->ipu, sync);

	mutex_unlock(&priv->mutex);
}
EXPORT_SYMBOL_GPL(ipu_dp_disable_channel);

void ipu_dp_disable(struct ipu_soc *ipu)
{
	struct ipu_dp_priv *priv = ipu->dp_priv;

	mutex_lock(&priv->mutex);

	priv->use_count--;

	if (!priv->use_count)
		ipu_module_disable(priv->ipu, IPU_CONF_DP_EN);

	if (priv->use_count < 0)
		priv->use_count = 0;

	mutex_unlock(&priv->mutex);
}
EXPORT_SYMBOL_GPL(ipu_dp_disable);

struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow)
{
	struct ipu_dp_priv *priv = ipu->dp_priv;
	struct ipu_dp *dp;

	if ((flow >> 1) >= IPUV3_NUM_FLOWS)
		return ERR_PTR(-EINVAL);

	if (flow & 1)
		dp = &priv->flow[flow >> 1].foreground;
	else
		dp = &priv->flow[flow >> 1].background;

	if (dp->in_use)
		return ERR_PTR(-EBUSY);

	dp->in_use = true;

	return dp;
}
EXPORT_SYMBOL_GPL(ipu_dp_get);

void ipu_dp_put(struct ipu_dp *dp)
{
	dp->in_use = false;
}
EXPORT_SYMBOL_GPL(ipu_dp_put);

int ipu_dp_init(struct ipu_soc *ipu, struct device *dev, unsigned long base)
{
	struct ipu_dp_priv *priv;
	int i;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;
	priv->dev = dev;
	priv->ipu = ipu;

	ipu->dp_priv = priv;

	priv->base = devm_ioremap(dev, base, PAGE_SIZE);
	if (!priv->base)
		return -ENOMEM;

	mutex_init(&priv->mutex);

	for (i = 0; i < IPUV3_NUM_FLOWS; i++) {
		priv->flow[i].background.in_cs = IPUV3_COLORSPACE_UNKNOWN;
		priv->flow[i].foreground.in_cs = IPUV3_COLORSPACE_UNKNOWN;
		priv->flow[i].foreground.foreground = true;
		priv->flow[i].base = priv->base + ipu_dp_flow_base[i];
		priv->flow[i].priv = priv;
	}

	return 0;
}

void ipu_dp_exit(struct ipu_soc *ipu)
{
}
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
aecfbdb1 SH	2	/*
	3	* Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
	4	* Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
aecfbdb1 SH	5	*/
	6	#include <linux/export.h>
	7	#include <linux/kernel.h>
	8	#include <linux/types.h>
	9	#include <linux/errno.h>
	10	#include <linux/io.h>
	11	#include <linux/err.h>
	12
39b9004d	13	#include <video/imx-ipu-v3.h>
aecfbdb1 SH	14	#include "ipu-prv.h"
	15
	16	#define DP_SYNC 0
	17	#define DP_ASYNC0 0x60
	18	#define DP_ASYNC1 0xBC
	19
	20	#define DP_COM_CONF 0x0
	21	#define DP_GRAPH_WIND_CTRL 0x0004
	22	#define DP_FG_POS 0x0008
	23	#define DP_CSC_A_0 0x0044
	24	#define DP_CSC_A_1 0x0048
	25	#define DP_CSC_A_2 0x004C
	26	#define DP_CSC_A_3 0x0050
	27	#define DP_CSC_0 0x0054
	28	#define DP_CSC_1 0x0058
	29
	30	#define DP_COM_CONF_FG_EN (1 << 0)
	31	#define DP_COM_CONF_GWSEL (1 << 1)
	32	#define DP_COM_CONF_GWAM (1 << 2)
	33	#define DP_COM_CONF_GWCKE (1 << 3)
	34	#define DP_COM_CONF_CSC_DEF_MASK (3 << 8)
	35	#define DP_COM_CONF_CSC_DEF_OFFSET 8
	36	#define DP_COM_CONF_CSC_DEF_FG (3 << 8)
	37	#define DP_COM_CONF_CSC_DEF_BG (2 << 8)
	38	#define DP_COM_CONF_CSC_DEF_BOTH (1 << 8)
	39
6fe9a899 FE	40	#define IPUV3_NUM_FLOWS 3
6fe9a899 FE	41
aecfbdb1 SH	42	struct ipu_dp_priv;
	43
	44	struct ipu_dp {
	45	u32 flow;
	46	bool in_use;
	47	bool foreground;
	48	enum ipu_color_space in_cs;
	49	};
	50
	51	struct ipu_flow {
	52	struct ipu_dp foreground;
	53	struct ipu_dp background;
	54	enum ipu_color_space out_cs;
	55	void __iomem *base;
	56	struct ipu_dp_priv *priv;
	57	};
	58
	59	struct ipu_dp_priv {
	60	struct ipu_soc *ipu;
	61	struct device *dev;
	62	void __iomem *base;
6fe9a899	63	struct ipu_flow flow[IPUV3_NUM_FLOWS];
aecfbdb1 SH	64	struct mutex mutex;
	65	int use_count;
	66	};
	67
	68	static u32 ipu_dp_flow_base[] = {DP_SYNC, DP_ASYNC0, DP_ASYNC1};
	69
	70	static inline struct ipu_flow to_flow(struct ipu_dp dp)
	71	{
	72	if (dp->foreground)
	73	return container_of(dp, struct ipu_flow, foreground);
	74	else
	75	return container_of(dp, struct ipu_flow, background);
	76	}
	77
	78	int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable,
	79	u8 alpha, bool bg_chan)
	80	{
	81	struct ipu_flow *flow = to_flow(dp);
	82	struct ipu_dp_priv *priv = flow->priv;
	83	u32 reg;
	84
	85	mutex_lock(&priv->mutex);
	86
	87	reg = readl(flow->base + DP_COM_CONF);
	88	if (bg_chan)
	89	reg &= ~DP_COM_CONF_GWSEL;
	90	else
	91	reg \|= DP_COM_CONF_GWSEL;
	92	writel(reg, flow->base + DP_COM_CONF);
	93
	94	if (enable) {
	95	reg = readl(flow->base + DP_GRAPH_WIND_CTRL) & 0x00FFFFFFL;
	96	writel(reg \| ((u32) alpha << 24),
	97	flow->base + DP_GRAPH_WIND_CTRL);
	98
	99	reg = readl(flow->base + DP_COM_CONF);
	100	writel(reg \| DP_COM_CONF_GWAM, flow->base + DP_COM_CONF);
	101	} else {
	102	reg = readl(flow->base + DP_COM_CONF);
	103	writel(reg & ~DP_COM_CONF_GWAM, flow->base + DP_COM_CONF);
	104	}
	105
f9bb7acb	106	ipu_srm_dp_update(priv->ipu, true);
aecfbdb1 SH	107
	108	mutex_unlock(&priv->mutex);
	109
	110	return 0;
	111	}
	112	EXPORT_SYMBOL_GPL(ipu_dp_set_global_alpha);
	113
	114	int ipu_dp_set_window_pos(struct ipu_dp *dp, u16 x_pos, u16 y_pos)
	115	{
	116	struct ipu_flow *flow = to_flow(dp);
	117	struct ipu_dp_priv *priv = flow->priv;
	118
	119	writel((x_pos << 16) \| y_pos, flow->base + DP_FG_POS);
	120
f9bb7acb	121	ipu_srm_dp_update(priv->ipu, true);
aecfbdb1 SH	122
	123	return 0;
	124	}
	125	EXPORT_SYMBOL_GPL(ipu_dp_set_window_pos);
	126
	127	static void ipu_dp_csc_init(struct ipu_flow *flow,
	128	enum ipu_color_space in,
	129	enum ipu_color_space out,
	130	u32 place)
	131	{
	132	u32 reg;
	133
	134	reg = readl(flow->base + DP_COM_CONF);
	135	reg &= ~DP_COM_CONF_CSC_DEF_MASK;
	136
	137	if (in == out) {
	138	writel(reg, flow->base + DP_COM_CONF);
	139	return;
	140	}
	141
	142	if (in == IPUV3_COLORSPACE_RGB && out == IPUV3_COLORSPACE_YUV) {
	143	writel(0x099 \| (0x12d << 16), flow->base + DP_CSC_A_0);
	144	writel(0x03a \| (0x3a9 << 16), flow->base + DP_CSC_A_1);
	145	writel(0x356 \| (0x100 << 16), flow->base + DP_CSC_A_2);
	146	writel(0x100 \| (0x329 << 16), flow->base + DP_CSC_A_3);
	147	writel(0x3d6 \| (0x0000 << 16) \| (2 << 30),
	148	flow->base + DP_CSC_0);
	149	writel(0x200 \| (2 << 14) \| (0x200 << 16) \| (2 << 30),
	150	flow->base + DP_CSC_1);
	151	} else {
	152	writel(0x095 \| (0x000 << 16), flow->base + DP_CSC_A_0);
	153	writel(0x0cc \| (0x095 << 16), flow->base + DP_CSC_A_1);
	154	writel(0x3ce \| (0x398 << 16), flow->base + DP_CSC_A_2);
	155	writel(0x095 \| (0x0ff << 16), flow->base + DP_CSC_A_3);
	156	writel(0x000 \| (0x3e42 << 16) \| (1 << 30),
	157	flow->base + DP_CSC_0);
	158	writel(0x10a \| (1 << 14) \| (0x3dd6 << 16) \| (1 << 30),
	159	flow->base + DP_CSC_1);
	160	}
	161
	162	reg \|= place;
	163
	164	writel(reg, flow->base + DP_COM_CONF);
	165	}
	166
	167	int ipu_dp_setup_channel(struct ipu_dp *dp,
	168	enum ipu_color_space in,
	169	enum ipu_color_space out)
	170	{
	171	struct ipu_flow *flow = to_flow(dp);
	172	struct ipu_dp_priv *priv = flow->priv;
	173
	174	mutex_lock(&priv->mutex);
	175
	176	dp->in_cs = in;
	177
	178	if (!dp->foreground)
	179	flow->out_cs = out;
	180
	181	if (flow->foreground.in_cs == flow->background.in_cs) {
	182	/*
	183	* foreground and background are of same colorspace, put
	184	* colorspace converter after combining unit.
	185	*/
186	ipu_dp_csc_init(flow, flow->foreground.in_cs, flow->out_cs,
187	DP_COM_CONF_CSC_DEF_BOTH);
188	} else {
d4fad0a4 LS	189	if (flow->foreground.in_cs == IPUV3_COLORSPACE_UNKNOWN \|\|
d4fad0a4 LS	190	flow->foreground.in_cs == flow->out_cs)
aecfbdb1 SH	191	/*
	192	* foreground identical to output, apply color
	193	* conversion on background
	194	*/
	195	ipu_dp_csc_init(flow, flow->background.in_cs,
	196	flow->out_cs, DP_COM_CONF_CSC_DEF_BG);
	197	else
	198	ipu_dp_csc_init(flow, flow->foreground.in_cs,
	199	flow->out_cs, DP_COM_CONF_CSC_DEF_FG);
	200	}
	201
f9bb7acb	202	ipu_srm_dp_update(priv->ipu, true);
aecfbdb1 SH	203
	204	mutex_unlock(&priv->mutex);
	205
	206	return 0;
	207	}
	208	EXPORT_SYMBOL_GPL(ipu_dp_setup_channel);
	209
285bbb01	210	int ipu_dp_enable(struct ipu_soc *ipu)
aecfbdb1	211	{
285bbb01	212	struct ipu_dp_priv *priv = ipu->dp_priv;
aecfbdb1 SH	213
	214	mutex_lock(&priv->mutex);
	215
	216	if (!priv->use_count)
	217	ipu_module_enable(priv->ipu, IPU_CONF_DP_EN);
	218
	219	priv->use_count++;
	220
285bbb01	221	mutex_unlock(&priv->mutex);
aecfbdb1	222
285bbb01 PZ	223	return 0;
	224	}
	225	EXPORT_SYMBOL_GPL(ipu_dp_enable);
aecfbdb1	226
285bbb01 PZ	227	int ipu_dp_enable_channel(struct ipu_dp *dp)
	228	{
	229	struct ipu_flow *flow = to_flow(dp);
	230	struct ipu_dp_priv *priv = flow->priv;
	231	u32 reg;
	232
	233	if (!dp->foreground)
	234	return 0;
	235
	236	mutex_lock(&priv->mutex);
	237
	238	reg = readl(flow->base + DP_COM_CONF);
	239	reg \|= DP_COM_CONF_FG_EN;
	240	writel(reg, flow->base + DP_COM_CONF);
	241
f9bb7acb	242	ipu_srm_dp_update(priv->ipu, true);
aecfbdb1 SH	243
	244	mutex_unlock(&priv->mutex);
	245
	246	return 0;
	247	}
	248	EXPORT_SYMBOL_GPL(ipu_dp_enable_channel);
	249
f9bb7acb	250	void ipu_dp_disable_channel(struct ipu_dp *dp, bool sync)
aecfbdb1 SH	251	{
	252	struct ipu_flow *flow = to_flow(dp);
	253	struct ipu_dp_priv *priv = flow->priv;
285bbb01 PZ	254	u32 reg, csc;
285bbb01 PZ	255
d4fad0a4 LS	256	dp->in_cs = IPUV3_COLORSPACE_UNKNOWN;
d4fad0a4 LS	257
285bbb01 PZ	258	if (!dp->foreground)
285bbb01 PZ	259	return;
aecfbdb1 SH	260
	261	mutex_lock(&priv->mutex);
	262
285bbb01 PZ	263	reg = readl(flow->base + DP_COM_CONF);
285bbb01 PZ	264	csc = reg & DP_COM_CONF_CSC_DEF_MASK;
d4fad0a4 LS	265	reg &= ~DP_COM_CONF_CSC_DEF_MASK;
	266	if (csc == DP_COM_CONF_CSC_DEF_BOTH \|\| csc == DP_COM_CONF_CSC_DEF_BG)
	267	reg \|= DP_COM_CONF_CSC_DEF_BG;
aecfbdb1	268
285bbb01 PZ	269	reg &= ~DP_COM_CONF_FG_EN;
285bbb01 PZ	270	writel(reg, flow->base + DP_COM_CONF);
aecfbdb1	271
285bbb01	272	writel(0, flow->base + DP_FG_POS);
f9bb7acb	273	ipu_srm_dp_update(priv->ipu, sync);
aecfbdb1	274
285bbb01 PZ	275	mutex_unlock(&priv->mutex);
	276	}
	277	EXPORT_SYMBOL_GPL(ipu_dp_disable_channel);
aecfbdb1	278
285bbb01 PZ	279	void ipu_dp_disable(struct ipu_soc *ipu)
	280	{
	281	struct ipu_dp_priv *priv = ipu->dp_priv;
	282
	283	mutex_lock(&priv->mutex);
	284
	285	priv->use_count--;
aecfbdb1 SH	286
	287	if (!priv->use_count)
	288	ipu_module_disable(priv->ipu, IPU_CONF_DP_EN);
	289
	290	if (priv->use_count < 0)
	291	priv->use_count = 0;
	292
	293	mutex_unlock(&priv->mutex);
	294	}
285bbb01	295	EXPORT_SYMBOL_GPL(ipu_dp_disable);
aecfbdb1 SH	296
	297	struct ipu_dp ipu_dp_get(struct ipu_soc ipu, unsigned int flow)
	298	{
	299	struct ipu_dp_priv *priv = ipu->dp_priv;
	300	struct ipu_dp *dp;
	301
6fe9a899	302	if ((flow >> 1) >= IPUV3_NUM_FLOWS)
aecfbdb1 SH	303	return ERR_PTR(-EINVAL);
	304
	305	if (flow & 1)
	306	dp = &priv->flow[flow >> 1].foreground;
	307	else
	308	dp = &priv->flow[flow >> 1].background;
	309
	310	if (dp->in_use)
	311	return ERR_PTR(-EBUSY);
	312
	313	dp->in_use = true;
	314
	315	return dp;
	316	}
	317	EXPORT_SYMBOL_GPL(ipu_dp_get);
	318
	319	void ipu_dp_put(struct ipu_dp *dp)
	320	{
	321	dp->in_use = false;
	322	}
	323	EXPORT_SYMBOL_GPL(ipu_dp_put);
	324
	325	int ipu_dp_init(struct ipu_soc ipu, struct device dev, unsigned long base)
	326	{
	327	struct ipu_dp_priv *priv;
	328	int i;
	329
	330	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
55b31cf4 FE	331	if (!priv)
55b31cf4 FE	332	return -ENOMEM;
aecfbdb1 SH	333	priv->dev = dev;
	334	priv->ipu = ipu;
	335
	336	ipu->dp_priv = priv;
	337
	338	priv->base = devm_ioremap(dev, base, PAGE_SIZE);
ded15b5a	339	if (!priv->base)
aecfbdb1	340	return -ENOMEM;
aecfbdb1 SH	341
	342	mutex_init(&priv->mutex);
	343
6fe9a899	344	for (i = 0; i < IPUV3_NUM_FLOWS; i++) {
d4fad0a4 LS	345	priv->flow[i].background.in_cs = IPUV3_COLORSPACE_UNKNOWN;
d4fad0a4 LS	346	priv->flow[i].foreground.in_cs = IPUV3_COLORSPACE_UNKNOWN;
89bc5be7	347	priv->flow[i].foreground.foreground = true;
aecfbdb1 SH	348	priv->flow[i].base = priv->base + ipu_dp_flow_base[i];
	349	priv->flow[i].priv = priv;
	350	}
	351
	352	return 0;
	353	}
	354
	355	void ipu_dp_exit(struct ipu_soc *ipu)
	356	{
	357	}