[linux-2.6-block.git] / drivers / gpu / ipu-v3 / ipu-cpmem.c

/*
 * Copyright (C) 2012 Mentor Graphics Inc.
 * Copyright 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */
#include <linux/types.h>
#include <linux/bitrev.h>
#include <linux/io.h>
#include <drm/drm_fourcc.h>
#include "ipu-prv.h"

struct ipu_cpmem_word {
	u32 data[5];
	u32 res[3];
};

struct ipu_ch_param {
	struct ipu_cpmem_word word[2];
};

struct ipu_cpmem {
	struct ipu_ch_param __iomem *base;
	u32 module;
	spinlock_t lock;
	int use_count;
	struct ipu_soc *ipu;
};

#define IPU_CPMEM_WORD(word, ofs, size) ((((word) * 160 + (ofs)) << 8) | (size))

#define IPU_FIELD_UBO		IPU_CPMEM_WORD(0, 46, 22)
#define IPU_FIELD_VBO		IPU_CPMEM_WORD(0, 68, 22)
#define IPU_FIELD_IOX		IPU_CPMEM_WORD(0, 90, 4)
#define IPU_FIELD_RDRW		IPU_CPMEM_WORD(0, 94, 1)
#define IPU_FIELD_SO		IPU_CPMEM_WORD(0, 113, 1)
#define IPU_FIELD_SLY		IPU_CPMEM_WORD(1, 102, 14)
#define IPU_FIELD_SLUV		IPU_CPMEM_WORD(1, 128, 14)

#define IPU_FIELD_XV		IPU_CPMEM_WORD(0, 0, 10)
#define IPU_FIELD_YV		IPU_CPMEM_WORD(0, 10, 9)
#define IPU_FIELD_XB		IPU_CPMEM_WORD(0, 19, 13)
#define IPU_FIELD_YB		IPU_CPMEM_WORD(0, 32, 12)
#define IPU_FIELD_NSB_B		IPU_CPMEM_WORD(0, 44, 1)
#define IPU_FIELD_CF		IPU_CPMEM_WORD(0, 45, 1)
#define IPU_FIELD_SX		IPU_CPMEM_WORD(0, 46, 12)
#define IPU_FIELD_SY		IPU_CPMEM_WORD(0, 58, 11)
#define IPU_FIELD_NS		IPU_CPMEM_WORD(0, 69, 10)
#define IPU_FIELD_SDX		IPU_CPMEM_WORD(0, 79, 7)
#define IPU_FIELD_SM		IPU_CPMEM_WORD(0, 86, 10)
#define IPU_FIELD_SCC		IPU_CPMEM_WORD(0, 96, 1)
#define IPU_FIELD_SCE		IPU_CPMEM_WORD(0, 97, 1)
#define IPU_FIELD_SDY		IPU_CPMEM_WORD(0, 98, 7)
#define IPU_FIELD_SDRX		IPU_CPMEM_WORD(0, 105, 1)
#define IPU_FIELD_SDRY		IPU_CPMEM_WORD(0, 106, 1)
#define IPU_FIELD_BPP		IPU_CPMEM_WORD(0, 107, 3)
#define IPU_FIELD_DEC_SEL	IPU_CPMEM_WORD(0, 110, 2)
#define IPU_FIELD_DIM		IPU_CPMEM_WORD(0, 112, 1)
#define IPU_FIELD_BNDM		IPU_CPMEM_WORD(0, 114, 3)
#define IPU_FIELD_BM		IPU_CPMEM_WORD(0, 117, 2)
#define IPU_FIELD_ROT		IPU_CPMEM_WORD(0, 119, 1)
#define IPU_FIELD_ROT_HF_VF	IPU_CPMEM_WORD(0, 119, 3)
#define IPU_FIELD_HF		IPU_CPMEM_WORD(0, 120, 1)
#define IPU_FIELD_VF		IPU_CPMEM_WORD(0, 121, 1)
#define IPU_FIELD_THE		IPU_CPMEM_WORD(0, 122, 1)
#define IPU_FIELD_CAP		IPU_CPMEM_WORD(0, 123, 1)
#define IPU_FIELD_CAE		IPU_CPMEM_WORD(0, 124, 1)
#define IPU_FIELD_FW		IPU_CPMEM_WORD(0, 125, 13)
#define IPU_FIELD_FH		IPU_CPMEM_WORD(0, 138, 12)
#define IPU_FIELD_EBA0		IPU_CPMEM_WORD(1, 0, 29)
#define IPU_FIELD_EBA1		IPU_CPMEM_WORD(1, 29, 29)
#define IPU_FIELD_ILO		IPU_CPMEM_WORD(1, 58, 20)
#define IPU_FIELD_NPB		IPU_CPMEM_WORD(1, 78, 7)
#define IPU_FIELD_PFS		IPU_CPMEM_WORD(1, 85, 4)
#define IPU_FIELD_ALU		IPU_CPMEM_WORD(1, 89, 1)
#define IPU_FIELD_ALBM		IPU_CPMEM_WORD(1, 90, 3)
#define IPU_FIELD_ID		IPU_CPMEM_WORD(1, 93, 2)
#define IPU_FIELD_TH		IPU_CPMEM_WORD(1, 95, 7)
#define IPU_FIELD_SL		IPU_CPMEM_WORD(1, 102, 14)
#define IPU_FIELD_WID0		IPU_CPMEM_WORD(1, 116, 3)
#define IPU_FIELD_WID1		IPU_CPMEM_WORD(1, 119, 3)
#define IPU_FIELD_WID2		IPU_CPMEM_WORD(1, 122, 3)
#define IPU_FIELD_WID3		IPU_CPMEM_WORD(1, 125, 3)
#define IPU_FIELD_OFS0		IPU_CPMEM_WORD(1, 128, 5)
#define IPU_FIELD_OFS1		IPU_CPMEM_WORD(1, 133, 5)
#define IPU_FIELD_OFS2		IPU_CPMEM_WORD(1, 138, 5)
#define IPU_FIELD_OFS3		IPU_CPMEM_WORD(1, 143, 5)
#define IPU_FIELD_SXYS		IPU_CPMEM_WORD(1, 148, 1)
#define IPU_FIELD_CRE		IPU_CPMEM_WORD(1, 149, 1)
#define IPU_FIELD_DEC_SEL2	IPU_CPMEM_WORD(1, 150, 1)

static inline struct ipu_ch_param __iomem *
ipu_get_cpmem(struct ipuv3_channel *ch)
{
	struct ipu_cpmem *cpmem = ch->ipu->cpmem_priv;

	return cpmem->base + ch->num;
}

static void ipu_ch_param_write_field(struct ipuv3_channel *ch, u32 wbs, u32 v)
{
	struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch);
	u32 bit = (wbs >> 8) % 160;
	u32 size = wbs & 0xff;
	u32 word = (wbs >> 8) / 160;
	u32 i = bit / 32;
	u32 ofs = bit % 32;
	u32 mask = (1 << size) - 1;
	u32 val;

	pr_debug("%s %d %d %d\n", __func__, word, bit , size);

	val = readl(&base->word[word].data[i]);
	val &= ~(mask << ofs);
	val |= v << ofs;
	writel(val, &base->word[word].data[i]);

	if ((bit + size - 1) / 32 > i) {
		val = readl(&base->word[word].data[i + 1]);
		val &= ~(mask >> (ofs ? (32 - ofs) : 0));
		val |= v >> (ofs ? (32 - ofs) : 0);
		writel(val, &base->word[word].data[i + 1]);
	}
}

static u32 ipu_ch_param_read_field(struct ipuv3_channel *ch, u32 wbs)
{
	struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch);
	u32 bit = (wbs >> 8) % 160;
	u32 size = wbs & 0xff;
	u32 word = (wbs >> 8) / 160;
	u32 i = bit / 32;
	u32 ofs = bit % 32;
	u32 mask = (1 << size) - 1;
	u32 val = 0;

	pr_debug("%s %d %d %d\n", __func__, word, bit , size);

	val = (readl(&base->word[word].data[i]) >> ofs) & mask;

	if ((bit + size - 1) / 32 > i) {
		u32 tmp;

		tmp = readl(&base->word[word].data[i + 1]);
		tmp &= mask >> (ofs ? (32 - ofs) : 0);
		val |= tmp << (ofs ? (32 - ofs) : 0);
	}

	return val;
}

/*
 * The V4L2 spec defines packed RGB formats in memory byte order, which from
 * point of view of the IPU corresponds to little-endian words with the first
 * component in the least significant bits.
 * The DRM pixel formats and IPU internal representation are ordered the other
 * way around, with the first named component ordered at the most significant
 * bits. Further, V4L2 formats are not well defined:
 *     http://linuxtv.org/downloads/v4l-dvb-apis/packed-rgb.html
 * We choose the interpretation which matches GStreamer behavior.
 */
static int v4l2_pix_fmt_to_drm_fourcc(u32 pixelformat)
{
	switch (pixelformat) {
	case V4L2_PIX_FMT_RGB565:
		/*
		 * Here we choose the 'corrected' interpretation of RGBP, a
		 * little-endian 16-bit word with the red component at the most
		 * significant bits:
		 * g[2:0]b[4:0] r[4:0]g[5:3] <=> [16:0] R:G:B
		 */
		return DRM_FORMAT_RGB565;
	case V4L2_PIX_FMT_BGR24:
		/* B G R <=> [24:0] R:G:B */
		return DRM_FORMAT_RGB888;
	case V4L2_PIX_FMT_RGB24:
		/* R G B <=> [24:0] B:G:R */
		return DRM_FORMAT_BGR888;
	case V4L2_PIX_FMT_BGR32:
		/* B G R A <=> [32:0] A:B:G:R */
		return DRM_FORMAT_XRGB8888;
	case V4L2_PIX_FMT_RGB32:
		/* R G B A <=> [32:0] A:B:G:R */
		return DRM_FORMAT_XBGR8888;
	case V4L2_PIX_FMT_UYVY:
		return DRM_FORMAT_UYVY;
	case V4L2_PIX_FMT_YUYV:
		return DRM_FORMAT_YUYV;
	case V4L2_PIX_FMT_YUV420:
		return DRM_FORMAT_YUV420;
	case V4L2_PIX_FMT_YVU420:
		return DRM_FORMAT_YVU420;
	}

	return -EINVAL;
}

void ipu_cpmem_zero(struct ipuv3_channel *ch)
{
	struct ipu_ch_param __iomem *p = ipu_get_cpmem(ch);
	void __iomem *base = p;
	int i;

	for (i = 0; i < sizeof(*p) / sizeof(u32); i++)
		writel(0, base + i * sizeof(u32));
}
EXPORT_SYMBOL_GPL(ipu_cpmem_zero);

void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres)
{
	ipu_ch_param_write_field(ch, IPU_FIELD_FW, xres - 1);
	ipu_ch_param_write_field(ch, IPU_FIELD_FH, yres - 1);
}
EXPORT_SYMBOL_GPL(ipu_cpmem_set_resolution);

void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride)
{
	ipu_ch_param_write_field(ch, IPU_FIELD_SLY, stride - 1);
}
EXPORT_SYMBOL_GPL(ipu_cpmem_set_stride);

void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch)
{
	struct ipu_soc *ipu = ch->ipu;
	u32 val;

	if (ipu->ipu_type == IPUV3EX)
		ipu_ch_param_write_field(ch, IPU_FIELD_ID, 1);

	val = ipu_idmac_read(ipu, IDMAC_CHA_PRI(ch->num));
	val |= 1 << (ch->num % 32);
	ipu_idmac_write(ipu, val, IDMAC_CHA_PRI(ch->num));
};
EXPORT_SYMBOL_GPL(ipu_cpmem_set_high_priority);

void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf)
{
	if (bufnum)
		ipu_ch_param_write_field(ch, IPU_FIELD_EBA1, buf >> 3);
	else
		ipu_ch_param_write_field(ch, IPU_FIELD_EBA0, buf >> 3);
}
EXPORT_SYMBOL_GPL(ipu_cpmem_set_buffer);

void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride)
{
	ipu_ch_param_write_field(ch, IPU_FIELD_SO, 1);
	ipu_ch_param_write_field(ch, IPU_FIELD_ILO, stride / 8);
	ipu_ch_param_write_field(ch, IPU_FIELD_SLY, (stride * 2) - 1);
};
EXPORT_SYMBOL_GPL(ipu_cpmem_interlaced_scan);

void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id)
{
	id &= 0x3;
	ipu_ch_param_write_field(ch, IPU_FIELD_ID, id);
}
EXPORT_SYMBOL_GPL(ipu_cpmem_set_axi_id);

void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize)
{
	ipu_ch_param_write_field(ch, IPU_FIELD_NPB, burstsize - 1);
};
EXPORT_SYMBOL_GPL(ipu_cpmem_set_burstsize);

void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch)
{
	ipu_ch_param_write_field(ch, IPU_FIELD_BM, 1);
}
EXPORT_SYMBOL_GPL(ipu_cpmem_set_block_mode);

void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
			    enum ipu_rotate_mode rot)
{
	u32 temp_rot = bitrev8(rot) >> 5;

	ipu_ch_param_write_field(ch, IPU_FIELD_ROT_HF_VF, temp_rot);
}
EXPORT_SYMBOL_GPL(ipu_cpmem_set_rotation);

int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
			     const struct ipu_rgb *rgb)
{
	int bpp = 0, npb = 0, ro, go, bo, to;

	ro = rgb->bits_per_pixel - rgb->red.length - rgb->red.offset;
	go = rgb->bits_per_pixel - rgb->green.length - rgb->green.offset;
	bo = rgb->bits_per_pixel - rgb->blue.length - rgb->blue.offset;
	to = rgb->bits_per_pixel - rgb->transp.length - rgb->transp.offset;

	ipu_ch_param_write_field(ch, IPU_FIELD_WID0, rgb->red.length - 1);
	ipu_ch_param_write_field(ch, IPU_FIELD_OFS0, ro);
	ipu_ch_param_write_field(ch, IPU_FIELD_WID1, rgb->green.length - 1);
	ipu_ch_param_write_field(ch, IPU_FIELD_OFS1, go);
	ipu_ch_param_write_field(ch, IPU_FIELD_WID2, rgb->blue.length - 1);
	ipu_ch_param_write_field(ch, IPU_FIELD_OFS2, bo);

	if (rgb->transp.length) {
		ipu_ch_param_write_field(ch, IPU_FIELD_WID3,
				rgb->transp.length - 1);
		ipu_ch_param_write_field(ch, IPU_FIELD_OFS3, to);
	} else {
		ipu_ch_param_write_field(ch, IPU_FIELD_WID3, 7);
		ipu_ch_param_write_field(ch, IPU_FIELD_OFS3,
				rgb->bits_per_pixel);
	}

	switch (rgb->bits_per_pixel) {
	case 32:
		bpp = 0;
		npb = 15;
		break;
	case 24:
		bpp = 1;
		npb = 19;
		break;
	case 16:
		bpp = 3;
		npb = 31;
		break;
	case 8:
		bpp = 5;
		npb = 63;
		break;
	default:
		return -EINVAL;
	}
	ipu_ch_param_write_field(ch, IPU_FIELD_BPP, bpp);
	ipu_ch_param_write_field(ch, IPU_FIELD_NPB, npb);
	ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 7); /* rgb mode */

	return 0;
}
EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_rgb);

int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width)
{
	int bpp = 0, npb = 0;

	switch (width) {
	case 32:
		bpp = 0;
		npb = 15;
		break;
	case 24:
		bpp = 1;
		npb = 19;
		break;
	case 16:
		bpp = 3;
		npb = 31;
		break;
	case 8:
		bpp = 5;
		npb = 63;
		break;
	default:
		return -EINVAL;
	}

	ipu_ch_param_write_field(ch, IPU_FIELD_BPP, bpp);
	ipu_ch_param_write_field(ch, IPU_FIELD_NPB, npb);
	ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 6); /* raw mode */

	return 0;
}
EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_passthrough);

void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format)
{
	switch (pixel_format) {
	case V4L2_PIX_FMT_UYVY:
		ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); /* bits/pixel */
		ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0xA);/* pix fmt */
		ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);/* burst size */
		break;
	case V4L2_PIX_FMT_YUYV:
		ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); /* bits/pixel */
		ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0x8);/* pix fmt */
		ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);/* burst size */
		break;
	}
}
EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_interleaved);

void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
				   u32 pixel_format, int stride,
				   int u_offset, int v_offset)
{
	switch (pixel_format) {
	case V4L2_PIX_FMT_YUV420:
		ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, (stride / 2) - 1);
		ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_offset / 8);
		ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_offset / 8);
		break;
	case V4L2_PIX_FMT_YVU420:
		ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, (stride / 2) - 1);
		ipu_ch_param_write_field(ch, IPU_FIELD_UBO, v_offset / 8);
		ipu_ch_param_write_field(ch, IPU_FIELD_VBO, u_offset / 8);
		break;
	}
}
EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar_full);

void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
			      u32 pixel_format, int stride, int height)
{
	int u_offset, v_offset;
	int uv_stride = 0;

	switch (pixel_format) {
	case V4L2_PIX_FMT_YUV420:
	case V4L2_PIX_FMT_YVU420:
		uv_stride = stride / 2;
		u_offset = stride * height;
		v_offset = u_offset + (uv_stride * height / 2);
		ipu_cpmem_set_yuv_planar_full(ch, pixel_format, stride,
					      u_offset, v_offset);
		break;
	}
}
EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar);

static const struct ipu_rgb def_rgb_32 = {
	.red	= { .offset = 16, .length = 8, },
	.green	= { .offset =  8, .length = 8, },
	.blue	= { .offset =  0, .length = 8, },
	.transp = { .offset = 24, .length = 8, },
	.bits_per_pixel = 32,
};

static const struct ipu_rgb def_bgr_32 = {
	.red	= { .offset =  0, .length = 8, },
	.green	= { .offset =  8, .length = 8, },
	.blue	= { .offset = 16, .length = 8, },
	.transp = { .offset = 24, .length = 8, },
	.bits_per_pixel = 32,
};

static const struct ipu_rgb def_rgb_24 = {
	.red	= { .offset = 16, .length = 8, },
	.green	= { .offset =  8, .length = 8, },
	.blue	= { .offset =  0, .length = 8, },
	.transp = { .offset =  0, .length = 0, },
	.bits_per_pixel = 24,
};

static const struct ipu_rgb def_bgr_24 = {
	.red	= { .offset =  0, .length = 8, },
	.green	= { .offset =  8, .length = 8, },
	.blue	= { .offset = 16, .length = 8, },
	.transp = { .offset =  0, .length = 0, },
	.bits_per_pixel = 24,
};

static const struct ipu_rgb def_rgb_16 = {
	.red	= { .offset = 11, .length = 5, },
	.green	= { .offset =  5, .length = 6, },
	.blue	= { .offset =  0, .length = 5, },
	.transp = { .offset =  0, .length = 0, },
	.bits_per_pixel = 16,
};

static const struct ipu_rgb def_bgr_16 = {
	.red	= { .offset =  0, .length = 5, },
	.green	= { .offset =  5, .length = 6, },
	.blue	= { .offset = 11, .length = 5, },
	.transp = { .offset =  0, .length = 0, },
	.bits_per_pixel = 16,
};

#define Y_OFFSET(pix, x, y)	((x) + pix->width * (y))
#define U_OFFSET(pix, x, y)	((pix->width * pix->height) + \
					(pix->width * (y) / 4) + (x) / 2)
#define V_OFFSET(pix, x, y)	((pix->width * pix->height) + \
					(pix->width * pix->height / 4) + \
					(pix->width * (y) / 4) + (x) / 2)

int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc)
{
	switch (drm_fourcc) {
	case DRM_FORMAT_YUV420:
	case DRM_FORMAT_YVU420:
		/* pix format */
		ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 2);
		/* burst size */
		ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
		break;
	case DRM_FORMAT_UYVY:
		/* bits/pixel */
		ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3);
		/* pix format */
		ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0xA);
		/* burst size */
		ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
		break;
	case DRM_FORMAT_YUYV:
		/* bits/pixel */
		ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3);
		/* pix format */
		ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0x8);
		/* burst size */
		ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
		break;
	case DRM_FORMAT_ABGR8888:
	case DRM_FORMAT_XBGR8888:
		ipu_cpmem_set_format_rgb(ch, &def_bgr_32);
		break;
	case DRM_FORMAT_ARGB8888:
	case DRM_FORMAT_XRGB8888:
		ipu_cpmem_set_format_rgb(ch, &def_rgb_32);
		break;
	case DRM_FORMAT_BGR888:
		ipu_cpmem_set_format_rgb(ch, &def_bgr_24);
		break;
	case DRM_FORMAT_RGB888:
		ipu_cpmem_set_format_rgb(ch, &def_rgb_24);
		break;
	case DRM_FORMAT_RGB565:
		ipu_cpmem_set_format_rgb(ch, &def_rgb_16);
		break;
	case DRM_FORMAT_BGR565:
		ipu_cpmem_set_format_rgb(ch, &def_bgr_16);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(ipu_cpmem_set_fmt);

int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image)
{
	struct v4l2_pix_format *pix = &image->pix;
	int offset, y_offset, u_offset, v_offset;

	pr_debug("%s: resolution: %dx%d stride: %d\n",
		 __func__, pix->width, pix->height,
		 pix->bytesperline);

	ipu_cpmem_set_resolution(ch, image->rect.width, image->rect.height);
	ipu_cpmem_set_stride(ch, pix->bytesperline);

	ipu_cpmem_set_fmt(ch, v4l2_pix_fmt_to_drm_fourcc(pix->pixelformat));

	switch (pix->pixelformat) {
	case V4L2_PIX_FMT_YUV420:
	case V4L2_PIX_FMT_YVU420:
		y_offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
		u_offset = U_OFFSET(pix, image->rect.left,
				    image->rect.top) - y_offset;
		v_offset = V_OFFSET(pix, image->rect.left,
				    image->rect.top) - y_offset;

		ipu_cpmem_set_yuv_planar_full(ch, pix->pixelformat,
				pix->bytesperline, u_offset, v_offset);
		ipu_cpmem_set_buffer(ch, 0, image->phys0 + y_offset);
		ipu_cpmem_set_buffer(ch, 1, image->phys1 + y_offset);
		break;
	case V4L2_PIX_FMT_UYVY:
	case V4L2_PIX_FMT_YUYV:
	case V4L2_PIX_FMT_RGB565:
		offset = image->rect.left * 2 +
			image->rect.top * pix->bytesperline;
		ipu_cpmem_set_buffer(ch, 0, image->phys0 + offset);
		ipu_cpmem_set_buffer(ch, 1, image->phys1 + offset);
		break;
	case V4L2_PIX_FMT_RGB32:
	case V4L2_PIX_FMT_BGR32:
		offset = image->rect.left * 4 +
			image->rect.top * pix->bytesperline;
		ipu_cpmem_set_buffer(ch, 0, image->phys0 + offset);
		ipu_cpmem_set_buffer(ch, 1, image->phys1 + offset);
		break;
	case V4L2_PIX_FMT_RGB24:
	case V4L2_PIX_FMT_BGR24:
		offset = image->rect.left * 3 +
			image->rect.top * pix->bytesperline;
		ipu_cpmem_set_buffer(ch, 0, image->phys0 + offset);
		ipu_cpmem_set_buffer(ch, 1, image->phys1 + offset);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(ipu_cpmem_set_image);

int ipu_cpmem_init(struct ipu_soc *ipu, struct device *dev, unsigned long base)
{
	struct ipu_cpmem *cpmem;

	cpmem = devm_kzalloc(dev, sizeof(*cpmem), GFP_KERNEL);
	if (!cpmem)
		return -ENOMEM;

	ipu->cpmem_priv = cpmem;

	spin_lock_init(&cpmem->lock);
	cpmem->base = devm_ioremap(dev, base, SZ_128K);
	if (!cpmem->base)
		return -ENOMEM;

	dev_dbg(dev, "CPMEM base: 0x%08lx remapped to %p\n",
		base, cpmem->base);
	cpmem->ipu = ipu;

	return 0;
}

void ipu_cpmem_exit(struct ipu_soc *ipu)
{
}
Commit	Line	Data
7d2691da SL	1	/*
	2	* Copyright (C) 2012 Mentor Graphics Inc.
	3	* Copyright 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12	#include <linux/types.h>
	13	#include <linux/bitrev.h>
	14	#include <linux/io.h>
	15	#include <drm/drm_fourcc.h>
	16	#include "ipu-prv.h"
	17
	18	struct ipu_cpmem_word {
	19	u32 data[5];
	20	u32 res[3];
	21	};
	22
	23	struct ipu_ch_param {
	24	struct ipu_cpmem_word word[2];
	25	};
	26
	27	struct ipu_cpmem {
	28	struct ipu_ch_param __iomem *base;
	29	u32 module;
	30	spinlock_t lock;
	31	int use_count;
	32	struct ipu_soc *ipu;
	33	};
	34
	35	#define IPU_CPMEM_WORD(word, ofs, size) ((((word) * 160 + (ofs)) << 8) \| (size))
	36
	37	#define IPU_FIELD_UBO IPU_CPMEM_WORD(0, 46, 22)
	38	#define IPU_FIELD_VBO IPU_CPMEM_WORD(0, 68, 22)
	39	#define IPU_FIELD_IOX IPU_CPMEM_WORD(0, 90, 4)
	40	#define IPU_FIELD_RDRW IPU_CPMEM_WORD(0, 94, 1)
	41	#define IPU_FIELD_SO IPU_CPMEM_WORD(0, 113, 1)
	42	#define IPU_FIELD_SLY IPU_CPMEM_WORD(1, 102, 14)
	43	#define IPU_FIELD_SLUV IPU_CPMEM_WORD(1, 128, 14)
	44
	45	#define IPU_FIELD_XV IPU_CPMEM_WORD(0, 0, 10)
	46	#define IPU_FIELD_YV IPU_CPMEM_WORD(0, 10, 9)
	47	#define IPU_FIELD_XB IPU_CPMEM_WORD(0, 19, 13)
	48	#define IPU_FIELD_YB IPU_CPMEM_WORD(0, 32, 12)
	49	#define IPU_FIELD_NSB_B IPU_CPMEM_WORD(0, 44, 1)
	50	#define IPU_FIELD_CF IPU_CPMEM_WORD(0, 45, 1)
	51	#define IPU_FIELD_SX IPU_CPMEM_WORD(0, 46, 12)
	52	#define IPU_FIELD_SY IPU_CPMEM_WORD(0, 58, 11)
	53	#define IPU_FIELD_NS IPU_CPMEM_WORD(0, 69, 10)
	54	#define IPU_FIELD_SDX IPU_CPMEM_WORD(0, 79, 7)
	55	#define IPU_FIELD_SM IPU_CPMEM_WORD(0, 86, 10)
	56	#define IPU_FIELD_SCC IPU_CPMEM_WORD(0, 96, 1)
	57	#define IPU_FIELD_SCE IPU_CPMEM_WORD(0, 97, 1)
	58	#define IPU_FIELD_SDY IPU_CPMEM_WORD(0, 98, 7)
	59	#define IPU_FIELD_SDRX IPU_CPMEM_WORD(0, 105, 1)
	60	#define IPU_FIELD_SDRY IPU_CPMEM_WORD(0, 106, 1)
	61	#define IPU_FIELD_BPP IPU_CPMEM_WORD(0, 107, 3)
	62	#define IPU_FIELD_DEC_SEL IPU_CPMEM_WORD(0, 110, 2)
	63	#define IPU_FIELD_DIM IPU_CPMEM_WORD(0, 112, 1)
	64	#define IPU_FIELD_BNDM IPU_CPMEM_WORD(0, 114, 3)
65	#define IPU_FIELD_BM IPU_CPMEM_WORD(0, 117, 2)
66	#define IPU_FIELD_ROT IPU_CPMEM_WORD(0, 119, 1)
c42d37ca	67	#define IPU_FIELD_ROT_HF_VF IPU_CPMEM_WORD(0, 119, 3)
7d2691da SL	68	#define IPU_FIELD_HF IPU_CPMEM_WORD(0, 120, 1)
	69	#define IPU_FIELD_VF IPU_CPMEM_WORD(0, 121, 1)
	70	#define IPU_FIELD_THE IPU_CPMEM_WORD(0, 122, 1)
	71	#define IPU_FIELD_CAP IPU_CPMEM_WORD(0, 123, 1)
	72	#define IPU_FIELD_CAE IPU_CPMEM_WORD(0, 124, 1)
	73	#define IPU_FIELD_FW IPU_CPMEM_WORD(0, 125, 13)
	74	#define IPU_FIELD_FH IPU_CPMEM_WORD(0, 138, 12)
	75	#define IPU_FIELD_EBA0 IPU_CPMEM_WORD(1, 0, 29)
	76	#define IPU_FIELD_EBA1 IPU_CPMEM_WORD(1, 29, 29)
	77	#define IPU_FIELD_ILO IPU_CPMEM_WORD(1, 58, 20)
	78	#define IPU_FIELD_NPB IPU_CPMEM_WORD(1, 78, 7)
	79	#define IPU_FIELD_PFS IPU_CPMEM_WORD(1, 85, 4)
	80	#define IPU_FIELD_ALU IPU_CPMEM_WORD(1, 89, 1)
	81	#define IPU_FIELD_ALBM IPU_CPMEM_WORD(1, 90, 3)
	82	#define IPU_FIELD_ID IPU_CPMEM_WORD(1, 93, 2)
	83	#define IPU_FIELD_TH IPU_CPMEM_WORD(1, 95, 7)
	84	#define IPU_FIELD_SL IPU_CPMEM_WORD(1, 102, 14)
	85	#define IPU_FIELD_WID0 IPU_CPMEM_WORD(1, 116, 3)
	86	#define IPU_FIELD_WID1 IPU_CPMEM_WORD(1, 119, 3)
	87	#define IPU_FIELD_WID2 IPU_CPMEM_WORD(1, 122, 3)
	88	#define IPU_FIELD_WID3 IPU_CPMEM_WORD(1, 125, 3)
	89	#define IPU_FIELD_OFS0 IPU_CPMEM_WORD(1, 128, 5)
	90	#define IPU_FIELD_OFS1 IPU_CPMEM_WORD(1, 133, 5)
	91	#define IPU_FIELD_OFS2 IPU_CPMEM_WORD(1, 138, 5)
	92	#define IPU_FIELD_OFS3 IPU_CPMEM_WORD(1, 143, 5)
	93	#define IPU_FIELD_SXYS IPU_CPMEM_WORD(1, 148, 1)
	94	#define IPU_FIELD_CRE IPU_CPMEM_WORD(1, 149, 1)
	95	#define IPU_FIELD_DEC_SEL2 IPU_CPMEM_WORD(1, 150, 1)
	96
	97	static inline struct ipu_ch_param __iomem *
	98	ipu_get_cpmem(struct ipuv3_channel *ch)
	99	{
	100	struct ipu_cpmem *cpmem = ch->ipu->cpmem_priv;
	101
	102	return cpmem->base + ch->num;
	103	}
	104
	105	static void ipu_ch_param_write_field(struct ipuv3_channel *ch, u32 wbs, u32 v)
	106	{
	107	struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch);
	108	u32 bit = (wbs >> 8) % 160;
	109	u32 size = wbs & 0xff;
	110	u32 word = (wbs >> 8) / 160;
	111	u32 i = bit / 32;
	112	u32 ofs = bit % 32;
	113	u32 mask = (1 << size) - 1;
	114	u32 val;
	115
	116	pr_debug("%s %d %d %d\n", __func__, word, bit , size);
	117
	118	val = readl(&base->word[word].data[i]);
	119	val &= ~(mask << ofs);
	120	val \|= v << ofs;
	121	writel(val, &base->word[word].data[i]);
	122
	123	if ((bit + size - 1) / 32 > i) {
	124	val = readl(&base->word[word].data[i + 1]);
	125	val &= ~(mask >> (ofs ? (32 - ofs) : 0));
	126	val \|= v >> (ofs ? (32 - ofs) : 0);
	127	writel(val, &base->word[word].data[i + 1]);
	128	}
	129	}
	130
	131	static u32 ipu_ch_param_read_field(struct ipuv3_channel *ch, u32 wbs)
132	{
133	struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch);
134	u32 bit = (wbs >> 8) % 160;
135	u32 size = wbs & 0xff;
136	u32 word = (wbs >> 8) / 160;
137	u32 i = bit / 32;
138	u32 ofs = bit % 32;
139	u32 mask = (1 << size) - 1;
140	u32 val = 0;
141
142	pr_debug("%s %d %d %d\n", __func__, word, bit , size);
143
144	val = (readl(&base->word[word].data[i]) >> ofs) & mask;
145
146	if ((bit + size - 1) / 32 > i) {
147	u32 tmp;
148
149	tmp = readl(&base->word[word].data[i + 1]);
150	tmp &= mask >> (ofs ? (32 - ofs) : 0);
151	val \|= tmp << (ofs ? (32 - ofs) : 0);
152	}
153
154	return val;
155	}
156
157	/*
158	* The V4L2 spec defines packed RGB formats in memory byte order, which from
159	* point of view of the IPU corresponds to little-endian words with the first
160	* component in the least significant bits.
161	* The DRM pixel formats and IPU internal representation are ordered the other
162	* way around, with the first named component ordered at the most significant
163	* bits. Further, V4L2 formats are not well defined:
164	* http://linuxtv.org/downloads/v4l-dvb-apis/packed-rgb.html
165	* We choose the interpretation which matches GStreamer behavior.
166	*/
167	static int v4l2_pix_fmt_to_drm_fourcc(u32 pixelformat)
168	{
169	switch (pixelformat) {
170	case V4L2_PIX_FMT_RGB565:
171	/*
172	* Here we choose the 'corrected' interpretation of RGBP, a
173	* little-endian 16-bit word with the red component at the most
174	* significant bits:
175	* g[2:0]b[4:0] r[4:0]g[5:3] <=> [16:0] R:G:B
176	*/
177	return DRM_FORMAT_RGB565;
178	case V4L2_PIX_FMT_BGR24:
179	/* B G R <=> [24:0] R:G:B */
180	return DRM_FORMAT_RGB888;
181	case V4L2_PIX_FMT_RGB24:
182	/* R G B <=> [24:0] B:G:R */
183	return DRM_FORMAT_BGR888;
184	case V4L2_PIX_FMT_BGR32:
185	/* B G R A <=> [32:0] A:B:G:R */
186	return DRM_FORMAT_XRGB8888;
187	case V4L2_PIX_FMT_RGB32:
188	/* R G B A <=> [32:0] A:B:G:R */
189	return DRM_FORMAT_XBGR8888;
190	case V4L2_PIX_FMT_UYVY:
191	return DRM_FORMAT_UYVY;
192	case V4L2_PIX_FMT_YUYV:
193	return DRM_FORMAT_YUYV;
194	case V4L2_PIX_FMT_YUV420:
195	return DRM_FORMAT_YUV420;
196	case V4L2_PIX_FMT_YVU420:
197	return DRM_FORMAT_YVU420;
198	}
199
200	return -EINVAL;
201	}
202
203	void ipu_cpmem_zero(struct ipuv3_channel *ch)
204	{
205	struct ipu_ch_param __iomem *p = ipu_get_cpmem(ch);
206	void __iomem *base = p;
207	int i;
208
209	for (i = 0; i < sizeof(*p) / sizeof(u32); i++)
210	writel(0, base + i * sizeof(u32));
211	}
212	EXPORT_SYMBOL_GPL(ipu_cpmem_zero);
213
214	void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres)
215	{
216	ipu_ch_param_write_field(ch, IPU_FIELD_FW, xres - 1);
217	ipu_ch_param_write_field(ch, IPU_FIELD_FH, yres - 1);
218	}
219	EXPORT_SYMBOL_GPL(ipu_cpmem_set_resolution);
220
221	void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride)
222	{
223	ipu_ch_param_write_field(ch, IPU_FIELD_SLY, stride - 1);
224	}
225	EXPORT_SYMBOL_GPL(ipu_cpmem_set_stride);
226
227	void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch)
228	{
229	struct ipu_soc *ipu = ch->ipu;
230	u32 val;
231
232	if (ipu->ipu_type == IPUV3EX)
233	ipu_ch_param_write_field(ch, IPU_FIELD_ID, 1);
234
235	val = ipu_idmac_read(ipu, IDMAC_CHA_PRI(ch->num));
236	val \|= 1 << (ch->num % 32);
237	ipu_idmac_write(ipu, val, IDMAC_CHA_PRI(ch->num));
238	};
239	EXPORT_SYMBOL_GPL(ipu_cpmem_set_high_priority);
240
241	void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf)
242	{
243	if (bufnum)
244	ipu_ch_param_write_field(ch, IPU_FIELD_EBA1, buf >> 3);
245	else
246	ipu_ch_param_write_field(ch, IPU_FIELD_EBA0, buf >> 3);
247	}
248	EXPORT_SYMBOL_GPL(ipu_cpmem_set_buffer);
249
250	void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride)
251	{
252	ipu_ch_param_write_field(ch, IPU_FIELD_SO, 1);
253	ipu_ch_param_write_field(ch, IPU_FIELD_ILO, stride / 8);
254	ipu_ch_param_write_field(ch, IPU_FIELD_SLY, (stride * 2) - 1);
255	};
256	EXPORT_SYMBOL_GPL(ipu_cpmem_interlaced_scan);
257
555f0e66 SL	258	void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id)
	259	{
	260	id &= 0x3;
	261	ipu_ch_param_write_field(ch, IPU_FIELD_ID, id);
	262	}
	263	EXPORT_SYMBOL_GPL(ipu_cpmem_set_axi_id);
	264
7d2691da SL	265	void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize)
	266	{
	267	ipu_ch_param_write_field(ch, IPU_FIELD_NPB, burstsize - 1);
	268	};
	269	EXPORT_SYMBOL_GPL(ipu_cpmem_set_burstsize);
	270
9b9da0be SL	271	void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch)
	272	{
	273	ipu_ch_param_write_field(ch, IPU_FIELD_BM, 1);
	274	}
	275	EXPORT_SYMBOL_GPL(ipu_cpmem_set_block_mode);
	276
c42d37ca SL	277	void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
	278	enum ipu_rotate_mode rot)
	279	{
	280	u32 temp_rot = bitrev8(rot) >> 5;
	281
	282	ipu_ch_param_write_field(ch, IPU_FIELD_ROT_HF_VF, temp_rot);
	283	}
	284	EXPORT_SYMBOL_GPL(ipu_cpmem_set_rotation);
	285
7d2691da SL	286	int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
	287	const struct ipu_rgb *rgb)
	288	{
	289	int bpp = 0, npb = 0, ro, go, bo, to;
	290
	291	ro = rgb->bits_per_pixel - rgb->red.length - rgb->red.offset;
	292	go = rgb->bits_per_pixel - rgb->green.length - rgb->green.offset;
	293	bo = rgb->bits_per_pixel - rgb->blue.length - rgb->blue.offset;
	294	to = rgb->bits_per_pixel - rgb->transp.length - rgb->transp.offset;
	295
	296	ipu_ch_param_write_field(ch, IPU_FIELD_WID0, rgb->red.length - 1);
	297	ipu_ch_param_write_field(ch, IPU_FIELD_OFS0, ro);
	298	ipu_ch_param_write_field(ch, IPU_FIELD_WID1, rgb->green.length - 1);
	299	ipu_ch_param_write_field(ch, IPU_FIELD_OFS1, go);
	300	ipu_ch_param_write_field(ch, IPU_FIELD_WID2, rgb->blue.length - 1);
	301	ipu_ch_param_write_field(ch, IPU_FIELD_OFS2, bo);
	302
	303	if (rgb->transp.length) {
	304	ipu_ch_param_write_field(ch, IPU_FIELD_WID3,
	305	rgb->transp.length - 1);
	306	ipu_ch_param_write_field(ch, IPU_FIELD_OFS3, to);
	307	} else {
	308	ipu_ch_param_write_field(ch, IPU_FIELD_WID3, 7);
	309	ipu_ch_param_write_field(ch, IPU_FIELD_OFS3,
	310	rgb->bits_per_pixel);
	311	}
	312
	313	switch (rgb->bits_per_pixel) {
	314	case 32:
	315	bpp = 0;
	316	npb = 15;
	317	break;
	318	case 24:
	319	bpp = 1;
	320	npb = 19;
	321	break;
	322	case 16:
	323	bpp = 3;
	324	npb = 31;
	325	break;
	326	case 8:
	327	bpp = 5;
	328	npb = 63;
	329	break;
	330	default:
	331	return -EINVAL;
	332	}
	333	ipu_ch_param_write_field(ch, IPU_FIELD_BPP, bpp);
	334	ipu_ch_param_write_field(ch, IPU_FIELD_NPB, npb);
	335	ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 7); /* rgb mode */
	336
	337	return 0;
	338	}
	339	EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_rgb);
	340
	341	int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width)
	342	{
	343	int bpp = 0, npb = 0;
	344
	345	switch (width) {
	346	case 32:
	347	bpp = 0;
	348	npb = 15;
	349	break;
350	case 24:
351	bpp = 1;
352	npb = 19;
353	break;
354	case 16:
355	bpp = 3;
356	npb = 31;
357	break;
358	case 8:
359	bpp = 5;
360	npb = 63;
361	break;
362	default:
363	return -EINVAL;
364	}
365
366	ipu_ch_param_write_field(ch, IPU_FIELD_BPP, bpp);
367	ipu_ch_param_write_field(ch, IPU_FIELD_NPB, npb);
368	ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 6); /* raw mode */
369
370	return 0;
371	}
372	EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_passthrough);
373
374	void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format)
375	{
376	switch (pixel_format) {
377	case V4L2_PIX_FMT_UYVY:
378	ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); /* bits/pixel */
379	ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0xA);/* pix fmt */
380	ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);/* burst size */
381	break;
382	case V4L2_PIX_FMT_YUYV:
383	ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); /* bits/pixel */
384	ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0x8);/* pix fmt */
385	ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);/* burst size */
386	break;
387	}
388	}
389	EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_interleaved);
390
391	void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
392	u32 pixel_format, int stride,
393	int u_offset, int v_offset)
394	{
395	switch (pixel_format) {
396	case V4L2_PIX_FMT_YUV420:
397	ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, (stride / 2) - 1);
398	ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_offset / 8);
399	ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_offset / 8);
400	break;
401	case V4L2_PIX_FMT_YVU420:
402	ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, (stride / 2) - 1);
403	ipu_ch_param_write_field(ch, IPU_FIELD_UBO, v_offset / 8);
404	ipu_ch_param_write_field(ch, IPU_FIELD_VBO, u_offset / 8);
405	break;
406	}
407	}
408	EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar_full);
409
410	void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
411	u32 pixel_format, int stride, int height)
412	{
413	int u_offset, v_offset;
414	int uv_stride = 0;
415
416	switch (pixel_format) {
417	case V4L2_PIX_FMT_YUV420:
418	case V4L2_PIX_FMT_YVU420:
419	uv_stride = stride / 2;
420	u_offset = stride * height;
421	v_offset = u_offset + (uv_stride * height / 2);
422	ipu_cpmem_set_yuv_planar_full(ch, pixel_format, stride,
423	u_offset, v_offset);
424	break;
425	}
426	}
427	EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar);
428
429	static const struct ipu_rgb def_rgb_32 = {
430	.red = { .offset = 16, .length = 8, },
431	.green = { .offset = 8, .length = 8, },
432	.blue = { .offset = 0, .length = 8, },
433	.transp = { .offset = 24, .length = 8, },
434	.bits_per_pixel = 32,
435	};
436
437	static const struct ipu_rgb def_bgr_32 = {
438	.red = { .offset = 0, .length = 8, },
439	.green = { .offset = 8, .length = 8, },
440	.blue = { .offset = 16, .length = 8, },
441	.transp = { .offset = 24, .length = 8, },
442	.bits_per_pixel = 32,
443	};
444
445	static const struct ipu_rgb def_rgb_24 = {
446	.red = { .offset = 16, .length = 8, },
447	.green = { .offset = 8, .length = 8, },
448	.blue = { .offset = 0, .length = 8, },
449	.transp = { .offset = 0, .length = 0, },
450	.bits_per_pixel = 24,
451	};
452
453	static const struct ipu_rgb def_bgr_24 = {
454	.red = { .offset = 0, .length = 8, },
455	.green = { .offset = 8, .length = 8, },
456	.blue = { .offset = 16, .length = 8, },
457	.transp = { .offset = 0, .length = 0, },
458	.bits_per_pixel = 24,
459	};
460
461	static const struct ipu_rgb def_rgb_16 = {
462	.red = { .offset = 11, .length = 5, },
463	.green = { .offset = 5, .length = 6, },
464	.blue = { .offset = 0, .length = 5, },
465	.transp = { .offset = 0, .length = 0, },
466	.bits_per_pixel = 16,
467	};
468
469	static const struct ipu_rgb def_bgr_16 = {
470	.red = { .offset = 0, .length = 5, },
471	.green = { .offset = 5, .length = 6, },
472	.blue = { .offset = 11, .length = 5, },
473	.transp = { .offset = 0, .length = 0, },
474	.bits_per_pixel = 16,
475	};
476
477	#define Y_OFFSET(pix, x, y) ((x) + pix->width * (y))
478	#define U_OFFSET(pix, x, y) ((pix->width * pix->height) + \
479	(pix->width * (y) / 4) + (x) / 2)
480	#define V_OFFSET(pix, x, y) ((pix->width * pix->height) + \
481	(pix->width * pix->height / 4) + \
482	(pix->width * (y) / 4) + (x) / 2)
483
484	int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc)
485	{
486	switch (drm_fourcc) {
487	case DRM_FORMAT_YUV420:
488	case DRM_FORMAT_YVU420:
489	/* pix format */
490	ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 2);
491	/* burst size */
492	ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
493	break;
494	case DRM_FORMAT_UYVY:
495	/* bits/pixel */
496	ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3);
497	/* pix format */
498	ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0xA);
499	/* burst size */
500	ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
501	break;
502	case DRM_FORMAT_YUYV:
503	/* bits/pixel */
504	ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3);
505	/* pix format */
506	ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0x8);
507	/* burst size */
508	ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
509	break;
510	case DRM_FORMAT_ABGR8888:
511	case DRM_FORMAT_XBGR8888:
512	ipu_cpmem_set_format_rgb(ch, &def_bgr_32);
513	break;
514	case DRM_FORMAT_ARGB8888:
515	case DRM_FORMAT_XRGB8888:
516	ipu_cpmem_set_format_rgb(ch, &def_rgb_32);
517	break;
518	case DRM_FORMAT_BGR888:
519	ipu_cpmem_set_format_rgb(ch, &def_bgr_24);
520	break;
521	case DRM_FORMAT_RGB888:
522	ipu_cpmem_set_format_rgb(ch, &def_rgb_24);
523	break;
524	case DRM_FORMAT_RGB565:
525	ipu_cpmem_set_format_rgb(ch, &def_rgb_16);
526	break;
527	case DRM_FORMAT_BGR565:
528	ipu_cpmem_set_format_rgb(ch, &def_bgr_16);
529	break;
530	default:
531	return -EINVAL;
532	}
533
534	return 0;
535	}
536	EXPORT_SYMBOL_GPL(ipu_cpmem_set_fmt);
537
538	int ipu_cpmem_set_image(struct ipuv3_channel ch, struct ipu_image image)
539	{
540	struct v4l2_pix_format *pix = &image->pix;
2094b603	541	int offset, y_offset, u_offset, v_offset;
7d2691da SL	542
	543	pr_debug("%s: resolution: %dx%d stride: %d\n",
	544	__func__, pix->width, pix->height,
	545	pix->bytesperline);
	546
	547	ipu_cpmem_set_resolution(ch, image->rect.width, image->rect.height);
	548	ipu_cpmem_set_stride(ch, pix->bytesperline);
	549
	550	ipu_cpmem_set_fmt(ch, v4l2_pix_fmt_to_drm_fourcc(pix->pixelformat));
	551
	552	switch (pix->pixelformat) {
	553	case V4L2_PIX_FMT_YUV420:
	554	case V4L2_PIX_FMT_YVU420:
	555	y_offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
	556	u_offset = U_OFFSET(pix, image->rect.left,
	557	image->rect.top) - y_offset;
	558	v_offset = V_OFFSET(pix, image->rect.left,
	559	image->rect.top) - y_offset;
	560
	561	ipu_cpmem_set_yuv_planar_full(ch, pix->pixelformat,
	562	pix->bytesperline, u_offset, v_offset);
2094b603 SL	563	ipu_cpmem_set_buffer(ch, 0, image->phys0 + y_offset);
2094b603 SL	564	ipu_cpmem_set_buffer(ch, 1, image->phys1 + y_offset);
7d2691da SL	565	break;
	566	case V4L2_PIX_FMT_UYVY:
	567	case V4L2_PIX_FMT_YUYV:
2094b603 SL	568	case V4L2_PIX_FMT_RGB565:
	569	offset = image->rect.left * 2 +
	570	image->rect.top * pix->bytesperline;
	571	ipu_cpmem_set_buffer(ch, 0, image->phys0 + offset);
	572	ipu_cpmem_set_buffer(ch, 1, image->phys1 + offset);
7d2691da SL	573	break;
	574	case V4L2_PIX_FMT_RGB32:
	575	case V4L2_PIX_FMT_BGR32:
2094b603 SL	576	offset = image->rect.left * 4 +
	577	image->rect.top * pix->bytesperline;
	578	ipu_cpmem_set_buffer(ch, 0, image->phys0 + offset);
	579	ipu_cpmem_set_buffer(ch, 1, image->phys1 + offset);
7d2691da SL	580	break;
	581	case V4L2_PIX_FMT_RGB24:
	582	case V4L2_PIX_FMT_BGR24:
2094b603 SL	583	offset = image->rect.left * 3 +
	584	image->rect.top * pix->bytesperline;
	585	ipu_cpmem_set_buffer(ch, 0, image->phys0 + offset);
	586	ipu_cpmem_set_buffer(ch, 1, image->phys1 + offset);
7d2691da SL	587	break;
	588	default:
	589	return -EINVAL;
	590	}
	591
	592	return 0;
	593	}
	594	EXPORT_SYMBOL_GPL(ipu_cpmem_set_image);
	595
	596	int ipu_cpmem_init(struct ipu_soc ipu, struct device dev, unsigned long base)
	597	{
	598	struct ipu_cpmem *cpmem;
	599
	600	cpmem = devm_kzalloc(dev, sizeof(*cpmem), GFP_KERNEL);
	601	if (!cpmem)
	602	return -ENOMEM;
	603
	604	ipu->cpmem_priv = cpmem;
	605
	606	spin_lock_init(&cpmem->lock);
	607	cpmem->base = devm_ioremap(dev, base, SZ_128K);
	608	if (!cpmem->base)
	609	return -ENOMEM;
	610
	611	dev_dbg(dev, "CPMEM base: 0x%08lx remapped to %p\n",
	612	base, cpmem->base);
	613	cpmem->ipu = ipu;
	614
	615	return 0;
	616	}
	617
	618	void ipu_cpmem_exit(struct ipu_soc *ipu)
	619	{
	620	}