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drm/tegra: Explicitly set irq_enabled
[linux-2.6-block.git] / drivers / gpu / host1x / drm / dc.c
CommitLineData
d8f4a9ed
TR		 1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
11#include <linux/debugfs.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
61fd290d 15#include <linux/clk/tegra.h>
d8f4a9ed 16
692e6d7b 17#include "host1x_client.h"
de2ba664
AM		 18#include "dc.h"
19#include "drm.h"
20#include "gem.h"
d8f4a9ed 21
f34bc787
TR		 22struct tegra_plane {
23 struct drm_plane base;
24 unsigned int index;
d8f4a9ed
TR		 25};
26
f34bc787
TR		 27static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
28{
29 return container_of(plane, struct tegra_plane, base);
30}
31
32static int tegra_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
33 struct drm_framebuffer *fb, int crtc_x,
34 int crtc_y, unsigned int crtc_w,
35 unsigned int crtc_h, uint32_t src_x,
36 uint32_t src_y, uint32_t src_w, uint32_t src_h)
37{
38 struct tegra_plane *p = to_tegra_plane(plane);
39 struct tegra_dc *dc = to_tegra_dc(crtc);
40 struct tegra_dc_window window;
41 unsigned int i;
42
43 memset(&window, 0, sizeof(window));
44 window.src.x = src_x >> 16;
45 window.src.y = src_y >> 16;
46 window.src.w = src_w >> 16;
47 window.src.h = src_h >> 16;
48 window.dst.x = crtc_x;
49 window.dst.y = crtc_y;
50 window.dst.w = crtc_w;
51 window.dst.h = crtc_h;
52 window.format = tegra_dc_format(fb->pixel_format);
53 window.bits_per_pixel = fb->bits_per_pixel;
54
55 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
de2ba664 56 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
f34bc787 57
de2ba664 58 window.base[i] = bo->paddr + fb->offsets[i];
f34bc787
TR		 59
60 /*
61 * Tegra doesn't support different strides for U and V planes
62 * so we display a warning if the user tries to display a
63 * framebuffer with such a configuration.
64 */
65 if (i >= 2) {
66 if (fb->pitches[i] != window.stride[1])
67 DRM_ERROR("unsupported UV-plane configuration\n");
68 } else {
69 window.stride[i] = fb->pitches[i];
70 }
71 }
72
73 return tegra_dc_setup_window(dc, p->index, &window);
74}
75
76static int tegra_plane_disable(struct drm_plane *plane)
77{
78 struct tegra_dc *dc = to_tegra_dc(plane->crtc);
79 struct tegra_plane *p = to_tegra_plane(plane);
80 unsigned long value;
81
2678aeba
TR		 82 if (!plane->crtc)
83 return 0;
84
f34bc787
TR		 85 value = WINDOW_A_SELECT << p->index;
86 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
87
88 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
89 value &= ~WIN_ENABLE;
90 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
91
92 tegra_dc_writel(dc, WIN_A_UPDATE << p->index, DC_CMD_STATE_CONTROL);
93 tegra_dc_writel(dc, WIN_A_ACT_REQ << p->index, DC_CMD_STATE_CONTROL);
94
95 return 0;
96}
97
98static void tegra_plane_destroy(struct drm_plane *plane)
99{
100 tegra_plane_disable(plane);
101 drm_plane_cleanup(plane);
102}
103
104static const struct drm_plane_funcs tegra_plane_funcs = {
105 .update_plane = tegra_plane_update,
106 .disable_plane = tegra_plane_disable,
107 .destroy = tegra_plane_destroy,
108};
109
110static const uint32_t plane_formats[] = {
dbe4d9a7 111 DRM_FORMAT_XBGR8888,
f34bc787 112 DRM_FORMAT_XRGB8888,
dbe4d9a7 113 DRM_FORMAT_RGB565,
f34bc787
TR		 114 DRM_FORMAT_UYVY,
115 DRM_FORMAT_YUV420,
116 DRM_FORMAT_YUV422,
117};
118
119static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
120{
121 unsigned int i;
122 int err = 0;
123
124 for (i = 0; i < 2; i++) {
125 struct tegra_plane *plane;
126
127 plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
128 if (!plane)
129 return -ENOMEM;
130
131 plane->index = 1 + i;
132
133 err = drm_plane_init(drm, &plane->base, 1 << dc->pipe,
134 &tegra_plane_funcs, plane_formats,
135 ARRAY_SIZE(plane_formats), false);
136 if (err < 0)
137 return err;
138 }
139
140 return 0;
141}
142
23fb4740
TR		 143static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
144 struct drm_framebuffer *fb)
145{
de2ba664 146 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
23fb4740
TR		 147 unsigned long value;
148
149 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
150
151 value = fb->offsets[0] + y * fb->pitches[0] +
152 x * fb->bits_per_pixel / 8;
153
de2ba664 154 tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR);
23fb4740
TR		 155 tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE);
156
157 value = GENERAL_UPDATE | WIN_A_UPDATE;
158 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
159
160 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
161 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
162
163 return 0;
164}
165
6e5ff998
TR		 166void tegra_dc_enable_vblank(struct tegra_dc *dc)
167{
168 unsigned long value, flags;
169
170 spin_lock_irqsave(&dc->lock, flags);
171
172 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
173 value |= VBLANK_INT;
174 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
175
176 spin_unlock_irqrestore(&dc->lock, flags);
177}
178
179void tegra_dc_disable_vblank(struct tegra_dc *dc)
180{
181 unsigned long value, flags;
182
183 spin_lock_irqsave(&dc->lock, flags);
184
185 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
186 value &= ~VBLANK_INT;
187 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
188
189 spin_unlock_irqrestore(&dc->lock, flags);
190}
191
3c03c46a
TR		 192static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
193{
194 struct drm_device *drm = dc->base.dev;
195 struct drm_crtc *crtc = &dc->base;
3c03c46a 196 unsigned long flags, base;
de2ba664 197 struct tegra_bo *bo;
3c03c46a
TR		 198
199 if (!dc->event)
200 return;
201
de2ba664 202 bo = tegra_fb_get_plane(crtc->fb, 0);
3c03c46a
TR		 203
204 /* check if new start address has been latched */
205 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
206 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
207 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
208
de2ba664 209 if (base == bo->paddr + crtc->fb->offsets[0]) {
3c03c46a
TR		 210 spin_lock_irqsave(&drm->event_lock, flags);
211 drm_send_vblank_event(drm, dc->pipe, dc->event);
212 drm_vblank_put(drm, dc->pipe);
213 dc->event = NULL;
214 spin_unlock_irqrestore(&drm->event_lock, flags);
215 }
216}
217
218void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
219{
220 struct tegra_dc *dc = to_tegra_dc(crtc);
221 struct drm_device *drm = crtc->dev;
222 unsigned long flags;
223
224 spin_lock_irqsave(&drm->event_lock, flags);
225
226 if (dc->event && dc->event->base.file_priv == file) {
227 dc->event->base.destroy(&dc->event->base);
228 drm_vblank_put(drm, dc->pipe);
229 dc->event = NULL;
230 }
231
232 spin_unlock_irqrestore(&drm->event_lock, flags);
233}
234
235static int tegra_dc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
236 struct drm_pending_vblank_event *event)
237{
238 struct tegra_dc *dc = to_tegra_dc(crtc);
239 struct drm_device *drm = crtc->dev;
240
241 if (dc->event)
242 return -EBUSY;
243
244 if (event) {
245 event->pipe = dc->pipe;
246 dc->event = event;
247 drm_vblank_get(drm, dc->pipe);
248 }
249
250 tegra_dc_set_base(dc, 0, 0, fb);
251 crtc->fb = fb;
252
253 return 0;
254}
255
d8f4a9ed 256static const struct drm_crtc_funcs tegra_crtc_funcs = {
3c03c46a 257 .page_flip = tegra_dc_page_flip,
d8f4a9ed
TR		 258 .set_config = drm_crtc_helper_set_config,
259 .destroy = drm_crtc_cleanup,
260};
261
f34bc787 262static void tegra_crtc_disable(struct drm_crtc *crtc)
d8f4a9ed 263{
f34bc787
TR		 264 struct drm_device *drm = crtc->dev;
265 struct drm_plane *plane;
266
267 list_for_each_entry(plane, &drm->mode_config.plane_list, head) {
268 if (plane->crtc == crtc) {
269 tegra_plane_disable(plane);
270 plane->crtc = NULL;
271
272 if (plane->fb) {
273 drm_framebuffer_unreference(plane->fb);
274 plane->fb = NULL;
275 }
276 }
277 }
d8f4a9ed
TR		 278}
279
280static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
281 const struct drm_display_mode *mode,
282 struct drm_display_mode *adjusted)
283{
284 return true;
285}
286
f34bc787 287static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
d8f4a9ed
TR		 288 unsigned int bpp)
289{
290 fixed20_12 outf = dfixed_init(out);
f34bc787 291 fixed20_12 inf = dfixed_init(in);
d8f4a9ed
TR		 292 u32 dda_inc;
293 int max;
294
295 if (v)
296 max = 15;
297 else {
298 switch (bpp) {
299 case 2:
300 max = 8;
301 break;
302
303 default:
304 WARN_ON_ONCE(1);
305 /* fallthrough */
306 case 4:
307 max = 4;
308 break;
309 }
310 }
311
312 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
313 inf.full -= dfixed_const(1);
314
315 dda_inc = dfixed_div(inf, outf);
316 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
317
318 return dda_inc;
319}
320
f34bc787 321static inline u32 compute_initial_dda(unsigned int in)
d8f4a9ed 322{
f34bc787
TR		 323 fixed20_12 inf = dfixed_init(in);
324 return dfixed_frac(inf);
d8f4a9ed
TR		 325}
326
327static int tegra_dc_set_timings(struct tegra_dc *dc,
328 struct drm_display_mode *mode)
329{
330 /* TODO: For HDMI compliance, h & v ref_to_sync should be set to 1 */
331 unsigned int h_ref_to_sync = 0;
332 unsigned int v_ref_to_sync = 0;
333 unsigned long value;
334
335 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
336
337 value = (v_ref_to_sync << 16) | h_ref_to_sync;
338 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
339
340 value = ((mode->vsync_end - mode->vsync_start) << 16) |
341 ((mode->hsync_end - mode->hsync_start) << 0);
342 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
343
d8f4a9ed
TR		 344 value = ((mode->vtotal - mode->vsync_end) << 16) |
345 ((mode->htotal - mode->hsync_end) << 0);
40495089
LS		 346 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
347
348 value = ((mode->vsync_start - mode->vdisplay) << 16) |
349 ((mode->hsync_start - mode->hdisplay) << 0);
d8f4a9ed
TR		 350 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
351
352 value = (mode->vdisplay << 16) | mode->hdisplay;
353 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
354
355 return 0;
356}
357
358static int tegra_crtc_setup_clk(struct drm_crtc *crtc,
359 struct drm_display_mode *mode,
360 unsigned long *div)
361{
362 unsigned long pclk = mode->clock * 1000, rate;
363 struct tegra_dc *dc = to_tegra_dc(crtc);
364 struct tegra_output *output = NULL;
365 struct drm_encoder *encoder;
366 long err;
367
368 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head)
369 if (encoder->crtc == crtc) {
370 output = encoder_to_output(encoder);
371 break;
372 }
373
374 if (!output)
375 return -ENODEV;
376
377 /*
378 * This assumes that the display controller will divide its parent
379 * clock by 2 to generate the pixel clock.
380 */
381 err = tegra_output_setup_clock(output, dc->clk, pclk * 2);
382 if (err < 0) {
383 dev_err(dc->dev, "failed to setup clock: %ld\n", err);
384 return err;
385 }
386
387 rate = clk_get_rate(dc->clk);
388 *div = (rate * 2 / pclk) - 2;
389
390 DRM_DEBUG_KMS("rate: %lu, div: %lu\n", rate, *div);
391
392 return 0;
393}
394
f34bc787
TR		 395static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
396{
397 switch (format) {
398 case WIN_COLOR_DEPTH_YCbCr422:
399 case WIN_COLOR_DEPTH_YUV422:
400 if (planar)
401 *planar = false;
402
403 return true;
404
405 case WIN_COLOR_DEPTH_YCbCr420P:
406 case WIN_COLOR_DEPTH_YUV420P:
407 case WIN_COLOR_DEPTH_YCbCr422P:
408 case WIN_COLOR_DEPTH_YUV422P:
409 case WIN_COLOR_DEPTH_YCbCr422R:
410 case WIN_COLOR_DEPTH_YUV422R:
411 case WIN_COLOR_DEPTH_YCbCr422RA:
412 case WIN_COLOR_DEPTH_YUV422RA:
413 if (planar)
414 *planar = true;
415
416 return true;
417 }
418
419 return false;
420}
421
422int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
423 const struct tegra_dc_window *window)
424{
425 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
426 unsigned long value;
427 bool yuv, planar;
428
429 /*
430 * For YUV planar modes, the number of bytes per pixel takes into
431 * account only the luma component and therefore is 1.
432 */
433 yuv = tegra_dc_format_is_yuv(window->format, &planar);
434 if (!yuv)
435 bpp = window->bits_per_pixel / 8;
436 else
437 bpp = planar ? 1 : 2;
438
439 value = WINDOW_A_SELECT << index;
440 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
441
442 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
443 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
444
445 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
446 tegra_dc_writel(dc, value, DC_WIN_POSITION);
447
448 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
449 tegra_dc_writel(dc, value, DC_WIN_SIZE);
450
451 h_offset = window->src.x * bpp;
452 v_offset = window->src.y;
453 h_size = window->src.w * bpp;
454 v_size = window->src.h;
455
456 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
457 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
458
459 /*
460 * For DDA computations the number of bytes per pixel for YUV planar
461 * modes needs to take into account all Y, U and V components.
462 */
463 if (yuv && planar)
464 bpp = 2;
465
466 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
467 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
468
469 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
470 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
471
472 h_dda = compute_initial_dda(window->src.x);
473 v_dda = compute_initial_dda(window->src.y);
474
475 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
476 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
477
478 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
479 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
480
481 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
482
483 if (yuv && planar) {
484 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
485 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
486 value = window->stride[1] << 16 | window->stride[0];
487 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
488 } else {
489 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
490 }
491
492 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
493 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
494
495 value = WIN_ENABLE;
496
497 if (yuv) {
498 /* setup default colorspace conversion coefficients */
499 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
500 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
501 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
502 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
503 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
504 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
505 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
506 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
507
508 value |= CSC_ENABLE;
84ff6b27 509 } else if (window->bits_per_pixel < 24) {
f34bc787
TR		 510 value |= COLOR_EXPAND;
511 }
512
513 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
514
515 /*
516 * Disable blending and assume Window A is the bottom-most window,
517 * Window C is the top-most window and Window B is in the middle.
518 */
519 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
520 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
521
522 switch (index) {
523 case 0:
524 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
525 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
526 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
527 break;
528
529 case 1:
530 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
531 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
532 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
533 break;
534
535 case 2:
536 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
537 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
538 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
539 break;
540 }
541
542 tegra_dc_writel(dc, WIN_A_UPDATE << index, DC_CMD_STATE_CONTROL);
543 tegra_dc_writel(dc, WIN_A_ACT_REQ << index, DC_CMD_STATE_CONTROL);
544
545 return 0;
546}
547
548unsigned int tegra_dc_format(uint32_t format)
549{
550 switch (format) {
dbe4d9a7
TR		 551 case DRM_FORMAT_XBGR8888:
552 return WIN_COLOR_DEPTH_R8G8B8A8;
553
f34bc787
TR		 554 case DRM_FORMAT_XRGB8888:
555 return WIN_COLOR_DEPTH_B8G8R8A8;
556
557 case DRM_FORMAT_RGB565:
558 return WIN_COLOR_DEPTH_B5G6R5;
559
560 case DRM_FORMAT_UYVY:
561 return WIN_COLOR_DEPTH_YCbCr422;
562
563 case DRM_FORMAT_YUV420:
564 return WIN_COLOR_DEPTH_YCbCr420P;
565
566 case DRM_FORMAT_YUV422:
567 return WIN_COLOR_DEPTH_YCbCr422P;
568
569 default:
570 break;
571 }
572
573 WARN(1, "unsupported pixel format %u, using default\n", format);
574 return WIN_COLOR_DEPTH_B8G8R8A8;
575}
576
d8f4a9ed
TR		 577static int tegra_crtc_mode_set(struct drm_crtc *crtc,
578 struct drm_display_mode *mode,
579 struct drm_display_mode *adjusted,
580 int x, int y, struct drm_framebuffer *old_fb)
581{
de2ba664 582 struct tegra_bo *bo = tegra_fb_get_plane(crtc->fb, 0);
d8f4a9ed 583 struct tegra_dc *dc = to_tegra_dc(crtc);
f34bc787 584 struct tegra_dc_window window;
d8f4a9ed
TR		 585 unsigned long div, value;
586 int err;
587
6e5ff998
TR		 588 drm_vblank_pre_modeset(crtc->dev, dc->pipe);
589
d8f4a9ed
TR		 590 err = tegra_crtc_setup_clk(crtc, mode, &div);
591 if (err) {
592 dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err);
593 return err;
594 }
595
596 /* program display mode */
597 tegra_dc_set_timings(dc, mode);
598
599 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
600 tegra_dc_writel(dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
601
602 value = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY(1));
603 value &= ~LVS_OUTPUT_POLARITY_LOW;
604 value &= ~LHS_OUTPUT_POLARITY_LOW;
605 tegra_dc_writel(dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
606
607 value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB |
608 DISP_ORDER_RED_BLUE;
609 tegra_dc_writel(dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
610
611 tegra_dc_writel(dc, 0x00010001, DC_DISP_SHIFT_CLOCK_OPTIONS);
612
613 value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
614 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
615
616 /* setup window parameters */
f34bc787
TR		 617 memset(&window, 0, sizeof(window));
618 window.src.x = 0;
619 window.src.y = 0;
620 window.src.w = mode->hdisplay;
621 window.src.h = mode->vdisplay;
622 window.dst.x = 0;
623 window.dst.y = 0;
624 window.dst.w = mode->hdisplay;
625 window.dst.h = mode->vdisplay;
626 window.format = tegra_dc_format(crtc->fb->pixel_format);
627 window.bits_per_pixel = crtc->fb->bits_per_pixel;
628 window.stride[0] = crtc->fb->pitches[0];
de2ba664 629 window.base[0] = bo->paddr;
f34bc787
TR		 630
631 err = tegra_dc_setup_window(dc, 0, &window);
632 if (err < 0)
633 dev_err(dc->dev, "failed to enable root plane\n");
d8f4a9ed 634
d8f4a9ed
TR		 635 return 0;
636}
d8f4a9ed 637
23fb4740
TR		 638static int tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
639 struct drm_framebuffer *old_fb)
640{
641 struct tegra_dc *dc = to_tegra_dc(crtc);
d8f4a9ed 642
23fb4740 643 return tegra_dc_set_base(dc, x, y, crtc->fb);
d8f4a9ed
TR		 644}
645
646static void tegra_crtc_prepare(struct drm_crtc *crtc)
647{
648 struct tegra_dc *dc = to_tegra_dc(crtc);
649 unsigned int syncpt;
650 unsigned long value;
651
652 /* hardware initialization */
653 tegra_periph_reset_deassert(dc->clk);
654 usleep_range(10000, 20000);
655
656 if (dc->pipe)
657 syncpt = SYNCPT_VBLANK1;
658 else
659 syncpt = SYNCPT_VBLANK0;
660
661 /* initialize display controller */
662 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
663 tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
664
665 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
666 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
667
668 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
669 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
670 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
671
672 value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
673 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
674 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
675
676 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
677 value |= DISP_CTRL_MODE_C_DISPLAY;
678 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
679
680 /* initialize timer */
681 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
682 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
683 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
684
685 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
686 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
687 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
688
d8f4a9ed
TR		 689 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
690 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
6e5ff998
TR		 691
692 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
693 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
d8f4a9ed
TR		 694}
695
696static void tegra_crtc_commit(struct drm_crtc *crtc)
697{
698 struct tegra_dc *dc = to_tegra_dc(crtc);
d8f4a9ed
TR		 699 unsigned long value;
700
3b9e71ea
TR		 701 value = GENERAL_UPDATE | WIN_A_UPDATE;
702 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
d8f4a9ed 703
3b9e71ea 704 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
6e5ff998 705 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
d8f4a9ed 706
6e5ff998 707 drm_vblank_post_modeset(crtc->dev, dc->pipe);
d8f4a9ed
TR		 708}
709
710static void tegra_crtc_load_lut(struct drm_crtc *crtc)
711{
712}
713
714static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
f34bc787 715 .disable = tegra_crtc_disable,
d8f4a9ed
TR		 716 .mode_fixup = tegra_crtc_mode_fixup,
717 .mode_set = tegra_crtc_mode_set,
23fb4740 718 .mode_set_base = tegra_crtc_mode_set_base,
d8f4a9ed
TR		 719 .prepare = tegra_crtc_prepare,
720 .commit = tegra_crtc_commit,
721 .load_lut = tegra_crtc_load_lut,
722};
723
6e5ff998 724static irqreturn_t tegra_dc_irq(int irq, void *data)
d8f4a9ed
TR		 725{
726 struct tegra_dc *dc = data;
727 unsigned long status;
728
729 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
730 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
731
732 if (status & FRAME_END_INT) {
733 /*
734 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
735 */
736 }
737
738 if (status & VBLANK_INT) {
739 /*
740 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
741 */
742 drm_handle_vblank(dc->base.dev, dc->pipe);
3c03c46a 743 tegra_dc_finish_page_flip(dc);
d8f4a9ed
TR		 744 }
745
746 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
747 /*
748 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
749 */
750 }
751
752 return IRQ_HANDLED;
753}
754
755static int tegra_dc_show_regs(struct seq_file *s, void *data)
756{
757 struct drm_info_node *node = s->private;
758 struct tegra_dc *dc = node->info_ent->data;
759
760#define DUMP_REG(name) \
761 seq_printf(s, "%-40s %#05x %08lx\n", #name, name, \
762 tegra_dc_readl(dc, name))
763
764 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
765 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
766 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
767 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
768 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
769 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
770 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
771 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
772 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
773 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
774 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
775 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
776 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
777 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
778 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
779 DUMP_REG(DC_CMD_SIGNAL_RAISE);
780 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
781 DUMP_REG(DC_CMD_INT_STATUS);
782 DUMP_REG(DC_CMD_INT_MASK);
783 DUMP_REG(DC_CMD_INT_ENABLE);
784 DUMP_REG(DC_CMD_INT_TYPE);
785 DUMP_REG(DC_CMD_INT_POLARITY);
786 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
787 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
788 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
789 DUMP_REG(DC_CMD_STATE_ACCESS);
790 DUMP_REG(DC_CMD_STATE_CONTROL);
791 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
792 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
793 DUMP_REG(DC_COM_CRC_CONTROL);
794 DUMP_REG(DC_COM_CRC_CHECKSUM);
795 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
796 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
797 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
798 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
799 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
800 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
801 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
802 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
803 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
804 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
805 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
806 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
807 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
808 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
809 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
810 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
811 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
812 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
813 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
814 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
815 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
816 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
817 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
818 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
819 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
820 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
821 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
822 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
823 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
824 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
825 DUMP_REG(DC_COM_SPI_CONTROL);
826 DUMP_REG(DC_COM_SPI_START_BYTE);
827 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
828 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
829 DUMP_REG(DC_COM_HSPI_CS_DC);
830 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
831 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
832 DUMP_REG(DC_COM_GPIO_CTRL);
833 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
834 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
835 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
836 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
837 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
838 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
839 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
840 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
841 DUMP_REG(DC_DISP_REF_TO_SYNC);
842 DUMP_REG(DC_DISP_SYNC_WIDTH);
843 DUMP_REG(DC_DISP_BACK_PORCH);
844 DUMP_REG(DC_DISP_ACTIVE);
845 DUMP_REG(DC_DISP_FRONT_PORCH);
846 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
847 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
848 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
849 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
850 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
851 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
852 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
853 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
854 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
855 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
856 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
857 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
858 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
859 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
860 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
861 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
862 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
863 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
864 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
865 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
866 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
867 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
868 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
869 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
870 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
871 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
872 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
873 DUMP_REG(DC_DISP_M0_CONTROL);
874 DUMP_REG(DC_DISP_M1_CONTROL);
875 DUMP_REG(DC_DISP_DI_CONTROL);
876 DUMP_REG(DC_DISP_PP_CONTROL);
877 DUMP_REG(DC_DISP_PP_SELECT_A);
878 DUMP_REG(DC_DISP_PP_SELECT_B);
879 DUMP_REG(DC_DISP_PP_SELECT_C);
880 DUMP_REG(DC_DISP_PP_SELECT_D);
881 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
882 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
883 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
884 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
885 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
886 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
887 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
888 DUMP_REG(DC_DISP_BORDER_COLOR);
889 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
890 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
891 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
892 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
893 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
894 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
895 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
896 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
897 DUMP_REG(DC_DISP_CURSOR_POSITION);
898 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
899 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
900 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
901 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
902 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
903 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
904 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
905 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
906 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
907 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
908 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
909 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
910 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
911 DUMP_REG(DC_DISP_SD_CONTROL);
912 DUMP_REG(DC_DISP_SD_CSC_COEFF);
913 DUMP_REG(DC_DISP_SD_LUT(0));
914 DUMP_REG(DC_DISP_SD_LUT(1));
915 DUMP_REG(DC_DISP_SD_LUT(2));
916 DUMP_REG(DC_DISP_SD_LUT(3));
917 DUMP_REG(DC_DISP_SD_LUT(4));
918 DUMP_REG(DC_DISP_SD_LUT(5));
919 DUMP_REG(DC_DISP_SD_LUT(6));
920 DUMP_REG(DC_DISP_SD_LUT(7));
921 DUMP_REG(DC_DISP_SD_LUT(8));
922 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
923 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
924 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
925 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
926 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
927 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
928 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
929 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
930 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
931 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
932 DUMP_REG(DC_DISP_SD_BL_TF(0));
933 DUMP_REG(DC_DISP_SD_BL_TF(1));
934 DUMP_REG(DC_DISP_SD_BL_TF(2));
935 DUMP_REG(DC_DISP_SD_BL_TF(3));
936 DUMP_REG(DC_DISP_SD_BL_CONTROL);
937 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
938 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
939 DUMP_REG(DC_WIN_WIN_OPTIONS);
940 DUMP_REG(DC_WIN_BYTE_SWAP);
941 DUMP_REG(DC_WIN_BUFFER_CONTROL);
942 DUMP_REG(DC_WIN_COLOR_DEPTH);
943 DUMP_REG(DC_WIN_POSITION);
944 DUMP_REG(DC_WIN_SIZE);
945 DUMP_REG(DC_WIN_PRESCALED_SIZE);
946 DUMP_REG(DC_WIN_H_INITIAL_DDA);
947 DUMP_REG(DC_WIN_V_INITIAL_DDA);
948 DUMP_REG(DC_WIN_DDA_INC);
949 DUMP_REG(DC_WIN_LINE_STRIDE);
950 DUMP_REG(DC_WIN_BUF_STRIDE);
951 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
952 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
953 DUMP_REG(DC_WIN_DV_CONTROL);
954 DUMP_REG(DC_WIN_BLEND_NOKEY);
955 DUMP_REG(DC_WIN_BLEND_1WIN);
956 DUMP_REG(DC_WIN_BLEND_2WIN_X);
957 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
f34bc787 958 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
d8f4a9ed
TR		 959 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
960 DUMP_REG(DC_WINBUF_START_ADDR);
961 DUMP_REG(DC_WINBUF_START_ADDR_NS);
962 DUMP_REG(DC_WINBUF_START_ADDR_U);
963 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
964 DUMP_REG(DC_WINBUF_START_ADDR_V);
965 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
966 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
967 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
968 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
969 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
970 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
971 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
972 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
973 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
974
975#undef DUMP_REG
976
977 return 0;
978}
979
980static struct drm_info_list debugfs_files[] = {
981 { "regs", tegra_dc_show_regs, 0, NULL },
982};
983
984static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
985{
986 unsigned int i;
987 char *name;
988 int err;
989
990 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
991 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
992 kfree(name);
993
994 if (!dc->debugfs)
995 return -ENOMEM;
996
997 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
998 GFP_KERNEL);
999 if (!dc->debugfs_files) {
1000 err = -ENOMEM;
1001 goto remove;
1002 }
1003
1004 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1005 dc->debugfs_files[i].data = dc;
1006
1007 err = drm_debugfs_create_files(dc->debugfs_files,
1008 ARRAY_SIZE(debugfs_files),
1009 dc->debugfs, minor);
1010 if (err < 0)
1011 goto free;
1012
1013 dc->minor = minor;
1014
1015 return 0;
1016
1017free:
1018 kfree(dc->debugfs_files);
1019 dc->debugfs_files = NULL;
1020remove:
1021 debugfs_remove(dc->debugfs);
1022 dc->debugfs = NULL;
1023
1024 return err;
1025}
1026
1027static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1028{
1029 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1030 dc->minor);
1031 dc->minor = NULL;
1032
1033 kfree(dc->debugfs_files);
1034 dc->debugfs_files = NULL;
1035
1036 debugfs_remove(dc->debugfs);
1037 dc->debugfs = NULL;
1038
1039 return 0;
1040}
1041
1042static int tegra_dc_drm_init(struct host1x_client *client,
1043 struct drm_device *drm)
1044{
1045 struct tegra_dc *dc = host1x_client_to_dc(client);
1046 int err;
1047
1048 dc->pipe = drm->mode_config.num_crtc;
1049
1050 drm_crtc_init(drm, &dc->base, &tegra_crtc_funcs);
1051 drm_mode_crtc_set_gamma_size(&dc->base, 256);
1052 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1053
1054 err = tegra_dc_rgb_init(drm, dc);
1055 if (err < 0 && err != -ENODEV) {
1056 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1057 return err;
1058 }
1059
f34bc787
TR		 1060 err = tegra_dc_add_planes(drm, dc);
1061 if (err < 0)
1062 return err;
1063
d8f4a9ed
TR		 1064 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1065 err = tegra_dc_debugfs_init(dc, drm->primary);
1066 if (err < 0)
1067 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1068 }
1069
6e5ff998 1070 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
d8f4a9ed
TR		 1071 dev_name(dc->dev), dc);
1072 if (err < 0) {
1073 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1074 err);
1075 return err;
1076 }
1077
1078 return 0;
1079}
1080
1081static int tegra_dc_drm_exit(struct host1x_client *client)
1082{
1083 struct tegra_dc *dc = host1x_client_to_dc(client);
1084 int err;
1085
1086 devm_free_irq(dc->dev, dc->irq, dc);
1087
1088 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1089 err = tegra_dc_debugfs_exit(dc);
1090 if (err < 0)
1091 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1092 }
1093
1094 err = tegra_dc_rgb_exit(dc);
1095 if (err) {
1096 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1097 return err;
1098 }
1099
1100 return 0;
1101}
1102
1103static const struct host1x_client_ops dc_client_ops = {
1104 .drm_init = tegra_dc_drm_init,
1105 .drm_exit = tegra_dc_drm_exit,
1106};
1107
1108static int tegra_dc_probe(struct platform_device *pdev)
1109{
692e6d7b 1110 struct host1x_drm *host1x = host1x_get_drm_data(pdev->dev.parent);
d8f4a9ed
TR		 1111 struct resource *regs;
1112 struct tegra_dc *dc;
1113 int err;
1114
1115 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1116 if (!dc)
1117 return -ENOMEM;
1118
6e5ff998 1119 spin_lock_init(&dc->lock);
d8f4a9ed
TR		 1120 INIT_LIST_HEAD(&dc->list);
1121 dc->dev = &pdev->dev;
1122
1123 dc->clk = devm_clk_get(&pdev->dev, NULL);
1124 if (IS_ERR(dc->clk)) {
1125 dev_err(&pdev->dev, "failed to get clock\n");
1126 return PTR_ERR(dc->clk);
1127 }
1128
1129 err = clk_prepare_enable(dc->clk);
1130 if (err < 0)
1131 return err;
1132
1133 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d4ed6025
TR		 1134 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
1135 if (IS_ERR(dc->regs))
1136 return PTR_ERR(dc->regs);
d8f4a9ed
TR		 1137
1138 dc->irq = platform_get_irq(pdev, 0);
1139 if (dc->irq < 0) {
1140 dev_err(&pdev->dev, "failed to get IRQ\n");
1141 return -ENXIO;
1142 }
1143
1144 INIT_LIST_HEAD(&dc->client.list);
1145 dc->client.ops = &dc_client_ops;
1146 dc->client.dev = &pdev->dev;
1147
1148 err = tegra_dc_rgb_probe(dc);
1149 if (err < 0 && err != -ENODEV) {
1150 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
1151 return err;
1152 }
1153
1154 err = host1x_register_client(host1x, &dc->client);
1155 if (err < 0) {
1156 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1157 err);
1158 return err;
1159 }
1160
1161 platform_set_drvdata(pdev, dc);
1162
1163 return 0;
1164}
1165
1166static int tegra_dc_remove(struct platform_device *pdev)
1167{
692e6d7b 1168 struct host1x_drm *host1x = host1x_get_drm_data(pdev->dev.parent);
d8f4a9ed
TR		 1169 struct tegra_dc *dc = platform_get_drvdata(pdev);
1170 int err;
1171
1172 err = host1x_unregister_client(host1x, &dc->client);
1173 if (err < 0) {
1174 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1175 err);
1176 return err;
1177 }
1178
1179 clk_disable_unprepare(dc->clk);
1180
1181 return 0;
1182}
1183
1184static struct of_device_id tegra_dc_of_match[] = {
219e8153 1185 { .compatible = "nvidia,tegra30-dc", },
d8f4a9ed
TR		 1186 { .compatible = "nvidia,tegra20-dc", },
1187 { },
1188};
1189
1190struct platform_driver tegra_dc_driver = {
1191 .driver = {
1192 .name = "tegra-dc",
1193 .owner = THIS_MODULE,
1194 .of_match_table = tegra_dc_of_match,
1195 },
1196 .probe = tegra_dc_probe,
1197 .remove = tegra_dc_remove,
1198};
Linux 6.x block layer and io_uring tree(s)