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Merge tag 'pinctrl-v6.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw...
[linux-block.git] / drivers / gpu / drm / xe / xe_guc_ads.c
CommitLineData
dd08ebf6
MB		 1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2022 Intel Corporation
4 */
5
ea9f879d
LDM		 6#include "xe_guc_ads.h"
7
dd08ebf6
MB		 8#include <drm/drm_managed.h>
9
b79e8fd9 10#include "regs/xe_engine_regs.h"
226bfec8 11#include "regs/xe_gt_regs.h"
a9b1a136 12#include "regs/xe_guc_regs.h"
dd08ebf6
MB		 13#include "xe_bo.h"
14#include "xe_gt.h"
0d97ecce 15#include "xe_gt_ccs_mode.h"
dd08ebf6 16#include "xe_guc.h"
dd08ebf6
MB		 17#include "xe_hw_engine.h"
18#include "xe_lrc.h"
19#include "xe_map.h"
20#include "xe_mmio.h"
21#include "xe_platform_types.h"
ea9f879d 22
dd08ebf6
MB		 23/* Slack of a few additional entries per engine */
24#define ADS_REGSET_EXTRA_MAX 8
25
26static struct xe_guc *
27ads_to_guc(struct xe_guc_ads *ads)
28{
29 return container_of(ads, struct xe_guc, ads);
30}
31
32static struct xe_gt *
33ads_to_gt(struct xe_guc_ads *ads)
34{
35 return container_of(ads, struct xe_gt, uc.guc.ads);
36}
37
38static struct xe_device *
39ads_to_xe(struct xe_guc_ads *ads)
40{
41 return gt_to_xe(ads_to_gt(ads));
42}
43
44static struct iosys_map *
45ads_to_map(struct xe_guc_ads *ads)
46{
47 return &ads->bo->vmap;
48}
49
50/* UM Queue parameters: */
51#define GUC_UM_QUEUE_SIZE (SZ_64K)
52#define GUC_PAGE_RES_TIMEOUT_US (-1)
53
54/*
55 * The Additional Data Struct (ADS) has pointers for different buffers used by
56 * the GuC. One single gem object contains the ADS struct itself (guc_ads) and
57 * all the extra buffers indirectly linked via the ADS struct's entries.
58 *
59 * Layout of the ADS blob allocated for the GuC:
60 *
61 * +---------------------------------------+ <== base
62 * | guc_ads |
63 * +---------------------------------------+
64 * | guc_policies |
65 * +---------------------------------------+
66 * | guc_gt_system_info |
67 * +---------------------------------------+
68 * | guc_engine_usage |
69 * +---------------------------------------+
70 * | guc_um_init_params |
71 * +---------------------------------------+ <== static
72 * | guc_mmio_reg[countA] (engine 0.0) |
73 * | guc_mmio_reg[countB] (engine 0.1) |
74 * | guc_mmio_reg[countC] (engine 1.0) |
75 * | ... |
76 * +---------------------------------------+ <== dynamic
77 * | padding |
78 * +---------------------------------------+ <== 4K aligned
79 * | golden contexts |
80 * +---------------------------------------+
81 * | padding |
82 * +---------------------------------------+ <== 4K aligned
83 * | capture lists |
84 * +---------------------------------------+
85 * | padding |
86 * +---------------------------------------+ <== 4K aligned
87 * | UM queues |
88 * +---------------------------------------+
89 * | padding |
90 * +---------------------------------------+ <== 4K aligned
91 * | private data |
92 * +---------------------------------------+
93 * | padding |
94 * +---------------------------------------+ <== 4K aligned
95 */
96struct __guc_ads_blob {
97 struct guc_ads ads;
98 struct guc_policies policies;
99 struct guc_gt_system_info system_info;
100 struct guc_engine_usage engine_usage;
101 struct guc_um_init_params um_init_params;
102 /* From here on, location is dynamic! Refer to above diagram. */
103 struct guc_mmio_reg regset[0];
104} __packed;
105
106#define ads_blob_read(ads_, field_) \
107 xe_map_rd_field(ads_to_xe(ads_), ads_to_map(ads_), 0, \
108 struct __guc_ads_blob, field_)
109
110#define ads_blob_write(ads_, field_, val_) \
111 xe_map_wr_field(ads_to_xe(ads_), ads_to_map(ads_), 0, \
112 struct __guc_ads_blob, field_, val_)
113
114#define info_map_write(xe_, map_, field_, val_) \
115 xe_map_wr_field(xe_, map_, 0, struct guc_gt_system_info, field_, val_)
116
117#define info_map_read(xe_, map_, field_) \
118 xe_map_rd_field(xe_, map_, 0, struct guc_gt_system_info, field_)
119
120static size_t guc_ads_regset_size(struct xe_guc_ads *ads)
121{
c73acc1e
FD		 122 struct xe_device *xe = ads_to_xe(ads);
123
124 xe_assert(xe, ads->regset_size);
dd08ebf6
MB		 125
126 return ads->regset_size;
127}
128
129static size_t guc_ads_golden_lrc_size(struct xe_guc_ads *ads)
130{
131 return PAGE_ALIGN(ads->golden_lrc_size);
132}
133
134static size_t guc_ads_capture_size(struct xe_guc_ads *ads)
135{
136 /* FIXME: Allocate a proper capture list */
137 return PAGE_ALIGN(PAGE_SIZE);
138}
139
140static size_t guc_ads_um_queues_size(struct xe_guc_ads *ads)
141{
142 struct xe_device *xe = ads_to_xe(ads);
143
5a92da34 144 if (!xe->info.has_usm)
dd08ebf6
MB		 145 return 0;
146
147 return GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX;
148}
149
150static size_t guc_ads_private_data_size(struct xe_guc_ads *ads)
151{
152 return PAGE_ALIGN(ads_to_guc(ads)->fw.private_data_size);
153}
154
155static size_t guc_ads_regset_offset(struct xe_guc_ads *ads)
156{
157 return offsetof(struct __guc_ads_blob, regset);
158}
159
160static size_t guc_ads_golden_lrc_offset(struct xe_guc_ads *ads)
161{
162 size_t offset;
163
164 offset = guc_ads_regset_offset(ads) +
165 guc_ads_regset_size(ads);
166
167 return PAGE_ALIGN(offset);
168}
169
170static size_t guc_ads_capture_offset(struct xe_guc_ads *ads)
171{
172 size_t offset;
173
174 offset = guc_ads_golden_lrc_offset(ads) +
175 guc_ads_golden_lrc_size(ads);
176
177 return PAGE_ALIGN(offset);
178}
179
180static size_t guc_ads_um_queues_offset(struct xe_guc_ads *ads)
181{
182 u32 offset;
183
184 offset = guc_ads_capture_offset(ads) +
185 guc_ads_capture_size(ads);
186
187 return PAGE_ALIGN(offset);
188}
189
190static size_t guc_ads_private_data_offset(struct xe_guc_ads *ads)
191{
192 size_t offset;
193
194 offset = guc_ads_um_queues_offset(ads) +
195 guc_ads_um_queues_size(ads);
196
197 return PAGE_ALIGN(offset);
198}
199
200static size_t guc_ads_size(struct xe_guc_ads *ads)
201{
202 return guc_ads_private_data_offset(ads) +
203 guc_ads_private_data_size(ads);
204}
205
f659ac15
MR		 206static bool needs_wa_1607983814(struct xe_device *xe)
207{
208 return GRAPHICS_VERx100(xe) < 1250;
209}
210
dd08ebf6
MB		 211static size_t calculate_regset_size(struct xe_gt *gt)
212{
213 struct xe_reg_sr_entry *sr_entry;
214 unsigned long sr_idx;
215 struct xe_hw_engine *hwe;
216 enum xe_hw_engine_id id;
217 unsigned int count = 0;
218
219 for_each_hw_engine(hwe, gt, id)
220 xa_for_each(&hwe->reg_sr.xa, sr_idx, sr_entry)
221 count++;
222
f659ac15
MR		 223 count += ADS_REGSET_EXTRA_MAX * XE_NUM_HW_ENGINES;
224
225 if (needs_wa_1607983814(gt_to_xe(gt)))
226 count += LNCFCMOCS_REG_COUNT;
dd08ebf6
MB		 227
228 return count * sizeof(struct guc_mmio_reg);
229}
230
231static u32 engine_enable_mask(struct xe_gt *gt, enum xe_engine_class class)
232{
233 struct xe_hw_engine *hwe;
234 enum xe_hw_engine_id id;
235 u32 mask = 0;
236
237 for_each_hw_engine(hwe, gt, id)
238 if (hwe->class == class)
239 mask |= BIT(hwe->instance);
240
241 return mask;
242}
243
244static size_t calculate_golden_lrc_size(struct xe_guc_ads *ads)
245{
246 struct xe_device *xe = ads_to_xe(ads);
247 struct xe_gt *gt = ads_to_gt(ads);
248 size_t total_size = 0, alloc_size, real_size;
249 int class;
250
251 for (class = 0; class < XE_ENGINE_CLASS_MAX; ++class) {
dd08ebf6
MB		 252 if (!engine_enable_mask(gt, class))
253 continue;
254
255 real_size = xe_lrc_size(xe, class);
256 alloc_size = PAGE_ALIGN(real_size);
257 total_size += alloc_size;
258 }
259
260 return total_size;
261}
262
263#define MAX_GOLDEN_LRC_SIZE (SZ_4K * 64)
264
265int xe_guc_ads_init(struct xe_guc_ads *ads)
266{
267 struct xe_device *xe = ads_to_xe(ads);
268 struct xe_gt *gt = ads_to_gt(ads);
876611c2 269 struct xe_tile *tile = gt_to_tile(gt);
dd08ebf6 270 struct xe_bo *bo;
dd08ebf6
MB		 271
272 ads->golden_lrc_size = calculate_golden_lrc_size(ads);
273 ads->regset_size = calculate_regset_size(gt);
274
0e1a47fc 275 bo = xe_managed_bo_create_pin_map(xe, tile, guc_ads_size(ads) + MAX_GOLDEN_LRC_SIZE,
a44bbace 276 XE_BO_CREATE_SYSTEM_BIT |
0e1a47fc 277 XE_BO_CREATE_GGTT_BIT);
dd08ebf6
MB		 278 if (IS_ERR(bo))
279 return PTR_ERR(bo);
280
281 ads->bo = bo;
282
dd08ebf6
MB		 283 return 0;
284}
285
286/**
287 * xe_guc_ads_init_post_hwconfig - initialize ADS post hwconfig load
288 * @ads: Additional data structures object
289 *
290 * Recalcuate golden_lrc_size & regset_size as the number hardware engines may
291 * have changed after the hwconfig was loaded. Also verify the new sizes fit in
292 * the already allocated ADS buffer object.
293 *
294 * Return: 0 on success, negative error code on error.
295 */
296int xe_guc_ads_init_post_hwconfig(struct xe_guc_ads *ads)
297{
298 struct xe_gt *gt = ads_to_gt(ads);
299 u32 prev_regset_size = ads->regset_size;
300
c73acc1e 301 xe_gt_assert(gt, ads->bo);
dd08ebf6
MB		 302
303 ads->golden_lrc_size = calculate_golden_lrc_size(ads);
304 ads->regset_size = calculate_regset_size(gt);
305
c73acc1e
FD		 306 xe_gt_assert(gt, ads->golden_lrc_size +
307 (ads->regset_size - prev_regset_size) <=
308 MAX_GOLDEN_LRC_SIZE);
dd08ebf6
MB		 309
310 return 0;
311}
312
313static void guc_policies_init(struct xe_guc_ads *ads)
314{
315 ads_blob_write(ads, policies.dpc_promote_time,
316 GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US);
317 ads_blob_write(ads, policies.max_num_work_items,
318 GLOBAL_POLICY_MAX_NUM_WI);
319 ads_blob_write(ads, policies.global_flags, 0);
320 ads_blob_write(ads, policies.is_valid, 1);
321}
322
323static void fill_engine_enable_masks(struct xe_gt *gt,
324 struct iosys_map *info_map)
325{
326 struct xe_device *xe = gt_to_xe(gt);
327
328 info_map_write(xe, info_map, engine_enabled_masks[GUC_RENDER_CLASS],
329 engine_enable_mask(gt, XE_ENGINE_CLASS_RENDER));
330 info_map_write(xe, info_map, engine_enabled_masks[GUC_BLITTER_CLASS],
331 engine_enable_mask(gt, XE_ENGINE_CLASS_COPY));
332 info_map_write(xe, info_map, engine_enabled_masks[GUC_VIDEO_CLASS],
333 engine_enable_mask(gt, XE_ENGINE_CLASS_VIDEO_DECODE));
334 info_map_write(xe, info_map,
335 engine_enabled_masks[GUC_VIDEOENHANCE_CLASS],
336 engine_enable_mask(gt, XE_ENGINE_CLASS_VIDEO_ENHANCE));
337 info_map_write(xe, info_map, engine_enabled_masks[GUC_COMPUTE_CLASS],
338 engine_enable_mask(gt, XE_ENGINE_CLASS_COMPUTE));
29654910
DCS		 339 info_map_write(xe, info_map, engine_enabled_masks[GUC_GSC_OTHER_CLASS],
340 engine_enable_mask(gt, XE_ENGINE_CLASS_OTHER));
dd08ebf6
MB		 341}
342
343static void guc_prep_golden_lrc_null(struct xe_guc_ads *ads)
344{
345 struct xe_device *xe = ads_to_xe(ads);
346 struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads),
347 offsetof(struct __guc_ads_blob, system_info));
348 u8 guc_class;
349
350 for (guc_class = 0; guc_class <= GUC_MAX_ENGINE_CLASSES; ++guc_class) {
351 if (!info_map_read(xe, &info_map,
352 engine_enabled_masks[guc_class]))
353 continue;
354
355 ads_blob_write(ads, ads.eng_state_size[guc_class],
356 guc_ads_golden_lrc_size(ads) -
357 xe_lrc_skip_size(xe));
358 ads_blob_write(ads, ads.golden_context_lrca[guc_class],
359 xe_bo_ggtt_addr(ads->bo) +
360 guc_ads_golden_lrc_offset(ads));
361 }
362}
363
364static void guc_mapping_table_init_invalid(struct xe_gt *gt,
365 struct iosys_map *info_map)
366{
367 struct xe_device *xe = gt_to_xe(gt);
368 unsigned int i, j;
369
370 /* Table must be set to invalid values for entries not used */
371 for (i = 0; i < GUC_MAX_ENGINE_CLASSES; ++i)
372 for (j = 0; j < GUC_MAX_INSTANCES_PER_CLASS; ++j)
373 info_map_write(xe, info_map, mapping_table[i][j],
374 GUC_MAX_INSTANCES_PER_CLASS);
375}
376
377static void guc_mapping_table_init(struct xe_gt *gt,
378 struct iosys_map *info_map)
379{
380 struct xe_device *xe = gt_to_xe(gt);
381 struct xe_hw_engine *hwe;
382 enum xe_hw_engine_id id;
383
384 guc_mapping_table_init_invalid(gt, info_map);
385
386 for_each_hw_engine(hwe, gt, id) {
387 u8 guc_class;
388
389 guc_class = xe_engine_class_to_guc_class(hwe->class);
390 info_map_write(xe, info_map,
391 mapping_table[guc_class][hwe->logical_instance],
392 hwe->instance);
393 }
394}
395
396static void guc_capture_list_init(struct xe_guc_ads *ads)
397{
398 int i, j;
399 u32 addr = xe_bo_ggtt_addr(ads->bo) + guc_ads_capture_offset(ads);
400
401 /* FIXME: Populate a proper capture list */
402 for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; i++) {
403 for (j = 0; j < GUC_MAX_ENGINE_CLASSES; j++) {
404 ads_blob_write(ads, ads.capture_instance[i][j], addr);
405 ads_blob_write(ads, ads.capture_class[i][j], addr);
406 }
407
408 ads_blob_write(ads, ads.capture_global[i], addr);
409 }
410}
411
412static void guc_mmio_regset_write_one(struct xe_guc_ads *ads,
413 struct iosys_map *regset_map,
98ce59e9 414 struct xe_reg reg,
dd08ebf6
MB		 415 unsigned int n_entry)
416{
417 struct guc_mmio_reg entry = {
ee21379a 418 .offset = reg.addr,
98ce59e9 419 .flags = reg.masked ? GUC_REGSET_MASKED : 0,
dd08ebf6
MB		 420 };
421
422 xe_map_memcpy_to(ads_to_xe(ads), regset_map, n_entry * sizeof(entry),
423 &entry, sizeof(entry));
424}
425
426static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads,
427 struct iosys_map *regset_map,
428 struct xe_hw_engine *hwe)
429{
f659ac15 430 struct xe_device *xe = ads_to_xe(ads);
dd08ebf6
MB		 431 struct xe_hw_engine *hwe_rcs_reset_domain =
432 xe_gt_any_hw_engine_by_reset_domain(hwe->gt, XE_ENGINE_CLASS_RENDER);
433 struct xe_reg_sr_entry *entry;
434 unsigned long idx;
3e8e7ee6 435 unsigned int count = 0;
dd08ebf6 436 const struct {
98ce59e9 437 struct xe_reg reg;
dd08ebf6
MB		 438 bool skip;
439 } *e, extra_regs[] = {
98ce59e9
LDM		 440 { .reg = RING_MODE(hwe->mmio_base), },
441 { .reg = RING_HWS_PGA(hwe->mmio_base), },
442 { .reg = RING_IMR(hwe->mmio_base), },
443 { .reg = RCU_MODE, .skip = hwe != hwe_rcs_reset_domain },
0d97ecce
NV		 444 { .reg = CCS_MODE,
445 .skip = hwe != hwe_rcs_reset_domain || !xe_gt_ccs_mode_enabled(hwe->gt) },
dd08ebf6
MB		 446 };
447 u32 i;
448
449 BUILD_BUG_ON(ARRAY_SIZE(extra_regs) > ADS_REGSET_EXTRA_MAX);
450
98ce59e9
LDM		 451 xa_for_each(&hwe->reg_sr.xa, idx, entry)
452 guc_mmio_regset_write_one(ads, regset_map, entry->reg, count++);
dd08ebf6
MB		 453
454 for (e = extra_regs; e < extra_regs + ARRAY_SIZE(extra_regs); e++) {
455 if (e->skip)
456 continue;
457
98ce59e9 458 guc_mmio_regset_write_one(ads, regset_map, e->reg, count++);
dd08ebf6
MB		 459 }
460
f659ac15
MR		 461 /* Wa_1607983814 */
462 if (needs_wa_1607983814(xe) && hwe->class == XE_ENGINE_CLASS_RENDER) {
463 for (i = 0; i < LNCFCMOCS_REG_COUNT; i++) {
464 guc_mmio_regset_write_one(ads, regset_map,
83af834e 465 XELP_LNCFCMOCS(i), count++);
f659ac15 466 }
dd08ebf6
MB		 467 }
468
dd08ebf6
MB		 469 return count;
470}
471
472static void guc_mmio_reg_state_init(struct xe_guc_ads *ads)
473{
474 size_t regset_offset = guc_ads_regset_offset(ads);
475 struct xe_gt *gt = ads_to_gt(ads);
476 struct xe_hw_engine *hwe;
477 enum xe_hw_engine_id id;
478 u32 addr = xe_bo_ggtt_addr(ads->bo) + regset_offset;
479 struct iosys_map regset_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads),
480 regset_offset);
39fd0b45 481 unsigned int regset_used = 0;
dd08ebf6
MB		 482
483 for_each_hw_engine(hwe, gt, id) {
484 unsigned int count;
485 u8 gc;
486
487 /*
9b9529ce 488 * 1. Write all MMIO entries for this exec queue to the table. No
dd08ebf6
MB		 489 * need to worry about fused-off engines and when there are
490 * entries in the regset: the reg_state_list has been zero'ed
491 * by xe_guc_ads_populate()
492 */
493 count = guc_mmio_regset_write(ads, &regset_map, hwe);
494 if (!count)
495 continue;
496
497 /*
498 * 2. Record in the header (ads.reg_state_list) the address
499 * location and number of entries
500 */
501 gc = xe_engine_class_to_guc_class(hwe->class);
502 ads_blob_write(ads, ads.reg_state_list[gc][hwe->instance].address, addr);
503 ads_blob_write(ads, ads.reg_state_list[gc][hwe->instance].count, count);
504
505 addr += count * sizeof(struct guc_mmio_reg);
506 iosys_map_incr(&regset_map, count * sizeof(struct guc_mmio_reg));
39fd0b45
MR		 507
508 regset_used += count * sizeof(struct guc_mmio_reg);
dd08ebf6 509 }
39fd0b45 510
c73acc1e 511 xe_gt_assert(gt, regset_used <= ads->regset_size);
dd08ebf6
MB		 512}
513
514static void guc_um_init_params(struct xe_guc_ads *ads)
515{
516 u32 um_queue_offset = guc_ads_um_queues_offset(ads);
517 u64 base_dpa;
518 u32 base_ggtt;
519 int i;
520
521 base_ggtt = xe_bo_ggtt_addr(ads->bo) + um_queue_offset;
522 base_dpa = xe_bo_main_addr(ads->bo, PAGE_SIZE) + um_queue_offset;
523
524 for (i = 0; i < GUC_UM_HW_QUEUE_MAX; ++i) {
525 ads_blob_write(ads, um_init_params.queue_params[i].base_dpa,
526 base_dpa + (i * GUC_UM_QUEUE_SIZE));
527 ads_blob_write(ads, um_init_params.queue_params[i].base_ggtt_address,
528 base_ggtt + (i * GUC_UM_QUEUE_SIZE));
529 ads_blob_write(ads, um_init_params.queue_params[i].size_in_bytes,
530 GUC_UM_QUEUE_SIZE);
531 }
532
533 ads_blob_write(ads, um_init_params.page_response_timeout_in_us,
534 GUC_PAGE_RES_TIMEOUT_US);
535}
536
537static void guc_doorbell_init(struct xe_guc_ads *ads)
538{
539 struct xe_device *xe = ads_to_xe(ads);
540 struct xe_gt *gt = ads_to_gt(ads);
541
542 if (GRAPHICS_VER(xe) >= 12 && !IS_DGFX(xe)) {
543 u32 distdbreg =
ce8bf5bd 544 xe_mmio_read32(gt, DIST_DBS_POPULATED);
dd08ebf6
MB		 545
546 ads_blob_write(ads,
547 system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI],
d9b79ad2 548 REG_FIELD_GET(DOORBELLS_PER_SQIDI_MASK, distdbreg) + 1);
dd08ebf6
MB		 549 }
550}
551
552/**
553 * xe_guc_ads_populate_minimal - populate minimal ADS
554 * @ads: Additional data structures object
555 *
556 * This function populates a minimal ADS that does not support submissions but
557 * enough so the GuC can load and the hwconfig table can be read.
558 */
559void xe_guc_ads_populate_minimal(struct xe_guc_ads *ads)
560{
561 struct xe_gt *gt = ads_to_gt(ads);
562 struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads),
563 offsetof(struct __guc_ads_blob, system_info));
564 u32 base = xe_bo_ggtt_addr(ads->bo);
565
c73acc1e 566 xe_gt_assert(gt, ads->bo);
dd08ebf6
MB		 567
568 xe_map_memset(ads_to_xe(ads), ads_to_map(ads), 0, 0, ads->bo->size);
569 guc_policies_init(ads);
570 guc_prep_golden_lrc_null(ads);
571 guc_mapping_table_init_invalid(gt, &info_map);
572 guc_doorbell_init(ads);
573
574 ads_blob_write(ads, ads.scheduler_policies, base +
575 offsetof(struct __guc_ads_blob, policies));
576 ads_blob_write(ads, ads.gt_system_info, base +
577 offsetof(struct __guc_ads_blob, system_info));
578 ads_blob_write(ads, ads.private_data, base +
579 guc_ads_private_data_offset(ads));
580}
581
582void xe_guc_ads_populate(struct xe_guc_ads *ads)
583{
584 struct xe_device *xe = ads_to_xe(ads);
585 struct xe_gt *gt = ads_to_gt(ads);
586 struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads),
587 offsetof(struct __guc_ads_blob, system_info));
588 u32 base = xe_bo_ggtt_addr(ads->bo);
589
c73acc1e 590 xe_gt_assert(gt, ads->bo);
dd08ebf6
MB		 591
592 xe_map_memset(ads_to_xe(ads), ads_to_map(ads), 0, 0, ads->bo->size);
593 guc_policies_init(ads);
594 fill_engine_enable_masks(gt, &info_map);
595 guc_mmio_reg_state_init(ads);
596 guc_prep_golden_lrc_null(ads);
597 guc_mapping_table_init(gt, &info_map);
598 guc_capture_list_init(ads);
599 guc_doorbell_init(ads);
600
5a92da34 601 if (xe->info.has_usm) {
dd08ebf6
MB		 602 guc_um_init_params(ads);
603 ads_blob_write(ads, ads.um_init_data, base +
604 offsetof(struct __guc_ads_blob, um_init_params));
605 }
606
607 ads_blob_write(ads, ads.scheduler_policies, base +
608 offsetof(struct __guc_ads_blob, policies));
609 ads_blob_write(ads, ads.gt_system_info, base +
610 offsetof(struct __guc_ads_blob, system_info));
611 ads_blob_write(ads, ads.private_data, base +
612 guc_ads_private_data_offset(ads));
613}
614
615static void guc_populate_golden_lrc(struct xe_guc_ads *ads)
616{
617 struct xe_device *xe = ads_to_xe(ads);
618 struct xe_gt *gt = ads_to_gt(ads);
619 struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads),
620 offsetof(struct __guc_ads_blob, system_info));
621 size_t total_size = 0, alloc_size, real_size;
622 u32 addr_ggtt, offset;
623 int class;
624
625 offset = guc_ads_golden_lrc_offset(ads);
626 addr_ggtt = xe_bo_ggtt_addr(ads->bo) + offset;
627
628 for (class = 0; class < XE_ENGINE_CLASS_MAX; ++class) {
629 u8 guc_class;
630
dd08ebf6
MB		 631 guc_class = xe_engine_class_to_guc_class(class);
632
633 if (!info_map_read(xe, &info_map,
634 engine_enabled_masks[guc_class]))
635 continue;
636
c73acc1e 637 xe_gt_assert(gt, gt->default_lrc[class]);
dd08ebf6
MB		 638
639 real_size = xe_lrc_size(xe, class);
640 alloc_size = PAGE_ALIGN(real_size);
641 total_size += alloc_size;
642
643 /*
644 * This interface is slightly confusing. We need to pass the
645 * base address of the full golden context and the size of just
646 * the engine state, which is the section of the context image
647 * that starts after the execlists LRC registers. This is
648 * required to allow the GuC to restore just the engine state
649 * when a watchdog reset occurs.
650 * We calculate the engine state size by removing the size of
651 * what comes before it in the context image (which is identical
652 * on all engines).
653 */
654 ads_blob_write(ads, ads.eng_state_size[guc_class],
655 real_size - xe_lrc_skip_size(xe));
656 ads_blob_write(ads, ads.golden_context_lrca[guc_class],
657 addr_ggtt);
658
659 xe_map_memcpy_to(xe, ads_to_map(ads), offset,
660 gt->default_lrc[class], real_size);
661
662 addr_ggtt += alloc_size;
663 offset += alloc_size;
664 }
665
c73acc1e 666 xe_gt_assert(gt, total_size == ads->golden_lrc_size);
dd08ebf6
MB		 667}
668
669void xe_guc_ads_populate_post_load(struct xe_guc_ads *ads)
670{
671 guc_populate_golden_lrc(ads);
672}
Linux 6.x block layer and io_uring tree(s)