projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 0d97ecce NV |
1 | // SPDX-License-Identifier: MIT |
| 2 | /* | |
| 3 | * Copyright © 2023 Intel Corporation | |
| 4 | */ | |
| 5 | ||
| 6 | #include "regs/xe_gt_regs.h" | |
| 7 | #include "xe_assert.h" | |
| 8 | #include "xe_gt.h" | |
| 9 | #include "xe_gt_ccs_mode.h" | |
| 10 | #include "xe_mmio.h" | |
| 11 | ||
| 12 | static void __xe_gt_apply_ccs_mode(struct xe_gt *gt, u32 num_engines) | |
| 13 | { | |
| 14 | u32 mode = CCS_MODE_CSLICE_0_3_MASK; /* disable all by default */ | |
| 15 | int num_slices = hweight32(CCS_MASK(gt)); | |
| 16 | struct xe_device *xe = gt_to_xe(gt); | |
| 17 | int width, cslice = 0; | |
| 18 | u32 config = 0; | |
| 19 | ||
| 20 | xe_assert(xe, xe_gt_ccs_mode_enabled(gt)); | |
| 21 | ||
| 22 | xe_assert(xe, num_engines && num_engines <= num_slices); | |
| 23 | xe_assert(xe, !(num_slices % num_engines)); | |
| 24 | ||
| 25 | /* | |
| 26 | * Loop over all available slices and assign each a user engine. | |
| 27 | * For example, if there are four compute slices available, the | |
| 28 | * assignment of compute slices to compute engines would be, | |
| 29 | * | |
| 30 | * With 1 engine (ccs0): | |
| 31 | * slice 0, 1, 2, 3: ccs0 | |
| 32 | * | |
| 33 | * With 2 engines (ccs0, ccs1): | |
| 34 | * slice 0, 2: ccs0 | |
| 35 | * slice 1, 3: ccs1 | |
| 36 | * | |
| 37 | * With 4 engines (ccs0, ccs1, ccs2, ccs3): | |
| 38 | * slice 0: ccs0 | |
| 39 | * slice 1: ccs1 | |
| 40 | * slice 2: ccs2 | |
| 41 | * slice 3: ccs3 | |
| 42 | */ | |
| 43 | for (width = num_slices / num_engines; width; width--) { | |
| 44 | struct xe_hw_engine *hwe; | |
| 45 | enum xe_hw_engine_id id; | |
| 46 | ||
| 47 | for_each_hw_engine(hwe, gt, id) { | |
| 48 | if (hwe->class != XE_ENGINE_CLASS_COMPUTE) | |
| 49 | continue; | |
| 50 | ||
| 51 | if (hwe->logical_instance >= num_engines) | |
| 52 | break; | |
| 53 | ||
| 54 | config |= BIT(hwe->instance) << XE_HW_ENGINE_CCS0; | |
| 55 | ||
| 56 | /* If a slice is fused off, leave disabled */ | |
| 57 | while ((CCS_MASK(gt) & BIT(cslice)) == 0) | |
| 58 | cslice++; | |
| 59 | ||
| 60 | mode &= ~CCS_MODE_CSLICE(cslice, CCS_MODE_CSLICE_MASK); | |
| 61 | mode |= CCS_MODE_CSLICE(cslice, hwe->instance); | |
| 62 | cslice++; | |
| 63 | } | |
| 64 | } | |
| 65 | ||
| 66 | xe_mmio_write32(gt, CCS_MODE, mode); | |
| 67 | ||
| 68 | xe_gt_info(gt, "CCS_MODE=%x config:%08x, num_engines:%d, num_slices:%d\n", | |
| 69 | mode, config, num_engines, num_slices); | |
| 70 | } | |
| 71 | ||
| 72 | void xe_gt_apply_ccs_mode(struct xe_gt *gt) | |
| 73 | { | |
| 74 | if (!gt->ccs_mode) | |
| 75 | return; | |
| 76 | ||
| 77 | __xe_gt_apply_ccs_mode(gt, gt->ccs_mode); | |
| 78 | } |