Merge tag 'irqchip-fixes-5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / gpu / drm / vmwgfx / vmwgfx_scrn.c
CommitLineData
dff96888 1// SPDX-License-Identifier: GPL-2.0 OR MIT
56d1c78d
JB
2/**************************************************************************
3 *
dff96888 4 * Copyright 2011-2015 VMware, Inc., Palo Alto, CA., USA
56d1c78d
JB
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
d7721ca7
SY
28#include <drm/drm_atomic.h>
29#include <drm/drm_atomic_helper.h>
61c21387 30#include <drm/drm_damage_helper.h>
d5c1f011
SR
31#include <drm/drm_fourcc.h>
32#include <drm/drm_plane_helper.h>
33#include <drm/drm_vblank.h>
56d1c78d 34
d5c1f011 35#include "vmwgfx_kms.h"
56d1c78d
JB
36
37#define vmw_crtc_to_sou(x) \
38 container_of(x, struct vmw_screen_object_unit, base.crtc)
39#define vmw_encoder_to_sou(x) \
40 container_of(x, struct vmw_screen_object_unit, base.encoder)
41#define vmw_connector_to_sou(x) \
42 container_of(x, struct vmw_screen_object_unit, base.connector)
43
10b1e0ca
TH
44/**
45 * struct vmw_kms_sou_surface_dirty - Closure structure for
46 * blit surface to screen command.
47 * @base: The base type we derive from. Used by vmw_kms_helper_dirty().
48 * @left: Left side of bounding box.
49 * @right: Right side of bounding box.
50 * @top: Top side of bounding box.
51 * @bottom: Bottom side of bounding box.
52 * @dst_x: Difference between source clip rects and framebuffer coordinates.
53 * @dst_y: Difference between source clip rects and framebuffer coordinates.
54 * @sid: Surface id of surface to copy from.
55 */
56struct vmw_kms_sou_surface_dirty {
57 struct vmw_kms_dirty base;
58 s32 left, right, top, bottom;
59 s32 dst_x, dst_y;
60 u32 sid;
61};
62
63/*
64 * SVGA commands that are used by this code. Please see the device headers
65 * for explanation.
66 */
67struct vmw_kms_sou_readback_blit {
68 uint32 header;
69 SVGAFifoCmdBlitScreenToGMRFB body;
70};
71
f1d34bfd 72struct vmw_kms_sou_bo_blit {
10b1e0ca
TH
73 uint32 header;
74 SVGAFifoCmdBlitGMRFBToScreen body;
75};
76
77struct vmw_kms_sou_dirty_cmd {
78 SVGA3dCmdHeader header;
79 SVGA3dCmdBlitSurfaceToScreen body;
80};
81
5d35abad
DR
82struct vmw_kms_sou_define_gmrfb {
83 uint32_t header;
84 SVGAFifoCmdDefineGMRFB body;
85};
86
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JB
87/**
88 * Display unit using screen objects.
89 */
90struct vmw_screen_object_unit {
91 struct vmw_display_unit base;
92
93 unsigned long buffer_size; /**< Size of allocated buffer */
f1d34bfd 94 struct vmw_buffer_object *buffer; /**< Backing store buffer */
56d1c78d
JB
95
96 bool defined;
56d1c78d
JB
97};
98
99static void vmw_sou_destroy(struct vmw_screen_object_unit *sou)
100{
c8261a96 101 vmw_du_cleanup(&sou->base);
56d1c78d
JB
102 kfree(sou);
103}
104
105
106/*
107 * Screen Object Display Unit CRTC functions
108 */
109
110static void vmw_sou_crtc_destroy(struct drm_crtc *crtc)
111{
112 vmw_sou_destroy(vmw_crtc_to_sou(crtc));
113}
114
56d1c78d
JB
115/**
116 * Send the fifo command to create a screen.
117 */
118static int vmw_sou_fifo_create(struct vmw_private *dev_priv,
119 struct vmw_screen_object_unit *sou,
3e79ecda 120 int x, int y,
56d1c78d
JB
121 struct drm_display_mode *mode)
122{
123 size_t fifo_size;
124
125 struct {
126 struct {
127 uint32_t cmdType;
128 } header;
129 SVGAScreenObject obj;
130 } *cmd;
131
132 BUG_ON(!sou->buffer);
133
134 fifo_size = sizeof(*cmd);
11c45419
DR
135 cmd = VMW_FIFO_RESERVE(dev_priv, fifo_size);
136 if (unlikely(cmd == NULL))
56d1c78d 137 return -ENOMEM;
56d1c78d
JB
138
139 memset(cmd, 0, fifo_size);
140 cmd->header.cmdType = SVGA_CMD_DEFINE_SCREEN;
141 cmd->obj.structSize = sizeof(SVGAScreenObject);
142 cmd->obj.id = sou->base.unit;
143 cmd->obj.flags = SVGA_SCREEN_HAS_ROOT |
144 (sou->base.unit == 0 ? SVGA_SCREEN_IS_PRIMARY : 0);
145 cmd->obj.size.width = mode->hdisplay;
146 cmd->obj.size.height = mode->vdisplay;
3e79ecda
DR
147 cmd->obj.root.x = x;
148 cmd->obj.root.y = y;
6dd687b4
TH
149 sou->base.set_gui_x = cmd->obj.root.x;
150 sou->base.set_gui_y = cmd->obj.root.y;
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JB
151
152 /* Ok to assume that buffer is pinned in vram */
b37a6b9a 153 vmw_bo_get_guest_ptr(&sou->buffer->base, &cmd->obj.backingStore.ptr);
56d1c78d
JB
154 cmd->obj.backingStore.pitch = mode->hdisplay * 4;
155
156 vmw_fifo_commit(dev_priv, fifo_size);
157
158 sou->defined = true;
159
160 return 0;
161}
162
163/**
164 * Send the fifo command to destroy a screen.
165 */
166static int vmw_sou_fifo_destroy(struct vmw_private *dev_priv,
167 struct vmw_screen_object_unit *sou)
168{
169 size_t fifo_size;
170 int ret;
171
172 struct {
173 struct {
174 uint32_t cmdType;
175 } header;
176 SVGAFifoCmdDestroyScreen body;
177 } *cmd;
178
179 /* no need to do anything */
180 if (unlikely(!sou->defined))
181 return 0;
182
183 fifo_size = sizeof(*cmd);
11c45419
DR
184 cmd = VMW_FIFO_RESERVE(dev_priv, fifo_size);
185 if (unlikely(cmd == NULL))
56d1c78d 186 return -ENOMEM;
56d1c78d
JB
187
188 memset(cmd, 0, fifo_size);
189 cmd->header.cmdType = SVGA_CMD_DESTROY_SCREEN;
190 cmd->body.screenId = sou->base.unit;
191
192 vmw_fifo_commit(dev_priv, fifo_size);
193
194 /* Force sync */
195 ret = vmw_fallback_wait(dev_priv, false, true, 0, false, 3*HZ);
196 if (unlikely(ret != 0))
197 DRM_ERROR("Failed to sync with HW");
198 else
199 sou->defined = false;
200
201 return ret;
202}
203
06ec4190
SY
204/**
205 * vmw_sou_crtc_mode_set_nofb - Create new screen
206 *
207 * @crtc: CRTC associated with the new screen
208 *
209 * This function creates/destroys a screen. This function cannot fail, so if
210 * somehow we run into a failure, just do the best we can to get out.
211 */
212static void vmw_sou_crtc_mode_set_nofb(struct drm_crtc *crtc)
213{
214 struct vmw_private *dev_priv;
215 struct vmw_screen_object_unit *sou;
216 struct vmw_framebuffer *vfb;
217 struct drm_framebuffer *fb;
218 struct drm_plane_state *ps;
219 struct vmw_plane_state *vps;
220 int ret;
221
3e79ecda 222 sou = vmw_crtc_to_sou(crtc);
06ec4190 223 dev_priv = vmw_priv(crtc->dev);
3e79ecda
DR
224 ps = crtc->primary->state;
225 fb = ps->fb;
226 vps = vmw_plane_state_to_vps(ps);
06ec4190
SY
227
228 vfb = (fb) ? vmw_framebuffer_to_vfb(fb) : NULL;
229
230 if (sou->defined) {
231 ret = vmw_sou_fifo_destroy(dev_priv, sou);
232 if (ret) {
233 DRM_ERROR("Failed to destroy Screen Object\n");
234 return;
235 }
236 }
237
238 if (vfb) {
3e79ecda
DR
239 struct drm_connector_state *conn_state;
240 struct vmw_connector_state *vmw_conn_state;
241 int x, y;
242
f1d34bfd
TH
243 sou->buffer = vps->bo;
244 sou->buffer_size = vps->bo_size;
06ec4190 245
9d9486e4
TH
246 conn_state = sou->base.connector.state;
247 vmw_conn_state = vmw_connector_state_to_vcs(conn_state);
248
249 x = vmw_conn_state->gui_x;
250 y = vmw_conn_state->gui_y;
06ec4190 251
3e79ecda 252 ret = vmw_sou_fifo_create(dev_priv, sou, x, y, &crtc->mode);
06ec4190
SY
253 if (ret)
254 DRM_ERROR("Failed to define Screen Object %dx%d\n",
255 crtc->x, crtc->y);
256
06ec4190
SY
257 } else {
258 sou->buffer = NULL;
259 sou->buffer_size = 0;
06ec4190
SY
260 }
261}
262
263/**
264 * vmw_sou_crtc_helper_prepare - Noop
265 *
266 * @crtc: CRTC associated with the new screen
267 *
268 * Prepares the CRTC for a mode set, but we don't need to do anything here.
269 */
270static void vmw_sou_crtc_helper_prepare(struct drm_crtc *crtc)
271{
272}
273
274/**
0b20a0f8 275 * vmw_sou_crtc_atomic_enable - Noop
06ec4190
SY
276 *
277 * @crtc: CRTC associated with the new screen
278 *
279 * This is called after a mode set has been completed.
280 */
0b20a0f8
LP
281static void vmw_sou_crtc_atomic_enable(struct drm_crtc *crtc,
282 struct drm_crtc_state *old_state)
06ec4190
SY
283{
284}
285
286/**
64581714 287 * vmw_sou_crtc_atomic_disable - Turns off CRTC
06ec4190
SY
288 *
289 * @crtc: CRTC to be turned off
290 */
64581714
LP
291static void vmw_sou_crtc_atomic_disable(struct drm_crtc *crtc,
292 struct drm_crtc_state *old_state)
06ec4190
SY
293{
294 struct vmw_private *dev_priv;
295 struct vmw_screen_object_unit *sou;
296 int ret;
297
298
299 if (!crtc) {
300 DRM_ERROR("CRTC is NULL\n");
301 return;
302 }
303
304 sou = vmw_crtc_to_sou(crtc);
305 dev_priv = vmw_priv(crtc->dev);
306
307 if (sou->defined) {
308 ret = vmw_sou_fifo_destroy(dev_priv, sou);
309 if (ret)
310 DRM_ERROR("Failed to destroy Screen Object\n");
311 }
312}
313
d7955fcf 314static const struct drm_crtc_funcs vmw_screen_object_crtc_funcs = {
56d1c78d
JB
315 .gamma_set = vmw_du_crtc_gamma_set,
316 .destroy = vmw_sou_crtc_destroy,
9c2542a4
SY
317 .reset = vmw_du_crtc_reset,
318 .atomic_duplicate_state = vmw_du_crtc_duplicate_state,
319 .atomic_destroy_state = vmw_du_crtc_destroy_state,
b4fa61ba 320 .set_config = drm_atomic_helper_set_config,
9a01135b 321 .page_flip = drm_atomic_helper_page_flip,
4bebe91a
TZ
322 .get_vblank_counter = vmw_get_vblank_counter,
323 .enable_vblank = vmw_enable_vblank,
324 .disable_vblank = vmw_disable_vblank,
56d1c78d
JB
325};
326
327/*
328 * Screen Object Display Unit encoder functions
329 */
330
331static void vmw_sou_encoder_destroy(struct drm_encoder *encoder)
332{
333 vmw_sou_destroy(vmw_encoder_to_sou(encoder));
334}
335
d7955fcf 336static const struct drm_encoder_funcs vmw_screen_object_encoder_funcs = {
56d1c78d
JB
337 .destroy = vmw_sou_encoder_destroy,
338};
339
340/*
341 * Screen Object Display Unit connector functions
342 */
343
344static void vmw_sou_connector_destroy(struct drm_connector *connector)
345{
346 vmw_sou_destroy(vmw_connector_to_sou(connector));
347}
348
d7955fcf 349static const struct drm_connector_funcs vmw_sou_connector_funcs = {
56d1c78d 350 .dpms = vmw_du_connector_dpms,
d17e67de
TR
351 .detect = vmw_du_connector_detect,
352 .fill_modes = vmw_du_connector_fill_modes,
56d1c78d 353 .destroy = vmw_sou_connector_destroy,
d7721ca7 354 .reset = vmw_du_connector_reset,
8a510a5c
RC
355 .atomic_duplicate_state = vmw_du_connector_duplicate_state,
356 .atomic_destroy_state = vmw_du_connector_destroy_state,
56d1c78d
JB
357};
358
d947d1b7
SY
359
360static const struct
361drm_connector_helper_funcs vmw_sou_connector_helper_funcs = {
d947d1b7
SY
362};
363
364
365
36cc79bc
SY
366/*
367 * Screen Object Display Plane Functions
368 */
369
060e2ad5
SY
370/**
371 * vmw_sou_primary_plane_cleanup_fb - Frees sou backing buffer
372 *
373 * @plane: display plane
374 * @old_state: Contains the FB to clean up
375 *
376 * Unpins the display surface
377 *
378 * Returns 0 on success
379 */
380static void
381vmw_sou_primary_plane_cleanup_fb(struct drm_plane *plane,
382 struct drm_plane_state *old_state)
383{
384 struct vmw_plane_state *vps = vmw_plane_state_to_vps(old_state);
20fb5a63
TH
385 struct drm_crtc *crtc = plane->state->crtc ?
386 plane->state->crtc : old_state->crtc;
060e2ad5 387
f1d34bfd
TH
388 if (vps->bo)
389 vmw_bo_unpin(vmw_priv(crtc->dev), vps->bo, false);
390 vmw_bo_unreference(&vps->bo);
391 vps->bo_size = 0;
060e2ad5
SY
392
393 vmw_du_plane_cleanup_fb(plane, old_state);
394}
395
396
397/**
398 * vmw_sou_primary_plane_prepare_fb - allocate backing buffer
399 *
400 * @plane: display plane
401 * @new_state: info on the new plane state, including the FB
402 *
403 * The SOU backing buffer is our equivalent of the display plane.
404 *
405 * Returns 0 on success
406 */
407static int
408vmw_sou_primary_plane_prepare_fb(struct drm_plane *plane,
409 struct drm_plane_state *new_state)
410{
411 struct drm_framebuffer *new_fb = new_state->fb;
412 struct drm_crtc *crtc = plane->state->crtc ?: new_state->crtc;
413 struct vmw_plane_state *vps = vmw_plane_state_to_vps(new_state);
414 struct vmw_private *dev_priv;
415 size_t size;
416 int ret;
417
418
419 if (!new_fb) {
f1d34bfd
TH
420 vmw_bo_unreference(&vps->bo);
421 vps->bo_size = 0;
060e2ad5
SY
422
423 return 0;
424 }
425
426 size = new_state->crtc_w * new_state->crtc_h * 4;
20fb5a63 427 dev_priv = vmw_priv(crtc->dev);
060e2ad5 428
f1d34bfd
TH
429 if (vps->bo) {
430 if (vps->bo_size == size) {
20fb5a63
TH
431 /*
432 * Note that this might temporarily up the pin-count
433 * to 2, until cleanup_fb() is called.
434 */
f1d34bfd 435 return vmw_bo_pin_in_vram(dev_priv, vps->bo,
20fb5a63
TH
436 true);
437 }
060e2ad5 438
f1d34bfd
TH
439 vmw_bo_unreference(&vps->bo);
440 vps->bo_size = 0;
060e2ad5
SY
441 }
442
f1d34bfd
TH
443 vps->bo = kzalloc(sizeof(*vps->bo), GFP_KERNEL);
444 if (!vps->bo)
060e2ad5
SY
445 return -ENOMEM;
446
060e2ad5
SY
447 vmw_svga_enable(dev_priv);
448
449 /* After we have alloced the backing store might not be able to
450 * resume the overlays, this is preferred to failing to alloc.
451 */
452 vmw_overlay_pause_all(dev_priv);
f1d34bfd 453 ret = vmw_bo_init(dev_priv, vps->bo, size,
060e2ad5 454 &vmw_vram_ne_placement,
f1d34bfd 455 false, &vmw_bo_bo_free);
060e2ad5 456 vmw_overlay_resume_all(dev_priv);
20fb5a63 457 if (ret) {
f1d34bfd 458 vps->bo = NULL; /* vmw_bo_init frees on error */
20fb5a63
TH
459 return ret;
460 }
060e2ad5 461
f1d34bfd 462 vps->bo_size = size;
91ba9f28 463
20fb5a63
TH
464 /*
465 * TTM already thinks the buffer is pinned, but make sure the
466 * pin_count is upped.
467 */
f1d34bfd 468 return vmw_bo_pin_in_vram(dev_priv, vps->bo, true);
060e2ad5
SY
469}
470
5d35abad
DR
471static uint32_t vmw_sou_bo_fifo_size(struct vmw_du_update_plane *update,
472 uint32_t num_hits)
473{
474 return sizeof(struct vmw_kms_sou_define_gmrfb) +
475 sizeof(struct vmw_kms_sou_bo_blit) * num_hits;
476}
477
478static uint32_t vmw_sou_bo_define_gmrfb(struct vmw_du_update_plane *update,
479 void *cmd)
480{
481 struct vmw_framebuffer_bo *vfbbo =
482 container_of(update->vfb, typeof(*vfbbo), base);
483 struct vmw_kms_sou_define_gmrfb *gmr = cmd;
484 int depth = update->vfb->base.format->depth;
485
486 /* Emulate RGBA support, contrary to svga_reg.h this is not
487 * supported by hosts. This is only a problem if we are reading
488 * this value later and expecting what we uploaded back.
489 */
490 if (depth == 32)
491 depth = 24;
492
493 gmr->header = SVGA_CMD_DEFINE_GMRFB;
494
495 gmr->body.format.bitsPerPixel = update->vfb->base.format->cpp[0] * 8;
496 gmr->body.format.colorDepth = depth;
497 gmr->body.format.reserved = 0;
498 gmr->body.bytesPerLine = update->vfb->base.pitches[0];
499 vmw_bo_get_guest_ptr(&vfbbo->buffer->base, &gmr->body.ptr);
500
501 return sizeof(*gmr);
502}
503
504static uint32_t vmw_sou_bo_populate_clip(struct vmw_du_update_plane *update,
505 void *cmd, struct drm_rect *clip,
506 uint32_t fb_x, uint32_t fb_y)
507{
508 struct vmw_kms_sou_bo_blit *blit = cmd;
509
510 blit->header = SVGA_CMD_BLIT_GMRFB_TO_SCREEN;
511 blit->body.destScreenId = update->du->unit;
512 blit->body.srcOrigin.x = fb_x;
513 blit->body.srcOrigin.y = fb_y;
514 blit->body.destRect.left = clip->x1;
515 blit->body.destRect.top = clip->y1;
516 blit->body.destRect.right = clip->x2;
517 blit->body.destRect.bottom = clip->y2;
518
519 return sizeof(*blit);
520}
521
522static uint32_t vmw_stud_bo_post_clip(struct vmw_du_update_plane *update,
523 void *cmd, struct drm_rect *bb)
524{
525 return 0;
526}
527
528/**
529 * vmw_sou_plane_update_bo - Update display unit for bo backed fb.
530 * @dev_priv: Device private.
531 * @plane: Plane state.
532 * @old_state: Old plane state.
533 * @vfb: Framebuffer which is blitted to display unit.
534 * @out_fence: If non-NULL, will return a ref-counted pointer to vmw_fence_obj.
535 * The returned fence pointer may be NULL in which case the device
536 * has already synchronized.
537 *
538 * Return: 0 on success or a negative error code on failure.
539 */
540static int vmw_sou_plane_update_bo(struct vmw_private *dev_priv,
541 struct drm_plane *plane,
542 struct drm_plane_state *old_state,
543 struct vmw_framebuffer *vfb,
544 struct vmw_fence_obj **out_fence)
545{
546 struct vmw_du_update_plane_buffer bo_update;
547
548 memset(&bo_update, 0, sizeof(struct vmw_du_update_plane_buffer));
549 bo_update.base.plane = plane;
550 bo_update.base.old_state = old_state;
551 bo_update.base.dev_priv = dev_priv;
552 bo_update.base.du = vmw_crtc_to_du(plane->state->crtc);
553 bo_update.base.vfb = vfb;
554 bo_update.base.out_fence = out_fence;
555 bo_update.base.mutex = NULL;
556 bo_update.base.cpu_blit = false;
557 bo_update.base.intr = true;
558
559 bo_update.base.calc_fifo_size = vmw_sou_bo_fifo_size;
560 bo_update.base.post_prepare = vmw_sou_bo_define_gmrfb;
561 bo_update.base.clip = vmw_sou_bo_populate_clip;
562 bo_update.base.post_clip = vmw_stud_bo_post_clip;
563
564 return vmw_du_helper_plane_update(&bo_update.base);
565}
566
43d1e627
DR
567static uint32_t vmw_sou_surface_fifo_size(struct vmw_du_update_plane *update,
568 uint32_t num_hits)
569{
570 return sizeof(struct vmw_kms_sou_dirty_cmd) + sizeof(SVGASignedRect) *
571 num_hits;
572}
573
574static uint32_t vmw_sou_surface_post_prepare(struct vmw_du_update_plane *update,
575 void *cmd)
576{
577 struct vmw_du_update_plane_surface *srf_update;
578
579 srf_update = container_of(update, typeof(*srf_update), base);
580
581 /*
582 * SOU SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN is special in the sense that
583 * its bounding box is filled before iterating over all the clips. So
584 * store the FIFO start address and revisit to fill the details.
585 */
586 srf_update->cmd_start = cmd;
587
588 return 0;
589}
590
591static uint32_t vmw_sou_surface_pre_clip(struct vmw_du_update_plane *update,
592 void *cmd, uint32_t num_hits)
593{
594 struct vmw_kms_sou_dirty_cmd *blit = cmd;
595 struct vmw_framebuffer_surface *vfbs;
596
597 vfbs = container_of(update->vfb, typeof(*vfbs), base);
598
599 blit->header.id = SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN;
600 blit->header.size = sizeof(blit->body) + sizeof(SVGASignedRect) *
601 num_hits;
602
603 blit->body.srcImage.sid = vfbs->surface->res.id;
604 blit->body.destScreenId = update->du->unit;
605
606 /* Update the source and destination bounding box later in post_clip */
607 blit->body.srcRect.left = 0;
608 blit->body.srcRect.top = 0;
609 blit->body.srcRect.right = 0;
610 blit->body.srcRect.bottom = 0;
611
612 blit->body.destRect.left = 0;
613 blit->body.destRect.top = 0;
614 blit->body.destRect.right = 0;
615 blit->body.destRect.bottom = 0;
616
617 return sizeof(*blit);
618}
619
620static uint32_t vmw_sou_surface_clip_rect(struct vmw_du_update_plane *update,
621 void *cmd, struct drm_rect *clip,
622 uint32_t src_x, uint32_t src_y)
623{
624 SVGASignedRect *rect = cmd;
625
626 /*
627 * rects are relative to dest bounding box rect on screen object, so
628 * translate to it later in post_clip
629 */
630 rect->left = clip->x1;
631 rect->top = clip->y1;
632 rect->right = clip->x2;
633 rect->bottom = clip->y2;
634
635 return sizeof(*rect);
636}
637
638static uint32_t vmw_sou_surface_post_clip(struct vmw_du_update_plane *update,
639 void *cmd, struct drm_rect *bb)
640{
641 struct vmw_du_update_plane_surface *srf_update;
642 struct drm_plane_state *state = update->plane->state;
643 struct drm_rect src_bb;
644 struct vmw_kms_sou_dirty_cmd *blit;
645 SVGASignedRect *rect;
646 uint32_t num_hits;
647 int translate_src_x;
648 int translate_src_y;
649 int i;
650
651 srf_update = container_of(update, typeof(*srf_update), base);
652
653 blit = srf_update->cmd_start;
654 rect = (SVGASignedRect *)&blit[1];
655
656 num_hits = (blit->header.size - sizeof(blit->body))/
657 sizeof(SVGASignedRect);
658
659 src_bb = *bb;
660
661 /* To translate bb back to fb src coord */
662 translate_src_x = (state->src_x >> 16) - state->crtc_x;
663 translate_src_y = (state->src_y >> 16) - state->crtc_y;
664
665 drm_rect_translate(&src_bb, translate_src_x, translate_src_y);
666
667 blit->body.srcRect.left = src_bb.x1;
668 blit->body.srcRect.top = src_bb.y1;
669 blit->body.srcRect.right = src_bb.x2;
670 blit->body.srcRect.bottom = src_bb.y2;
671
672 blit->body.destRect.left = bb->x1;
673 blit->body.destRect.top = bb->y1;
674 blit->body.destRect.right = bb->x2;
675 blit->body.destRect.bottom = bb->y2;
676
677 /* rects are relative to dest bb rect */
678 for (i = 0; i < num_hits; i++) {
679 rect->left -= bb->x1;
680 rect->top -= bb->y1;
681 rect->right -= bb->x1;
682 rect->bottom -= bb->y1;
683 rect++;
684 }
685
686 return 0;
687}
688
689/**
690 * vmw_sou_plane_update_surface - Update display unit for surface backed fb.
691 * @dev_priv: Device private.
692 * @plane: Plane state.
693 * @old_state: Old plane state.
694 * @vfb: Framebuffer which is blitted to display unit
695 * @out_fence: If non-NULL, will return a ref-counted pointer to vmw_fence_obj.
696 * The returned fence pointer may be NULL in which case the device
697 * has already synchronized.
698 *
699 * Return: 0 on success or a negative error code on failure.
700 */
701static int vmw_sou_plane_update_surface(struct vmw_private *dev_priv,
702 struct drm_plane *plane,
703 struct drm_plane_state *old_state,
704 struct vmw_framebuffer *vfb,
705 struct vmw_fence_obj **out_fence)
706{
707 struct vmw_du_update_plane_surface srf_update;
708
709 memset(&srf_update, 0, sizeof(struct vmw_du_update_plane_surface));
710 srf_update.base.plane = plane;
711 srf_update.base.old_state = old_state;
712 srf_update.base.dev_priv = dev_priv;
713 srf_update.base.du = vmw_crtc_to_du(plane->state->crtc);
714 srf_update.base.vfb = vfb;
715 srf_update.base.out_fence = out_fence;
716 srf_update.base.mutex = &dev_priv->cmdbuf_mutex;
717 srf_update.base.cpu_blit = false;
718 srf_update.base.intr = true;
719
720 srf_update.base.calc_fifo_size = vmw_sou_surface_fifo_size;
721 srf_update.base.post_prepare = vmw_sou_surface_post_prepare;
722 srf_update.base.pre_clip = vmw_sou_surface_pre_clip;
723 srf_update.base.clip = vmw_sou_surface_clip_rect;
724 srf_update.base.post_clip = vmw_sou_surface_post_clip;
725
726 return vmw_du_helper_plane_update(&srf_update.base);
727}
060e2ad5
SY
728
729static void
730vmw_sou_primary_plane_atomic_update(struct drm_plane *plane,
731 struct drm_plane_state *old_state)
732{
b0119cb9 733 struct drm_crtc *crtc = plane->state->crtc;
aa64b3f1
DR
734 struct drm_pending_vblank_event *event = NULL;
735 struct vmw_fence_obj *fence = NULL;
736 int ret;
737
31da2df8 738 /* In case of device error, maintain consistent atomic state */
aa64b3f1
DR
739 if (crtc && plane->state->fb) {
740 struct vmw_private *dev_priv = vmw_priv(crtc->dev);
741 struct vmw_framebuffer *vfb =
742 vmw_framebuffer_to_vfb(plane->state->fb);
aa64b3f1 743
f1d34bfd 744 if (vfb->bo)
67a51b3d
DR
745 ret = vmw_sou_plane_update_bo(dev_priv, plane,
746 old_state, vfb, &fence);
aa64b3f1 747 else
67a51b3d
DR
748 ret = vmw_sou_plane_update_surface(dev_priv, plane,
749 old_state, vfb,
750 &fence);
aa64b3f1
DR
751 if (ret != 0)
752 DRM_ERROR("Failed to update screen.\n");
aa64b3f1 753 } else {
31da2df8 754 /* Do nothing when fb and crtc is NULL (blank crtc) */
aa64b3f1
DR
755 return;
756 }
757
31da2df8 758 /* For error case vblank event is send from vmw_du_crtc_atomic_flush */
aa64b3f1 759 event = crtc->state->event;
aa64b3f1
DR
760 if (event && fence) {
761 struct drm_file *file_priv = event->base.file_priv;
762
763 ret = vmw_event_fence_action_queue(file_priv,
764 fence,
765 &event->base,
766 &event->event.vbl.tv_sec,
767 &event->event.vbl.tv_usec,
768 true);
769
770 if (unlikely(ret != 0))
771 DRM_ERROR("Failed to queue event on fence.\n");
772 else
773 crtc->state->event = NULL;
774 }
775
776 if (fence)
777 vmw_fence_obj_unreference(&fence);
060e2ad5
SY
778}
779
780
36cc79bc 781static const struct drm_plane_funcs vmw_sou_plane_funcs = {
b0119cb9
SY
782 .update_plane = drm_atomic_helper_update_plane,
783 .disable_plane = drm_atomic_helper_disable_plane,
36cc79bc 784 .destroy = vmw_du_primary_plane_destroy,
cc5ec459
SY
785 .reset = vmw_du_plane_reset,
786 .atomic_duplicate_state = vmw_du_plane_duplicate_state,
787 .atomic_destroy_state = vmw_du_plane_destroy_state,
36cc79bc
SY
788};
789
790static const struct drm_plane_funcs vmw_sou_cursor_funcs = {
b0119cb9
SY
791 .update_plane = drm_atomic_helper_update_plane,
792 .disable_plane = drm_atomic_helper_disable_plane,
36cc79bc 793 .destroy = vmw_du_cursor_plane_destroy,
cc5ec459
SY
794 .reset = vmw_du_plane_reset,
795 .atomic_duplicate_state = vmw_du_plane_duplicate_state,
796 .atomic_destroy_state = vmw_du_plane_destroy_state,
36cc79bc
SY
797};
798
06ec4190
SY
799/*
800 * Atomic Helpers
801 */
060e2ad5
SY
802static const struct
803drm_plane_helper_funcs vmw_sou_cursor_plane_helper_funcs = {
804 .atomic_check = vmw_du_cursor_plane_atomic_check,
805 .atomic_update = vmw_du_cursor_plane_atomic_update,
806 .prepare_fb = vmw_du_cursor_plane_prepare_fb,
807 .cleanup_fb = vmw_du_plane_cleanup_fb,
808};
809
810static const struct
811drm_plane_helper_funcs vmw_sou_primary_plane_helper_funcs = {
812 .atomic_check = vmw_du_primary_plane_atomic_check,
813 .atomic_update = vmw_sou_primary_plane_atomic_update,
814 .prepare_fb = vmw_sou_primary_plane_prepare_fb,
815 .cleanup_fb = vmw_sou_primary_plane_cleanup_fb,
816};
817
06ec4190
SY
818static const struct drm_crtc_helper_funcs vmw_sou_crtc_helper_funcs = {
819 .prepare = vmw_sou_crtc_helper_prepare,
06ec4190
SY
820 .mode_set_nofb = vmw_sou_crtc_mode_set_nofb,
821 .atomic_check = vmw_du_crtc_atomic_check,
822 .atomic_begin = vmw_du_crtc_atomic_begin,
823 .atomic_flush = vmw_du_crtc_atomic_flush,
0b20a0f8 824 .atomic_enable = vmw_sou_crtc_atomic_enable,
64581714 825 .atomic_disable = vmw_sou_crtc_atomic_disable,
06ec4190
SY
826};
827
36cc79bc 828
56d1c78d
JB
829static int vmw_sou_init(struct vmw_private *dev_priv, unsigned unit)
830{
831 struct vmw_screen_object_unit *sou;
832 struct drm_device *dev = dev_priv->dev;
833 struct drm_connector *connector;
834 struct drm_encoder *encoder;
cc5ec459 835 struct drm_plane *primary, *cursor;
56d1c78d 836 struct drm_crtc *crtc;
36cc79bc 837 int ret;
56d1c78d
JB
838
839 sou = kzalloc(sizeof(*sou), GFP_KERNEL);
840 if (!sou)
841 return -ENOMEM;
842
843 sou->base.unit = unit;
844 crtc = &sou->base.crtc;
845 encoder = &sou->base.encoder;
846 connector = &sou->base.connector;
cc5ec459
SY
847 primary = &sou->base.primary;
848 cursor = &sou->base.cursor;
56d1c78d 849
56d1c78d 850 sou->base.pref_active = (unit == 0);
eb4f923b
JB
851 sou->base.pref_width = dev_priv->initial_width;
852 sou->base.pref_height = dev_priv->initial_height;
56d1c78d 853 sou->base.pref_mode = NULL;
9c2542a4
SY
854
855 /*
856 * Remove this after enabling atomic because property values can
857 * only exist in a state object
858 */
2e69b25b 859 sou->base.is_implicit = false;
56d1c78d 860
36cc79bc 861 /* Initialize primary plane */
cc5ec459
SY
862 vmw_du_plane_reset(primary);
863
36cc79bc
SY
864 ret = drm_universal_plane_init(dev, &sou->base.primary,
865 0, &vmw_sou_plane_funcs,
866 vmw_primary_plane_formats,
867 ARRAY_SIZE(vmw_primary_plane_formats),
e6fc3b68 868 NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
36cc79bc
SY
869 if (ret) {
870 DRM_ERROR("Failed to initialize primary plane");
871 goto err_free;
872 }
873
060e2ad5 874 drm_plane_helper_add(primary, &vmw_sou_primary_plane_helper_funcs);
61c21387 875 drm_plane_enable_fb_damage_clips(primary);
060e2ad5 876
36cc79bc 877 /* Initialize cursor plane */
cc5ec459
SY
878 vmw_du_plane_reset(cursor);
879
36cc79bc
SY
880 ret = drm_universal_plane_init(dev, &sou->base.cursor,
881 0, &vmw_sou_cursor_funcs,
882 vmw_cursor_plane_formats,
883 ARRAY_SIZE(vmw_cursor_plane_formats),
e6fc3b68 884 NULL, DRM_PLANE_TYPE_CURSOR, NULL);
36cc79bc
SY
885 if (ret) {
886 DRM_ERROR("Failed to initialize cursor plane");
887 drm_plane_cleanup(&sou->base.primary);
888 goto err_free;
889 }
890
060e2ad5
SY
891 drm_plane_helper_add(cursor, &vmw_sou_cursor_plane_helper_funcs);
892
893 vmw_du_connector_reset(connector);
36cc79bc
SY
894 ret = drm_connector_init(dev, connector, &vmw_sou_connector_funcs,
895 DRM_MODE_CONNECTOR_VIRTUAL);
896 if (ret) {
897 DRM_ERROR("Failed to initialize connector\n");
898 goto err_free;
899 }
900
d947d1b7 901 drm_connector_helper_add(connector, &vmw_sou_connector_helper_funcs);
56d1c78d
JB
902 connector->status = vmw_du_connector_detect(connector, true);
903
36cc79bc
SY
904 ret = drm_encoder_init(dev, encoder, &vmw_screen_object_encoder_funcs,
905 DRM_MODE_ENCODER_VIRTUAL, NULL);
906 if (ret) {
907 DRM_ERROR("Failed to initialize encoder\n");
908 goto err_free_connector;
909 }
910
cde4c44d 911 (void) drm_connector_attach_encoder(connector, encoder);
56d1c78d
JB
912 encoder->possible_crtcs = (1 << unit);
913 encoder->possible_clones = 0;
914
36cc79bc
SY
915 ret = drm_connector_register(connector);
916 if (ret) {
917 DRM_ERROR("Failed to register connector\n");
918 goto err_free_encoder;
919 }
6a0a7a9e 920
d7721ca7
SY
921
922 vmw_du_crtc_reset(crtc);
36cc79bc
SY
923 ret = drm_crtc_init_with_planes(dev, crtc, &sou->base.primary,
924 &sou->base.cursor,
925 &vmw_screen_object_crtc_funcs, NULL);
926 if (ret) {
927 DRM_ERROR("Failed to initialize CRTC\n");
928 goto err_free_unregister;
929 }
56d1c78d 930
06ec4190
SY
931 drm_crtc_helper_add(crtc, &vmw_sou_crtc_helper_funcs);
932
56d1c78d
JB
933 drm_mode_crtc_set_gamma_size(crtc, 256);
934
578e609a
TH
935 drm_object_attach_property(&connector->base,
936 dev_priv->hotplug_mode_update_property, 1);
937 drm_object_attach_property(&connector->base,
938 dev->mode_config.suggested_x_property, 0);
939 drm_object_attach_property(&connector->base,
940 dev->mode_config.suggested_y_property, 0);
56d1c78d 941 return 0;
36cc79bc
SY
942
943err_free_unregister:
944 drm_connector_unregister(connector);
945err_free_encoder:
946 drm_encoder_cleanup(encoder);
947err_free_connector:
948 drm_connector_cleanup(connector);
949err_free:
950 kfree(sou);
951 return ret;
56d1c78d
JB
952}
953
c8261a96 954int vmw_kms_sou_init_display(struct vmw_private *dev_priv)
56d1c78d
JB
955{
956 struct drm_device *dev = dev_priv->dev;
74b5ea30 957 int i, ret;
56d1c78d 958
29a16e95 959 if (!(dev_priv->capabilities & SVGA_CAP_SCREEN_OBJECT_2)) {
56d1c78d
JB
960 DRM_INFO("Not using screen objects,"
961 " missing cap SCREEN_OBJECT_2\n");
962 return -ENOSYS;
963 }
964
965 ret = -ENOMEM;
56d1c78d
JB
966
967 ret = drm_vblank_init(dev, VMWGFX_NUM_DISPLAY_UNITS);
968 if (unlikely(ret != 0))
75c06855 969 return ret;
56d1c78d 970
56d1c78d
JB
971 for (i = 0; i < VMWGFX_NUM_DISPLAY_UNITS; ++i)
972 vmw_sou_init(dev_priv, i);
973
c8261a96
SY
974 dev_priv->active_display_unit = vmw_du_screen_object;
975
976 DRM_INFO("Screen Objects Display Unit initialized\n");
56d1c78d
JB
977
978 return 0;
56d1c78d
JB
979}
980
f1d34bfd 981static int do_bo_define_gmrfb(struct vmw_private *dev_priv,
c8261a96 982 struct vmw_framebuffer *framebuffer)
b5ec427e 983{
f1d34bfd
TH
984 struct vmw_buffer_object *buf =
985 container_of(framebuffer, struct vmw_framebuffer_bo,
10b1e0ca 986 base)->buffer;
b00c600e 987 int depth = framebuffer->base.format->depth;
c8261a96
SY
988 struct {
989 uint32_t header;
990 SVGAFifoCmdDefineGMRFB body;
991 } *cmd;
b5ec427e 992
c8261a96
SY
993 /* Emulate RGBA support, contrary to svga_reg.h this is not
994 * supported by hosts. This is only a problem if we are reading
995 * this value later and expecting what we uploaded back.
996 */
997 if (depth == 32)
998 depth = 24;
b5ec427e 999
11c45419
DR
1000 cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
1001 if (!cmd)
c8261a96 1002 return -ENOMEM;
c8261a96 1003
c8261a96 1004 cmd->header = SVGA_CMD_DEFINE_GMRFB;
272725c7 1005 cmd->body.format.bitsPerPixel = framebuffer->base.format->cpp[0] * 8;
c8261a96
SY
1006 cmd->body.format.colorDepth = depth;
1007 cmd->body.format.reserved = 0;
1008 cmd->body.bytesPerLine = framebuffer->base.pitches[0];
10b1e0ca
TH
1009 /* Buffer is reserved in vram or GMR */
1010 vmw_bo_get_guest_ptr(&buf->base, &cmd->body.ptr);
1011 vmw_fifo_commit(dev_priv, sizeof(*cmd));
1012
1013 return 0;
1014}
1015
1016/**
1017 * vmw_sou_surface_fifo_commit - Callback to fill in and submit a
1018 * blit surface to screen command.
1019 *
1020 * @dirty: The closure structure.
1021 *
1022 * Fills in the missing fields in the command, and translates the cliprects
1023 * to match the destination bounding box encoded.
1024 */
1025static void vmw_sou_surface_fifo_commit(struct vmw_kms_dirty *dirty)
1026{
1027 struct vmw_kms_sou_surface_dirty *sdirty =
1028 container_of(dirty, typeof(*sdirty), base);
1029 struct vmw_kms_sou_dirty_cmd *cmd = dirty->cmd;
1030 s32 trans_x = dirty->unit->crtc.x - sdirty->dst_x;
1031 s32 trans_y = dirty->unit->crtc.y - sdirty->dst_y;
1032 size_t region_size = dirty->num_hits * sizeof(SVGASignedRect);
1033 SVGASignedRect *blit = (SVGASignedRect *) &cmd[1];
1034 int i;
1035
fea7dd54
TH
1036 if (!dirty->num_hits) {
1037 vmw_fifo_commit(dirty->dev_priv, 0);
1038 return;
1039 }
1040
10b1e0ca
TH
1041 cmd->header.id = SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN;
1042 cmd->header.size = sizeof(cmd->body) + region_size;
1043
1044 /*
1045 * Use the destination bounding box to specify destination - and
1046 * source bounding regions.
1047 */
1048 cmd->body.destRect.left = sdirty->left;
1049 cmd->body.destRect.right = sdirty->right;
1050 cmd->body.destRect.top = sdirty->top;
1051 cmd->body.destRect.bottom = sdirty->bottom;
1052
1053 cmd->body.srcRect.left = sdirty->left + trans_x;
1054 cmd->body.srcRect.right = sdirty->right + trans_x;
1055 cmd->body.srcRect.top = sdirty->top + trans_y;
1056 cmd->body.srcRect.bottom = sdirty->bottom + trans_y;
1057
1058 cmd->body.srcImage.sid = sdirty->sid;
1059 cmd->body.destScreenId = dirty->unit->unit;
1060
1061 /* Blits are relative to the destination rect. Translate. */
1062 for (i = 0; i < dirty->num_hits; ++i, ++blit) {
1063 blit->left -= sdirty->left;
1064 blit->right -= sdirty->left;
1065 blit->top -= sdirty->top;
1066 blit->bottom -= sdirty->top;
1067 }
1068
1069 vmw_fifo_commit(dirty->dev_priv, region_size + sizeof(*cmd));
1070
1071 sdirty->left = sdirty->top = S32_MAX;
1072 sdirty->right = sdirty->bottom = S32_MIN;
1073}
1074
1075/**
1076 * vmw_sou_surface_clip - Callback to encode a blit surface to screen cliprect.
1077 *
1078 * @dirty: The closure structure
1079 *
1080 * Encodes a SVGASignedRect cliprect and updates the bounding box of the
1081 * BLIT_SURFACE_TO_SCREEN command.
1082 */
1083static void vmw_sou_surface_clip(struct vmw_kms_dirty *dirty)
1084{
1085 struct vmw_kms_sou_surface_dirty *sdirty =
1086 container_of(dirty, typeof(*sdirty), base);
1087 struct vmw_kms_sou_dirty_cmd *cmd = dirty->cmd;
1088 SVGASignedRect *blit = (SVGASignedRect *) &cmd[1];
1089
1090 /* Destination rect. */
1091 blit += dirty->num_hits;
1092 blit->left = dirty->unit_x1;
1093 blit->top = dirty->unit_y1;
1094 blit->right = dirty->unit_x2;
1095 blit->bottom = dirty->unit_y2;
1096
1097 /* Destination bounding box */
1098 sdirty->left = min_t(s32, sdirty->left, dirty->unit_x1);
1099 sdirty->top = min_t(s32, sdirty->top, dirty->unit_y1);
1100 sdirty->right = max_t(s32, sdirty->right, dirty->unit_x2);
1101 sdirty->bottom = max_t(s32, sdirty->bottom, dirty->unit_y2);
1102
1103 dirty->num_hits++;
1104}
1105
1106/**
1107 * vmw_kms_sou_do_surface_dirty - Dirty part of a surface backed framebuffer
1108 *
1109 * @dev_priv: Pointer to the device private structure.
1110 * @framebuffer: Pointer to the surface-buffer backed framebuffer.
1111 * @clips: Array of clip rects. Either @clips or @vclips must be NULL.
1112 * @vclips: Alternate array of clip rects. Either @clips or @vclips must
1113 * be NULL.
1114 * @srf: Pointer to surface to blit from. If NULL, the surface attached
1115 * to @framebuffer will be used.
1116 * @dest_x: X coordinate offset to align @srf with framebuffer coordinates.
1117 * @dest_y: Y coordinate offset to align @srf with framebuffer coordinates.
1118 * @num_clips: Number of clip rects in @clips.
1119 * @inc: Increment to use when looping over @clips.
1120 * @out_fence: If non-NULL, will return a ref-counted pointer to a
1121 * struct vmw_fence_obj. The returned fence pointer may be NULL in which
1122 * case the device has already synchronized.
91e9f352 1123 * @crtc: If crtc is passed, perform surface dirty on that crtc only.
10b1e0ca
TH
1124 *
1125 * Returns 0 on success, negative error code on failure. -ERESTARTSYS if
1126 * interrupted.
1127 */
1128int vmw_kms_sou_do_surface_dirty(struct vmw_private *dev_priv,
1129 struct vmw_framebuffer *framebuffer,
1130 struct drm_clip_rect *clips,
1131 struct drm_vmw_rect *vclips,
1132 struct vmw_resource *srf,
1133 s32 dest_x,
1134 s32 dest_y,
1135 unsigned num_clips, int inc,
91e9f352
DR
1136 struct vmw_fence_obj **out_fence,
1137 struct drm_crtc *crtc)
10b1e0ca
TH
1138{
1139 struct vmw_framebuffer_surface *vfbs =
1140 container_of(framebuffer, typeof(*vfbs), base);
1141 struct vmw_kms_sou_surface_dirty sdirty;
2724b2d5 1142 DECLARE_VAL_CONTEXT(val_ctx, NULL, 0);
10b1e0ca
TH
1143 int ret;
1144
1145 if (!srf)
1146 srf = &vfbs->surface->res;
1147
a9f58c45
TH
1148 ret = vmw_validation_add_resource(&val_ctx, srf, 0, VMW_RES_DIRTY_NONE,
1149 NULL, NULL);
10b1e0ca
TH
1150 if (ret)
1151 return ret;
1152
2724b2d5
TH
1153 ret = vmw_validation_prepare(&val_ctx, &dev_priv->cmdbuf_mutex, true);
1154 if (ret)
1155 goto out_unref;
1156
10b1e0ca
TH
1157 sdirty.base.fifo_commit = vmw_sou_surface_fifo_commit;
1158 sdirty.base.clip = vmw_sou_surface_clip;
1159 sdirty.base.dev_priv = dev_priv;
1160 sdirty.base.fifo_reserve_size = sizeof(struct vmw_kms_sou_dirty_cmd) +
1161 sizeof(SVGASignedRect) * num_clips;
91e9f352 1162 sdirty.base.crtc = crtc;
c8261a96 1163
10b1e0ca
TH
1164 sdirty.sid = srf->id;
1165 sdirty.left = sdirty.top = S32_MAX;
1166 sdirty.right = sdirty.bottom = S32_MIN;
1167 sdirty.dst_x = dest_x;
1168 sdirty.dst_y = dest_y;
c8261a96 1169
10b1e0ca
TH
1170 ret = vmw_kms_helper_dirty(dev_priv, framebuffer, clips, vclips,
1171 dest_x, dest_y, num_clips, inc,
1172 &sdirty.base);
2724b2d5
TH
1173 vmw_kms_helper_validation_finish(dev_priv, NULL, &val_ctx, out_fence,
1174 NULL);
c8261a96
SY
1175
1176 return ret;
2724b2d5
TH
1177
1178out_unref:
1179 vmw_validation_unref_lists(&val_ctx);
1180 return ret;
b5ec427e
JB
1181}
1182
10b1e0ca 1183/**
f1d34bfd 1184 * vmw_sou_bo_fifo_commit - Callback to submit a set of readback clips.
10b1e0ca
TH
1185 *
1186 * @dirty: The closure structure.
1187 *
1188 * Commits a previously built command buffer of readback clips.
1189 */
f1d34bfd 1190static void vmw_sou_bo_fifo_commit(struct vmw_kms_dirty *dirty)
10b1e0ca 1191{
fea7dd54
TH
1192 if (!dirty->num_hits) {
1193 vmw_fifo_commit(dirty->dev_priv, 0);
1194 return;
1195 }
1196
10b1e0ca 1197 vmw_fifo_commit(dirty->dev_priv,
f1d34bfd 1198 sizeof(struct vmw_kms_sou_bo_blit) *
10b1e0ca
TH
1199 dirty->num_hits);
1200}
1201
1202/**
f1d34bfd 1203 * vmw_sou_bo_clip - Callback to encode a readback cliprect.
10b1e0ca
TH
1204 *
1205 * @dirty: The closure structure
1206 *
1207 * Encodes a BLIT_GMRFB_TO_SCREEN cliprect.
1208 */
f1d34bfd 1209static void vmw_sou_bo_clip(struct vmw_kms_dirty *dirty)
10b1e0ca 1210{
f1d34bfd 1211 struct vmw_kms_sou_bo_blit *blit = dirty->cmd;
10b1e0ca
TH
1212
1213 blit += dirty->num_hits;
1214 blit->header = SVGA_CMD_BLIT_GMRFB_TO_SCREEN;
1215 blit->body.destScreenId = dirty->unit->unit;
1216 blit->body.srcOrigin.x = dirty->fb_x;
1217 blit->body.srcOrigin.y = dirty->fb_y;
1218 blit->body.destRect.left = dirty->unit_x1;
1219 blit->body.destRect.top = dirty->unit_y1;
1220 blit->body.destRect.right = dirty->unit_x2;
1221 blit->body.destRect.bottom = dirty->unit_y2;
1222 dirty->num_hits++;
1223}
1224
1225/**
f1d34bfd 1226 * vmw_kms_do_bo_dirty - Dirty part of a buffer-object backed framebuffer
10b1e0ca
TH
1227 *
1228 * @dev_priv: Pointer to the device private structure.
f1d34bfd 1229 * @framebuffer: Pointer to the buffer-object backed framebuffer.
10b1e0ca 1230 * @clips: Array of clip rects.
897b8180
TH
1231 * @vclips: Alternate array of clip rects. Either @clips or @vclips must
1232 * be NULL.
10b1e0ca
TH
1233 * @num_clips: Number of clip rects in @clips.
1234 * @increment: Increment to use when looping over @clips.
1235 * @interruptible: Whether to perform waits interruptible if possible.
1236 * @out_fence: If non-NULL, will return a ref-counted pointer to a
1237 * struct vmw_fence_obj. The returned fence pointer may be NULL in which
1238 * case the device has already synchronized.
f1d34bfd 1239 * @crtc: If crtc is passed, perform bo dirty on that crtc only.
10b1e0ca
TH
1240 *
1241 * Returns 0 on success, negative error code on failure. -ERESTARTSYS if
1242 * interrupted.
1243 */
f1d34bfd 1244int vmw_kms_sou_do_bo_dirty(struct vmw_private *dev_priv,
c8261a96 1245 struct vmw_framebuffer *framebuffer,
c8261a96 1246 struct drm_clip_rect *clips,
897b8180 1247 struct drm_vmw_rect *vclips,
c8261a96 1248 unsigned num_clips, int increment,
10b1e0ca 1249 bool interruptible,
91e9f352
DR
1250 struct vmw_fence_obj **out_fence,
1251 struct drm_crtc *crtc)
b5ec427e 1252{
f1d34bfd
TH
1253 struct vmw_buffer_object *buf =
1254 container_of(framebuffer, struct vmw_framebuffer_bo,
10b1e0ca
TH
1255 base)->buffer;
1256 struct vmw_kms_dirty dirty;
2724b2d5 1257 DECLARE_VAL_CONTEXT(val_ctx, NULL, 0);
10b1e0ca 1258 int ret;
b5ec427e 1259
2724b2d5 1260 ret = vmw_validation_add_bo(&val_ctx, buf, false, false);
10b1e0ca
TH
1261 if (ret)
1262 return ret;
b5ec427e 1263
2724b2d5
TH
1264 ret = vmw_validation_prepare(&val_ctx, NULL, interruptible);
1265 if (ret)
1266 goto out_unref;
1267
f1d34bfd 1268 ret = do_bo_define_gmrfb(dev_priv, framebuffer);
c8261a96 1269 if (unlikely(ret != 0))
10b1e0ca 1270 goto out_revert;
c8261a96 1271
91e9f352 1272 dirty.crtc = crtc;
f1d34bfd
TH
1273 dirty.fifo_commit = vmw_sou_bo_fifo_commit;
1274 dirty.clip = vmw_sou_bo_clip;
1275 dirty.fifo_reserve_size = sizeof(struct vmw_kms_sou_bo_blit) *
10b1e0ca 1276 num_clips;
897b8180 1277 ret = vmw_kms_helper_dirty(dev_priv, framebuffer, clips, vclips,
10b1e0ca 1278 0, 0, num_clips, increment, &dirty);
2724b2d5
TH
1279 vmw_kms_helper_validation_finish(dev_priv, NULL, &val_ctx, out_fence,
1280 NULL);
c8261a96 1281
10b1e0ca 1282 return ret;
c8261a96 1283
10b1e0ca 1284out_revert:
2724b2d5
TH
1285 vmw_validation_revert(&val_ctx);
1286out_unref:
1287 vmw_validation_unref_lists(&val_ctx);
c8261a96 1288
10b1e0ca
TH
1289 return ret;
1290}
c8261a96 1291
c8261a96 1292
10b1e0ca
TH
1293/**
1294 * vmw_sou_readback_fifo_commit - Callback to submit a set of readback clips.
1295 *
1296 * @dirty: The closure structure.
1297 *
1298 * Commits a previously built command buffer of readback clips.
1299 */
1300static void vmw_sou_readback_fifo_commit(struct vmw_kms_dirty *dirty)
1301{
fea7dd54
TH
1302 if (!dirty->num_hits) {
1303 vmw_fifo_commit(dirty->dev_priv, 0);
1304 return;
1305 }
1306
10b1e0ca
TH
1307 vmw_fifo_commit(dirty->dev_priv,
1308 sizeof(struct vmw_kms_sou_readback_blit) *
1309 dirty->num_hits);
b5ec427e 1310}
c8261a96 1311
10b1e0ca
TH
1312/**
1313 * vmw_sou_readback_clip - Callback to encode a readback cliprect.
1314 *
1315 * @dirty: The closure structure
1316 *
1317 * Encodes a BLIT_SCREEN_TO_GMRFB cliprect.
1318 */
1319static void vmw_sou_readback_clip(struct vmw_kms_dirty *dirty)
1320{
1321 struct vmw_kms_sou_readback_blit *blit = dirty->cmd;
1322
1323 blit += dirty->num_hits;
1324 blit->header = SVGA_CMD_BLIT_SCREEN_TO_GMRFB;
1325 blit->body.srcScreenId = dirty->unit->unit;
1326 blit->body.destOrigin.x = dirty->fb_x;
1327 blit->body.destOrigin.y = dirty->fb_y;
1328 blit->body.srcRect.left = dirty->unit_x1;
1329 blit->body.srcRect.top = dirty->unit_y1;
1330 blit->body.srcRect.right = dirty->unit_x2;
1331 blit->body.srcRect.bottom = dirty->unit_y2;
1332 dirty->num_hits++;
1333}
1334
1335/**
1336 * vmw_kms_sou_readback - Perform a readback from the screen object system to
f1d34bfd 1337 * a buffer-object backed framebuffer.
10b1e0ca
TH
1338 *
1339 * @dev_priv: Pointer to the device private structure.
1340 * @file_priv: Pointer to a struct drm_file identifying the caller.
1341 * Must be set to NULL if @user_fence_rep is NULL.
f1d34bfd 1342 * @vfb: Pointer to the buffer-object backed framebuffer.
10b1e0ca
TH
1343 * @user_fence_rep: User-space provided structure for fence information.
1344 * Must be set to non-NULL if @file_priv is non-NULL.
1345 * @vclips: Array of clip rects.
1346 * @num_clips: Number of clip rects in @vclips.
91e9f352 1347 * @crtc: If crtc is passed, readback on that crtc only.
10b1e0ca
TH
1348 *
1349 * Returns 0 on success, negative error code on failure. -ERESTARTSYS if
1350 * interrupted.
1351 */
1352int vmw_kms_sou_readback(struct vmw_private *dev_priv,
1353 struct drm_file *file_priv,
1354 struct vmw_framebuffer *vfb,
1355 struct drm_vmw_fence_rep __user *user_fence_rep,
1356 struct drm_vmw_rect *vclips,
91e9f352
DR
1357 uint32_t num_clips,
1358 struct drm_crtc *crtc)
10b1e0ca 1359{
f1d34bfd
TH
1360 struct vmw_buffer_object *buf =
1361 container_of(vfb, struct vmw_framebuffer_bo, base)->buffer;
10b1e0ca 1362 struct vmw_kms_dirty dirty;
2724b2d5 1363 DECLARE_VAL_CONTEXT(val_ctx, NULL, 0);
10b1e0ca
TH
1364 int ret;
1365
2724b2d5 1366 ret = vmw_validation_add_bo(&val_ctx, buf, false, false);
10b1e0ca
TH
1367 if (ret)
1368 return ret;
1369
2724b2d5
TH
1370 ret = vmw_validation_prepare(&val_ctx, NULL, true);
1371 if (ret)
1372 goto out_unref;
1373
f1d34bfd 1374 ret = do_bo_define_gmrfb(dev_priv, vfb);
10b1e0ca
TH
1375 if (unlikely(ret != 0))
1376 goto out_revert;
1377
91e9f352 1378 dirty.crtc = crtc;
10b1e0ca
TH
1379 dirty.fifo_commit = vmw_sou_readback_fifo_commit;
1380 dirty.clip = vmw_sou_readback_clip;
1381 dirty.fifo_reserve_size = sizeof(struct vmw_kms_sou_readback_blit) *
1382 num_clips;
1383 ret = vmw_kms_helper_dirty(dev_priv, vfb, NULL, vclips,
1384 0, 0, num_clips, 1, &dirty);
2724b2d5
TH
1385 vmw_kms_helper_validation_finish(dev_priv, file_priv, &val_ctx, NULL,
1386 user_fence_rep);
10b1e0ca
TH
1387
1388 return ret;
1389
1390out_revert:
2724b2d5
TH
1391 vmw_validation_revert(&val_ctx);
1392out_unref:
1393 vmw_validation_unref_lists(&val_ctx);
1394
10b1e0ca
TH
1395 return ret;
1396}