[linux-2.6-block.git] / drivers / gpu / drm / vmwgfx / vmwgfx_fifo.c

/**************************************************************************
 *
 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 **************************************************************************/

#include "vmwgfx_drv.h"
#include <drm/drmP.h>
#include <drm/ttm/ttm_placement.h>

bool vmw_fifo_have_3d(struct vmw_private *dev_priv)
{
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	uint32_t fifo_min, hwversion;
	const struct vmw_fifo_state *fifo = &dev_priv->fifo;

	if (!(dev_priv->capabilities & SVGA_CAP_3D))
		return false;

	if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
		uint32_t result;

		if (!dev_priv->has_mob)
			return false;

		mutex_lock(&dev_priv->hw_mutex);
		vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D);
		result = vmw_read(dev_priv, SVGA_REG_DEV_CAP);
		mutex_unlock(&dev_priv->hw_mutex);

		return (result != 0);
	}

	if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
		return false;

	fifo_min = ioread32(fifo_mem  + SVGA_FIFO_MIN);
	if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int))
		return false;

	hwversion = ioread32(fifo_mem +
			     ((fifo->capabilities &
			       SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ?
			      SVGA_FIFO_3D_HWVERSION_REVISED :
			      SVGA_FIFO_3D_HWVERSION));

	if (hwversion == 0)
		return false;

	if (hwversion < SVGA3D_HWVERSION_WS8_B1)
		return false;

	/* Non-Screen Object path does not support surfaces */
	if (!dev_priv->sou_priv)
		return false;

	return true;
}

bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv)
{
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	uint32_t caps;

	if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
		return false;

	caps = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
	if (caps & SVGA_FIFO_CAP_PITCHLOCK)
		return true;

	return false;
}

int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
{
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	uint32_t max;
	uint32_t min;
	uint32_t dummy;

	fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE;
	fifo->static_buffer = vmalloc(fifo->static_buffer_size);
	if (unlikely(fifo->static_buffer == NULL))
		return -ENOMEM;

	fifo->dynamic_buffer = NULL;
	fifo->reserved_size = 0;
	fifo->using_bounce_buffer = false;

	mutex_init(&fifo->fifo_mutex);
	init_rwsem(&fifo->rwsem);

	/*
	 * Allow mapping the first page read-only to user-space.
	 */

	DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH));
	DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT));
	DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL));

	mutex_lock(&dev_priv->hw_mutex);
	dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
	dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
	dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
	vmw_write(dev_priv, SVGA_REG_ENABLE, 1);

	min = 4;
	if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)
		min = vmw_read(dev_priv, SVGA_REG_MEM_REGS);
	min <<= 2;

	if (min < PAGE_SIZE)
		min = PAGE_SIZE;

	iowrite32(min, fifo_mem + SVGA_FIFO_MIN);
	iowrite32(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX);
	wmb();
	iowrite32(min,  fifo_mem + SVGA_FIFO_NEXT_CMD);
	iowrite32(min,  fifo_mem + SVGA_FIFO_STOP);
	iowrite32(0, fifo_mem + SVGA_FIFO_BUSY);
	mb();

	vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
	mutex_unlock(&dev_priv->hw_mutex);

	max = ioread32(fifo_mem + SVGA_FIFO_MAX);
	min = ioread32(fifo_mem  + SVGA_FIFO_MIN);
	fifo->capabilities = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);

	DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
		 (unsigned int) max,
		 (unsigned int) min,
		 (unsigned int) fifo->capabilities);

	atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);
	iowrite32(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE);
	vmw_marker_queue_init(&fifo->marker_queue);
	return vmw_fifo_send_fence(dev_priv, &dummy);
}

void vmw_fifo_ping_host_locked(struct vmw_private *dev_priv, uint32_t reason)
{
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;

	if (unlikely(ioread32(fifo_mem + SVGA_FIFO_BUSY) == 0)) {
		iowrite32(1, fifo_mem + SVGA_FIFO_BUSY);
		vmw_write(dev_priv, SVGA_REG_SYNC, reason);
	}
}

void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)
{
	mutex_lock(&dev_priv->hw_mutex);

	vmw_fifo_ping_host_locked(dev_priv, reason);

	mutex_unlock(&dev_priv->hw_mutex);
}

void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
{
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;

	mutex_lock(&dev_priv->hw_mutex);

	vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
	while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0)
		;

	dev_priv->last_read_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE);

	vmw_write(dev_priv, SVGA_REG_CONFIG_DONE,
		  dev_priv->config_done_state);
	vmw_write(dev_priv, SVGA_REG_ENABLE,
		  dev_priv->enable_state);
	vmw_write(dev_priv, SVGA_REG_TRACES,
		  dev_priv->traces_state);

	mutex_unlock(&dev_priv->hw_mutex);
	vmw_marker_queue_takedown(&fifo->marker_queue);

	if (likely(fifo->static_buffer != NULL)) {
		vfree(fifo->static_buffer);
		fifo->static_buffer = NULL;
	}

	if (likely(fifo->dynamic_buffer != NULL)) {
		vfree(fifo->dynamic_buffer);
		fifo->dynamic_buffer = NULL;
	}
}

static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)
{
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
	uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
	uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
	uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);

	return ((max - next_cmd) + (stop - min) <= bytes);
}

static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv,
			       uint32_t bytes, bool interruptible,
			       unsigned long timeout)
{
	int ret = 0;
	unsigned long end_jiffies = jiffies + timeout;
	DEFINE_WAIT(__wait);

	DRM_INFO("Fifo wait noirq.\n");

	for (;;) {
		prepare_to_wait(&dev_priv->fifo_queue, &__wait,
				(interruptible) ?
				TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
		if (!vmw_fifo_is_full(dev_priv, bytes))
			break;
		if (time_after_eq(jiffies, end_jiffies)) {
			ret = -EBUSY;
			DRM_ERROR("SVGA device lockup.\n");
			break;
		}
		schedule_timeout(1);
		if (interruptible && signal_pending(current)) {
			ret = -ERESTARTSYS;
			break;
		}
	}
	finish_wait(&dev_priv->fifo_queue, &__wait);
	wake_up_all(&dev_priv->fifo_queue);
	DRM_INFO("Fifo noirq exit.\n");
	return ret;
}

static int vmw_fifo_wait(struct vmw_private *dev_priv,
			 uint32_t bytes, bool interruptible,
			 unsigned long timeout)
{
	long ret = 1L;
	unsigned long irq_flags;

	if (likely(!vmw_fifo_is_full(dev_priv, bytes)))
		return 0;

	vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL);
	if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
		return vmw_fifo_wait_noirq(dev_priv, bytes,
					   interruptible, timeout);

	mutex_lock(&dev_priv->hw_mutex);
	if (atomic_add_return(1, &dev_priv->fifo_queue_waiters) > 0) {
		spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
		outl(SVGA_IRQFLAG_FIFO_PROGRESS,
		     dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
		dev_priv->irq_mask |= SVGA_IRQFLAG_FIFO_PROGRESS;
		vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
		spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
	}
	mutex_unlock(&dev_priv->hw_mutex);

	if (interruptible)
		ret = wait_event_interruptible_timeout
		    (dev_priv->fifo_queue,
		     !vmw_fifo_is_full(dev_priv, bytes), timeout);
	else
		ret = wait_event_timeout
		    (dev_priv->fifo_queue,
		     !vmw_fifo_is_full(dev_priv, bytes), timeout);

	if (unlikely(ret == 0))
		ret = -EBUSY;
	else if (likely(ret > 0))
		ret = 0;

	mutex_lock(&dev_priv->hw_mutex);
	if (atomic_dec_and_test(&dev_priv->fifo_queue_waiters)) {
		spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
		dev_priv->irq_mask &= ~SVGA_IRQFLAG_FIFO_PROGRESS;
		vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
		spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
	}
	mutex_unlock(&dev_priv->hw_mutex);

	return ret;
}

/**
 * Reserve @bytes number of bytes in the fifo.
 *
 * This function will return NULL (error) on two conditions:
 *  If it timeouts waiting for fifo space, or if @bytes is larger than the
 *   available fifo space.
 *
 * Returns:
 *   Pointer to the fifo, or null on error (possible hardware hang).
 */
void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes)
{
	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	uint32_t max;
	uint32_t min;
	uint32_t next_cmd;
	uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
	int ret;

	mutex_lock(&fifo_state->fifo_mutex);
	max = ioread32(fifo_mem + SVGA_FIFO_MAX);
	min = ioread32(fifo_mem + SVGA_FIFO_MIN);
	next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);

	if (unlikely(bytes >= (max - min)))
		goto out_err;

	BUG_ON(fifo_state->reserved_size != 0);
	BUG_ON(fifo_state->dynamic_buffer != NULL);

	fifo_state->reserved_size = bytes;

	while (1) {
		uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
		bool need_bounce = false;
		bool reserve_in_place = false;

		if (next_cmd >= stop) {
			if (likely((next_cmd + bytes < max ||
				    (next_cmd + bytes == max && stop > min))))
				reserve_in_place = true;

			else if (vmw_fifo_is_full(dev_priv, bytes)) {
				ret = vmw_fifo_wait(dev_priv, bytes,
						    false, 3 * HZ);
				if (unlikely(ret != 0))
					goto out_err;
			} else
				need_bounce = true;

		} else {

			if (likely((next_cmd + bytes < stop)))
				reserve_in_place = true;
			else {
				ret = vmw_fifo_wait(dev_priv, bytes,
						    false, 3 * HZ);
				if (unlikely(ret != 0))
					goto out_err;
			}
		}

		if (reserve_in_place) {
			if (reserveable || bytes <= sizeof(uint32_t)) {
				fifo_state->using_bounce_buffer = false;

				if (reserveable)
					iowrite32(bytes, fifo_mem +
						  SVGA_FIFO_RESERVED);
				return fifo_mem + (next_cmd >> 2);
			} else {
				need_bounce = true;
			}
		}

		if (need_bounce) {
			fifo_state->using_bounce_buffer = true;
			if (bytes < fifo_state->static_buffer_size)
				return fifo_state->static_buffer;
			else {
				fifo_state->dynamic_buffer = vmalloc(bytes);
				return fifo_state->dynamic_buffer;
			}
		}
	}
out_err:
	fifo_state->reserved_size = 0;
	mutex_unlock(&fifo_state->fifo_mutex);
	return NULL;
}

static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state,
			      __le32 __iomem *fifo_mem,
			      uint32_t next_cmd,
			      uint32_t max, uint32_t min, uint32_t bytes)
{
	uint32_t chunk_size = max - next_cmd;
	uint32_t rest;
	uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
	    fifo_state->dynamic_buffer : fifo_state->static_buffer;

	if (bytes < chunk_size)
		chunk_size = bytes;

	iowrite32(bytes, fifo_mem + SVGA_FIFO_RESERVED);
	mb();
	memcpy_toio(fifo_mem + (next_cmd >> 2), buffer, chunk_size);
	rest = bytes - chunk_size;
	if (rest)
		memcpy_toio(fifo_mem + (min >> 2), buffer + (chunk_size >> 2),
			    rest);
}

static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state,
			       __le32 __iomem *fifo_mem,
			       uint32_t next_cmd,
			       uint32_t max, uint32_t min, uint32_t bytes)
{
	uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
	    fifo_state->dynamic_buffer : fifo_state->static_buffer;

	while (bytes > 0) {
		iowrite32(*buffer++, fifo_mem + (next_cmd >> 2));
		next_cmd += sizeof(uint32_t);
		if (unlikely(next_cmd == max))
			next_cmd = min;
		mb();
		iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
		mb();
		bytes -= sizeof(uint32_t);
	}
}

void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
{
	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
	uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
	uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
	bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;

	BUG_ON((bytes & 3) != 0);
	BUG_ON(bytes > fifo_state->reserved_size);

	fifo_state->reserved_size = 0;

	if (fifo_state->using_bounce_buffer) {
		if (reserveable)
			vmw_fifo_res_copy(fifo_state, fifo_mem,
					  next_cmd, max, min, bytes);
		else
			vmw_fifo_slow_copy(fifo_state, fifo_mem,
					   next_cmd, max, min, bytes);

		if (fifo_state->dynamic_buffer) {
			vfree(fifo_state->dynamic_buffer);
			fifo_state->dynamic_buffer = NULL;
		}

	}

	down_write(&fifo_state->rwsem);
	if (fifo_state->using_bounce_buffer || reserveable) {
		next_cmd += bytes;
		if (next_cmd >= max)
			next_cmd -= max - min;
		mb();
		iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
	}

	if (reserveable)
		iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED);
	mb();
	up_write(&fifo_state->rwsem);
	vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
	mutex_unlock(&fifo_state->fifo_mutex);
}

int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno)
{
	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
	struct svga_fifo_cmd_fence *cmd_fence;
	void *fm;
	int ret = 0;
	uint32_t bytes = sizeof(__le32) + sizeof(*cmd_fence);

	fm = vmw_fifo_reserve(dev_priv, bytes);
	if (unlikely(fm == NULL)) {
		*seqno = atomic_read(&dev_priv->marker_seq);
		ret = -ENOMEM;
		(void)vmw_fallback_wait(dev_priv, false, true, *seqno,
					false, 3*HZ);
		goto out_err;
	}

	do {
		*seqno = atomic_add_return(1, &dev_priv->marker_seq);
	} while (*seqno == 0);

	if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) {

		/*
		 * Don't request hardware to send a fence. The
		 * waiting code in vmwgfx_irq.c will emulate this.
		 */

		vmw_fifo_commit(dev_priv, 0);
		return 0;
	}

	*(__le32 *) fm = cpu_to_le32(SVGA_CMD_FENCE);
	cmd_fence = (struct svga_fifo_cmd_fence *)
	    ((unsigned long)fm + sizeof(__le32));

	iowrite32(*seqno, &cmd_fence->fence);
	vmw_fifo_commit(dev_priv, bytes);
	(void) vmw_marker_push(&fifo_state->marker_queue, *seqno);
	vmw_update_seqno(dev_priv, fifo_state);

out_err:
	return ret;
}

/**
 * vmw_fifo_emit_dummy_legacy_query - emits a dummy query to the fifo using
 * legacy query commands.
 *
 * @dev_priv: The device private structure.
 * @cid: The hardware context id used for the query.
 *
 * See the vmw_fifo_emit_dummy_query documentation.
 */
static int vmw_fifo_emit_dummy_legacy_query(struct vmw_private *dev_priv,
					    uint32_t cid)
{
	/*
	 * A query wait without a preceding query end will
	 * actually finish all queries for this cid
	 * without writing to the query result structure.
	 */

	struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
	struct {
		SVGA3dCmdHeader header;
		SVGA3dCmdWaitForQuery body;
	} *cmd;

	cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));

	if (unlikely(cmd == NULL)) {
		DRM_ERROR("Out of fifo space for dummy query.\n");
		return -ENOMEM;
	}

	cmd->header.id = SVGA_3D_CMD_WAIT_FOR_QUERY;
	cmd->header.size = sizeof(cmd->body);
	cmd->body.cid = cid;
	cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;

	if (bo->mem.mem_type == TTM_PL_VRAM) {
		cmd->body.guestResult.gmrId = SVGA_GMR_FRAMEBUFFER;
		cmd->body.guestResult.offset = bo->offset;
	} else {
		cmd->body.guestResult.gmrId = bo->mem.start;
		cmd->body.guestResult.offset = 0;
	}

	vmw_fifo_commit(dev_priv, sizeof(*cmd));

	return 0;
}

/**
 * vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using
 * guest-backed resource query commands.
 *
 * @dev_priv: The device private structure.
 * @cid: The hardware context id used for the query.
 *
 * See the vmw_fifo_emit_dummy_query documentation.
 */
static int vmw_fifo_emit_dummy_gb_query(struct vmw_private *dev_priv,
					uint32_t cid)
{
	/*
	 * A query wait without a preceding query end will
	 * actually finish all queries for this cid
	 * without writing to the query result structure.
	 */

	struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
	struct {
		SVGA3dCmdHeader header;
		SVGA3dCmdWaitForGBQuery body;
	} *cmd;

	cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));

	if (unlikely(cmd == NULL)) {
		DRM_ERROR("Out of fifo space for dummy query.\n");
		return -ENOMEM;
	}

	cmd->header.id = SVGA_3D_CMD_WAIT_FOR_GB_QUERY;
	cmd->header.size = sizeof(cmd->body);
	cmd->body.cid = cid;
	cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;
	BUG_ON(bo->mem.mem_type != VMW_PL_MOB);
	cmd->body.mobid = bo->mem.start;
	cmd->body.offset = 0;

	vmw_fifo_commit(dev_priv, sizeof(*cmd));

	return 0;
}


/**
 * vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using
 * appropriate resource query commands.
 *
 * @dev_priv: The device private structure.
 * @cid: The hardware context id used for the query.
 *
 * This function is used to emit a dummy occlusion query with
 * no primitives rendered between query begin and query end.
 * It's used to provide a query barrier, in order to know that when
 * this query is finished, all preceding queries are also finished.
 *
 * A Query results structure should have been initialized at the start
 * of the dev_priv->dummy_query_bo buffer object. And that buffer object
 * must also be either reserved or pinned when this function is called.
 *
 * Returns -ENOMEM on failure to reserve fifo space.
 */
int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv,
			      uint32_t cid)
{
	if (dev_priv->has_mob)
		return vmw_fifo_emit_dummy_gb_query(dev_priv, cid);

	return vmw_fifo_emit_dummy_legacy_query(dev_priv, cid);
}
Commit	Line	Data
fb1d9738 JB	1	/**************************************************************************
	2	*
	3	* Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
	4	* All Rights Reserved.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the
	8	* "Software"), to deal in the Software without restriction, including
	9	* without limitation the rights to use, copy, modify, merge, publish,
	10	* distribute, sub license, and/or sell copies of the Software, and to
	11	* permit persons to whom the Software is furnished to do so, subject to
	12	* the following conditions:
	13	*
	14	* The above copyright notice and this permission notice (including the
	15	* next paragraph) shall be included in all copies or substantial portions
	16	* of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	21	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	22	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	23	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
	24	* USE OR OTHER DEALINGS IN THE SOFTWARE.
	25	*
	26	**************************************************************************/
	27
	28	#include "vmwgfx_drv.h"
760285e7 DH	29	#include <drm/drmP.h>
760285e7 DH	30	#include <drm/ttm/ttm_placement.h>
fb1d9738	31
8e19a951 JB	32	bool vmw_fifo_have_3d(struct vmw_private *dev_priv)
	33	{
	34	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	35	uint32_t fifo_min, hwversion;
ebd4c6f6	36	const struct vmw_fifo_state *fifo = &dev_priv->fifo;
8e19a951	37
d8c08b2b TH	38	if (!(dev_priv->capabilities & SVGA_CAP_3D))
	39	return false;
	40
	41	if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
	42	uint32_t result;
	43
	44	if (!dev_priv->has_mob)
	45	return false;
	46
	47	mutex_lock(&dev_priv->hw_mutex);
	48	vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D);
	49	result = vmw_read(dev_priv, SVGA_REG_DEV_CAP);
	50	mutex_unlock(&dev_priv->hw_mutex);
	51
	52	return (result != 0);
	53	}
	54
d7e1958d JB	55	if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
	56	return false;
	57
8e19a951 JB	58	fifo_min = ioread32(fifo_mem + SVGA_FIFO_MIN);
	59	if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int))
	60	return false;
	61
ebd4c6f6 TH	62	hwversion = ioread32(fifo_mem +
	63	((fifo->capabilities &
	64	SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ?
	65	SVGA_FIFO_3D_HWVERSION_REVISED :
	66	SVGA_FIFO_3D_HWVERSION));
	67
8e19a951 JB	68	if (hwversion == 0)
	69	return false;
	70
b7b70024	71	if (hwversion < SVGA3D_HWVERSION_WS8_B1)
8e19a951 JB	72	return false;
8e19a951 JB	73
01e81419 JB	74	/* Non-Screen Object path does not support surfaces */
	75	if (!dev_priv->sou_priv)
	76	return false;
	77
8e19a951 JB	78	return true;
	79	}
	80
d7e1958d JB	81	bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv)
	82	{
	83	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	84	uint32_t caps;
	85
	86	if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
	87	return false;
	88
	89	caps = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
	90	if (caps & SVGA_FIFO_CAP_PITCHLOCK)
	91	return true;
	92
	93	return false;
	94	}
	95
fb1d9738 JB	96	int vmw_fifo_init(struct vmw_private dev_priv, struct vmw_fifo_state fifo)
	97	{
	98	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	99	uint32_t max;
	100	uint32_t min;
	101	uint32_t dummy;
fb1d9738 JB	102
	103	fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE;
	104	fifo->static_buffer = vmalloc(fifo->static_buffer_size);
	105	if (unlikely(fifo->static_buffer == NULL))
	106	return -ENOMEM;
	107
fb1d9738 JB	108	fifo->dynamic_buffer = NULL;
	109	fifo->reserved_size = 0;
	110	fifo->using_bounce_buffer = false;
	111
85b9e487	112	mutex_init(&fifo->fifo_mutex);
fb1d9738 JB	113	init_rwsem(&fifo->rwsem);
	114
	115	/*
	116	* Allow mapping the first page read-only to user-space.
	117	*/
	118
	119	DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH));
	120	DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT));
	121	DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL));
	122
	123	mutex_lock(&dev_priv->hw_mutex);
	124	dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
	125	dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
30c78bb8	126	dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
fb1d9738 JB	127	vmw_write(dev_priv, SVGA_REG_ENABLE, 1);
	128
	129	min = 4;
	130	if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)
	131	min = vmw_read(dev_priv, SVGA_REG_MEM_REGS);
	132	min <<= 2;
	133
	134	if (min < PAGE_SIZE)
	135	min = PAGE_SIZE;
	136
	137	iowrite32(min, fifo_mem + SVGA_FIFO_MIN);
	138	iowrite32(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX);
	139	wmb();
	140	iowrite32(min, fifo_mem + SVGA_FIFO_NEXT_CMD);
	141	iowrite32(min, fifo_mem + SVGA_FIFO_STOP);
	142	iowrite32(0, fifo_mem + SVGA_FIFO_BUSY);
	143	mb();
	144
	145	vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
	146	mutex_unlock(&dev_priv->hw_mutex);
	147
	148	max = ioread32(fifo_mem + SVGA_FIFO_MAX);
	149	min = ioread32(fifo_mem + SVGA_FIFO_MIN);
	150	fifo->capabilities = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
	151
	152	DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
	153	(unsigned int) max,
	154	(unsigned int) min,
	155	(unsigned int) fifo->capabilities);
	156
6bcd8d3c TH	157	atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);
	158	iowrite32(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE);
	159	vmw_marker_queue_init(&fifo->marker_queue);
fb1d9738	160	return vmw_fifo_send_fence(dev_priv, &dummy);
fb1d9738 JB	161	}
fb1d9738 JB	162
2298e804	163	void vmw_fifo_ping_host_locked(struct vmw_private *dev_priv, uint32_t reason)
fb1d9738 JB	164	{
	165	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	166
fb1d9738 JB	167	if (unlikely(ioread32(fifo_mem + SVGA_FIFO_BUSY) == 0)) {
	168	iowrite32(1, fifo_mem + SVGA_FIFO_BUSY);
	169	vmw_write(dev_priv, SVGA_REG_SYNC, reason);
	170	}
2298e804 ML	171	}
	172
	173	void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)
	174	{
	175	mutex_lock(&dev_priv->hw_mutex);
	176
	177	vmw_fifo_ping_host_locked(dev_priv, reason);
fb1d9738 JB	178
	179	mutex_unlock(&dev_priv->hw_mutex);
	180	}
	181
	182	void vmw_fifo_release(struct vmw_private dev_priv, struct vmw_fifo_state fifo)
	183	{
	184	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	185
	186	mutex_lock(&dev_priv->hw_mutex);
	187
f01ea0c3	188	vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
fb1d9738	189	while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0)
f01ea0c3	190	;
fb1d9738	191
6bcd8d3c	192	dev_priv->last_read_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE);
fb1d9738 JB	193
	194	vmw_write(dev_priv, SVGA_REG_CONFIG_DONE,
	195	dev_priv->config_done_state);
	196	vmw_write(dev_priv, SVGA_REG_ENABLE,
	197	dev_priv->enable_state);
30c78bb8 TH	198	vmw_write(dev_priv, SVGA_REG_TRACES,
30c78bb8 TH	199	dev_priv->traces_state);
fb1d9738 JB	200
fb1d9738 JB	201	mutex_unlock(&dev_priv->hw_mutex);
6bcd8d3c	202	vmw_marker_queue_takedown(&fifo->marker_queue);
fb1d9738	203
fb1d9738 JB	204	if (likely(fifo->static_buffer != NULL)) {
	205	vfree(fifo->static_buffer);
	206	fifo->static_buffer = NULL;
	207	}
	208
	209	if (likely(fifo->dynamic_buffer != NULL)) {
	210	vfree(fifo->dynamic_buffer);
	211	fifo->dynamic_buffer = NULL;
	212	}
	213	}
	214
	215	static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)
	216	{
	217	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	218	uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
	219	uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
	220	uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
	221	uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
	222
	223	return ((max - next_cmd) + (stop - min) <= bytes);
	224	}
	225
	226	static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv,
	227	uint32_t bytes, bool interruptible,
	228	unsigned long timeout)
	229	{
	230	int ret = 0;
	231	unsigned long end_jiffies = jiffies + timeout;
	232	DEFINE_WAIT(__wait);
	233
	234	DRM_INFO("Fifo wait noirq.\n");
	235
	236	for (;;) {
	237	prepare_to_wait(&dev_priv->fifo_queue, &__wait,
	238	(interruptible) ?
	239	TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
	240	if (!vmw_fifo_is_full(dev_priv, bytes))
	241	break;
	242	if (time_after_eq(jiffies, end_jiffies)) {
	243	ret = -EBUSY;
	244	DRM_ERROR("SVGA device lockup.\n");
	245	break;
	246	}
	247	schedule_timeout(1);
	248	if (interruptible && signal_pending(current)) {
3d3a5b32	249	ret = -ERESTARTSYS;
fb1d9738 JB	250	break;
	251	}
	252	}
	253	finish_wait(&dev_priv->fifo_queue, &__wait);
	254	wake_up_all(&dev_priv->fifo_queue);
	255	DRM_INFO("Fifo noirq exit.\n");
	256	return ret;
	257	}
	258
	259	static int vmw_fifo_wait(struct vmw_private *dev_priv,
	260	uint32_t bytes, bool interruptible,
	261	unsigned long timeout)
	262	{
	263	long ret = 1L;
	264	unsigned long irq_flags;
	265
	266	if (likely(!vmw_fifo_is_full(dev_priv, bytes)))
	267	return 0;
	268
	269	vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL);
	270	if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
	271	return vmw_fifo_wait_noirq(dev_priv, bytes,
	272	interruptible, timeout);
	273
	274	mutex_lock(&dev_priv->hw_mutex);
	275	if (atomic_add_return(1, &dev_priv->fifo_queue_waiters) > 0) {
	276	spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
	277	outl(SVGA_IRQFLAG_FIFO_PROGRESS,
	278	dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
57c5ee79 TH	279	dev_priv->irq_mask \|= SVGA_IRQFLAG_FIFO_PROGRESS;
57c5ee79 TH	280	vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
fb1d9738 JB	281	spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
	282	}
	283	mutex_unlock(&dev_priv->hw_mutex);
	284
	285	if (interruptible)
	286	ret = wait_event_interruptible_timeout
	287	(dev_priv->fifo_queue,
	288	!vmw_fifo_is_full(dev_priv, bytes), timeout);
	289	else
	290	ret = wait_event_timeout
	291	(dev_priv->fifo_queue,
	292	!vmw_fifo_is_full(dev_priv, bytes), timeout);
	293
3d3a5b32	294	if (unlikely(ret == 0))
fb1d9738 JB	295	ret = -EBUSY;
	296	else if (likely(ret > 0))
	297	ret = 0;
	298
	299	mutex_lock(&dev_priv->hw_mutex);
	300	if (atomic_dec_and_test(&dev_priv->fifo_queue_waiters)) {
	301	spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
57c5ee79 TH	302	dev_priv->irq_mask &= ~SVGA_IRQFLAG_FIFO_PROGRESS;
57c5ee79 TH	303	vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
fb1d9738 JB	304	spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
	305	}
	306	mutex_unlock(&dev_priv->hw_mutex);
	307
	308	return ret;
	309	}
	310
de12d44f JB	311	/**
	312	* Reserve @bytes number of bytes in the fifo.
	313	*
	314	* This function will return NULL (error) on two conditions:
	315	* If it timeouts waiting for fifo space, or if @bytes is larger than the
	316	* available fifo space.
	317	*
	318	* Returns:
	319	* Pointer to the fifo, or null on error (possible hardware hang).
	320	*/
fb1d9738 JB	321	void vmw_fifo_reserve(struct vmw_private dev_priv, uint32_t bytes)
	322	{
	323	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
	324	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	325	uint32_t max;
	326	uint32_t min;
	327	uint32_t next_cmd;
	328	uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
	329	int ret;
	330
85b9e487	331	mutex_lock(&fifo_state->fifo_mutex);
fb1d9738 JB	332	max = ioread32(fifo_mem + SVGA_FIFO_MAX);
	333	min = ioread32(fifo_mem + SVGA_FIFO_MIN);
	334	next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
	335
	336	if (unlikely(bytes >= (max - min)))
	337	goto out_err;
	338
	339	BUG_ON(fifo_state->reserved_size != 0);
	340	BUG_ON(fifo_state->dynamic_buffer != NULL);
	341
	342	fifo_state->reserved_size = bytes;
	343
	344	while (1) {
	345	uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
	346	bool need_bounce = false;
	347	bool reserve_in_place = false;
	348
	349	if (next_cmd >= stop) {
	350	if (likely((next_cmd + bytes < max \|\|
	351	(next_cmd + bytes == max && stop > min))))
	352	reserve_in_place = true;
	353
	354	else if (vmw_fifo_is_full(dev_priv, bytes)) {
	355	ret = vmw_fifo_wait(dev_priv, bytes,
	356	false, 3 * HZ);
	357	if (unlikely(ret != 0))
	358	goto out_err;
	359	} else
	360	need_bounce = true;
	361
	362	} else {
	363
	364	if (likely((next_cmd + bytes < stop)))
	365	reserve_in_place = true;
	366	else {
	367	ret = vmw_fifo_wait(dev_priv, bytes,
	368	false, 3 * HZ);
	369	if (unlikely(ret != 0))
	370	goto out_err;
	371	}
	372	}
	373
	374	if (reserve_in_place) {
	375	if (reserveable \|\| bytes <= sizeof(uint32_t)) {
	376	fifo_state->using_bounce_buffer = false;
	377
	378	if (reserveable)
	379	iowrite32(bytes, fifo_mem +
	380	SVGA_FIFO_RESERVED);
	381	return fifo_mem + (next_cmd >> 2);
	382	} else {
	383	need_bounce = true;
	384	}
	385	}
	386
	387	if (need_bounce) {
	388	fifo_state->using_bounce_buffer = true;
	389	if (bytes < fifo_state->static_buffer_size)
	390	return fifo_state->static_buffer;
	391	else {
	392	fifo_state->dynamic_buffer = vmalloc(bytes);
	393	return fifo_state->dynamic_buffer;
	394	}
	395	}
396	}
397	out_err:
398	fifo_state->reserved_size = 0;
85b9e487	399	mutex_unlock(&fifo_state->fifo_mutex);
fb1d9738 JB	400	return NULL;
	401	}
	402
	403	static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state,
	404	__le32 __iomem *fifo_mem,
	405	uint32_t next_cmd,
	406	uint32_t max, uint32_t min, uint32_t bytes)
	407	{
	408	uint32_t chunk_size = max - next_cmd;
	409	uint32_t rest;
	410	uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
	411	fifo_state->dynamic_buffer : fifo_state->static_buffer;
	412
	413	if (bytes < chunk_size)
	414	chunk_size = bytes;
	415
	416	iowrite32(bytes, fifo_mem + SVGA_FIFO_RESERVED);
	417	mb();
	418	memcpy_toio(fifo_mem + (next_cmd >> 2), buffer, chunk_size);
	419	rest = bytes - chunk_size;
	420	if (rest)
	421	memcpy_toio(fifo_mem + (min >> 2), buffer + (chunk_size >> 2),
	422	rest);
	423	}
	424
	425	static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state,
	426	__le32 __iomem *fifo_mem,
	427	uint32_t next_cmd,
	428	uint32_t max, uint32_t min, uint32_t bytes)
	429	{
	430	uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
	431	fifo_state->dynamic_buffer : fifo_state->static_buffer;
	432
	433	while (bytes > 0) {
	434	iowrite32(*buffer++, fifo_mem + (next_cmd >> 2));
	435	next_cmd += sizeof(uint32_t);
	436	if (unlikely(next_cmd == max))
	437	next_cmd = min;
	438	mb();
	439	iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
	440	mb();
	441	bytes -= sizeof(uint32_t);
	442	}
	443	}
	444
	445	void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
	446	{
	447	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
	448	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	449	uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
	450	uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
	451	uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
	452	bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
	453
	454	BUG_ON((bytes & 3) != 0);
	455	BUG_ON(bytes > fifo_state->reserved_size);
	456
	457	fifo_state->reserved_size = 0;
	458
	459	if (fifo_state->using_bounce_buffer) {
	460	if (reserveable)
	461	vmw_fifo_res_copy(fifo_state, fifo_mem,
	462	next_cmd, max, min, bytes);
	463	else
464	vmw_fifo_slow_copy(fifo_state, fifo_mem,
465	next_cmd, max, min, bytes);
466
467	if (fifo_state->dynamic_buffer) {
468	vfree(fifo_state->dynamic_buffer);
469	fifo_state->dynamic_buffer = NULL;
470	}
471
472	}
473
85b9e487	474	down_write(&fifo_state->rwsem);
fb1d9738 JB	475	if (fifo_state->using_bounce_buffer \|\| reserveable) {
	476	next_cmd += bytes;
	477	if (next_cmd >= max)
	478	next_cmd -= max - min;
	479	mb();
	480	iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
	481	}
	482
	483	if (reserveable)
	484	iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED);
	485	mb();
fb1d9738	486	up_write(&fifo_state->rwsem);
85b9e487 TH	487	vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
85b9e487 TH	488	mutex_unlock(&fifo_state->fifo_mutex);
fb1d9738 JB	489	}
fb1d9738 JB	490
6bcd8d3c	491	int vmw_fifo_send_fence(struct vmw_private dev_priv, uint32_t seqno)
fb1d9738 JB	492	{
	493	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
	494	struct svga_fifo_cmd_fence *cmd_fence;
	495	void *fm;
	496	int ret = 0;
	497	uint32_t bytes = sizeof(__le32) + sizeof(*cmd_fence);
	498
	499	fm = vmw_fifo_reserve(dev_priv, bytes);
	500	if (unlikely(fm == NULL)) {
6bcd8d3c	501	*seqno = atomic_read(&dev_priv->marker_seq);
fb1d9738	502	ret = -ENOMEM;
6bcd8d3c	503	(void)vmw_fallback_wait(dev_priv, false, true, *seqno,
fb1d9738 JB	504	false, 3*HZ);
	505	goto out_err;
	506	}
	507
	508	do {
6bcd8d3c TH	509	*seqno = atomic_add_return(1, &dev_priv->marker_seq);
6bcd8d3c TH	510	} while (*seqno == 0);
fb1d9738 JB	511
	512	if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) {
	513
	514	/*
	515	* Don't request hardware to send a fence. The
	516	* waiting code in vmwgfx_irq.c will emulate this.
	517	*/
	518
	519	vmw_fifo_commit(dev_priv, 0);
	520	return 0;
	521	}
	522
	523	(__le32 ) fm = cpu_to_le32(SVGA_CMD_FENCE);
	524	cmd_fence = (struct svga_fifo_cmd_fence *)
	525	((unsigned long)fm + sizeof(__le32));
	526
6bcd8d3c	527	iowrite32(*seqno, &cmd_fence->fence);
fb1d9738	528	vmw_fifo_commit(dev_priv, bytes);
6bcd8d3c TH	529	(void) vmw_marker_push(&fifo_state->marker_queue, *seqno);
6bcd8d3c TH	530	vmw_update_seqno(dev_priv, fifo_state);
fb1d9738 JB	531
	532	out_err:
	533	return ret;
	534	}
e2fa3a76 TH	535
e2fa3a76 TH	536	/**
ddcda24e TH	537	* vmw_fifo_emit_dummy_legacy_query - emits a dummy query to the fifo using
ddcda24e TH	538	* legacy query commands.
e2fa3a76 TH	539	*
	540	* @dev_priv: The device private structure.
	541	* @cid: The hardware context id used for the query.
	542	*
ddcda24e	543	* See the vmw_fifo_emit_dummy_query documentation.
e2fa3a76	544	*/
ddcda24e TH	545	static int vmw_fifo_emit_dummy_legacy_query(struct vmw_private *dev_priv,
ddcda24e TH	546	uint32_t cid)
e2fa3a76 TH	547	{
	548	/*
	549	* A query wait without a preceding query end will
	550	* actually finish all queries for this cid
	551	* without writing to the query result structure.
	552	*/
	553
	554	struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
	555	struct {
	556	SVGA3dCmdHeader header;
	557	SVGA3dCmdWaitForQuery body;
	558	} *cmd;
	559
	560	cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
	561
	562	if (unlikely(cmd == NULL)) {
	563	DRM_ERROR("Out of fifo space for dummy query.\n");
	564	return -ENOMEM;
	565	}
	566
	567	cmd->header.id = SVGA_3D_CMD_WAIT_FOR_QUERY;
	568	cmd->header.size = sizeof(cmd->body);
	569	cmd->body.cid = cid;
	570	cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;
	571
	572	if (bo->mem.mem_type == TTM_PL_VRAM) {
	573	cmd->body.guestResult.gmrId = SVGA_GMR_FRAMEBUFFER;
	574	cmd->body.guestResult.offset = bo->offset;
	575	} else {
	576	cmd->body.guestResult.gmrId = bo->mem.start;
	577	cmd->body.guestResult.offset = 0;
	578	}
	579
	580	vmw_fifo_commit(dev_priv, sizeof(*cmd));
	581
	582	return 0;
	583	}
ddcda24e TH	584
	585	/**
	586	* vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using
	587	* guest-backed resource query commands.
	588	*
	589	* @dev_priv: The device private structure.
	590	* @cid: The hardware context id used for the query.
	591	*
	592	* See the vmw_fifo_emit_dummy_query documentation.
	593	*/
	594	static int vmw_fifo_emit_dummy_gb_query(struct vmw_private *dev_priv,
	595	uint32_t cid)
	596	{
	597	/*
	598	* A query wait without a preceding query end will
	599	* actually finish all queries for this cid
	600	* without writing to the query result structure.
	601	*/
	602
	603	struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
	604	struct {
	605	SVGA3dCmdHeader header;
	606	SVGA3dCmdWaitForGBQuery body;
	607	} *cmd;
	608
	609	cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
	610
	611	if (unlikely(cmd == NULL)) {
	612	DRM_ERROR("Out of fifo space for dummy query.\n");
	613	return -ENOMEM;
	614	}
	615
	616	cmd->header.id = SVGA_3D_CMD_WAIT_FOR_GB_QUERY;
	617	cmd->header.size = sizeof(cmd->body);
	618	cmd->body.cid = cid;
	619	cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;
	620	BUG_ON(bo->mem.mem_type != VMW_PL_MOB);
	621	cmd->body.mobid = bo->mem.start;
	622	cmd->body.offset = 0;
	623
	624	vmw_fifo_commit(dev_priv, sizeof(*cmd));
	625
	626	return 0;
	627	}
	628
	629
	630	/**
	631	* vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using
	632	* appropriate resource query commands.
	633	*
	634	* @dev_priv: The device private structure.
	635	* @cid: The hardware context id used for the query.
	636	*
	637	* This function is used to emit a dummy occlusion query with
	638	* no primitives rendered between query begin and query end.
	639	* It's used to provide a query barrier, in order to know that when
	640	* this query is finished, all preceding queries are also finished.
	641	*
	642	* A Query results structure should have been initialized at the start
	643	* of the dev_priv->dummy_query_bo buffer object. And that buffer object
	644	* must also be either reserved or pinned when this function is called.
	645	*
	646	* Returns -ENOMEM on failure to reserve fifo space.
	647	*/
648	int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv,
649	uint32_t cid)
650	{
651	if (dev_priv->has_mob)
652	return vmw_fifo_emit_dummy_gb_query(dev_priv, cid);
653
654	return vmw_fifo_emit_dummy_legacy_query(dev_priv, cid);
655	}