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fb1d9738 JB |
1 | /************************************************************************** |
2 | * | |
54fbde8a | 3 | * Copyright © 2009-2015 VMware, Inc., Palo Alto, CA., USA |
fb1d9738 JB |
4 | * All Rights Reserved. |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the | |
8 | * "Software"), to deal in the Software without restriction, including | |
9 | * without limitation the rights to use, copy, modify, merge, publish, | |
10 | * distribute, sub license, and/or sell copies of the Software, and to | |
11 | * permit persons to whom the Software is furnished to do so, subject to | |
12 | * the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice (including the | |
15 | * next paragraph) shall be included in all copies or substantial portions | |
16 | * of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | **************************************************************************/ | |
27 | ||
28 | #include "vmwgfx_drv.h" | |
760285e7 DH |
29 | #include <drm/drmP.h> |
30 | #include <drm/ttm/ttm_placement.h> | |
fb1d9738 | 31 | |
d80efd5c TH |
32 | struct vmw_temp_set_context { |
33 | SVGA3dCmdHeader header; | |
34 | SVGA3dCmdDXTempSetContext body; | |
35 | }; | |
36 | ||
8e19a951 JB |
37 | bool vmw_fifo_have_3d(struct vmw_private *dev_priv) |
38 | { | |
b76ff5ea | 39 | u32 *fifo_mem = dev_priv->mmio_virt; |
8e19a951 | 40 | uint32_t fifo_min, hwversion; |
ebd4c6f6 | 41 | const struct vmw_fifo_state *fifo = &dev_priv->fifo; |
8e19a951 | 42 | |
d8c08b2b TH |
43 | if (!(dev_priv->capabilities & SVGA_CAP_3D)) |
44 | return false; | |
45 | ||
46 | if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { | |
47 | uint32_t result; | |
48 | ||
49 | if (!dev_priv->has_mob) | |
50 | return false; | |
51 | ||
496eb6fd | 52 | spin_lock(&dev_priv->cap_lock); |
d8c08b2b TH |
53 | vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D); |
54 | result = vmw_read(dev_priv, SVGA_REG_DEV_CAP); | |
496eb6fd | 55 | spin_unlock(&dev_priv->cap_lock); |
d8c08b2b TH |
56 | |
57 | return (result != 0); | |
58 | } | |
59 | ||
d7e1958d JB |
60 | if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)) |
61 | return false; | |
62 | ||
b76ff5ea | 63 | fifo_min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN); |
8e19a951 JB |
64 | if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int)) |
65 | return false; | |
66 | ||
b76ff5ea TH |
67 | hwversion = vmw_mmio_read(fifo_mem + |
68 | ((fifo->capabilities & | |
69 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ? | |
70 | SVGA_FIFO_3D_HWVERSION_REVISED : | |
71 | SVGA_FIFO_3D_HWVERSION)); | |
ebd4c6f6 | 72 | |
8e19a951 JB |
73 | if (hwversion == 0) |
74 | return false; | |
75 | ||
b7b70024 | 76 | if (hwversion < SVGA3D_HWVERSION_WS8_B1) |
8e19a951 JB |
77 | return false; |
78 | ||
c8261a96 SY |
79 | /* Legacy Display Unit does not support surfaces */ |
80 | if (dev_priv->active_display_unit == vmw_du_legacy) | |
01e81419 JB |
81 | return false; |
82 | ||
8e19a951 JB |
83 | return true; |
84 | } | |
85 | ||
d7e1958d JB |
86 | bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv) |
87 | { | |
b76ff5ea | 88 | u32 *fifo_mem = dev_priv->mmio_virt; |
d7e1958d JB |
89 | uint32_t caps; |
90 | ||
91 | if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)) | |
92 | return false; | |
93 | ||
b76ff5ea | 94 | caps = vmw_mmio_read(fifo_mem + SVGA_FIFO_CAPABILITIES); |
d7e1958d JB |
95 | if (caps & SVGA_FIFO_CAP_PITCHLOCK) |
96 | return true; | |
97 | ||
98 | return false; | |
99 | } | |
100 | ||
fb1d9738 JB |
101 | int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) |
102 | { | |
b76ff5ea | 103 | u32 *fifo_mem = dev_priv->mmio_virt; |
fb1d9738 JB |
104 | uint32_t max; |
105 | uint32_t min; | |
fb1d9738 | 106 | |
d80efd5c | 107 | fifo->dx = false; |
fb1d9738 JB |
108 | fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE; |
109 | fifo->static_buffer = vmalloc(fifo->static_buffer_size); | |
110 | if (unlikely(fifo->static_buffer == NULL)) | |
111 | return -ENOMEM; | |
112 | ||
fb1d9738 JB |
113 | fifo->dynamic_buffer = NULL; |
114 | fifo->reserved_size = 0; | |
115 | fifo->using_bounce_buffer = false; | |
116 | ||
85b9e487 | 117 | mutex_init(&fifo->fifo_mutex); |
fb1d9738 JB |
118 | init_rwsem(&fifo->rwsem); |
119 | ||
fb1d9738 JB |
120 | DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH)); |
121 | DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT)); | |
122 | DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL)); | |
123 | ||
fb1d9738 JB |
124 | dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); |
125 | dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); | |
30c78bb8 | 126 | dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); |
153b3d5b | 127 | |
8ce75f8a SY |
128 | vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE | |
129 | SVGA_REG_ENABLE_HIDE); | |
153b3d5b | 130 | vmw_write(dev_priv, SVGA_REG_TRACES, 0); |
fb1d9738 JB |
131 | |
132 | min = 4; | |
133 | if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO) | |
134 | min = vmw_read(dev_priv, SVGA_REG_MEM_REGS); | |
135 | min <<= 2; | |
136 | ||
137 | if (min < PAGE_SIZE) | |
138 | min = PAGE_SIZE; | |
139 | ||
b76ff5ea TH |
140 | vmw_mmio_write(min, fifo_mem + SVGA_FIFO_MIN); |
141 | vmw_mmio_write(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX); | |
fb1d9738 | 142 | wmb(); |
b76ff5ea TH |
143 | vmw_mmio_write(min, fifo_mem + SVGA_FIFO_NEXT_CMD); |
144 | vmw_mmio_write(min, fifo_mem + SVGA_FIFO_STOP); | |
145 | vmw_mmio_write(0, fifo_mem + SVGA_FIFO_BUSY); | |
fb1d9738 JB |
146 | mb(); |
147 | ||
148 | vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1); | |
fb1d9738 | 149 | |
b76ff5ea TH |
150 | max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX); |
151 | min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN); | |
152 | fifo->capabilities = vmw_mmio_read(fifo_mem + SVGA_FIFO_CAPABILITIES); | |
fb1d9738 JB |
153 | |
154 | DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n", | |
155 | (unsigned int) max, | |
156 | (unsigned int) min, | |
157 | (unsigned int) fifo->capabilities); | |
158 | ||
6bcd8d3c | 159 | atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno); |
b76ff5ea | 160 | vmw_mmio_write(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE); |
6bcd8d3c | 161 | vmw_marker_queue_init(&fifo->marker_queue); |
153b3d5b TH |
162 | |
163 | return 0; | |
fb1d9738 JB |
164 | } |
165 | ||
496eb6fd | 166 | void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason) |
fb1d9738 | 167 | { |
b76ff5ea | 168 | u32 *fifo_mem = dev_priv->mmio_virt; |
fb1d9738 | 169 | |
b76ff5ea TH |
170 | preempt_disable(); |
171 | if (cmpxchg(fifo_mem + SVGA_FIFO_BUSY, 0, 1) == 0) | |
fb1d9738 | 172 | vmw_write(dev_priv, SVGA_REG_SYNC, reason); |
b76ff5ea | 173 | preempt_enable(); |
fb1d9738 JB |
174 | } |
175 | ||
176 | void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) | |
177 | { | |
b76ff5ea | 178 | u32 *fifo_mem = dev_priv->mmio_virt; |
fb1d9738 | 179 | |
f01ea0c3 | 180 | vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC); |
fb1d9738 | 181 | while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0) |
f01ea0c3 | 182 | ; |
fb1d9738 | 183 | |
b76ff5ea | 184 | dev_priv->last_read_seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE); |
fb1d9738 JB |
185 | |
186 | vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, | |
187 | dev_priv->config_done_state); | |
188 | vmw_write(dev_priv, SVGA_REG_ENABLE, | |
189 | dev_priv->enable_state); | |
30c78bb8 TH |
190 | vmw_write(dev_priv, SVGA_REG_TRACES, |
191 | dev_priv->traces_state); | |
fb1d9738 | 192 | |
6bcd8d3c | 193 | vmw_marker_queue_takedown(&fifo->marker_queue); |
fb1d9738 | 194 | |
fb1d9738 JB |
195 | if (likely(fifo->static_buffer != NULL)) { |
196 | vfree(fifo->static_buffer); | |
197 | fifo->static_buffer = NULL; | |
198 | } | |
199 | ||
200 | if (likely(fifo->dynamic_buffer != NULL)) { | |
201 | vfree(fifo->dynamic_buffer); | |
202 | fifo->dynamic_buffer = NULL; | |
203 | } | |
204 | } | |
205 | ||
206 | static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes) | |
207 | { | |
b76ff5ea TH |
208 | u32 *fifo_mem = dev_priv->mmio_virt; |
209 | uint32_t max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX); | |
210 | uint32_t next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD); | |
211 | uint32_t min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN); | |
212 | uint32_t stop = vmw_mmio_read(fifo_mem + SVGA_FIFO_STOP); | |
fb1d9738 JB |
213 | |
214 | return ((max - next_cmd) + (stop - min) <= bytes); | |
215 | } | |
216 | ||
217 | static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv, | |
218 | uint32_t bytes, bool interruptible, | |
219 | unsigned long timeout) | |
220 | { | |
221 | int ret = 0; | |
222 | unsigned long end_jiffies = jiffies + timeout; | |
223 | DEFINE_WAIT(__wait); | |
224 | ||
225 | DRM_INFO("Fifo wait noirq.\n"); | |
226 | ||
227 | for (;;) { | |
228 | prepare_to_wait(&dev_priv->fifo_queue, &__wait, | |
229 | (interruptible) ? | |
230 | TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); | |
231 | if (!vmw_fifo_is_full(dev_priv, bytes)) | |
232 | break; | |
233 | if (time_after_eq(jiffies, end_jiffies)) { | |
234 | ret = -EBUSY; | |
235 | DRM_ERROR("SVGA device lockup.\n"); | |
236 | break; | |
237 | } | |
238 | schedule_timeout(1); | |
239 | if (interruptible && signal_pending(current)) { | |
3d3a5b32 | 240 | ret = -ERESTARTSYS; |
fb1d9738 JB |
241 | break; |
242 | } | |
243 | } | |
244 | finish_wait(&dev_priv->fifo_queue, &__wait); | |
245 | wake_up_all(&dev_priv->fifo_queue); | |
246 | DRM_INFO("Fifo noirq exit.\n"); | |
247 | return ret; | |
248 | } | |
249 | ||
250 | static int vmw_fifo_wait(struct vmw_private *dev_priv, | |
251 | uint32_t bytes, bool interruptible, | |
252 | unsigned long timeout) | |
253 | { | |
254 | long ret = 1L; | |
255 | unsigned long irq_flags; | |
256 | ||
257 | if (likely(!vmw_fifo_is_full(dev_priv, bytes))) | |
258 | return 0; | |
259 | ||
260 | vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL); | |
261 | if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK)) | |
262 | return vmw_fifo_wait_noirq(dev_priv, bytes, | |
263 | interruptible, timeout); | |
264 | ||
496eb6fd | 265 | spin_lock(&dev_priv->waiter_lock); |
fb1d9738 JB |
266 | if (atomic_add_return(1, &dev_priv->fifo_queue_waiters) > 0) { |
267 | spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); | |
268 | outl(SVGA_IRQFLAG_FIFO_PROGRESS, | |
269 | dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); | |
57c5ee79 TH |
270 | dev_priv->irq_mask |= SVGA_IRQFLAG_FIFO_PROGRESS; |
271 | vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); | |
fb1d9738 JB |
272 | spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); |
273 | } | |
496eb6fd | 274 | spin_unlock(&dev_priv->waiter_lock); |
fb1d9738 JB |
275 | |
276 | if (interruptible) | |
277 | ret = wait_event_interruptible_timeout | |
278 | (dev_priv->fifo_queue, | |
279 | !vmw_fifo_is_full(dev_priv, bytes), timeout); | |
280 | else | |
281 | ret = wait_event_timeout | |
282 | (dev_priv->fifo_queue, | |
283 | !vmw_fifo_is_full(dev_priv, bytes), timeout); | |
284 | ||
3d3a5b32 | 285 | if (unlikely(ret == 0)) |
fb1d9738 JB |
286 | ret = -EBUSY; |
287 | else if (likely(ret > 0)) | |
288 | ret = 0; | |
289 | ||
496eb6fd | 290 | spin_lock(&dev_priv->waiter_lock); |
fb1d9738 JB |
291 | if (atomic_dec_and_test(&dev_priv->fifo_queue_waiters)) { |
292 | spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); | |
57c5ee79 TH |
293 | dev_priv->irq_mask &= ~SVGA_IRQFLAG_FIFO_PROGRESS; |
294 | vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); | |
fb1d9738 JB |
295 | spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); |
296 | } | |
496eb6fd | 297 | spin_unlock(&dev_priv->waiter_lock); |
fb1d9738 JB |
298 | |
299 | return ret; | |
300 | } | |
301 | ||
de12d44f JB |
302 | /** |
303 | * Reserve @bytes number of bytes in the fifo. | |
304 | * | |
305 | * This function will return NULL (error) on two conditions: | |
306 | * If it timeouts waiting for fifo space, or if @bytes is larger than the | |
307 | * available fifo space. | |
308 | * | |
309 | * Returns: | |
310 | * Pointer to the fifo, or null on error (possible hardware hang). | |
311 | */ | |
3eab3d9e TH |
312 | static void *vmw_local_fifo_reserve(struct vmw_private *dev_priv, |
313 | uint32_t bytes) | |
fb1d9738 JB |
314 | { |
315 | struct vmw_fifo_state *fifo_state = &dev_priv->fifo; | |
b76ff5ea | 316 | u32 *fifo_mem = dev_priv->mmio_virt; |
fb1d9738 JB |
317 | uint32_t max; |
318 | uint32_t min; | |
319 | uint32_t next_cmd; | |
320 | uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE; | |
321 | int ret; | |
322 | ||
85b9e487 | 323 | mutex_lock(&fifo_state->fifo_mutex); |
b76ff5ea TH |
324 | max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX); |
325 | min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN); | |
326 | next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD); | |
fb1d9738 JB |
327 | |
328 | if (unlikely(bytes >= (max - min))) | |
329 | goto out_err; | |
330 | ||
331 | BUG_ON(fifo_state->reserved_size != 0); | |
332 | BUG_ON(fifo_state->dynamic_buffer != NULL); | |
333 | ||
334 | fifo_state->reserved_size = bytes; | |
335 | ||
336 | while (1) { | |
b76ff5ea | 337 | uint32_t stop = vmw_mmio_read(fifo_mem + SVGA_FIFO_STOP); |
fb1d9738 JB |
338 | bool need_bounce = false; |
339 | bool reserve_in_place = false; | |
340 | ||
341 | if (next_cmd >= stop) { | |
342 | if (likely((next_cmd + bytes < max || | |
343 | (next_cmd + bytes == max && stop > min)))) | |
344 | reserve_in_place = true; | |
345 | ||
346 | else if (vmw_fifo_is_full(dev_priv, bytes)) { | |
347 | ret = vmw_fifo_wait(dev_priv, bytes, | |
348 | false, 3 * HZ); | |
349 | if (unlikely(ret != 0)) | |
350 | goto out_err; | |
351 | } else | |
352 | need_bounce = true; | |
353 | ||
354 | } else { | |
355 | ||
356 | if (likely((next_cmd + bytes < stop))) | |
357 | reserve_in_place = true; | |
358 | else { | |
359 | ret = vmw_fifo_wait(dev_priv, bytes, | |
360 | false, 3 * HZ); | |
361 | if (unlikely(ret != 0)) | |
362 | goto out_err; | |
363 | } | |
364 | } | |
365 | ||
366 | if (reserve_in_place) { | |
367 | if (reserveable || bytes <= sizeof(uint32_t)) { | |
368 | fifo_state->using_bounce_buffer = false; | |
369 | ||
370 | if (reserveable) | |
b76ff5ea TH |
371 | vmw_mmio_write(bytes, fifo_mem + |
372 | SVGA_FIFO_RESERVED); | |
b9eb1a61 TH |
373 | return (void __force *) (fifo_mem + |
374 | (next_cmd >> 2)); | |
fb1d9738 JB |
375 | } else { |
376 | need_bounce = true; | |
377 | } | |
378 | } | |
379 | ||
380 | if (need_bounce) { | |
381 | fifo_state->using_bounce_buffer = true; | |
382 | if (bytes < fifo_state->static_buffer_size) | |
383 | return fifo_state->static_buffer; | |
384 | else { | |
385 | fifo_state->dynamic_buffer = vmalloc(bytes); | |
386 | return fifo_state->dynamic_buffer; | |
387 | } | |
388 | } | |
389 | } | |
390 | out_err: | |
391 | fifo_state->reserved_size = 0; | |
85b9e487 | 392 | mutex_unlock(&fifo_state->fifo_mutex); |
3eab3d9e | 393 | |
fb1d9738 JB |
394 | return NULL; |
395 | } | |
396 | ||
d80efd5c TH |
397 | void *vmw_fifo_reserve_dx(struct vmw_private *dev_priv, uint32_t bytes, |
398 | int ctx_id) | |
3eab3d9e TH |
399 | { |
400 | void *ret; | |
401 | ||
402 | if (dev_priv->cman) | |
403 | ret = vmw_cmdbuf_reserve(dev_priv->cman, bytes, | |
d80efd5c TH |
404 | ctx_id, false, NULL); |
405 | else if (ctx_id == SVGA3D_INVALID_ID) | |
3eab3d9e | 406 | ret = vmw_local_fifo_reserve(dev_priv, bytes); |
d80efd5c TH |
407 | else { |
408 | WARN_ON("Command buffer has not been allocated.\n"); | |
409 | ret = NULL; | |
410 | } | |
3eab3d9e TH |
411 | if (IS_ERR_OR_NULL(ret)) { |
412 | DRM_ERROR("Fifo reserve failure of %u bytes.\n", | |
413 | (unsigned) bytes); | |
414 | dump_stack(); | |
415 | return NULL; | |
416 | } | |
417 | ||
418 | return ret; | |
419 | } | |
420 | ||
fb1d9738 | 421 | static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state, |
b76ff5ea | 422 | u32 *fifo_mem, |
fb1d9738 JB |
423 | uint32_t next_cmd, |
424 | uint32_t max, uint32_t min, uint32_t bytes) | |
425 | { | |
426 | uint32_t chunk_size = max - next_cmd; | |
427 | uint32_t rest; | |
428 | uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ? | |
429 | fifo_state->dynamic_buffer : fifo_state->static_buffer; | |
430 | ||
431 | if (bytes < chunk_size) | |
432 | chunk_size = bytes; | |
433 | ||
b76ff5ea | 434 | vmw_mmio_write(bytes, fifo_mem + SVGA_FIFO_RESERVED); |
fb1d9738 | 435 | mb(); |
b76ff5ea | 436 | memcpy(fifo_mem + (next_cmd >> 2), buffer, chunk_size); |
fb1d9738 JB |
437 | rest = bytes - chunk_size; |
438 | if (rest) | |
b76ff5ea | 439 | memcpy(fifo_mem + (min >> 2), buffer + (chunk_size >> 2), rest); |
fb1d9738 JB |
440 | } |
441 | ||
442 | static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state, | |
b76ff5ea | 443 | u32 *fifo_mem, |
fb1d9738 JB |
444 | uint32_t next_cmd, |
445 | uint32_t max, uint32_t min, uint32_t bytes) | |
446 | { | |
447 | uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ? | |
448 | fifo_state->dynamic_buffer : fifo_state->static_buffer; | |
449 | ||
450 | while (bytes > 0) { | |
b76ff5ea | 451 | vmw_mmio_write(*buffer++, fifo_mem + (next_cmd >> 2)); |
fb1d9738 JB |
452 | next_cmd += sizeof(uint32_t); |
453 | if (unlikely(next_cmd == max)) | |
454 | next_cmd = min; | |
455 | mb(); | |
b76ff5ea | 456 | vmw_mmio_write(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD); |
fb1d9738 JB |
457 | mb(); |
458 | bytes -= sizeof(uint32_t); | |
459 | } | |
460 | } | |
461 | ||
b9eb1a61 | 462 | static void vmw_local_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes) |
fb1d9738 JB |
463 | { |
464 | struct vmw_fifo_state *fifo_state = &dev_priv->fifo; | |
b76ff5ea TH |
465 | u32 *fifo_mem = dev_priv->mmio_virt; |
466 | uint32_t next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD); | |
467 | uint32_t max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX); | |
468 | uint32_t min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN); | |
fb1d9738 JB |
469 | bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE; |
470 | ||
d80efd5c TH |
471 | if (fifo_state->dx) |
472 | bytes += sizeof(struct vmw_temp_set_context); | |
473 | ||
474 | fifo_state->dx = false; | |
fb1d9738 JB |
475 | BUG_ON((bytes & 3) != 0); |
476 | BUG_ON(bytes > fifo_state->reserved_size); | |
477 | ||
478 | fifo_state->reserved_size = 0; | |
479 | ||
480 | if (fifo_state->using_bounce_buffer) { | |
481 | if (reserveable) | |
482 | vmw_fifo_res_copy(fifo_state, fifo_mem, | |
483 | next_cmd, max, min, bytes); | |
484 | else | |
485 | vmw_fifo_slow_copy(fifo_state, fifo_mem, | |
486 | next_cmd, max, min, bytes); | |
487 | ||
488 | if (fifo_state->dynamic_buffer) { | |
489 | vfree(fifo_state->dynamic_buffer); | |
490 | fifo_state->dynamic_buffer = NULL; | |
491 | } | |
492 | ||
493 | } | |
494 | ||
85b9e487 | 495 | down_write(&fifo_state->rwsem); |
fb1d9738 JB |
496 | if (fifo_state->using_bounce_buffer || reserveable) { |
497 | next_cmd += bytes; | |
498 | if (next_cmd >= max) | |
499 | next_cmd -= max - min; | |
500 | mb(); | |
b76ff5ea | 501 | vmw_mmio_write(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD); |
fb1d9738 JB |
502 | } |
503 | ||
504 | if (reserveable) | |
b76ff5ea | 505 | vmw_mmio_write(0, fifo_mem + SVGA_FIFO_RESERVED); |
fb1d9738 | 506 | mb(); |
fb1d9738 | 507 | up_write(&fifo_state->rwsem); |
85b9e487 TH |
508 | vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC); |
509 | mutex_unlock(&fifo_state->fifo_mutex); | |
fb1d9738 JB |
510 | } |
511 | ||
3eab3d9e TH |
512 | void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes) |
513 | { | |
514 | if (dev_priv->cman) | |
515 | vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, false); | |
516 | else | |
517 | vmw_local_fifo_commit(dev_priv, bytes); | |
518 | } | |
519 | ||
520 | ||
521 | /** | |
522 | * vmw_fifo_commit_flush - Commit fifo space and flush any buffered commands. | |
523 | * | |
524 | * @dev_priv: Pointer to device private structure. | |
525 | * @bytes: Number of bytes to commit. | |
526 | */ | |
d80efd5c | 527 | void vmw_fifo_commit_flush(struct vmw_private *dev_priv, uint32_t bytes) |
3eab3d9e TH |
528 | { |
529 | if (dev_priv->cman) | |
530 | vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, true); | |
531 | else | |
532 | vmw_local_fifo_commit(dev_priv, bytes); | |
533 | } | |
534 | ||
535 | /** | |
536 | * vmw_fifo_flush - Flush any buffered commands and make sure command processing | |
537 | * starts. | |
538 | * | |
539 | * @dev_priv: Pointer to device private structure. | |
540 | * @interruptible: Whether to wait interruptible if function needs to sleep. | |
541 | */ | |
542 | int vmw_fifo_flush(struct vmw_private *dev_priv, bool interruptible) | |
543 | { | |
544 | might_sleep(); | |
545 | ||
546 | if (dev_priv->cman) | |
547 | return vmw_cmdbuf_cur_flush(dev_priv->cman, interruptible); | |
548 | else | |
549 | return 0; | |
550 | } | |
551 | ||
6bcd8d3c | 552 | int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno) |
fb1d9738 JB |
553 | { |
554 | struct vmw_fifo_state *fifo_state = &dev_priv->fifo; | |
555 | struct svga_fifo_cmd_fence *cmd_fence; | |
b9eb1a61 | 556 | u32 *fm; |
fb1d9738 | 557 | int ret = 0; |
b9eb1a61 | 558 | uint32_t bytes = sizeof(u32) + sizeof(*cmd_fence); |
fb1d9738 JB |
559 | |
560 | fm = vmw_fifo_reserve(dev_priv, bytes); | |
561 | if (unlikely(fm == NULL)) { | |
6bcd8d3c | 562 | *seqno = atomic_read(&dev_priv->marker_seq); |
fb1d9738 | 563 | ret = -ENOMEM; |
6bcd8d3c | 564 | (void)vmw_fallback_wait(dev_priv, false, true, *seqno, |
fb1d9738 JB |
565 | false, 3*HZ); |
566 | goto out_err; | |
567 | } | |
568 | ||
569 | do { | |
6bcd8d3c TH |
570 | *seqno = atomic_add_return(1, &dev_priv->marker_seq); |
571 | } while (*seqno == 0); | |
fb1d9738 JB |
572 | |
573 | if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) { | |
574 | ||
575 | /* | |
576 | * Don't request hardware to send a fence. The | |
577 | * waiting code in vmwgfx_irq.c will emulate this. | |
578 | */ | |
579 | ||
580 | vmw_fifo_commit(dev_priv, 0); | |
581 | return 0; | |
582 | } | |
583 | ||
b9eb1a61 TH |
584 | *fm++ = SVGA_CMD_FENCE; |
585 | cmd_fence = (struct svga_fifo_cmd_fence *) fm; | |
586 | cmd_fence->fence = *seqno; | |
3eab3d9e | 587 | vmw_fifo_commit_flush(dev_priv, bytes); |
6bcd8d3c TH |
588 | (void) vmw_marker_push(&fifo_state->marker_queue, *seqno); |
589 | vmw_update_seqno(dev_priv, fifo_state); | |
fb1d9738 JB |
590 | |
591 | out_err: | |
592 | return ret; | |
593 | } | |
e2fa3a76 TH |
594 | |
595 | /** | |
ddcda24e TH |
596 | * vmw_fifo_emit_dummy_legacy_query - emits a dummy query to the fifo using |
597 | * legacy query commands. | |
e2fa3a76 TH |
598 | * |
599 | * @dev_priv: The device private structure. | |
600 | * @cid: The hardware context id used for the query. | |
601 | * | |
ddcda24e | 602 | * See the vmw_fifo_emit_dummy_query documentation. |
e2fa3a76 | 603 | */ |
ddcda24e TH |
604 | static int vmw_fifo_emit_dummy_legacy_query(struct vmw_private *dev_priv, |
605 | uint32_t cid) | |
e2fa3a76 TH |
606 | { |
607 | /* | |
608 | * A query wait without a preceding query end will | |
609 | * actually finish all queries for this cid | |
610 | * without writing to the query result structure. | |
611 | */ | |
612 | ||
459d0fa7 | 613 | struct ttm_buffer_object *bo = &dev_priv->dummy_query_bo->base; |
e2fa3a76 TH |
614 | struct { |
615 | SVGA3dCmdHeader header; | |
616 | SVGA3dCmdWaitForQuery body; | |
617 | } *cmd; | |
618 | ||
619 | cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd)); | |
620 | ||
621 | if (unlikely(cmd == NULL)) { | |
622 | DRM_ERROR("Out of fifo space for dummy query.\n"); | |
623 | return -ENOMEM; | |
624 | } | |
625 | ||
626 | cmd->header.id = SVGA_3D_CMD_WAIT_FOR_QUERY; | |
627 | cmd->header.size = sizeof(cmd->body); | |
628 | cmd->body.cid = cid; | |
629 | cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION; | |
630 | ||
631 | if (bo->mem.mem_type == TTM_PL_VRAM) { | |
632 | cmd->body.guestResult.gmrId = SVGA_GMR_FRAMEBUFFER; | |
633 | cmd->body.guestResult.offset = bo->offset; | |
634 | } else { | |
635 | cmd->body.guestResult.gmrId = bo->mem.start; | |
636 | cmd->body.guestResult.offset = 0; | |
637 | } | |
638 | ||
639 | vmw_fifo_commit(dev_priv, sizeof(*cmd)); | |
640 | ||
641 | return 0; | |
642 | } | |
ddcda24e TH |
643 | |
644 | /** | |
645 | * vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using | |
646 | * guest-backed resource query commands. | |
647 | * | |
648 | * @dev_priv: The device private structure. | |
649 | * @cid: The hardware context id used for the query. | |
650 | * | |
651 | * See the vmw_fifo_emit_dummy_query documentation. | |
652 | */ | |
653 | static int vmw_fifo_emit_dummy_gb_query(struct vmw_private *dev_priv, | |
654 | uint32_t cid) | |
655 | { | |
656 | /* | |
657 | * A query wait without a preceding query end will | |
658 | * actually finish all queries for this cid | |
659 | * without writing to the query result structure. | |
660 | */ | |
661 | ||
459d0fa7 | 662 | struct ttm_buffer_object *bo = &dev_priv->dummy_query_bo->base; |
ddcda24e TH |
663 | struct { |
664 | SVGA3dCmdHeader header; | |
665 | SVGA3dCmdWaitForGBQuery body; | |
666 | } *cmd; | |
667 | ||
668 | cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd)); | |
669 | ||
670 | if (unlikely(cmd == NULL)) { | |
671 | DRM_ERROR("Out of fifo space for dummy query.\n"); | |
672 | return -ENOMEM; | |
673 | } | |
674 | ||
675 | cmd->header.id = SVGA_3D_CMD_WAIT_FOR_GB_QUERY; | |
676 | cmd->header.size = sizeof(cmd->body); | |
677 | cmd->body.cid = cid; | |
678 | cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION; | |
679 | BUG_ON(bo->mem.mem_type != VMW_PL_MOB); | |
680 | cmd->body.mobid = bo->mem.start; | |
681 | cmd->body.offset = 0; | |
682 | ||
683 | vmw_fifo_commit(dev_priv, sizeof(*cmd)); | |
684 | ||
685 | return 0; | |
686 | } | |
687 | ||
688 | ||
689 | /** | |
690 | * vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using | |
691 | * appropriate resource query commands. | |
692 | * | |
693 | * @dev_priv: The device private structure. | |
694 | * @cid: The hardware context id used for the query. | |
695 | * | |
696 | * This function is used to emit a dummy occlusion query with | |
697 | * no primitives rendered between query begin and query end. | |
698 | * It's used to provide a query barrier, in order to know that when | |
699 | * this query is finished, all preceding queries are also finished. | |
700 | * | |
701 | * A Query results structure should have been initialized at the start | |
702 | * of the dev_priv->dummy_query_bo buffer object. And that buffer object | |
703 | * must also be either reserved or pinned when this function is called. | |
704 | * | |
705 | * Returns -ENOMEM on failure to reserve fifo space. | |
706 | */ | |
707 | int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv, | |
708 | uint32_t cid) | |
709 | { | |
710 | if (dev_priv->has_mob) | |
711 | return vmw_fifo_emit_dummy_gb_query(dev_priv, cid); | |
712 | ||
713 | return vmw_fifo_emit_dummy_legacy_query(dev_priv, cid); | |
714 | } | |
d80efd5c TH |
715 | |
716 | void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes) | |
717 | { | |
718 | return vmw_fifo_reserve_dx(dev_priv, bytes, SVGA3D_INVALID_ID); | |
719 | } |