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dff96888 | 1 | // SPDX-License-Identifier: GPL-2.0 OR MIT |
fb1d9738 JB |
2 | /************************************************************************** |
3 | * | |
96554415 ZR |
4 | * Copyright (c) 2009-2025 Broadcom. All Rights Reserved. The term |
5 | * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. | |
fb1d9738 JB |
6 | * |
7 | **************************************************************************/ | |
96554415 | 8 | |
09881d29 ZR |
9 | #include "vmwgfx_binding.h" |
10 | #include "vmwgfx_bo.h" | |
fb1d9738 | 11 | #include "vmwgfx_drv.h" |
09881d29 ZR |
12 | #include "vmwgfx_mksstat.h" |
13 | #include "vmwgfx_so.h" | |
14 | ||
a3185f91 | 15 | #include <drm/ttm/ttm_bo.h> |
760285e7 | 16 | #include <drm/ttm/ttm_placement.h> |
fb1d9738 | 17 | |
09881d29 ZR |
18 | #include <linux/sync_file.h> |
19 | #include <linux/hashtable.h> | |
0069455b | 20 | #include <linux/vmalloc.h> |
c0951b79 | 21 | |
6f74fd91 DR |
22 | /* |
23 | * Helper macro to get dx_ctx_node if available otherwise print an error | |
24 | * message. This is for use in command verifier function where if dx_ctx_node | |
25 | * is not set then command is invalid. | |
26 | */ | |
27 | #define VMW_GET_CTX_NODE(__sw_context) \ | |
28 | ({ \ | |
29 | __sw_context->dx_ctx_node ? __sw_context->dx_ctx_node : ({ \ | |
5724f899 | 30 | VMW_DEBUG_USER("SM context is not set at %s\n", __func__); \ |
6f74fd91 DR |
31 | __sw_context->dx_ctx_node; \ |
32 | }); \ | |
33 | }) | |
34 | ||
d01316d0 DR |
35 | #define VMW_DECLARE_CMD_VAR(__var, __type) \ |
36 | struct { \ | |
37 | SVGA3dCmdHeader header; \ | |
38 | __type body; \ | |
39 | } __var | |
40 | ||
680360a4 | 41 | /** |
fc18afcf TH |
42 | * struct vmw_relocation - Buffer object relocation |
43 | * | |
44 | * @head: List head for the command submission context's relocation list | |
cc1e3b79 | 45 | * @vbo: Non ref-counted pointer to buffer object |
fc18afcf TH |
46 | * @mob_loc: Pointer to location for mob id to be modified |
47 | * @location: Pointer to location for guest pointer to be modified | |
fc18afcf TH |
48 | */ |
49 | struct vmw_relocation { | |
50 | struct list_head head; | |
09881d29 | 51 | struct vmw_bo *vbo; |
cc1e3b79 TH |
52 | union { |
53 | SVGAMobId *mob_loc; | |
54 | SVGAGuestPtr *location; | |
55 | }; | |
fc18afcf TH |
56 | }; |
57 | ||
a1944030 TH |
58 | /** |
59 | * enum vmw_resource_relocation_type - Relocation type for resources | |
60 | * | |
61 | * @vmw_res_rel_normal: Traditional relocation. The resource id in the | |
62 | * command stream is replaced with the actual id after validation. | |
63 | * @vmw_res_rel_nop: NOP relocation. The command is unconditionally replaced | |
64 | * with a NOP. | |
680360a4 DR |
65 | * @vmw_res_rel_cond_nop: Conditional NOP relocation. If the resource id after |
66 | * validation is -1, the command is replaced with a NOP. Otherwise no action. | |
7450bf76 LJ |
67 | * @vmw_res_rel_max: Last value in the enum - used for error checking |
68 | */ | |
a1944030 TH |
69 | enum vmw_resource_relocation_type { |
70 | vmw_res_rel_normal, | |
71 | vmw_res_rel_nop, | |
72 | vmw_res_rel_cond_nop, | |
73 | vmw_res_rel_max | |
74 | }; | |
75 | ||
c0951b79 TH |
76 | /** |
77 | * struct vmw_resource_relocation - Relocation info for resources | |
78 | * | |
79 | * @head: List head for the software context's relocation list. | |
80 | * @res: Non-ref-counted pointer to the resource. | |
680360a4 DR |
81 | * @offset: Offset of single byte entries into the command buffer where the id |
82 | * that needs fixup is located. | |
a1944030 | 83 | * @rel_type: Type of relocation. |
c0951b79 TH |
84 | */ |
85 | struct vmw_resource_relocation { | |
86 | struct list_head head; | |
87 | const struct vmw_resource *res; | |
a1944030 TH |
88 | u32 offset:29; |
89 | enum vmw_resource_relocation_type rel_type:3; | |
c0951b79 TH |
90 | }; |
91 | ||
680360a4 | 92 | /** |
9c079b8c | 93 | * struct vmw_ctx_validation_info - Extra validation metadata for contexts |
680360a4 | 94 | * |
9c079b8c TH |
95 | * @head: List head of context list |
96 | * @ctx: The context resource | |
97 | * @cur: The context's persistent binding state | |
98 | * @staged: The binding state changes of this command buffer | |
c0951b79 | 99 | */ |
9c079b8c | 100 | struct vmw_ctx_validation_info { |
c0951b79 | 101 | struct list_head head; |
9c079b8c TH |
102 | struct vmw_resource *ctx; |
103 | struct vmw_ctx_binding_state *cur; | |
104 | struct vmw_ctx_binding_state *staged; | |
c0951b79 TH |
105 | }; |
106 | ||
c373d4ea TH |
107 | /** |
108 | * struct vmw_cmd_entry - Describe a command for the verifier | |
109 | * | |
7450bf76 | 110 | * @func: Call-back to handle the command. |
c373d4ea TH |
111 | * @user_allow: Whether allowed from the execbuf ioctl. |
112 | * @gb_disable: Whether disabled if guest-backed objects are available. | |
113 | * @gb_enable: Whether enabled iff guest-backed objects are available. | |
7450bf76 | 114 | * @cmd_name: Name of the command. |
c373d4ea TH |
115 | */ |
116 | struct vmw_cmd_entry { | |
117 | int (*func) (struct vmw_private *, struct vmw_sw_context *, | |
118 | SVGA3dCmdHeader *); | |
119 | bool user_allow; | |
120 | bool gb_disable; | |
121 | bool gb_enable; | |
65b97a2b | 122 | const char *cmd_name; |
c373d4ea TH |
123 | }; |
124 | ||
125 | #define VMW_CMD_DEF(_cmd, _func, _user_allow, _gb_disable, _gb_enable) \ | |
126 | [(_cmd) - SVGA_3D_CMD_BASE] = {(_func), (_user_allow),\ | |
65b97a2b | 127 | (_gb_disable), (_gb_enable), #_cmd} |
c373d4ea | 128 | |
d80efd5c TH |
129 | static int vmw_resource_context_res_add(struct vmw_private *dev_priv, |
130 | struct vmw_sw_context *sw_context, | |
131 | struct vmw_resource *ctx); | |
fd11a3c0 SY |
132 | static int vmw_translate_mob_ptr(struct vmw_private *dev_priv, |
133 | struct vmw_sw_context *sw_context, | |
134 | SVGAMobId *id, | |
09881d29 | 135 | struct vmw_bo **vmw_bo_p); |
e7a45284 TH |
136 | /** |
137 | * vmw_ptr_diff - Compute the offset from a to b in bytes | |
138 | * | |
139 | * @a: A starting pointer. | |
140 | * @b: A pointer offset in the same address space. | |
141 | * | |
142 | * Returns: The offset in bytes between the two pointers. | |
143 | */ | |
144 | static size_t vmw_ptr_diff(void *a, void *b) | |
145 | { | |
146 | return (unsigned long) b - (unsigned long) a; | |
147 | } | |
d80efd5c | 148 | |
c0951b79 | 149 | /** |
9c079b8c | 150 | * vmw_execbuf_bindings_commit - Commit modified binding state |
680360a4 | 151 | * |
9c079b8c | 152 | * @sw_context: The command submission context |
680360a4 DR |
153 | * @backoff: Whether this is part of the error path and binding state changes |
154 | * should be ignored | |
c0951b79 | 155 | */ |
9c079b8c TH |
156 | static void vmw_execbuf_bindings_commit(struct vmw_sw_context *sw_context, |
157 | bool backoff) | |
c0951b79 | 158 | { |
fc18afcf | 159 | struct vmw_ctx_validation_info *entry; |
c0951b79 | 160 | |
fc18afcf | 161 | list_for_each_entry(entry, &sw_context->ctx_list, head) { |
9c079b8c TH |
162 | if (!backoff) |
163 | vmw_binding_state_commit(entry->cur, entry->staged); | |
680360a4 | 164 | |
9c079b8c TH |
165 | if (entry->staged != sw_context->staged_bindings) |
166 | vmw_binding_state_free(entry->staged); | |
167 | else | |
168 | sw_context->staged_bindings_inuse = false; | |
c0951b79 | 169 | } |
fc18afcf TH |
170 | |
171 | /* List entries are freed with the validation context */ | |
172 | INIT_LIST_HEAD(&sw_context->ctx_list); | |
c0951b79 TH |
173 | } |
174 | ||
9c079b8c TH |
175 | /** |
176 | * vmw_bind_dx_query_mob - Bind the DX query MOB if referenced | |
680360a4 | 177 | * |
9c079b8c TH |
178 | * @sw_context: The command submission context |
179 | */ | |
180 | static void vmw_bind_dx_query_mob(struct vmw_sw_context *sw_context) | |
181 | { | |
182 | if (sw_context->dx_query_mob) | |
183 | vmw_context_bind_dx_query(sw_context->dx_query_ctx, | |
184 | sw_context->dx_query_mob); | |
185 | } | |
186 | ||
d80efd5c | 187 | /** |
680360a4 DR |
188 | * vmw_cmd_ctx_first_setup - Perform the setup needed when a context is added to |
189 | * the validate list. | |
d80efd5c TH |
190 | * |
191 | * @dev_priv: Pointer to the device private: | |
9c079b8c | 192 | * @sw_context: The command submission context |
7450bf76 | 193 | * @res: Pointer to the resource |
9c079b8c | 194 | * @node: The validation node holding the context resource metadata |
d80efd5c TH |
195 | */ |
196 | static int vmw_cmd_ctx_first_setup(struct vmw_private *dev_priv, | |
197 | struct vmw_sw_context *sw_context, | |
9c079b8c TH |
198 | struct vmw_resource *res, |
199 | struct vmw_ctx_validation_info *node) | |
d80efd5c TH |
200 | { |
201 | int ret; | |
202 | ||
9c079b8c | 203 | ret = vmw_resource_context_res_add(dev_priv, sw_context, res); |
d80efd5c TH |
204 | if (unlikely(ret != 0)) |
205 | goto out_err; | |
206 | ||
207 | if (!sw_context->staged_bindings) { | |
680360a4 | 208 | sw_context->staged_bindings = vmw_binding_state_alloc(dev_priv); |
d80efd5c | 209 | if (IS_ERR(sw_context->staged_bindings)) { |
d80efd5c TH |
210 | ret = PTR_ERR(sw_context->staged_bindings); |
211 | sw_context->staged_bindings = NULL; | |
212 | goto out_err; | |
213 | } | |
214 | } | |
215 | ||
216 | if (sw_context->staged_bindings_inuse) { | |
9c079b8c TH |
217 | node->staged = vmw_binding_state_alloc(dev_priv); |
218 | if (IS_ERR(node->staged)) { | |
9c079b8c TH |
219 | ret = PTR_ERR(node->staged); |
220 | node->staged = NULL; | |
d80efd5c TH |
221 | goto out_err; |
222 | } | |
223 | } else { | |
9c079b8c | 224 | node->staged = sw_context->staged_bindings; |
d80efd5c TH |
225 | sw_context->staged_bindings_inuse = true; |
226 | } | |
227 | ||
9c079b8c TH |
228 | node->ctx = res; |
229 | node->cur = vmw_context_binding_state(res); | |
230 | list_add_tail(&node->head, &sw_context->ctx_list); | |
231 | ||
d80efd5c | 232 | return 0; |
680360a4 | 233 | |
d80efd5c TH |
234 | out_err: |
235 | return ret; | |
236 | } | |
c0951b79 TH |
237 | |
238 | /** | |
680360a4 DR |
239 | * vmw_execbuf_res_size - calculate extra size fore the resource validation node |
240 | * | |
e8c66efb TH |
241 | * @dev_priv: Pointer to the device private struct. |
242 | * @res_type: The resource type. | |
c0951b79 | 243 | * |
680360a4 DR |
244 | * Guest-backed contexts and DX contexts require extra size to store execbuf |
245 | * private information in the validation node. Typically the binding manager | |
246 | * associated data structures. | |
e8c66efb TH |
247 | * |
248 | * Returns: The extra size requirement based on resource type. | |
249 | */ | |
250 | static unsigned int vmw_execbuf_res_size(struct vmw_private *dev_priv, | |
251 | enum vmw_res_type res_type) | |
252 | { | |
253 | return (res_type == vmw_res_dx_context || | |
254 | (res_type == vmw_res_context && dev_priv->has_mob)) ? | |
255 | sizeof(struct vmw_ctx_validation_info) : 0; | |
256 | } | |
257 | ||
258 | /** | |
259 | * vmw_execbuf_rcache_update - Update a resource-node cache entry | |
260 | * | |
261 | * @rcache: Pointer to the entry to update. | |
c0951b79 | 262 | * @res: Pointer to the resource. |
680360a4 DR |
263 | * @private: Pointer to the execbuf-private space in the resource validation |
264 | * node. | |
c0951b79 | 265 | */ |
e8c66efb TH |
266 | static void vmw_execbuf_rcache_update(struct vmw_res_cache_entry *rcache, |
267 | struct vmw_resource *res, | |
268 | void *private) | |
269 | { | |
270 | rcache->res = res; | |
271 | rcache->private = private; | |
272 | rcache->valid = 1; | |
273 | rcache->valid_handle = 0; | |
274 | } | |
275 | ||
a309c719 ZR |
276 | enum vmw_val_add_flags { |
277 | vmw_val_add_flag_none = 0, | |
278 | vmw_val_add_flag_noctx = 1 << 0, | |
279 | }; | |
280 | ||
e8c66efb | 281 | /** |
a309c719 | 282 | * vmw_execbuf_res_val_add - Add a resource to the validation list. |
680360a4 | 283 | * |
e8c66efb TH |
284 | * @sw_context: Pointer to the software context. |
285 | * @res: Unreferenced rcu-protected pointer to the resource. | |
a9f58c45 | 286 | * @dirty: Whether to change dirty status. |
a309c719 | 287 | * @flags: specifies whether to use the context or not |
e8c66efb | 288 | * |
680360a4 DR |
289 | * Returns: 0 on success. Negative error code on failure. Typical error codes |
290 | * are %-EINVAL on inconsistency and %-ESRCH if the resource was doomed. | |
e8c66efb | 291 | */ |
a309c719 ZR |
292 | static int vmw_execbuf_res_val_add(struct vmw_sw_context *sw_context, |
293 | struct vmw_resource *res, | |
294 | u32 dirty, | |
295 | u32 flags) | |
c0951b79 | 296 | { |
d80efd5c | 297 | struct vmw_private *dev_priv = res->dev_priv; |
c0951b79 | 298 | int ret; |
9c079b8c TH |
299 | enum vmw_res_type res_type = vmw_res_type(res); |
300 | struct vmw_res_cache_entry *rcache; | |
301 | struct vmw_ctx_validation_info *ctx_info; | |
302 | bool first_usage; | |
e8c66efb | 303 | unsigned int priv_size; |
c0951b79 | 304 | |
e8c66efb TH |
305 | rcache = &sw_context->res_cache[res_type]; |
306 | if (likely(rcache->valid && rcache->res == res)) { | |
a9f58c45 TH |
307 | if (dirty) |
308 | vmw_validation_res_set_dirty(sw_context->ctx, | |
309 | rcache->private, dirty); | |
e8c66efb TH |
310 | return 0; |
311 | } | |
c0951b79 | 312 | |
a309c719 ZR |
313 | if ((flags & vmw_val_add_flag_noctx) != 0) { |
314 | ret = vmw_validation_add_resource(sw_context->ctx, res, 0, dirty, | |
315 | (void **)&ctx_info, NULL); | |
316 | if (ret) | |
317 | return ret; | |
c0951b79 | 318 | |
a309c719 ZR |
319 | } else { |
320 | priv_size = vmw_execbuf_res_size(dev_priv, res_type); | |
321 | ret = vmw_validation_add_resource(sw_context->ctx, res, priv_size, | |
322 | dirty, (void **)&ctx_info, | |
323 | &first_usage); | |
324 | if (ret) | |
9c079b8c | 325 | return ret; |
a309c719 ZR |
326 | |
327 | if (priv_size && first_usage) { | |
328 | ret = vmw_cmd_ctx_first_setup(dev_priv, sw_context, res, | |
329 | ctx_info); | |
330 | if (ret) { | |
331 | VMW_DEBUG_USER("Failed first usage context setup.\n"); | |
332 | return ret; | |
333 | } | |
b2898404 | 334 | } |
d80efd5c TH |
335 | } |
336 | ||
e8c66efb TH |
337 | vmw_execbuf_rcache_update(rcache, res, ctx_info); |
338 | return 0; | |
339 | } | |
340 | ||
d80efd5c | 341 | /** |
680360a4 DR |
342 | * vmw_view_res_val_add - Add a view and the surface it's pointing to to the |
343 | * validation list | |
d80efd5c TH |
344 | * |
345 | * @sw_context: The software context holding the validation list. | |
346 | * @view: Pointer to the view resource. | |
347 | * | |
348 | * Returns 0 if success, negative error code otherwise. | |
349 | */ | |
350 | static int vmw_view_res_val_add(struct vmw_sw_context *sw_context, | |
351 | struct vmw_resource *view) | |
352 | { | |
353 | int ret; | |
354 | ||
355 | /* | |
680360a4 DR |
356 | * First add the resource the view is pointing to, otherwise it may be |
357 | * swapped out when the view is validated. | |
d80efd5c | 358 | */ |
a309c719 ZR |
359 | ret = vmw_execbuf_res_val_add(sw_context, vmw_view_srf(view), |
360 | vmw_view_dirtying(view), vmw_val_add_flag_noctx); | |
d80efd5c TH |
361 | if (ret) |
362 | return ret; | |
363 | ||
a309c719 ZR |
364 | return vmw_execbuf_res_val_add(sw_context, view, VMW_RES_DIRTY_NONE, |
365 | vmw_val_add_flag_noctx); | |
d80efd5c TH |
366 | } |
367 | ||
368 | /** | |
680360a4 DR |
369 | * vmw_view_id_val_add - Look up a view and add it and the surface it's pointing |
370 | * to to the validation list. | |
d80efd5c TH |
371 | * |
372 | * @sw_context: The software context holding the validation list. | |
373 | * @view_type: The view type to look up. | |
374 | * @id: view id of the view. | |
375 | * | |
680360a4 DR |
376 | * The view is represented by a view id and the DX context it's created on, or |
377 | * scheduled for creation on. If there is no DX context set, the function will | |
378 | * return an -EINVAL error pointer. | |
508108ea TH |
379 | * |
380 | * Returns: Unreferenced pointer to the resource on success, negative error | |
381 | * pointer on failure. | |
d80efd5c | 382 | */ |
508108ea TH |
383 | static struct vmw_resource * |
384 | vmw_view_id_val_add(struct vmw_sw_context *sw_context, | |
385 | enum vmw_view_type view_type, u32 id) | |
d80efd5c | 386 | { |
9c079b8c | 387 | struct vmw_ctx_validation_info *ctx_node = sw_context->dx_ctx_node; |
d80efd5c TH |
388 | struct vmw_resource *view; |
389 | int ret; | |
390 | ||
b2898404 | 391 | if (!ctx_node) |
508108ea | 392 | return ERR_PTR(-EINVAL); |
d80efd5c TH |
393 | |
394 | view = vmw_view_lookup(sw_context->man, view_type, id); | |
395 | if (IS_ERR(view)) | |
508108ea | 396 | return view; |
d80efd5c TH |
397 | |
398 | ret = vmw_view_res_val_add(sw_context, view); | |
508108ea TH |
399 | if (ret) |
400 | return ERR_PTR(ret); | |
d80efd5c | 401 | |
508108ea | 402 | return view; |
c0951b79 TH |
403 | } |
404 | ||
30f82d81 TH |
405 | /** |
406 | * vmw_resource_context_res_add - Put resources previously bound to a context on | |
407 | * the validation list | |
408 | * | |
409 | * @dev_priv: Pointer to a device private structure | |
410 | * @sw_context: Pointer to a software context used for this command submission | |
411 | * @ctx: Pointer to the context resource | |
412 | * | |
680360a4 DR |
413 | * This function puts all resources that were previously bound to @ctx on the |
414 | * resource validation list. This is part of the context state reemission | |
30f82d81 TH |
415 | */ |
416 | static int vmw_resource_context_res_add(struct vmw_private *dev_priv, | |
417 | struct vmw_sw_context *sw_context, | |
418 | struct vmw_resource *ctx) | |
419 | { | |
420 | struct list_head *binding_list; | |
d80efd5c | 421 | struct vmw_ctx_bindinfo *entry; |
30f82d81 TH |
422 | int ret = 0; |
423 | struct vmw_resource *res; | |
d80efd5c | 424 | u32 i; |
5e8ec0d9 DR |
425 | u32 cotable_max = has_sm5_context(ctx->dev_priv) ? |
426 | SVGA_COTABLE_MAX : SVGA_COTABLE_DX10_MAX; | |
d80efd5c TH |
427 | |
428 | /* Add all cotables to the validation list. */ | |
878c6ecd DR |
429 | if (has_sm4_context(dev_priv) && |
430 | vmw_res_type(ctx) == vmw_res_dx_context) { | |
5e8ec0d9 | 431 | for (i = 0; i < cotable_max; ++i) { |
d80efd5c | 432 | res = vmw_context_cotable(ctx, i); |
517621b7 | 433 | if (IS_ERR_OR_NULL(res)) |
d80efd5c TH |
434 | continue; |
435 | ||
a309c719 ZR |
436 | ret = vmw_execbuf_res_val_add(sw_context, res, |
437 | VMW_RES_DIRTY_SET, | |
438 | vmw_val_add_flag_noctx); | |
d80efd5c TH |
439 | if (unlikely(ret != 0)) |
440 | return ret; | |
441 | } | |
442 | } | |
443 | ||
d80efd5c | 444 | /* Add all resources bound to the context to the validation list */ |
30f82d81 TH |
445 | mutex_lock(&dev_priv->binding_mutex); |
446 | binding_list = vmw_context_binding_list(ctx); | |
447 | ||
448 | list_for_each_entry(entry, binding_list, ctx_list) { | |
d80efd5c TH |
449 | if (vmw_res_type(entry->res) == vmw_res_view) |
450 | ret = vmw_view_res_val_add(sw_context, entry->res); | |
451 | else | |
a309c719 ZR |
452 | ret = vmw_execbuf_res_val_add(sw_context, entry->res, |
453 | vmw_binding_dirtying(entry->bt), | |
454 | vmw_val_add_flag_noctx); | |
30f82d81 TH |
455 | if (unlikely(ret != 0)) |
456 | break; | |
457 | } | |
458 | ||
878c6ecd DR |
459 | if (has_sm4_context(dev_priv) && |
460 | vmw_res_type(ctx) == vmw_res_dx_context) { | |
09881d29 | 461 | struct vmw_bo *dx_query_mob; |
fd11a3c0 SY |
462 | |
463 | dx_query_mob = vmw_context_get_dx_query_mob(ctx); | |
39985eea ZR |
464 | if (dx_query_mob) { |
465 | vmw_bo_placement_set(dx_query_mob, | |
466 | VMW_BO_DOMAIN_MOB, | |
467 | VMW_BO_DOMAIN_MOB); | |
9c079b8c | 468 | ret = vmw_validation_add_bo(sw_context->ctx, |
39985eea ZR |
469 | dx_query_mob); |
470 | } | |
fd11a3c0 SY |
471 | } |
472 | ||
30f82d81 TH |
473 | mutex_unlock(&dev_priv->binding_mutex); |
474 | return ret; | |
475 | } | |
476 | ||
c0951b79 TH |
477 | /** |
478 | * vmw_resource_relocation_add - Add a relocation to the relocation list | |
479 | * | |
7450bf76 | 480 | * @sw_context: Pointer to the software context. |
c0951b79 | 481 | * @res: The resource. |
680360a4 DR |
482 | * @offset: Offset into the command buffer currently being parsed where the id |
483 | * that needs fixup is located. Granularity is one byte. | |
a1944030 | 484 | * @rel_type: Relocation type. |
c0951b79 | 485 | */ |
fc18afcf | 486 | static int vmw_resource_relocation_add(struct vmw_sw_context *sw_context, |
c0951b79 | 487 | const struct vmw_resource *res, |
a1944030 TH |
488 | unsigned long offset, |
489 | enum vmw_resource_relocation_type | |
490 | rel_type) | |
c0951b79 TH |
491 | { |
492 | struct vmw_resource_relocation *rel; | |
493 | ||
fc18afcf | 494 | rel = vmw_validation_mem_alloc(sw_context->ctx, sizeof(*rel)); |
1a4adb05 | 495 | if (unlikely(!rel)) { |
5724f899 | 496 | VMW_DEBUG_USER("Failed to allocate a resource relocation.\n"); |
c0951b79 TH |
497 | return -ENOMEM; |
498 | } | |
499 | ||
500 | rel->res = res; | |
501 | rel->offset = offset; | |
a1944030 | 502 | rel->rel_type = rel_type; |
fc18afcf | 503 | list_add_tail(&rel->head, &sw_context->res_relocations); |
c0951b79 TH |
504 | |
505 | return 0; | |
506 | } | |
507 | ||
508 | /** | |
509 | * vmw_resource_relocations_free - Free all relocations on a list | |
510 | * | |
fc18afcf | 511 | * @list: Pointer to the head of the relocation list |
c0951b79 TH |
512 | */ |
513 | static void vmw_resource_relocations_free(struct list_head *list) | |
514 | { | |
fc18afcf | 515 | /* Memory is validation context memory, so no need to free it */ |
fc18afcf | 516 | INIT_LIST_HEAD(list); |
c0951b79 TH |
517 | } |
518 | ||
519 | /** | |
520 | * vmw_resource_relocations_apply - Apply all relocations on a list | |
521 | * | |
680360a4 DR |
522 | * @cb: Pointer to the start of the command buffer bein patch. This need not be |
523 | * the same buffer as the one being parsed when the relocation list was built, | |
524 | * but the contents must be the same modulo the resource ids. | |
c0951b79 TH |
525 | * @list: Pointer to the head of the relocation list. |
526 | */ | |
527 | static void vmw_resource_relocations_apply(uint32_t *cb, | |
528 | struct list_head *list) | |
529 | { | |
530 | struct vmw_resource_relocation *rel; | |
531 | ||
a1944030 TH |
532 | /* Validate the struct vmw_resource_relocation member size */ |
533 | BUILD_BUG_ON(SVGA_CB_MAX_SIZE >= (1 << 29)); | |
534 | BUILD_BUG_ON(vmw_res_rel_max >= (1 << 3)); | |
535 | ||
d5bde956 | 536 | list_for_each_entry(rel, list, head) { |
e7a45284 | 537 | u32 *addr = (u32 *)((unsigned long) cb + rel->offset); |
a1944030 TH |
538 | switch (rel->rel_type) { |
539 | case vmw_res_rel_normal: | |
e7a45284 | 540 | *addr = rel->res->id; |
a1944030 TH |
541 | break; |
542 | case vmw_res_rel_nop: | |
e7a45284 | 543 | *addr = SVGA_3D_CMD_NOP; |
a1944030 TH |
544 | break; |
545 | default: | |
546 | if (rel->res->id == -1) | |
547 | *addr = SVGA_3D_CMD_NOP; | |
548 | break; | |
549 | } | |
d5bde956 | 550 | } |
c0951b79 TH |
551 | } |
552 | ||
fb1d9738 JB |
553 | static int vmw_cmd_invalid(struct vmw_private *dev_priv, |
554 | struct vmw_sw_context *sw_context, | |
555 | SVGA3dCmdHeader *header) | |
556 | { | |
fcfffdd8 | 557 | return -EINVAL; |
fb1d9738 JB |
558 | } |
559 | ||
560 | static int vmw_cmd_ok(struct vmw_private *dev_priv, | |
561 | struct vmw_sw_context *sw_context, | |
562 | SVGA3dCmdHeader *header) | |
563 | { | |
564 | return 0; | |
565 | } | |
566 | ||
c0951b79 | 567 | /** |
680360a4 DR |
568 | * vmw_resources_reserve - Reserve all resources on the sw_context's resource |
569 | * list. | |
c0951b79 TH |
570 | * |
571 | * @sw_context: Pointer to the software context. | |
572 | * | |
680360a4 DR |
573 | * Note that since vmware's command submission currently is protected by the |
574 | * cmdbuf mutex, no fancy deadlock avoidance is required for resources, since | |
575 | * only a single thread at once will attempt this. | |
c0951b79 TH |
576 | */ |
577 | static int vmw_resources_reserve(struct vmw_sw_context *sw_context) | |
fb1d9738 | 578 | { |
9c079b8c | 579 | int ret; |
c0951b79 | 580 | |
9c079b8c TH |
581 | ret = vmw_validation_res_reserve(sw_context->ctx, true); |
582 | if (ret) | |
583 | return ret; | |
2f633e5e | 584 | |
fd11a3c0 | 585 | if (sw_context->dx_query_mob) { |
09881d29 | 586 | struct vmw_bo *expected_dx_query_mob; |
fd11a3c0 SY |
587 | |
588 | expected_dx_query_mob = | |
589 | vmw_context_get_dx_query_mob(sw_context->dx_query_ctx); | |
590 | if (expected_dx_query_mob && | |
591 | expected_dx_query_mob != sw_context->dx_query_mob) { | |
592 | ret = -EINVAL; | |
593 | } | |
594 | } | |
595 | ||
596 | return ret; | |
c0951b79 | 597 | } |
fb1d9738 | 598 | |
c0951b79 | 599 | /** |
680360a4 DR |
600 | * vmw_cmd_res_check - Check that a resource is present and if so, put it on the |
601 | * resource validate list unless it's already there. | |
c0951b79 TH |
602 | * |
603 | * @dev_priv: Pointer to a device private structure. | |
604 | * @sw_context: Pointer to the software context. | |
605 | * @res_type: Resource type. | |
a9f58c45 | 606 | * @dirty: Whether to change dirty status. |
ecc8271f | 607 | * @converter: User-space visible type specific information. |
680360a4 DR |
608 | * @id_loc: Pointer to the location in the command buffer currently being parsed |
609 | * from where the user-space resource id handle is located. | |
ecc8271f | 610 | * @p_res: Pointer to pointer to resource validation node. Populated on |
680360a4 | 611 | * exit. |
c0951b79 | 612 | */ |
d5bde956 | 613 | static int |
18e4a466 TH |
614 | vmw_cmd_res_check(struct vmw_private *dev_priv, |
615 | struct vmw_sw_context *sw_context, | |
616 | enum vmw_res_type res_type, | |
a9f58c45 | 617 | u32 dirty, |
18e4a466 TH |
618 | const struct vmw_user_resource_conv *converter, |
619 | uint32_t *id_loc, | |
9c079b8c | 620 | struct vmw_resource **p_res) |
fb1d9738 | 621 | { |
e8c66efb | 622 | struct vmw_res_cache_entry *rcache = &sw_context->res_cache[res_type]; |
be38ab6e | 623 | struct vmw_resource *res; |
a309c719 ZR |
624 | int ret = 0; |
625 | bool needs_unref = false; | |
be38ab6e | 626 | |
9c079b8c TH |
627 | if (p_res) |
628 | *p_res = NULL; | |
629 | ||
18e4a466 | 630 | if (*id_loc == SVGA3D_INVALID_ID) { |
b5c3b1a6 | 631 | if (res_type == vmw_res_context) { |
5724f899 | 632 | VMW_DEBUG_USER("Illegal context invalid id.\n"); |
b5c3b1a6 TH |
633 | return -EINVAL; |
634 | } | |
7a73ba74 | 635 | return 0; |
b5c3b1a6 | 636 | } |
7a73ba74 | 637 | |
9c079b8c | 638 | if (likely(rcache->valid_handle && *id_loc == rcache->handle)) { |
e8c66efb | 639 | res = rcache->res; |
a9f58c45 TH |
640 | if (dirty) |
641 | vmw_validation_res_set_dirty(sw_context->ctx, | |
642 | rcache->private, dirty); | |
e8c66efb TH |
643 | } else { |
644 | unsigned int size = vmw_execbuf_res_size(dev_priv, res_type); | |
c0951b79 | 645 | |
e8c66efb TH |
646 | ret = vmw_validation_preload_res(sw_context->ctx, size); |
647 | if (ret) | |
648 | return ret; | |
c0951b79 | 649 | |
a309c719 ZR |
650 | ret = vmw_user_resource_lookup_handle |
651 | (dev_priv, sw_context->fp->tfile, *id_loc, converter, &res); | |
652 | if (ret != 0) { | |
5724f899 DR |
653 | VMW_DEBUG_USER("Could not find/use resource 0x%08x.\n", |
654 | (unsigned int) *id_loc); | |
a309c719 | 655 | return ret; |
e8c66efb | 656 | } |
a309c719 | 657 | needs_unref = true; |
be38ab6e | 658 | |
a309c719 | 659 | ret = vmw_execbuf_res_val_add(sw_context, res, dirty, vmw_val_add_flag_none); |
e8c66efb | 660 | if (unlikely(ret != 0)) |
a309c719 | 661 | goto res_check_done; |
5bb39e81 | 662 | |
e8c66efb TH |
663 | if (rcache->valid && rcache->res == res) { |
664 | rcache->valid_handle = true; | |
665 | rcache->handle = *id_loc; | |
666 | } | |
667 | } | |
f18c8840 | 668 | |
e8c66efb TH |
669 | ret = vmw_resource_relocation_add(sw_context, res, |
670 | vmw_ptr_diff(sw_context->buf_start, | |
671 | id_loc), | |
672 | vmw_res_rel_normal); | |
9c079b8c TH |
673 | if (p_res) |
674 | *p_res = res; | |
675 | ||
a309c719 ZR |
676 | res_check_done: |
677 | if (needs_unref) | |
678 | vmw_resource_unreference(&res); | |
679 | ||
680 | return ret; | |
fb1d9738 JB |
681 | } |
682 | ||
fd11a3c0 | 683 | /** |
2cd80dbd | 684 | * vmw_rebind_all_dx_query - Rebind DX query associated with the context |
fd11a3c0 SY |
685 | * |
686 | * @ctx_res: context the query belongs to | |
687 | * | |
688 | * This function assumes binding_mutex is held. | |
689 | */ | |
690 | static int vmw_rebind_all_dx_query(struct vmw_resource *ctx_res) | |
691 | { | |
692 | struct vmw_private *dev_priv = ctx_res->dev_priv; | |
09881d29 | 693 | struct vmw_bo *dx_query_mob; |
d01316d0 | 694 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdDXBindAllQuery); |
fd11a3c0 SY |
695 | |
696 | dx_query_mob = vmw_context_get_dx_query_mob(ctx_res); | |
697 | ||
698 | if (!dx_query_mob || dx_query_mob->dx_query_ctx) | |
699 | return 0; | |
700 | ||
8426ed9c | 701 | cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), ctx_res->id); |
b2898404 | 702 | if (cmd == NULL) |
fd11a3c0 | 703 | return -ENOMEM; |
fd11a3c0 SY |
704 | |
705 | cmd->header.id = SVGA_3D_CMD_DX_BIND_ALL_QUERY; | |
706 | cmd->header.size = sizeof(cmd->body); | |
707 | cmd->body.cid = ctx_res->id; | |
668b2066 | 708 | cmd->body.mobid = dx_query_mob->tbo.resource->start; |
8426ed9c | 709 | vmw_cmd_commit(dev_priv, sizeof(*cmd)); |
fd11a3c0 SY |
710 | |
711 | vmw_context_bind_dx_query(ctx_res, dx_query_mob); | |
712 | ||
713 | return 0; | |
714 | } | |
715 | ||
30f82d81 | 716 | /** |
680360a4 DR |
717 | * vmw_rebind_contexts - Rebind all resources previously bound to referenced |
718 | * contexts. | |
30f82d81 TH |
719 | * |
720 | * @sw_context: Pointer to the software context. | |
721 | * | |
722 | * Rebind context binding points that have been scrubbed because of eviction. | |
723 | */ | |
724 | static int vmw_rebind_contexts(struct vmw_sw_context *sw_context) | |
725 | { | |
9c079b8c | 726 | struct vmw_ctx_validation_info *val; |
30f82d81 TH |
727 | int ret; |
728 | ||
9c079b8c TH |
729 | list_for_each_entry(val, &sw_context->ctx_list, head) { |
730 | ret = vmw_binding_rebind_all(val->cur); | |
30f82d81 TH |
731 | if (unlikely(ret != 0)) { |
732 | if (ret != -ERESTARTSYS) | |
5724f899 | 733 | VMW_DEBUG_USER("Failed to rebind context.\n"); |
30f82d81 TH |
734 | return ret; |
735 | } | |
fd11a3c0 | 736 | |
9c079b8c | 737 | ret = vmw_rebind_all_dx_query(val->ctx); |
b2898404 DR |
738 | if (ret != 0) { |
739 | VMW_DEBUG_USER("Failed to rebind queries.\n"); | |
fd11a3c0 | 740 | return ret; |
b2898404 | 741 | } |
30f82d81 TH |
742 | } |
743 | ||
744 | return 0; | |
745 | } | |
746 | ||
d80efd5c | 747 | /** |
680360a4 DR |
748 | * vmw_view_bindings_add - Add an array of view bindings to a context binding |
749 | * state tracker. | |
d80efd5c TH |
750 | * |
751 | * @sw_context: The execbuf state used for this command. | |
752 | * @view_type: View type for the bindings. | |
753 | * @binding_type: Binding type for the bindings. | |
754 | * @shader_slot: The shader slot to user for the bindings. | |
755 | * @view_ids: Array of view ids to be bound. | |
756 | * @num_views: Number of view ids in @view_ids. | |
757 | * @first_slot: The binding slot to be used for the first view id in @view_ids. | |
758 | */ | |
759 | static int vmw_view_bindings_add(struct vmw_sw_context *sw_context, | |
760 | enum vmw_view_type view_type, | |
761 | enum vmw_ctx_binding_type binding_type, | |
762 | uint32 shader_slot, | |
763 | uint32 view_ids[], u32 num_views, | |
764 | u32 first_slot) | |
765 | { | |
6f74fd91 | 766 | struct vmw_ctx_validation_info *ctx_node = VMW_GET_CTX_NODE(sw_context); |
d80efd5c | 767 | u32 i; |
d80efd5c | 768 | |
6f74fd91 | 769 | if (!ctx_node) |
d80efd5c | 770 | return -EINVAL; |
d80efd5c | 771 | |
d80efd5c TH |
772 | for (i = 0; i < num_views; ++i) { |
773 | struct vmw_ctx_bindinfo_view binding; | |
774 | struct vmw_resource *view = NULL; | |
775 | ||
776 | if (view_ids[i] != SVGA3D_INVALID_ID) { | |
508108ea TH |
777 | view = vmw_view_id_val_add(sw_context, view_type, |
778 | view_ids[i]); | |
d80efd5c | 779 | if (IS_ERR(view)) { |
5724f899 | 780 | VMW_DEBUG_USER("View not found.\n"); |
d80efd5c TH |
781 | return PTR_ERR(view); |
782 | } | |
d80efd5c | 783 | } |
9c079b8c | 784 | binding.bi.ctx = ctx_node->ctx; |
d80efd5c TH |
785 | binding.bi.res = view; |
786 | binding.bi.bt = binding_type; | |
787 | binding.shader_slot = shader_slot; | |
788 | binding.slot = first_slot + i; | |
9c079b8c | 789 | vmw_binding_add(ctx_node->staged, &binding.bi, |
d80efd5c | 790 | shader_slot, binding.slot); |
d80efd5c TH |
791 | } |
792 | ||
793 | return 0; | |
794 | } | |
795 | ||
c0951b79 TH |
796 | /** |
797 | * vmw_cmd_cid_check - Check a command header for valid context information. | |
798 | * | |
799 | * @dev_priv: Pointer to a device private structure. | |
800 | * @sw_context: Pointer to the software context. | |
801 | * @header: A command header with an embedded user-space context handle. | |
802 | * | |
803 | * Convenience function: Call vmw_cmd_res_check with the user-space context | |
804 | * handle embedded in @header. | |
805 | */ | |
806 | static int vmw_cmd_cid_check(struct vmw_private *dev_priv, | |
807 | struct vmw_sw_context *sw_context, | |
808 | SVGA3dCmdHeader *header) | |
809 | { | |
d01316d0 DR |
810 | VMW_DECLARE_CMD_VAR(*cmd, uint32_t) = |
811 | container_of(header, typeof(*cmd), header); | |
c0951b79 | 812 | |
c0951b79 | 813 | return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context, |
a9f58c45 | 814 | VMW_RES_DIRTY_SET, user_context_converter, |
d01316d0 | 815 | &cmd->body, NULL); |
c0951b79 | 816 | } |
fb1d9738 | 817 | |
9c079b8c TH |
818 | /** |
819 | * vmw_execbuf_info_from_res - Get the private validation metadata for a | |
820 | * recently validated resource | |
680360a4 | 821 | * |
9c079b8c TH |
822 | * @sw_context: Pointer to the command submission context |
823 | * @res: The resource | |
824 | * | |
825 | * The resource pointed to by @res needs to be present in the command submission | |
826 | * context's resource cache and hence the last resource of that type to be | |
827 | * processed by the validation code. | |
828 | * | |
680360a4 DR |
829 | * Return: a pointer to the private metadata of the resource, or NULL if it |
830 | * wasn't found | |
9c079b8c TH |
831 | */ |
832 | static struct vmw_ctx_validation_info * | |
833 | vmw_execbuf_info_from_res(struct vmw_sw_context *sw_context, | |
834 | struct vmw_resource *res) | |
835 | { | |
836 | struct vmw_res_cache_entry *rcache = | |
837 | &sw_context->res_cache[vmw_res_type(res)]; | |
838 | ||
839 | if (rcache->valid && rcache->res == res) | |
840 | return rcache->private; | |
841 | ||
842 | WARN_ON_ONCE(true); | |
843 | return NULL; | |
844 | } | |
845 | ||
fb1d9738 JB |
846 | static int vmw_cmd_set_render_target_check(struct vmw_private *dev_priv, |
847 | struct vmw_sw_context *sw_context, | |
848 | SVGA3dCmdHeader *header) | |
849 | { | |
d01316d0 | 850 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdSetRenderTarget); |
9c079b8c TH |
851 | struct vmw_resource *ctx; |
852 | struct vmw_resource *res; | |
fb1d9738 JB |
853 | int ret; |
854 | ||
d01316d0 | 855 | cmd = container_of(header, typeof(*cmd), header); |
b5c3b1a6 | 856 | |
d80efd5c | 857 | if (cmd->body.type >= SVGA3D_RT_MAX) { |
5724f899 DR |
858 | VMW_DEBUG_USER("Illegal render target type %u.\n", |
859 | (unsigned int) cmd->body.type); | |
d80efd5c TH |
860 | return -EINVAL; |
861 | } | |
862 | ||
b5c3b1a6 | 863 | ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context, |
a9f58c45 TH |
864 | VMW_RES_DIRTY_SET, user_context_converter, |
865 | &cmd->body.cid, &ctx); | |
fb1d9738 JB |
866 | if (unlikely(ret != 0)) |
867 | return ret; | |
868 | ||
c0951b79 | 869 | ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, |
a9f58c45 TH |
870 | VMW_RES_DIRTY_SET, user_surface_converter, |
871 | &cmd->body.target.sid, &res); | |
e8c66efb | 872 | if (unlikely(ret)) |
b5c3b1a6 TH |
873 | return ret; |
874 | ||
875 | if (dev_priv->has_mob) { | |
d80efd5c | 876 | struct vmw_ctx_bindinfo_view binding; |
9c079b8c | 877 | struct vmw_ctx_validation_info *node; |
b5c3b1a6 | 878 | |
9c079b8c TH |
879 | node = vmw_execbuf_info_from_res(sw_context, ctx); |
880 | if (!node) | |
881 | return -EINVAL; | |
882 | ||
883 | binding.bi.ctx = ctx; | |
884 | binding.bi.res = res; | |
d80efd5c TH |
885 | binding.bi.bt = vmw_ctx_binding_rt; |
886 | binding.slot = cmd->body.type; | |
9c079b8c | 887 | vmw_binding_add(node->staged, &binding.bi, 0, binding.slot); |
b5c3b1a6 TH |
888 | } |
889 | ||
890 | return 0; | |
fb1d9738 JB |
891 | } |
892 | ||
893 | static int vmw_cmd_surface_copy_check(struct vmw_private *dev_priv, | |
894 | struct vmw_sw_context *sw_context, | |
895 | SVGA3dCmdHeader *header) | |
896 | { | |
d01316d0 | 897 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdSurfaceCopy); |
fb1d9738 JB |
898 | int ret; |
899 | ||
d01316d0 | 900 | cmd = container_of(header, typeof(*cmd), header); |
c9146cd9 | 901 | |
6bf6bf03 | 902 | ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, |
a9f58c45 TH |
903 | VMW_RES_DIRTY_NONE, user_surface_converter, |
904 | &cmd->body.src.sid, NULL); | |
6bf6bf03 TH |
905 | if (ret) |
906 | return ret; | |
c9146cd9 | 907 | |
c0951b79 | 908 | return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, |
a9f58c45 | 909 | VMW_RES_DIRTY_SET, user_surface_converter, |
c0951b79 | 910 | &cmd->body.dest.sid, NULL); |
fb1d9738 JB |
911 | } |
912 | ||
0fca749e | 913 | static int vmw_cmd_buffer_copy_check(struct vmw_private *dev_priv, |
680360a4 DR |
914 | struct vmw_sw_context *sw_context, |
915 | SVGA3dCmdHeader *header) | |
0fca749e | 916 | { |
d01316d0 | 917 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdDXBufferCopy); |
0fca749e NB |
918 | int ret; |
919 | ||
920 | cmd = container_of(header, typeof(*cmd), header); | |
921 | ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, | |
a9f58c45 | 922 | VMW_RES_DIRTY_NONE, user_surface_converter, |
0fca749e NB |
923 | &cmd->body.src, NULL); |
924 | if (ret != 0) | |
925 | return ret; | |
926 | ||
927 | return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, | |
a9f58c45 | 928 | VMW_RES_DIRTY_SET, user_surface_converter, |
0fca749e NB |
929 | &cmd->body.dest, NULL); |
930 | } | |
931 | ||
932 | static int vmw_cmd_pred_copy_check(struct vmw_private *dev_priv, | |
933 | struct vmw_sw_context *sw_context, | |
934 | SVGA3dCmdHeader *header) | |
935 | { | |
d01316d0 | 936 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdDXPredCopyRegion); |
0fca749e NB |
937 | int ret; |
938 | ||
939 | cmd = container_of(header, typeof(*cmd), header); | |
940 | ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, | |
a9f58c45 | 941 | VMW_RES_DIRTY_NONE, user_surface_converter, |
0fca749e NB |
942 | &cmd->body.srcSid, NULL); |
943 | if (ret != 0) | |
944 | return ret; | |
945 | ||
946 | return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, | |
a9f58c45 | 947 | VMW_RES_DIRTY_SET, user_surface_converter, |
0fca749e NB |
948 | &cmd->body.dstSid, NULL); |
949 | } | |
950 | ||
fb1d9738 JB |
951 | static int vmw_cmd_stretch_blt_check(struct vmw_private *dev_priv, |
952 | struct vmw_sw_context *sw_context, | |
953 | SVGA3dCmdHeader *header) | |
954 | { | |
d01316d0 | 955 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdSurfaceStretchBlt); |
fb1d9738 JB |
956 | int ret; |
957 | ||
d01316d0 | 958 | cmd = container_of(header, typeof(*cmd), header); |
c0951b79 | 959 | ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, |
a9f58c45 | 960 | VMW_RES_DIRTY_NONE, user_surface_converter, |
c0951b79 | 961 | &cmd->body.src.sid, NULL); |
fb1d9738 JB |
962 | if (unlikely(ret != 0)) |
963 | return ret; | |
680360a4 | 964 | |
c0951b79 | 965 | return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, |
a9f58c45 | 966 | VMW_RES_DIRTY_SET, user_surface_converter, |
c0951b79 | 967 | &cmd->body.dest.sid, NULL); |
fb1d9738 JB |
968 | } |
969 | ||
970 | static int vmw_cmd_blt_surf_screen_check(struct vmw_private *dev_priv, | |
971 | struct vmw_sw_context *sw_context, | |
972 | SVGA3dCmdHeader *header) | |
973 | { | |
d01316d0 DR |
974 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdBlitSurfaceToScreen) = |
975 | container_of(header, typeof(*cmd), header); | |
0cff60c6 | 976 | |
c0951b79 | 977 | return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, |
a9f58c45 | 978 | VMW_RES_DIRTY_NONE, user_surface_converter, |
c0951b79 | 979 | &cmd->body.srcImage.sid, NULL); |
fb1d9738 JB |
980 | } |
981 | ||
982 | static int vmw_cmd_present_check(struct vmw_private *dev_priv, | |
983 | struct vmw_sw_context *sw_context, | |
984 | SVGA3dCmdHeader *header) | |
985 | { | |
d01316d0 DR |
986 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdPresent) = |
987 | container_of(header, typeof(*cmd), header); | |
0cff60c6 | 988 | |
c0951b79 | 989 | return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, |
a9f58c45 TH |
990 | VMW_RES_DIRTY_NONE, user_surface_converter, |
991 | &cmd->body.sid, NULL); | |
fb1d9738 JB |
992 | } |
993 | ||
e2fa3a76 TH |
994 | /** |
995 | * vmw_query_bo_switch_prepare - Prepare to switch pinned buffer for queries. | |
996 | * | |
997 | * @dev_priv: The device private structure. | |
e2fa3a76 TH |
998 | * @new_query_bo: The new buffer holding query results. |
999 | * @sw_context: The software context used for this command submission. | |
1000 | * | |
680360a4 DR |
1001 | * This function checks whether @new_query_bo is suitable for holding query |
1002 | * results, and if another buffer currently is pinned for query results. If so, | |
1003 | * the function prepares the state of @sw_context for switching pinned buffers | |
1004 | * after successful submission of the current command batch. | |
e2fa3a76 TH |
1005 | */ |
1006 | static int vmw_query_bo_switch_prepare(struct vmw_private *dev_priv, | |
09881d29 | 1007 | struct vmw_bo *new_query_bo, |
e2fa3a76 TH |
1008 | struct vmw_sw_context *sw_context) |
1009 | { | |
c0951b79 TH |
1010 | struct vmw_res_cache_entry *ctx_entry = |
1011 | &sw_context->res_cache[vmw_res_context]; | |
e2fa3a76 | 1012 | int ret; |
c0951b79 TH |
1013 | |
1014 | BUG_ON(!ctx_entry->valid); | |
1015 | sw_context->last_query_ctx = ctx_entry->res; | |
e2fa3a76 TH |
1016 | |
1017 | if (unlikely(new_query_bo != sw_context->cur_query_bo)) { | |
1018 | ||
668b2066 | 1019 | if (unlikely(PFN_UP(new_query_bo->tbo.resource->size) > 4)) { |
5724f899 | 1020 | VMW_DEBUG_USER("Query buffer too large.\n"); |
e2fa3a76 TH |
1021 | return -EINVAL; |
1022 | } | |
1023 | ||
1024 | if (unlikely(sw_context->cur_query_bo != NULL)) { | |
c0951b79 | 1025 | sw_context->needs_post_query_barrier = true; |
39985eea | 1026 | vmw_bo_placement_set_default_accelerated(sw_context->cur_query_bo); |
9c079b8c | 1027 | ret = vmw_validation_add_bo(sw_context->ctx, |
39985eea | 1028 | sw_context->cur_query_bo); |
e2fa3a76 TH |
1029 | if (unlikely(ret != 0)) |
1030 | return ret; | |
1031 | } | |
1032 | sw_context->cur_query_bo = new_query_bo; | |
1033 | ||
39985eea | 1034 | vmw_bo_placement_set_default_accelerated(dev_priv->dummy_query_bo); |
9c079b8c | 1035 | ret = vmw_validation_add_bo(sw_context->ctx, |
39985eea | 1036 | dev_priv->dummy_query_bo); |
e2fa3a76 TH |
1037 | if (unlikely(ret != 0)) |
1038 | return ret; | |
e2fa3a76 TH |
1039 | } |
1040 | ||
e2fa3a76 TH |
1041 | return 0; |
1042 | } | |
1043 | ||
e2fa3a76 TH |
1044 | /** |
1045 | * vmw_query_bo_switch_commit - Finalize switching pinned query buffer | |
1046 | * | |
1047 | * @dev_priv: The device private structure. | |
1048 | * @sw_context: The software context used for this command submission batch. | |
1049 | * | |
1050 | * This function will check if we're switching query buffers, and will then, | |
e2fa3a76 | 1051 | * issue a dummy occlusion query wait used as a query barrier. When the fence |
680360a4 DR |
1052 | * object following that query wait has signaled, we are sure that all preceding |
1053 | * queries have finished, and the old query buffer can be unpinned. However, | |
1054 | * since both the new query buffer and the old one are fenced with that fence, | |
1055 | * we can do an asynchronus unpin now, and be sure that the old query buffer | |
1056 | * won't be moved until the fence has signaled. | |
e2fa3a76 TH |
1057 | * |
1058 | * As mentioned above, both the new - and old query buffers need to be fenced | |
1059 | * using a sequence emitted *after* calling this function. | |
1060 | */ | |
1061 | static void vmw_query_bo_switch_commit(struct vmw_private *dev_priv, | |
1062 | struct vmw_sw_context *sw_context) | |
1063 | { | |
e2fa3a76 TH |
1064 | /* |
1065 | * The validate list should still hold references to all | |
1066 | * contexts here. | |
1067 | */ | |
c0951b79 TH |
1068 | if (sw_context->needs_post_query_barrier) { |
1069 | struct vmw_res_cache_entry *ctx_entry = | |
1070 | &sw_context->res_cache[vmw_res_context]; | |
1071 | struct vmw_resource *ctx; | |
1072 | int ret; | |
e2fa3a76 | 1073 | |
c0951b79 TH |
1074 | BUG_ON(!ctx_entry->valid); |
1075 | ctx = ctx_entry->res; | |
e2fa3a76 | 1076 | |
8426ed9c | 1077 | ret = vmw_cmd_emit_dummy_query(dev_priv, ctx->id); |
e2fa3a76 TH |
1078 | |
1079 | if (unlikely(ret != 0)) | |
5724f899 | 1080 | VMW_DEBUG_USER("Out of fifo space for dummy query.\n"); |
e2fa3a76 TH |
1081 | } |
1082 | ||
1083 | if (dev_priv->pinned_bo != sw_context->cur_query_bo) { | |
1084 | if (dev_priv->pinned_bo) { | |
459d0fa7 | 1085 | vmw_bo_pin_reserved(dev_priv->pinned_bo, false); |
f1d34bfd | 1086 | vmw_bo_unreference(&dev_priv->pinned_bo); |
e2fa3a76 TH |
1087 | } |
1088 | ||
c0951b79 | 1089 | if (!sw_context->needs_post_query_barrier) { |
459d0fa7 | 1090 | vmw_bo_pin_reserved(sw_context->cur_query_bo, true); |
e2fa3a76 | 1091 | |
c0951b79 TH |
1092 | /* |
1093 | * We pin also the dummy_query_bo buffer so that we | |
680360a4 DR |
1094 | * don't need to validate it when emitting dummy queries |
1095 | * in context destroy paths. | |
c0951b79 | 1096 | */ |
459d0fa7 TH |
1097 | if (!dev_priv->dummy_query_bo_pinned) { |
1098 | vmw_bo_pin_reserved(dev_priv->dummy_query_bo, | |
1099 | true); | |
1100 | dev_priv->dummy_query_bo_pinned = true; | |
1101 | } | |
e2fa3a76 | 1102 | |
c0951b79 TH |
1103 | BUG_ON(sw_context->last_query_ctx == NULL); |
1104 | dev_priv->query_cid = sw_context->last_query_ctx->id; | |
1105 | dev_priv->query_cid_valid = true; | |
1106 | dev_priv->pinned_bo = | |
f1d34bfd | 1107 | vmw_bo_reference(sw_context->cur_query_bo); |
c0951b79 | 1108 | } |
e2fa3a76 TH |
1109 | } |
1110 | } | |
1111 | ||
ddcda24e | 1112 | /** |
2cd80dbd | 1113 | * vmw_translate_mob_ptr - Prepare to translate a user-space buffer handle |
680360a4 | 1114 | * to a MOB id. |
ddcda24e TH |
1115 | * |
1116 | * @dev_priv: Pointer to a device private structure. | |
1117 | * @sw_context: The software context used for this command batch validation. | |
1118 | * @id: Pointer to the user-space handle to be translated. | |
680360a4 DR |
1119 | * @vmw_bo_p: Points to a location that, on successful return will carry a |
1120 | * non-reference-counted pointer to the buffer object identified by the | |
ddcda24e TH |
1121 | * user-space handle in @id. |
1122 | * | |
1123 | * This function saves information needed to translate a user-space buffer | |
1124 | * handle to a MOB id. The translation does not take place immediately, but | |
680360a4 DR |
1125 | * during a call to vmw_apply_relocations(). |
1126 | * | |
1127 | * This function builds a relocation list and a list of buffers to validate. The | |
1128 | * former needs to be freed using either vmw_apply_relocations() or | |
1129 | * vmw_free_relocations(). The latter needs to be freed using | |
1130 | * vmw_clear_validations. | |
ddcda24e TH |
1131 | */ |
1132 | static int vmw_translate_mob_ptr(struct vmw_private *dev_priv, | |
1133 | struct vmw_sw_context *sw_context, | |
1134 | SVGAMobId *id, | |
09881d29 | 1135 | struct vmw_bo **vmw_bo_p) |
ddcda24e | 1136 | { |
91398b41 | 1137 | struct vmw_bo *vmw_bo, *tmp_bo; |
ddcda24e TH |
1138 | uint32_t handle = *id; |
1139 | struct vmw_relocation *reloc; | |
1140 | int ret; | |
1141 | ||
b139d43d | 1142 | vmw_validation_preload_bo(sw_context->ctx); |
a309c719 ZR |
1143 | ret = vmw_user_bo_lookup(sw_context->filp, handle, &vmw_bo); |
1144 | if (ret != 0) { | |
1145 | drm_dbg(&dev_priv->drm, "Could not find or use MOB buffer.\n"); | |
b139d43d | 1146 | return PTR_ERR(vmw_bo); |
ddcda24e | 1147 | } |
39985eea ZR |
1148 | vmw_bo_placement_set(vmw_bo, VMW_BO_DOMAIN_MOB, VMW_BO_DOMAIN_MOB); |
1149 | ret = vmw_validation_add_bo(sw_context->ctx, vmw_bo); | |
91398b41 ZR |
1150 | tmp_bo = vmw_bo; |
1151 | vmw_user_bo_unref(&tmp_bo); | |
b139d43d TH |
1152 | if (unlikely(ret != 0)) |
1153 | return ret; | |
1154 | ||
fc18afcf TH |
1155 | reloc = vmw_validation_mem_alloc(sw_context->ctx, sizeof(*reloc)); |
1156 | if (!reloc) | |
b139d43d | 1157 | return -ENOMEM; |
ddcda24e | 1158 | |
ddcda24e | 1159 | reloc->mob_loc = id; |
9c079b8c | 1160 | reloc->vbo = vmw_bo; |
ddcda24e | 1161 | |
ddcda24e | 1162 | *vmw_bo_p = vmw_bo; |
fc18afcf TH |
1163 | list_add_tail(&reloc->head, &sw_context->bo_relocations); |
1164 | ||
ddcda24e | 1165 | return 0; |
ddcda24e TH |
1166 | } |
1167 | ||
e2fa3a76 | 1168 | /** |
2cd80dbd | 1169 | * vmw_translate_guest_ptr - Prepare to translate a user-space buffer handle |
680360a4 | 1170 | * to a valid SVGAGuestPtr |
e2fa3a76 | 1171 | * |
c0951b79 TH |
1172 | * @dev_priv: Pointer to a device private structure. |
1173 | * @sw_context: The software context used for this command batch validation. | |
1174 | * @ptr: Pointer to the user-space handle to be translated. | |
680360a4 DR |
1175 | * @vmw_bo_p: Points to a location that, on successful return will carry a |
1176 | * non-reference-counted pointer to the DMA buffer identified by the user-space | |
1177 | * handle in @id. | |
e2fa3a76 | 1178 | * |
c0951b79 TH |
1179 | * This function saves information needed to translate a user-space buffer |
1180 | * handle to a valid SVGAGuestPtr. The translation does not take place | |
1181 | * immediately, but during a call to vmw_apply_relocations(). | |
680360a4 | 1182 | * |
c0951b79 TH |
1183 | * This function builds a relocation list and a list of buffers to validate. |
1184 | * The former needs to be freed using either vmw_apply_relocations() or | |
1185 | * vmw_free_relocations(). The latter needs to be freed using | |
1186 | * vmw_clear_validations. | |
e2fa3a76 | 1187 | */ |
4e4ddd47 TH |
1188 | static int vmw_translate_guest_ptr(struct vmw_private *dev_priv, |
1189 | struct vmw_sw_context *sw_context, | |
1190 | SVGAGuestPtr *ptr, | |
09881d29 | 1191 | struct vmw_bo **vmw_bo_p) |
fb1d9738 | 1192 | { |
91398b41 | 1193 | struct vmw_bo *vmw_bo, *tmp_bo; |
4e4ddd47 | 1194 | uint32_t handle = ptr->gmrId; |
fb1d9738 | 1195 | struct vmw_relocation *reloc; |
4e4ddd47 | 1196 | int ret; |
fb1d9738 | 1197 | |
b139d43d | 1198 | vmw_validation_preload_bo(sw_context->ctx); |
a309c719 ZR |
1199 | ret = vmw_user_bo_lookup(sw_context->filp, handle, &vmw_bo); |
1200 | if (ret != 0) { | |
1201 | drm_dbg(&dev_priv->drm, "Could not find or use GMR region.\n"); | |
b139d43d | 1202 | return PTR_ERR(vmw_bo); |
fb1d9738 | 1203 | } |
39985eea ZR |
1204 | vmw_bo_placement_set(vmw_bo, VMW_BO_DOMAIN_GMR | VMW_BO_DOMAIN_VRAM, |
1205 | VMW_BO_DOMAIN_GMR | VMW_BO_DOMAIN_VRAM); | |
1206 | ret = vmw_validation_add_bo(sw_context->ctx, vmw_bo); | |
91398b41 ZR |
1207 | tmp_bo = vmw_bo; |
1208 | vmw_user_bo_unref(&tmp_bo); | |
b139d43d TH |
1209 | if (unlikely(ret != 0)) |
1210 | return ret; | |
1211 | ||
fc18afcf TH |
1212 | reloc = vmw_validation_mem_alloc(sw_context->ctx, sizeof(*reloc)); |
1213 | if (!reloc) | |
b139d43d | 1214 | return -ENOMEM; |
fb1d9738 | 1215 | |
4e4ddd47 | 1216 | reloc->location = ptr; |
9c079b8c | 1217 | reloc->vbo = vmw_bo; |
4e4ddd47 | 1218 | *vmw_bo_p = vmw_bo; |
fc18afcf TH |
1219 | list_add_tail(&reloc->head, &sw_context->bo_relocations); |
1220 | ||
4e4ddd47 | 1221 | return 0; |
4e4ddd47 TH |
1222 | } |
1223 | ||
fd11a3c0 | 1224 | /** |
680360a4 | 1225 | * vmw_cmd_dx_define_query - validate SVGA_3D_CMD_DX_DEFINE_QUERY command. |
fd11a3c0 SY |
1226 | * |
1227 | * @dev_priv: Pointer to a device private struct. | |
1228 | * @sw_context: The software context used for this command submission. | |
1229 | * @header: Pointer to the command header in the command stream. | |
1230 | * | |
1231 | * This function adds the new query into the query COTABLE | |
1232 | */ | |
1233 | static int vmw_cmd_dx_define_query(struct vmw_private *dev_priv, | |
1234 | struct vmw_sw_context *sw_context, | |
1235 | SVGA3dCmdHeader *header) | |
1236 | { | |
d01316d0 | 1237 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdDXDefineQuery); |
6f74fd91 | 1238 | struct vmw_ctx_validation_info *ctx_node = VMW_GET_CTX_NODE(sw_context); |
fd11a3c0 | 1239 | struct vmw_resource *cotable_res; |
d01316d0 | 1240 | int ret; |
fd11a3c0 | 1241 | |
6f74fd91 | 1242 | if (!ctx_node) |
fd11a3c0 | 1243 | return -EINVAL; |
fd11a3c0 | 1244 | |
d01316d0 | 1245 | cmd = container_of(header, typeof(*cmd), header); |
fd11a3c0 | 1246 | |
d01316d0 DR |
1247 | if (cmd->body.type < SVGA3D_QUERYTYPE_MIN || |
1248 | cmd->body.type >= SVGA3D_QUERYTYPE_MAX) | |
fd11a3c0 SY |
1249 | return -EINVAL; |
1250 | ||
9c079b8c | 1251 | cotable_res = vmw_context_cotable(ctx_node->ctx, SVGA_COTABLE_DXQUERY); |
517621b7 ZR |
1252 | if (IS_ERR_OR_NULL(cotable_res)) |
1253 | return cotable_res ? PTR_ERR(cotable_res) : -EINVAL; | |
d01316d0 | 1254 | ret = vmw_cotable_notify(cotable_res, cmd->body.queryId); |
fd11a3c0 SY |
1255 | |
1256 | return ret; | |
1257 | } | |
1258 | ||
fd11a3c0 | 1259 | /** |
680360a4 | 1260 | * vmw_cmd_dx_bind_query - validate SVGA_3D_CMD_DX_BIND_QUERY command. |
fd11a3c0 SY |
1261 | * |
1262 | * @dev_priv: Pointer to a device private struct. | |
1263 | * @sw_context: The software context used for this command submission. | |
1264 | * @header: Pointer to the command header in the command stream. | |
1265 | * | |
680360a4 DR |
1266 | * The query bind operation will eventually associate the query ID with its |
1267 | * backing MOB. In this function, we take the user mode MOB ID and use | |
1268 | * vmw_translate_mob_ptr() to translate it to its kernel mode equivalent. | |
fd11a3c0 SY |
1269 | */ |
1270 | static int vmw_cmd_dx_bind_query(struct vmw_private *dev_priv, | |
1271 | struct vmw_sw_context *sw_context, | |
1272 | SVGA3dCmdHeader *header) | |
1273 | { | |
d01316d0 | 1274 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdDXBindQuery); |
09881d29 | 1275 | struct vmw_bo *vmw_bo; |
d01316d0 | 1276 | int ret; |
fd11a3c0 | 1277 | |
d01316d0 | 1278 | cmd = container_of(header, typeof(*cmd), header); |
fd11a3c0 SY |
1279 | |
1280 | /* | |
1281 | * Look up the buffer pointed to by q.mobid, put it on the relocation | |
1282 | * list so its kernel mode MOB ID can be filled in later | |
1283 | */ | |
d01316d0 | 1284 | ret = vmw_translate_mob_ptr(dev_priv, sw_context, &cmd->body.mobid, |
fd11a3c0 SY |
1285 | &vmw_bo); |
1286 | ||
1287 | if (ret != 0) | |
1288 | return ret; | |
1289 | ||
1290 | sw_context->dx_query_mob = vmw_bo; | |
9c079b8c | 1291 | sw_context->dx_query_ctx = sw_context->dx_ctx_node->ctx; |
b139d43d | 1292 | return 0; |
fd11a3c0 SY |
1293 | } |
1294 | ||
ddcda24e | 1295 | /** |
680360a4 | 1296 | * vmw_cmd_begin_gb_query - validate SVGA_3D_CMD_BEGIN_GB_QUERY command. |
ddcda24e TH |
1297 | * |
1298 | * @dev_priv: Pointer to a device private struct. | |
1299 | * @sw_context: The software context used for this command submission. | |
1300 | * @header: Pointer to the command header in the command stream. | |
1301 | */ | |
1302 | static int vmw_cmd_begin_gb_query(struct vmw_private *dev_priv, | |
1303 | struct vmw_sw_context *sw_context, | |
1304 | SVGA3dCmdHeader *header) | |
1305 | { | |
d01316d0 DR |
1306 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdBeginGBQuery) = |
1307 | container_of(header, typeof(*cmd), header); | |
ddcda24e TH |
1308 | |
1309 | return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context, | |
a9f58c45 | 1310 | VMW_RES_DIRTY_SET, user_context_converter, |
d01316d0 | 1311 | &cmd->body.cid, NULL); |
ddcda24e TH |
1312 | } |
1313 | ||
c0951b79 | 1314 | /** |
680360a4 | 1315 | * vmw_cmd_begin_query - validate SVGA_3D_CMD_BEGIN_QUERY command. |
c0951b79 TH |
1316 | * |
1317 | * @dev_priv: Pointer to a device private struct. | |
1318 | * @sw_context: The software context used for this command submission. | |
1319 | * @header: Pointer to the command header in the command stream. | |
1320 | */ | |
1321 | static int vmw_cmd_begin_query(struct vmw_private *dev_priv, | |
1322 | struct vmw_sw_context *sw_context, | |
1323 | SVGA3dCmdHeader *header) | |
1324 | { | |
d01316d0 DR |
1325 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdBeginQuery) = |
1326 | container_of(header, typeof(*cmd), header); | |
c0951b79 | 1327 | |
ddcda24e | 1328 | if (unlikely(dev_priv->has_mob)) { |
d01316d0 | 1329 | VMW_DECLARE_CMD_VAR(gb_cmd, SVGA3dCmdBeginGBQuery); |
ddcda24e TH |
1330 | |
1331 | BUG_ON(sizeof(gb_cmd) != sizeof(*cmd)); | |
1332 | ||
1333 | gb_cmd.header.id = SVGA_3D_CMD_BEGIN_GB_QUERY; | |
1334 | gb_cmd.header.size = cmd->header.size; | |
d01316d0 DR |
1335 | gb_cmd.body.cid = cmd->body.cid; |
1336 | gb_cmd.body.type = cmd->body.type; | |
ddcda24e TH |
1337 | |
1338 | memcpy(cmd, &gb_cmd, sizeof(*cmd)); | |
1339 | return vmw_cmd_begin_gb_query(dev_priv, sw_context, header); | |
1340 | } | |
1341 | ||
c0951b79 | 1342 | return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context, |
a9f58c45 | 1343 | VMW_RES_DIRTY_SET, user_context_converter, |
d01316d0 | 1344 | &cmd->body.cid, NULL); |
c0951b79 TH |
1345 | } |
1346 | ||
ddcda24e | 1347 | /** |
680360a4 | 1348 | * vmw_cmd_end_gb_query - validate SVGA_3D_CMD_END_GB_QUERY command. |
ddcda24e TH |
1349 | * |
1350 | * @dev_priv: Pointer to a device private struct. | |
1351 | * @sw_context: The software context used for this command submission. | |
1352 | * @header: Pointer to the command header in the command stream. | |
1353 | */ | |
1354 | static int vmw_cmd_end_gb_query(struct vmw_private *dev_priv, | |
1355 | struct vmw_sw_context *sw_context, | |
1356 | SVGA3dCmdHeader *header) | |
1357 | { | |
09881d29 | 1358 | struct vmw_bo *vmw_bo; |
d01316d0 | 1359 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdEndGBQuery); |
ddcda24e TH |
1360 | int ret; |
1361 | ||
d01316d0 | 1362 | cmd = container_of(header, typeof(*cmd), header); |
ddcda24e TH |
1363 | ret = vmw_cmd_cid_check(dev_priv, sw_context, header); |
1364 | if (unlikely(ret != 0)) | |
1365 | return ret; | |
1366 | ||
680360a4 | 1367 | ret = vmw_translate_mob_ptr(dev_priv, sw_context, &cmd->body.mobid, |
ddcda24e TH |
1368 | &vmw_bo); |
1369 | if (unlikely(ret != 0)) | |
1370 | return ret; | |
1371 | ||
459d0fa7 | 1372 | ret = vmw_query_bo_switch_prepare(dev_priv, vmw_bo, sw_context); |
ddcda24e | 1373 | |
ddcda24e TH |
1374 | return ret; |
1375 | } | |
1376 | ||
c0951b79 | 1377 | /** |
680360a4 | 1378 | * vmw_cmd_end_query - validate SVGA_3D_CMD_END_QUERY command. |
c0951b79 TH |
1379 | * |
1380 | * @dev_priv: Pointer to a device private struct. | |
1381 | * @sw_context: The software context used for this command submission. | |
1382 | * @header: Pointer to the command header in the command stream. | |
1383 | */ | |
4e4ddd47 TH |
1384 | static int vmw_cmd_end_query(struct vmw_private *dev_priv, |
1385 | struct vmw_sw_context *sw_context, | |
1386 | SVGA3dCmdHeader *header) | |
1387 | { | |
09881d29 | 1388 | struct vmw_bo *vmw_bo; |
d01316d0 | 1389 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdEndQuery); |
4e4ddd47 TH |
1390 | int ret; |
1391 | ||
d01316d0 | 1392 | cmd = container_of(header, typeof(*cmd), header); |
ddcda24e | 1393 | if (dev_priv->has_mob) { |
d01316d0 | 1394 | VMW_DECLARE_CMD_VAR(gb_cmd, SVGA3dCmdEndGBQuery); |
ddcda24e TH |
1395 | |
1396 | BUG_ON(sizeof(gb_cmd) != sizeof(*cmd)); | |
1397 | ||
1398 | gb_cmd.header.id = SVGA_3D_CMD_END_GB_QUERY; | |
1399 | gb_cmd.header.size = cmd->header.size; | |
d01316d0 DR |
1400 | gb_cmd.body.cid = cmd->body.cid; |
1401 | gb_cmd.body.type = cmd->body.type; | |
1402 | gb_cmd.body.mobid = cmd->body.guestResult.gmrId; | |
1403 | gb_cmd.body.offset = cmd->body.guestResult.offset; | |
ddcda24e TH |
1404 | |
1405 | memcpy(cmd, &gb_cmd, sizeof(*cmd)); | |
1406 | return vmw_cmd_end_gb_query(dev_priv, sw_context, header); | |
1407 | } | |
1408 | ||
4e4ddd47 TH |
1409 | ret = vmw_cmd_cid_check(dev_priv, sw_context, header); |
1410 | if (unlikely(ret != 0)) | |
1411 | return ret; | |
1412 | ||
1413 | ret = vmw_translate_guest_ptr(dev_priv, sw_context, | |
680360a4 | 1414 | &cmd->body.guestResult, &vmw_bo); |
4e4ddd47 TH |
1415 | if (unlikely(ret != 0)) |
1416 | return ret; | |
1417 | ||
459d0fa7 | 1418 | ret = vmw_query_bo_switch_prepare(dev_priv, vmw_bo, sw_context); |
e2fa3a76 | 1419 | |
e2fa3a76 | 1420 | return ret; |
4e4ddd47 | 1421 | } |
fb1d9738 | 1422 | |
ddcda24e | 1423 | /** |
680360a4 | 1424 | * vmw_cmd_wait_gb_query - validate SVGA_3D_CMD_WAIT_GB_QUERY command. |
ddcda24e TH |
1425 | * |
1426 | * @dev_priv: Pointer to a device private struct. | |
1427 | * @sw_context: The software context used for this command submission. | |
1428 | * @header: Pointer to the command header in the command stream. | |
1429 | */ | |
1430 | static int vmw_cmd_wait_gb_query(struct vmw_private *dev_priv, | |
1431 | struct vmw_sw_context *sw_context, | |
1432 | SVGA3dCmdHeader *header) | |
1433 | { | |
09881d29 | 1434 | struct vmw_bo *vmw_bo; |
d01316d0 | 1435 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdWaitForGBQuery); |
ddcda24e TH |
1436 | int ret; |
1437 | ||
d01316d0 | 1438 | cmd = container_of(header, typeof(*cmd), header); |
ddcda24e TH |
1439 | ret = vmw_cmd_cid_check(dev_priv, sw_context, header); |
1440 | if (unlikely(ret != 0)) | |
1441 | return ret; | |
1442 | ||
680360a4 | 1443 | ret = vmw_translate_mob_ptr(dev_priv, sw_context, &cmd->body.mobid, |
ddcda24e TH |
1444 | &vmw_bo); |
1445 | if (unlikely(ret != 0)) | |
1446 | return ret; | |
1447 | ||
ddcda24e TH |
1448 | return 0; |
1449 | } | |
1450 | ||
1451 | /** | |
680360a4 | 1452 | * vmw_cmd_wait_query - validate SVGA_3D_CMD_WAIT_QUERY command. |
c0951b79 TH |
1453 | * |
1454 | * @dev_priv: Pointer to a device private struct. | |
1455 | * @sw_context: The software context used for this command submission. | |
1456 | * @header: Pointer to the command header in the command stream. | |
1457 | */ | |
4e4ddd47 TH |
1458 | static int vmw_cmd_wait_query(struct vmw_private *dev_priv, |
1459 | struct vmw_sw_context *sw_context, | |
1460 | SVGA3dCmdHeader *header) | |
1461 | { | |
09881d29 | 1462 | struct vmw_bo *vmw_bo; |
d01316d0 | 1463 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdWaitForQuery); |
4e4ddd47 TH |
1464 | int ret; |
1465 | ||
d01316d0 | 1466 | cmd = container_of(header, typeof(*cmd), header); |
ddcda24e | 1467 | if (dev_priv->has_mob) { |
d01316d0 | 1468 | VMW_DECLARE_CMD_VAR(gb_cmd, SVGA3dCmdWaitForGBQuery); |
ddcda24e TH |
1469 | |
1470 | BUG_ON(sizeof(gb_cmd) != sizeof(*cmd)); | |
1471 | ||
1472 | gb_cmd.header.id = SVGA_3D_CMD_WAIT_FOR_GB_QUERY; | |
1473 | gb_cmd.header.size = cmd->header.size; | |
d01316d0 DR |
1474 | gb_cmd.body.cid = cmd->body.cid; |
1475 | gb_cmd.body.type = cmd->body.type; | |
1476 | gb_cmd.body.mobid = cmd->body.guestResult.gmrId; | |
1477 | gb_cmd.body.offset = cmd->body.guestResult.offset; | |
ddcda24e TH |
1478 | |
1479 | memcpy(cmd, &gb_cmd, sizeof(*cmd)); | |
1480 | return vmw_cmd_wait_gb_query(dev_priv, sw_context, header); | |
1481 | } | |
1482 | ||
4e4ddd47 TH |
1483 | ret = vmw_cmd_cid_check(dev_priv, sw_context, header); |
1484 | if (unlikely(ret != 0)) | |
1485 | return ret; | |
1486 | ||
1487 | ret = vmw_translate_guest_ptr(dev_priv, sw_context, | |
680360a4 | 1488 | &cmd->body.guestResult, &vmw_bo); |
4e4ddd47 TH |
1489 | if (unlikely(ret != 0)) |
1490 | return ret; | |
1491 | ||
4e4ddd47 TH |
1492 | return 0; |
1493 | } | |
1494 | ||
4e4ddd47 TH |
1495 | static int vmw_cmd_dma(struct vmw_private *dev_priv, |
1496 | struct vmw_sw_context *sw_context, | |
1497 | SVGA3dCmdHeader *header) | |
1498 | { | |
09881d29 | 1499 | struct vmw_bo *vmw_bo = NULL; |
4e4ddd47 | 1500 | struct vmw_surface *srf = NULL; |
d01316d0 | 1501 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdSurfaceDMA); |
4e4ddd47 | 1502 | int ret; |
cbd75e97 TH |
1503 | SVGA3dCmdSurfaceDMASuffix *suffix; |
1504 | uint32_t bo_size; | |
a9f58c45 | 1505 | bool dirty; |
4e4ddd47 | 1506 | |
d01316d0 DR |
1507 | cmd = container_of(header, typeof(*cmd), header); |
1508 | suffix = (SVGA3dCmdSurfaceDMASuffix *)((unsigned long) &cmd->body + | |
cbd75e97 TH |
1509 | header->size - sizeof(*suffix)); |
1510 | ||
1511 | /* Make sure device and verifier stays in sync. */ | |
1512 | if (unlikely(suffix->suffixSize != sizeof(*suffix))) { | |
5724f899 | 1513 | VMW_DEBUG_USER("Invalid DMA suffix size.\n"); |
cbd75e97 TH |
1514 | return -EINVAL; |
1515 | } | |
1516 | ||
4e4ddd47 | 1517 | ret = vmw_translate_guest_ptr(dev_priv, sw_context, |
680360a4 | 1518 | &cmd->body.guest.ptr, &vmw_bo); |
4e4ddd47 TH |
1519 | if (unlikely(ret != 0)) |
1520 | return ret; | |
1521 | ||
cbd75e97 | 1522 | /* Make sure DMA doesn't cross BO boundaries. */ |
668b2066 | 1523 | bo_size = vmw_bo->tbo.base.size; |
d01316d0 | 1524 | if (unlikely(cmd->body.guest.ptr.offset > bo_size)) { |
5724f899 | 1525 | VMW_DEBUG_USER("Invalid DMA offset.\n"); |
cbd75e97 TH |
1526 | return -EINVAL; |
1527 | } | |
1528 | ||
d01316d0 | 1529 | bo_size -= cmd->body.guest.ptr.offset; |
cbd75e97 TH |
1530 | if (unlikely(suffix->maximumOffset > bo_size)) |
1531 | suffix->maximumOffset = bo_size; | |
1532 | ||
d01316d0 | 1533 | dirty = (cmd->body.transfer == SVGA3D_WRITE_HOST_VRAM) ? |
a9f58c45 | 1534 | VMW_RES_DIRTY_SET : 0; |
c0951b79 | 1535 | ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, |
a9f58c45 | 1536 | dirty, user_surface_converter, |
d01316d0 | 1537 | &cmd->body.host.sid, NULL); |
5bb39e81 | 1538 | if (unlikely(ret != 0)) { |
c0951b79 | 1539 | if (unlikely(ret != -ERESTARTSYS)) |
5724f899 | 1540 | VMW_DEBUG_USER("could not find surface for DMA.\n"); |
b139d43d | 1541 | return ret; |
5bb39e81 TH |
1542 | } |
1543 | ||
c0951b79 | 1544 | srf = vmw_res_to_srf(sw_context->res_cache[vmw_res_surface].res); |
f18c8840 | 1545 | |
668b2066 | 1546 | vmw_kms_cursor_snoop(srf, sw_context->fp->tfile, &vmw_bo->tbo, header); |
fb1d9738 | 1547 | |
b139d43d | 1548 | return 0; |
fb1d9738 JB |
1549 | } |
1550 | ||
7a73ba74 TH |
1551 | static int vmw_cmd_draw(struct vmw_private *dev_priv, |
1552 | struct vmw_sw_context *sw_context, | |
1553 | SVGA3dCmdHeader *header) | |
1554 | { | |
d01316d0 | 1555 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdDrawPrimitives); |
7a73ba74 TH |
1556 | SVGA3dVertexDecl *decl = (SVGA3dVertexDecl *)( |
1557 | (unsigned long)header + sizeof(*cmd)); | |
1558 | SVGA3dPrimitiveRange *range; | |
1559 | uint32_t i; | |
1560 | uint32_t maxnum; | |
1561 | int ret; | |
1562 | ||
1563 | ret = vmw_cmd_cid_check(dev_priv, sw_context, header); | |
1564 | if (unlikely(ret != 0)) | |
1565 | return ret; | |
1566 | ||
d01316d0 | 1567 | cmd = container_of(header, typeof(*cmd), header); |
7a73ba74 TH |
1568 | maxnum = (header->size - sizeof(cmd->body)) / sizeof(*decl); |
1569 | ||
1570 | if (unlikely(cmd->body.numVertexDecls > maxnum)) { | |
5724f899 | 1571 | VMW_DEBUG_USER("Illegal number of vertex declarations.\n"); |
7a73ba74 TH |
1572 | return -EINVAL; |
1573 | } | |
1574 | ||
1575 | for (i = 0; i < cmd->body.numVertexDecls; ++i, ++decl) { | |
c0951b79 | 1576 | ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, |
a9f58c45 | 1577 | VMW_RES_DIRTY_NONE, |
c0951b79 TH |
1578 | user_surface_converter, |
1579 | &decl->array.surfaceId, NULL); | |
7a73ba74 TH |
1580 | if (unlikely(ret != 0)) |
1581 | return ret; | |
1582 | } | |
1583 | ||
1584 | maxnum = (header->size - sizeof(cmd->body) - | |
1585 | cmd->body.numVertexDecls * sizeof(*decl)) / sizeof(*range); | |
1586 | if (unlikely(cmd->body.numRanges > maxnum)) { | |
5724f899 | 1587 | VMW_DEBUG_USER("Illegal number of index ranges.\n"); |
7a73ba74 TH |
1588 | return -EINVAL; |
1589 | } | |
1590 | ||
1591 | range = (SVGA3dPrimitiveRange *) decl; | |
1592 | for (i = 0; i < cmd->body.numRanges; ++i, ++range) { | |
c0951b79 | 1593 | ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, |
a9f58c45 | 1594 | VMW_RES_DIRTY_NONE, |
c0951b79 TH |
1595 | user_surface_converter, |
1596 | &range->indexArray.surfaceId, NULL); | |
7a73ba74 TH |
1597 | if (unlikely(ret != 0)) |
1598 | return ret; | |
1599 | } | |
1600 | return 0; | |
1601 | } | |
1602 | ||
7a73ba74 TH |
1603 | static int vmw_cmd_tex_state(struct vmw_private *dev_priv, |
1604 | struct vmw_sw_context *sw_context, | |
1605 | SVGA3dCmdHeader *header) | |
1606 | { | |
d01316d0 | 1607 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdSetTextureState); |
7a73ba74 | 1608 | SVGA3dTextureState *last_state = (SVGA3dTextureState *) |
39465cac | 1609 | ((unsigned long) header + header->size + sizeof(*header)); |
7a73ba74 | 1610 | SVGA3dTextureState *cur_state = (SVGA3dTextureState *) |
d01316d0 | 1611 | ((unsigned long) header + sizeof(*cmd)); |
9c079b8c TH |
1612 | struct vmw_resource *ctx; |
1613 | struct vmw_resource *res; | |
7a73ba74 TH |
1614 | int ret; |
1615 | ||
d01316d0 | 1616 | cmd = container_of(header, typeof(*cmd), header); |
b5c3b1a6 TH |
1617 | |
1618 | ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context, | |
a9f58c45 | 1619 | VMW_RES_DIRTY_SET, user_context_converter, |
d01316d0 | 1620 | &cmd->body.cid, &ctx); |
7a73ba74 TH |
1621 | if (unlikely(ret != 0)) |
1622 | return ret; | |
1623 | ||
1624 | for (; cur_state < last_state; ++cur_state) { | |
1625 | if (likely(cur_state->name != SVGA3D_TS_BIND_TEXTURE)) | |
1626 | continue; | |
1627 | ||
d80efd5c | 1628 | if (cur_state->stage >= SVGA3D_NUM_TEXTURE_UNITS) { |
5724f899 DR |
1629 | VMW_DEBUG_USER("Illegal texture/sampler unit %u.\n", |
1630 | (unsigned int) cur_state->stage); | |
d80efd5c TH |
1631 | return -EINVAL; |
1632 | } | |
1633 | ||
c0951b79 | 1634 | ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, |
a9f58c45 | 1635 | VMW_RES_DIRTY_NONE, |
c0951b79 | 1636 | user_surface_converter, |
9c079b8c | 1637 | &cur_state->value, &res); |
7a73ba74 TH |
1638 | if (unlikely(ret != 0)) |
1639 | return ret; | |
b5c3b1a6 TH |
1640 | |
1641 | if (dev_priv->has_mob) { | |
d80efd5c | 1642 | struct vmw_ctx_bindinfo_tex binding; |
9c079b8c | 1643 | struct vmw_ctx_validation_info *node; |
d80efd5c | 1644 | |
9c079b8c TH |
1645 | node = vmw_execbuf_info_from_res(sw_context, ctx); |
1646 | if (!node) | |
1647 | return -EINVAL; | |
1648 | ||
1649 | binding.bi.ctx = ctx; | |
1650 | binding.bi.res = res; | |
d80efd5c TH |
1651 | binding.bi.bt = vmw_ctx_binding_tex; |
1652 | binding.texture_stage = cur_state->stage; | |
9c079b8c TH |
1653 | vmw_binding_add(node->staged, &binding.bi, 0, |
1654 | binding.texture_stage); | |
b5c3b1a6 | 1655 | } |
7a73ba74 TH |
1656 | } |
1657 | ||
1658 | return 0; | |
1659 | } | |
1660 | ||
4084fb89 JB |
1661 | static int vmw_cmd_check_define_gmrfb(struct vmw_private *dev_priv, |
1662 | struct vmw_sw_context *sw_context, | |
1663 | void *buf) | |
1664 | { | |
09881d29 | 1665 | struct vmw_bo *vmw_bo; |
4084fb89 JB |
1666 | |
1667 | struct { | |
1668 | uint32_t header; | |
1669 | SVGAFifoCmdDefineGMRFB body; | |
1670 | } *cmd = buf; | |
1671 | ||
680360a4 | 1672 | return vmw_translate_guest_ptr(dev_priv, sw_context, &cmd->body.ptr, |
b139d43d | 1673 | &vmw_bo); |
4084fb89 JB |
1674 | } |
1675 | ||
d80efd5c TH |
1676 | /** |
1677 | * vmw_cmd_res_switch_backup - Utility function to handle backup buffer | |
1678 | * switching | |
1679 | * | |
1680 | * @dev_priv: Pointer to a device private struct. | |
1681 | * @sw_context: The software context being used for this batch. | |
7450bf76 | 1682 | * @res: Pointer to the resource. |
d80efd5c TH |
1683 | * @buf_id: Pointer to the user-space backup buffer handle in the command |
1684 | * stream. | |
1685 | * @backup_offset: Offset of backup into MOB. | |
1686 | * | |
680360a4 DR |
1687 | * This function prepares for registering a switch of backup buffers in the |
1688 | * resource metadata just prior to unreserving. It's basically a wrapper around | |
1689 | * vmw_cmd_res_switch_backup with a different interface. | |
d80efd5c TH |
1690 | */ |
1691 | static int vmw_cmd_res_switch_backup(struct vmw_private *dev_priv, | |
1692 | struct vmw_sw_context *sw_context, | |
680360a4 | 1693 | struct vmw_resource *res, uint32_t *buf_id, |
d80efd5c TH |
1694 | unsigned long backup_offset) |
1695 | { | |
09881d29 | 1696 | struct vmw_bo *vbo; |
9c079b8c | 1697 | void *info; |
d80efd5c TH |
1698 | int ret; |
1699 | ||
9c079b8c TH |
1700 | info = vmw_execbuf_info_from_res(sw_context, res); |
1701 | if (!info) | |
1702 | return -EINVAL; | |
1703 | ||
1704 | ret = vmw_translate_mob_ptr(dev_priv, sw_context, buf_id, &vbo); | |
d80efd5c TH |
1705 | if (ret) |
1706 | return ret; | |
1707 | ||
9c079b8c TH |
1708 | vmw_validation_res_switch_backup(sw_context->ctx, info, vbo, |
1709 | backup_offset); | |
d80efd5c TH |
1710 | return 0; |
1711 | } | |
1712 | ||
a97e2192 TH |
1713 | /** |
1714 | * vmw_cmd_switch_backup - Utility function to handle backup buffer switching | |
1715 | * | |
1716 | * @dev_priv: Pointer to a device private struct. | |
1717 | * @sw_context: The software context being used for this batch. | |
1718 | * @res_type: The resource type. | |
1719 | * @converter: Information about user-space binding for this resource type. | |
1720 | * @res_id: Pointer to the user-space resource handle in the command stream. | |
1721 | * @buf_id: Pointer to the user-space backup buffer handle in the command | |
1722 | * stream. | |
1723 | * @backup_offset: Offset of backup into MOB. | |
1724 | * | |
680360a4 DR |
1725 | * This function prepares for registering a switch of backup buffers in the |
1726 | * resource metadata just prior to unreserving. It's basically a wrapper around | |
1727 | * vmw_cmd_res_switch_backup with a different interface. | |
a97e2192 TH |
1728 | */ |
1729 | static int vmw_cmd_switch_backup(struct vmw_private *dev_priv, | |
1730 | struct vmw_sw_context *sw_context, | |
1731 | enum vmw_res_type res_type, | |
1732 | const struct vmw_user_resource_conv | |
680360a4 | 1733 | *converter, uint32_t *res_id, uint32_t *buf_id, |
a97e2192 TH |
1734 | unsigned long backup_offset) |
1735 | { | |
9c079b8c | 1736 | struct vmw_resource *res; |
d80efd5c | 1737 | int ret; |
a97e2192 TH |
1738 | |
1739 | ret = vmw_cmd_res_check(dev_priv, sw_context, res_type, | |
a9f58c45 | 1740 | VMW_RES_DIRTY_NONE, converter, res_id, &res); |
d80efd5c | 1741 | if (ret) |
a97e2192 TH |
1742 | return ret; |
1743 | ||
680360a4 DR |
1744 | return vmw_cmd_res_switch_backup(dev_priv, sw_context, res, buf_id, |
1745 | backup_offset); | |
a97e2192 TH |
1746 | } |
1747 | ||
1748 | /** | |
680360a4 | 1749 | * vmw_cmd_bind_gb_surface - Validate SVGA_3D_CMD_BIND_GB_SURFACE command |
a97e2192 TH |
1750 | * |
1751 | * @dev_priv: Pointer to a device private struct. | |
1752 | * @sw_context: The software context being used for this batch. | |
1753 | * @header: Pointer to the command header in the command stream. | |
1754 | */ | |
1755 | static int vmw_cmd_bind_gb_surface(struct vmw_private *dev_priv, | |
1756 | struct vmw_sw_context *sw_context, | |
1757 | SVGA3dCmdHeader *header) | |
1758 | { | |
d01316d0 DR |
1759 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdBindGBSurface) = |
1760 | container_of(header, typeof(*cmd), header); | |
a97e2192 TH |
1761 | |
1762 | return vmw_cmd_switch_backup(dev_priv, sw_context, vmw_res_surface, | |
680360a4 DR |
1763 | user_surface_converter, &cmd->body.sid, |
1764 | &cmd->body.mobid, 0); | |
a97e2192 TH |
1765 | } |
1766 | ||
1767 | /** | |
680360a4 | 1768 | * vmw_cmd_update_gb_image - Validate SVGA_3D_CMD_UPDATE_GB_IMAGE command |
a97e2192 TH |
1769 | * |
1770 | * @dev_priv: Pointer to a device private struct. | |
1771 | * @sw_context: The software context being used for this batch. | |
1772 | * @header: Pointer to the command header in the command stream. | |
1773 | */ | |
1774 | static int vmw_cmd_update_gb_image(struct vmw_private *dev_priv, | |
1775 | struct vmw_sw_context *sw_context, | |
1776 | SVGA3dCmdHeader *header) | |
1777 | { | |
d01316d0 DR |
1778 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdUpdateGBImage) = |
1779 | container_of(header, typeof(*cmd), header); | |
a97e2192 TH |
1780 | |
1781 | return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, | |
a9f58c45 | 1782 | VMW_RES_DIRTY_NONE, user_surface_converter, |
a97e2192 TH |
1783 | &cmd->body.image.sid, NULL); |
1784 | } | |
1785 | ||
1786 | /** | |
680360a4 | 1787 | * vmw_cmd_update_gb_surface - Validate SVGA_3D_CMD_UPDATE_GB_SURFACE command |
a97e2192 TH |
1788 | * |
1789 | * @dev_priv: Pointer to a device private struct. | |
1790 | * @sw_context: The software context being used for this batch. | |
1791 | * @header: Pointer to the command header in the command stream. | |
1792 | */ | |
1793 | static int vmw_cmd_update_gb_surface(struct vmw_private *dev_priv, | |
1794 | struct vmw_sw_context *sw_context, | |
1795 | SVGA3dCmdHeader *header) | |
1796 | { | |
d01316d0 DR |
1797 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdUpdateGBSurface) = |
1798 | container_of(header, typeof(*cmd), header); | |
a97e2192 TH |
1799 | |
1800 | return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, | |
a9f58c45 | 1801 | VMW_RES_DIRTY_CLEAR, user_surface_converter, |
a97e2192 TH |
1802 | &cmd->body.sid, NULL); |
1803 | } | |
1804 | ||
1805 | /** | |
680360a4 | 1806 | * vmw_cmd_readback_gb_image - Validate SVGA_3D_CMD_READBACK_GB_IMAGE command |
a97e2192 TH |
1807 | * |
1808 | * @dev_priv: Pointer to a device private struct. | |
1809 | * @sw_context: The software context being used for this batch. | |
1810 | * @header: Pointer to the command header in the command stream. | |
1811 | */ | |
1812 | static int vmw_cmd_readback_gb_image(struct vmw_private *dev_priv, | |
1813 | struct vmw_sw_context *sw_context, | |
1814 | SVGA3dCmdHeader *header) | |
1815 | { | |
d01316d0 DR |
1816 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdReadbackGBImage) = |
1817 | container_of(header, typeof(*cmd), header); | |
a97e2192 TH |
1818 | |
1819 | return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, | |
a9f58c45 | 1820 | VMW_RES_DIRTY_NONE, user_surface_converter, |
a97e2192 TH |
1821 | &cmd->body.image.sid, NULL); |
1822 | } | |
1823 | ||
1824 | /** | |
680360a4 | 1825 | * vmw_cmd_readback_gb_surface - Validate SVGA_3D_CMD_READBACK_GB_SURFACE |
a97e2192 TH |
1826 | * command |
1827 | * | |
1828 | * @dev_priv: Pointer to a device private struct. | |
1829 | * @sw_context: The software context being used for this batch. | |
1830 | * @header: Pointer to the command header in the command stream. | |
1831 | */ | |
1832 | static int vmw_cmd_readback_gb_surface(struct vmw_private *dev_priv, | |
1833 | struct vmw_sw_context *sw_context, | |
1834 | SVGA3dCmdHeader *header) | |
1835 | { | |
d01316d0 DR |
1836 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdReadbackGBSurface) = |
1837 | container_of(header, typeof(*cmd), header); | |
a97e2192 TH |
1838 | |
1839 | return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, | |
a9f58c45 | 1840 | VMW_RES_DIRTY_CLEAR, user_surface_converter, |
a97e2192 TH |
1841 | &cmd->body.sid, NULL); |
1842 | } | |
1843 | ||
1844 | /** | |
680360a4 | 1845 | * vmw_cmd_invalidate_gb_image - Validate SVGA_3D_CMD_INVALIDATE_GB_IMAGE |
a97e2192 TH |
1846 | * command |
1847 | * | |
1848 | * @dev_priv: Pointer to a device private struct. | |
1849 | * @sw_context: The software context being used for this batch. | |
1850 | * @header: Pointer to the command header in the command stream. | |
1851 | */ | |
1852 | static int vmw_cmd_invalidate_gb_image(struct vmw_private *dev_priv, | |
1853 | struct vmw_sw_context *sw_context, | |
1854 | SVGA3dCmdHeader *header) | |
1855 | { | |
d01316d0 DR |
1856 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdInvalidateGBImage) = |
1857 | container_of(header, typeof(*cmd), header); | |
a97e2192 TH |
1858 | |
1859 | return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, | |
a9f58c45 | 1860 | VMW_RES_DIRTY_NONE, user_surface_converter, |
a97e2192 TH |
1861 | &cmd->body.image.sid, NULL); |
1862 | } | |
1863 | ||
1864 | /** | |
680360a4 DR |
1865 | * vmw_cmd_invalidate_gb_surface - Validate SVGA_3D_CMD_INVALIDATE_GB_SURFACE |
1866 | * command | |
a97e2192 TH |
1867 | * |
1868 | * @dev_priv: Pointer to a device private struct. | |
1869 | * @sw_context: The software context being used for this batch. | |
1870 | * @header: Pointer to the command header in the command stream. | |
1871 | */ | |
1872 | static int vmw_cmd_invalidate_gb_surface(struct vmw_private *dev_priv, | |
1873 | struct vmw_sw_context *sw_context, | |
1874 | SVGA3dCmdHeader *header) | |
1875 | { | |
d01316d0 DR |
1876 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdInvalidateGBSurface) = |
1877 | container_of(header, typeof(*cmd), header); | |
a97e2192 TH |
1878 | |
1879 | return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, | |
a9f58c45 | 1880 | VMW_RES_DIRTY_CLEAR, user_surface_converter, |
a97e2192 TH |
1881 | &cmd->body.sid, NULL); |
1882 | } | |
1883 | ||
d5bde956 | 1884 | /** |
680360a4 | 1885 | * vmw_cmd_shader_define - Validate SVGA_3D_CMD_SHADER_DEFINE command |
d5bde956 TH |
1886 | * |
1887 | * @dev_priv: Pointer to a device private struct. | |
1888 | * @sw_context: The software context being used for this batch. | |
1889 | * @header: Pointer to the command header in the command stream. | |
1890 | */ | |
1891 | static int vmw_cmd_shader_define(struct vmw_private *dev_priv, | |
1892 | struct vmw_sw_context *sw_context, | |
1893 | SVGA3dCmdHeader *header) | |
1894 | { | |
d01316d0 | 1895 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdDefineShader); |
d5bde956 TH |
1896 | int ret; |
1897 | size_t size; | |
9c079b8c | 1898 | struct vmw_resource *ctx; |
d5bde956 | 1899 | |
d01316d0 | 1900 | cmd = container_of(header, typeof(*cmd), header); |
d5bde956 TH |
1901 | |
1902 | ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context, | |
a9f58c45 TH |
1903 | VMW_RES_DIRTY_SET, user_context_converter, |
1904 | &cmd->body.cid, &ctx); | |
d5bde956 TH |
1905 | if (unlikely(ret != 0)) |
1906 | return ret; | |
1907 | ||
1908 | if (unlikely(!dev_priv->has_mob)) | |
1909 | return 0; | |
1910 | ||
1911 | size = cmd->header.size - sizeof(cmd->body); | |
680360a4 DR |
1912 | ret = vmw_compat_shader_add(dev_priv, vmw_context_res_man(ctx), |
1913 | cmd->body.shid, cmd + 1, cmd->body.type, | |
1914 | size, &sw_context->staged_cmd_res); | |
d5bde956 TH |
1915 | if (unlikely(ret != 0)) |
1916 | return ret; | |
1917 | ||
680360a4 | 1918 | return vmw_resource_relocation_add(sw_context, NULL, |
e7a45284 | 1919 | vmw_ptr_diff(sw_context->buf_start, |
a1944030 TH |
1920 | &cmd->header.id), |
1921 | vmw_res_rel_nop); | |
d5bde956 TH |
1922 | } |
1923 | ||
1924 | /** | |
680360a4 | 1925 | * vmw_cmd_shader_destroy - Validate SVGA_3D_CMD_SHADER_DESTROY command |
d5bde956 TH |
1926 | * |
1927 | * @dev_priv: Pointer to a device private struct. | |
1928 | * @sw_context: The software context being used for this batch. | |
1929 | * @header: Pointer to the command header in the command stream. | |
1930 | */ | |
1931 | static int vmw_cmd_shader_destroy(struct vmw_private *dev_priv, | |
1932 | struct vmw_sw_context *sw_context, | |
1933 | SVGA3dCmdHeader *header) | |
1934 | { | |
d01316d0 | 1935 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdDestroyShader); |
d5bde956 | 1936 | int ret; |
9c079b8c | 1937 | struct vmw_resource *ctx; |
d5bde956 | 1938 | |
d01316d0 | 1939 | cmd = container_of(header, typeof(*cmd), header); |
d5bde956 TH |
1940 | |
1941 | ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context, | |
a9f58c45 TH |
1942 | VMW_RES_DIRTY_SET, user_context_converter, |
1943 | &cmd->body.cid, &ctx); | |
d5bde956 TH |
1944 | if (unlikely(ret != 0)) |
1945 | return ret; | |
1946 | ||
1947 | if (unlikely(!dev_priv->has_mob)) | |
1948 | return 0; | |
1949 | ||
680360a4 DR |
1950 | ret = vmw_shader_remove(vmw_context_res_man(ctx), cmd->body.shid, |
1951 | cmd->body.type, &sw_context->staged_cmd_res); | |
d5bde956 TH |
1952 | if (unlikely(ret != 0)) |
1953 | return ret; | |
1954 | ||
680360a4 | 1955 | return vmw_resource_relocation_add(sw_context, NULL, |
e7a45284 | 1956 | vmw_ptr_diff(sw_context->buf_start, |
a1944030 TH |
1957 | &cmd->header.id), |
1958 | vmw_res_rel_nop); | |
d5bde956 TH |
1959 | } |
1960 | ||
c0951b79 | 1961 | /** |
680360a4 | 1962 | * vmw_cmd_set_shader - Validate SVGA_3D_CMD_SET_SHADER command |
c0951b79 TH |
1963 | * |
1964 | * @dev_priv: Pointer to a device private struct. | |
1965 | * @sw_context: The software context being used for this batch. | |
1966 | * @header: Pointer to the command header in the command stream. | |
1967 | */ | |
1968 | static int vmw_cmd_set_shader(struct vmw_private *dev_priv, | |
1969 | struct vmw_sw_context *sw_context, | |
1970 | SVGA3dCmdHeader *header) | |
1971 | { | |
d01316d0 | 1972 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdSetShader); |
d80efd5c | 1973 | struct vmw_ctx_bindinfo_shader binding; |
9c079b8c TH |
1974 | struct vmw_resource *ctx, *res = NULL; |
1975 | struct vmw_ctx_validation_info *ctx_info; | |
c0951b79 TH |
1976 | int ret; |
1977 | ||
d01316d0 | 1978 | cmd = container_of(header, typeof(*cmd), header); |
c0951b79 | 1979 | |
14abdfae | 1980 | if (!vmw_shadertype_is_valid(VMW_SM_LEGACY, cmd->body.type)) { |
5724f899 DR |
1981 | VMW_DEBUG_USER("Illegal shader type %u.\n", |
1982 | (unsigned int) cmd->body.type); | |
d80efd5c TH |
1983 | return -EINVAL; |
1984 | } | |
1985 | ||
b5c3b1a6 | 1986 | ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context, |
a9f58c45 TH |
1987 | VMW_RES_DIRTY_SET, user_context_converter, |
1988 | &cmd->body.cid, &ctx); | |
c0951b79 TH |
1989 | if (unlikely(ret != 0)) |
1990 | return ret; | |
1991 | ||
18e4a466 TH |
1992 | if (!dev_priv->has_mob) |
1993 | return 0; | |
1994 | ||
1995 | if (cmd->body.shid != SVGA3D_INVALID_ID) { | |
e41c20cf TH |
1996 | /* |
1997 | * This is the compat shader path - Per device guest-backed | |
1998 | * shaders, but user-space thinks it's per context host- | |
1999 | * backed shaders. | |
2000 | */ | |
9c079b8c | 2001 | res = vmw_shader_lookup(vmw_context_res_man(ctx), |
680360a4 | 2002 | cmd->body.shid, cmd->body.type); |
18e4a466 | 2003 | if (!IS_ERR(res)) { |
a309c719 ZR |
2004 | ret = vmw_execbuf_res_val_add(sw_context, res, |
2005 | VMW_RES_DIRTY_NONE, | |
2006 | vmw_val_add_flag_noctx); | |
18e4a466 TH |
2007 | if (unlikely(ret != 0)) |
2008 | return ret; | |
e41c20cf TH |
2009 | |
2010 | ret = vmw_resource_relocation_add | |
2011 | (sw_context, res, | |
2012 | vmw_ptr_diff(sw_context->buf_start, | |
2013 | &cmd->body.shid), | |
2014 | vmw_res_rel_normal); | |
2015 | if (unlikely(ret != 0)) | |
2016 | return ret; | |
18e4a466 TH |
2017 | } |
2018 | } | |
2019 | ||
9c079b8c | 2020 | if (IS_ERR_OR_NULL(res)) { |
680360a4 DR |
2021 | ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_shader, |
2022 | VMW_RES_DIRTY_NONE, | |
2023 | user_shader_converter, &cmd->body.shid, | |
2024 | &res); | |
b5c3b1a6 TH |
2025 | if (unlikely(ret != 0)) |
2026 | return ret; | |
b5c3b1a6 | 2027 | } |
c74c162f | 2028 | |
9c079b8c TH |
2029 | ctx_info = vmw_execbuf_info_from_res(sw_context, ctx); |
2030 | if (!ctx_info) | |
2031 | return -EINVAL; | |
2032 | ||
2033 | binding.bi.ctx = ctx; | |
2034 | binding.bi.res = res; | |
d80efd5c TH |
2035 | binding.bi.bt = vmw_ctx_binding_shader; |
2036 | binding.shader_slot = cmd->body.type - SVGA3D_SHADERTYPE_MIN; | |
680360a4 DR |
2037 | vmw_binding_add(ctx_info->staged, &binding.bi, binding.shader_slot, 0); |
2038 | ||
d80efd5c | 2039 | return 0; |
c0951b79 TH |
2040 | } |
2041 | ||
0ccbbae4 | 2042 | /** |
680360a4 | 2043 | * vmw_cmd_set_shader_const - Validate SVGA_3D_CMD_SET_SHADER_CONST command |
0ccbbae4 TH |
2044 | * |
2045 | * @dev_priv: Pointer to a device private struct. | |
2046 | * @sw_context: The software context being used for this batch. | |
2047 | * @header: Pointer to the command header in the command stream. | |
2048 | */ | |
2049 | static int vmw_cmd_set_shader_const(struct vmw_private *dev_priv, | |
2050 | struct vmw_sw_context *sw_context, | |
2051 | SVGA3dCmdHeader *header) | |
2052 | { | |
d01316d0 | 2053 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdSetShaderConst); |
0ccbbae4 TH |
2054 | int ret; |
2055 | ||
d01316d0 | 2056 | cmd = container_of(header, typeof(*cmd), header); |
0ccbbae4 TH |
2057 | |
2058 | ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context, | |
a9f58c45 TH |
2059 | VMW_RES_DIRTY_SET, user_context_converter, |
2060 | &cmd->body.cid, NULL); | |
0ccbbae4 TH |
2061 | if (unlikely(ret != 0)) |
2062 | return ret; | |
2063 | ||
2064 | if (dev_priv->has_mob) | |
2065 | header->id = SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE; | |
2066 | ||
2067 | return 0; | |
2068 | } | |
2069 | ||
c74c162f | 2070 | /** |
680360a4 | 2071 | * vmw_cmd_bind_gb_shader - Validate SVGA_3D_CMD_BIND_GB_SHADER command |
c74c162f TH |
2072 | * |
2073 | * @dev_priv: Pointer to a device private struct. | |
2074 | * @sw_context: The software context being used for this batch. | |
2075 | * @header: Pointer to the command header in the command stream. | |
2076 | */ | |
2077 | static int vmw_cmd_bind_gb_shader(struct vmw_private *dev_priv, | |
2078 | struct vmw_sw_context *sw_context, | |
2079 | SVGA3dCmdHeader *header) | |
2080 | { | |
d01316d0 DR |
2081 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdBindGBShader) = |
2082 | container_of(header, typeof(*cmd), header); | |
c74c162f TH |
2083 | |
2084 | return vmw_cmd_switch_backup(dev_priv, sw_context, vmw_res_shader, | |
680360a4 DR |
2085 | user_shader_converter, &cmd->body.shid, |
2086 | &cmd->body.mobid, cmd->body.offsetInBytes); | |
c74c162f TH |
2087 | } |
2088 | ||
d80efd5c | 2089 | /** |
680360a4 | 2090 | * vmw_cmd_dx_set_single_constant_buffer - Validate |
d80efd5c TH |
2091 | * SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER command. |
2092 | * | |
2093 | * @dev_priv: Pointer to a device private struct. | |
2094 | * @sw_context: The software context being used for this batch. | |
2095 | * @header: Pointer to the command header in the command stream. | |
2096 | */ | |
2097 | static int | |
2098 | vmw_cmd_dx_set_single_constant_buffer(struct vmw_private *dev_priv, | |
2099 | struct vmw_sw_context *sw_context, | |
2100 | SVGA3dCmdHeader *header) | |
4084fb89 | 2101 | { |
d01316d0 | 2102 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdDXSetSingleConstantBuffer); |
d2e90ab3 | 2103 | |
9c079b8c | 2104 | struct vmw_resource *res = NULL; |
6f74fd91 | 2105 | struct vmw_ctx_validation_info *ctx_node = VMW_GET_CTX_NODE(sw_context); |
d80efd5c TH |
2106 | struct vmw_ctx_bindinfo_cb binding; |
2107 | int ret; | |
4084fb89 | 2108 | |
6f74fd91 | 2109 | if (!ctx_node) |
4084fb89 | 2110 | return -EINVAL; |
4084fb89 | 2111 | |
d80efd5c TH |
2112 | cmd = container_of(header, typeof(*cmd), header); |
2113 | ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, | |
a9f58c45 | 2114 | VMW_RES_DIRTY_NONE, user_surface_converter, |
9c079b8c | 2115 | &cmd->body.sid, &res); |
d80efd5c TH |
2116 | if (unlikely(ret != 0)) |
2117 | return ret; | |
4084fb89 | 2118 | |
14abdfae ZR |
2119 | if (!vmw_shadertype_is_valid(dev_priv->sm_type, cmd->body.type) || |
2120 | cmd->body.slot >= SVGA3D_DX_MAX_CONSTBUFFERS) { | |
2121 | VMW_DEBUG_USER("Illegal const buffer shader %u slot %u.\n", | |
2122 | (unsigned int) cmd->body.type, | |
2123 | (unsigned int) cmd->body.slot); | |
2124 | return -EINVAL; | |
2125 | } | |
2126 | ||
9c079b8c TH |
2127 | binding.bi.ctx = ctx_node->ctx; |
2128 | binding.bi.res = res; | |
d80efd5c TH |
2129 | binding.bi.bt = vmw_ctx_binding_cb; |
2130 | binding.shader_slot = cmd->body.type - SVGA3D_SHADERTYPE_MIN; | |
2131 | binding.offset = cmd->body.offsetInBytes; | |
2132 | binding.size = cmd->body.sizeInBytes; | |
2133 | binding.slot = cmd->body.slot; | |
2134 | ||
680360a4 DR |
2135 | vmw_binding_add(ctx_node->staged, &binding.bi, binding.shader_slot, |
2136 | binding.slot); | |
4084fb89 JB |
2137 | |
2138 | return 0; | |
2139 | } | |
fb1d9738 | 2140 | |
bf625870 RS |
2141 | /** |
2142 | * vmw_cmd_dx_set_constant_buffer_offset - Validate | |
2143 | * SVGA_3D_CMD_DX_SET_VS/PS/GS/HS/DS/CS_CONSTANT_BUFFER_OFFSET command. | |
2144 | * | |
2145 | * @dev_priv: Pointer to a device private struct. | |
2146 | * @sw_context: The software context being used for this batch. | |
2147 | * @header: Pointer to the command header in the command stream. | |
2148 | */ | |
2149 | static int | |
2150 | vmw_cmd_dx_set_constant_buffer_offset(struct vmw_private *dev_priv, | |
2151 | struct vmw_sw_context *sw_context, | |
2152 | SVGA3dCmdHeader *header) | |
2153 | { | |
2154 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdDXSetConstantBufferOffset); | |
2155 | ||
2156 | struct vmw_ctx_validation_info *ctx_node = VMW_GET_CTX_NODE(sw_context); | |
2157 | u32 shader_slot; | |
2158 | ||
2159 | if (!has_sm5_context(dev_priv)) | |
2160 | return -EINVAL; | |
2161 | ||
2162 | if (!ctx_node) | |
2163 | return -EINVAL; | |
2164 | ||
2165 | cmd = container_of(header, typeof(*cmd), header); | |
2166 | if (cmd->body.slot >= SVGA3D_DX_MAX_CONSTBUFFERS) { | |
2167 | VMW_DEBUG_USER("Illegal const buffer slot %u.\n", | |
2168 | (unsigned int) cmd->body.slot); | |
2169 | return -EINVAL; | |
2170 | } | |
2171 | ||
2172 | shader_slot = cmd->header.id - SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET; | |
2173 | vmw_binding_cb_offset_update(ctx_node->staged, shader_slot, | |
2174 | cmd->body.slot, cmd->body.offsetInBytes); | |
2175 | ||
2176 | return 0; | |
2177 | } | |
2178 | ||
d80efd5c | 2179 | /** |
680360a4 DR |
2180 | * vmw_cmd_dx_set_shader_res - Validate SVGA_3D_CMD_DX_SET_SHADER_RESOURCES |
2181 | * command | |
d80efd5c TH |
2182 | * |
2183 | * @dev_priv: Pointer to a device private struct. | |
2184 | * @sw_context: The software context being used for this batch. | |
2185 | * @header: Pointer to the command header in the command stream. | |
2186 | */ | |
2187 | static int vmw_cmd_dx_set_shader_res(struct vmw_private *dev_priv, | |
2188 | struct vmw_sw_context *sw_context, | |
2189 | SVGA3dCmdHeader *header) | |
2190 | { | |
d01316d0 DR |
2191 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdDXSetShaderResources) = |
2192 | container_of(header, typeof(*cmd), header); | |
d2e90ab3 | 2193 | |
d80efd5c TH |
2194 | u32 num_sr_view = (cmd->header.size - sizeof(cmd->body)) / |
2195 | sizeof(SVGA3dShaderResourceViewId); | |
2196 | ||
2197 | if ((u64) cmd->body.startView + (u64) num_sr_view > | |
2198 | (u64) SVGA3D_DX_MAX_SRVIEWS || | |
14abdfae | 2199 | !vmw_shadertype_is_valid(dev_priv->sm_type, cmd->body.type)) { |
5724f899 | 2200 | VMW_DEBUG_USER("Invalid shader binding.\n"); |
d80efd5c TH |
2201 | return -EINVAL; |
2202 | } | |
2203 | ||
2204 | return vmw_view_bindings_add(sw_context, vmw_view_sr, | |
2205 | vmw_ctx_binding_sr, | |
2206 | cmd->body.type - SVGA3D_SHADERTYPE_MIN, | |
2207 | (void *) &cmd[1], num_sr_view, | |
2208 | cmd->body.startView); | |
2209 | } | |
2210 | ||
2211 | /** | |
680360a4 | 2212 | * vmw_cmd_dx_set_shader - Validate SVGA_3D_CMD_DX_SET_SHADER command |
d80efd5c TH |
2213 | * |
2214 | * @dev_priv: Pointer to a device private struct. | |
2215 | * @sw_context: The software context being used for this batch. | |
2216 | * @header: Pointer to the command header in the command stream. | |
2217 | */ | |
2218 | static int vmw_cmd_dx_set_shader(struct vmw_private *dev_priv, | |
2219 | struct vmw_sw_context *sw_context, | |
2220 | SVGA3dCmdHeader *header) | |
2221 | { | |
d01316d0 | 2222 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdDXSetShader); |
d80efd5c | 2223 | struct vmw_resource *res = NULL; |
6f74fd91 | 2224 | struct vmw_ctx_validation_info *ctx_node = VMW_GET_CTX_NODE(sw_context); |
d80efd5c TH |
2225 | struct vmw_ctx_bindinfo_shader binding; |
2226 | int ret = 0; | |
2227 | ||
6f74fd91 | 2228 | if (!ctx_node) |
d80efd5c | 2229 | return -EINVAL; |
d80efd5c TH |
2230 | |
2231 | cmd = container_of(header, typeof(*cmd), header); | |
2232 | ||
14abdfae | 2233 | if (!vmw_shadertype_is_valid(dev_priv->sm_type, cmd->body.type)) { |
5724f899 DR |
2234 | VMW_DEBUG_USER("Illegal shader type %u.\n", |
2235 | (unsigned int) cmd->body.type); | |
d80efd5c TH |
2236 | return -EINVAL; |
2237 | } | |
2238 | ||
2239 | if (cmd->body.shaderId != SVGA3D_INVALID_ID) { | |
2240 | res = vmw_shader_lookup(sw_context->man, cmd->body.shaderId, 0); | |
2241 | if (IS_ERR(res)) { | |
5724f899 | 2242 | VMW_DEBUG_USER("Could not find shader for binding.\n"); |
d80efd5c TH |
2243 | return PTR_ERR(res); |
2244 | } | |
2245 | ||
a309c719 ZR |
2246 | ret = vmw_execbuf_res_val_add(sw_context, res, |
2247 | VMW_RES_DIRTY_NONE, | |
2248 | vmw_val_add_flag_noctx); | |
d80efd5c | 2249 | if (ret) |
508108ea | 2250 | return ret; |
d80efd5c TH |
2251 | } |
2252 | ||
9c079b8c | 2253 | binding.bi.ctx = ctx_node->ctx; |
d80efd5c TH |
2254 | binding.bi.res = res; |
2255 | binding.bi.bt = vmw_ctx_binding_dx_shader; | |
2256 | binding.shader_slot = cmd->body.type - SVGA3D_SHADERTYPE_MIN; | |
2257 | ||
680360a4 | 2258 | vmw_binding_add(ctx_node->staged, &binding.bi, binding.shader_slot, 0); |
d80efd5c | 2259 | |
508108ea | 2260 | return 0; |
d80efd5c TH |
2261 | } |
2262 | ||
2263 | /** | |
680360a4 DR |
2264 | * vmw_cmd_dx_set_vertex_buffers - Validates SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS |
2265 | * command | |
d80efd5c TH |
2266 | * |
2267 | * @dev_priv: Pointer to a device private struct. | |
2268 | * @sw_context: The software context being used for this batch. | |
2269 | * @header: Pointer to the command header in the command stream. | |
2270 | */ | |
2271 | static int vmw_cmd_dx_set_vertex_buffers(struct vmw_private *dev_priv, | |
2272 | struct vmw_sw_context *sw_context, | |
2273 | SVGA3dCmdHeader *header) | |
2274 | { | |
6f74fd91 | 2275 | struct vmw_ctx_validation_info *ctx_node = VMW_GET_CTX_NODE(sw_context); |
d80efd5c | 2276 | struct vmw_ctx_bindinfo_vb binding; |
9c079b8c | 2277 | struct vmw_resource *res; |
d80efd5c TH |
2278 | struct { |
2279 | SVGA3dCmdHeader header; | |
2280 | SVGA3dCmdDXSetVertexBuffers body; | |
2281 | SVGA3dVertexBuffer buf[]; | |
2282 | } *cmd; | |
2283 | int i, ret, num; | |
2284 | ||
6f74fd91 | 2285 | if (!ctx_node) |
d80efd5c | 2286 | return -EINVAL; |
d80efd5c TH |
2287 | |
2288 | cmd = container_of(header, typeof(*cmd), header); | |
2289 | num = (cmd->header.size - sizeof(cmd->body)) / | |
2290 | sizeof(SVGA3dVertexBuffer); | |
2291 | if ((u64)num + (u64)cmd->body.startBuffer > | |
2292 | (u64)SVGA3D_DX_MAX_VERTEXBUFFERS) { | |
5724f899 | 2293 | VMW_DEBUG_USER("Invalid number of vertex buffers.\n"); |
d80efd5c TH |
2294 | return -EINVAL; |
2295 | } | |
2296 | ||
2297 | for (i = 0; i < num; i++) { | |
2298 | ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, | |
a9f58c45 | 2299 | VMW_RES_DIRTY_NONE, |
d80efd5c | 2300 | user_surface_converter, |
9c079b8c | 2301 | &cmd->buf[i].sid, &res); |
d80efd5c TH |
2302 | if (unlikely(ret != 0)) |
2303 | return ret; | |
2304 | ||
9c079b8c | 2305 | binding.bi.ctx = ctx_node->ctx; |
d80efd5c | 2306 | binding.bi.bt = vmw_ctx_binding_vb; |
9c079b8c | 2307 | binding.bi.res = res; |
d80efd5c TH |
2308 | binding.offset = cmd->buf[i].offset; |
2309 | binding.stride = cmd->buf[i].stride; | |
2310 | binding.slot = i + cmd->body.startBuffer; | |
2311 | ||
680360a4 | 2312 | vmw_binding_add(ctx_node->staged, &binding.bi, 0, binding.slot); |
d80efd5c TH |
2313 | } |
2314 | ||
2315 | return 0; | |
2316 | } | |
2317 | ||
2318 | /** | |
2cd80dbd | 2319 | * vmw_cmd_dx_set_index_buffer - Validate |
8bd6287f | 2320 | * SVGA_3D_CMD_DX_IA_SET_INDEX_BUFFER command. |
d80efd5c TH |
2321 | * |
2322 | * @dev_priv: Pointer to a device private struct. | |
2323 | * @sw_context: The software context being used for this batch. | |
2324 | * @header: Pointer to the command header in the command stream. | |
2325 | */ | |
2326 | static int vmw_cmd_dx_set_index_buffer(struct vmw_private *dev_priv, | |
2327 | struct vmw_sw_context *sw_context, | |
2328 | SVGA3dCmdHeader *header) | |
2329 | { | |
6f74fd91 | 2330 | struct vmw_ctx_validation_info *ctx_node = VMW_GET_CTX_NODE(sw_context); |
d80efd5c | 2331 | struct vmw_ctx_bindinfo_ib binding; |
9c079b8c | 2332 | struct vmw_resource *res; |
d01316d0 | 2333 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdDXSetIndexBuffer); |
d80efd5c TH |
2334 | int ret; |
2335 | ||
6f74fd91 | 2336 | if (!ctx_node) |
d80efd5c | 2337 | return -EINVAL; |
d80efd5c TH |
2338 | |
2339 | cmd = container_of(header, typeof(*cmd), header); | |
2340 | ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, | |
a9f58c45 | 2341 | VMW_RES_DIRTY_NONE, user_surface_converter, |
9c079b8c | 2342 | &cmd->body.sid, &res); |
d80efd5c TH |
2343 | if (unlikely(ret != 0)) |
2344 | return ret; | |
2345 | ||
9c079b8c TH |
2346 | binding.bi.ctx = ctx_node->ctx; |
2347 | binding.bi.res = res; | |
d80efd5c TH |
2348 | binding.bi.bt = vmw_ctx_binding_ib; |
2349 | binding.offset = cmd->body.offset; | |
2350 | binding.format = cmd->body.format; | |
2351 | ||
9c079b8c | 2352 | vmw_binding_add(ctx_node->staged, &binding.bi, 0, 0); |
d80efd5c TH |
2353 | |
2354 | return 0; | |
2355 | } | |
2356 | ||
2357 | /** | |
2cd80dbd | 2358 | * vmw_cmd_dx_set_rendertargets - Validate SVGA_3D_CMD_DX_SET_RENDERTARGETS |
680360a4 | 2359 | * command |
d80efd5c TH |
2360 | * |
2361 | * @dev_priv: Pointer to a device private struct. | |
2362 | * @sw_context: The software context being used for this batch. | |
2363 | * @header: Pointer to the command header in the command stream. | |
2364 | */ | |
2365 | static int vmw_cmd_dx_set_rendertargets(struct vmw_private *dev_priv, | |
2366 | struct vmw_sw_context *sw_context, | |
2367 | SVGA3dCmdHeader *header) | |
2368 | { | |
d01316d0 DR |
2369 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdDXSetRenderTargets) = |
2370 | container_of(header, typeof(*cmd), header); | |
d80efd5c TH |
2371 | u32 num_rt_view = (cmd->header.size - sizeof(cmd->body)) / |
2372 | sizeof(SVGA3dRenderTargetViewId); | |
d01316d0 | 2373 | int ret; |
d80efd5c | 2374 | |
ebc9ac7c | 2375 | if (num_rt_view > SVGA3D_DX_MAX_RENDER_TARGETS) { |
5724f899 | 2376 | VMW_DEBUG_USER("Invalid DX Rendertarget binding.\n"); |
d80efd5c TH |
2377 | return -EINVAL; |
2378 | } | |
2379 | ||
680360a4 DR |
2380 | ret = vmw_view_bindings_add(sw_context, vmw_view_ds, vmw_ctx_binding_ds, |
2381 | 0, &cmd->body.depthStencilViewId, 1, 0); | |
d80efd5c TH |
2382 | if (ret) |
2383 | return ret; | |
2384 | ||
2385 | return vmw_view_bindings_add(sw_context, vmw_view_rt, | |
680360a4 DR |
2386 | vmw_ctx_binding_dx_rt, 0, (void *)&cmd[1], |
2387 | num_rt_view, 0); | |
d80efd5c TH |
2388 | } |
2389 | ||
2390 | /** | |
680360a4 | 2391 | * vmw_cmd_dx_clear_rendertarget_view - Validate |
d80efd5c TH |
2392 | * SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW command |
2393 | * | |
2394 | * @dev_priv: Pointer to a device private struct. | |
2395 | * @sw_context: The software context being used for this batch. | |
2396 | * @header: Pointer to the command header in the command stream. | |
2397 | */ | |
2398 | static int vmw_cmd_dx_clear_rendertarget_view(struct vmw_private *dev_priv, | |
2399 | struct vmw_sw_context *sw_context, | |
2400 | SVGA3dCmdHeader *header) | |
2401 | { | |
d01316d0 DR |
2402 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdDXClearRenderTargetView) = |
2403 | container_of(header, typeof(*cmd), header); | |
a26ca967 | 2404 | struct vmw_resource *ret; |
d80efd5c | 2405 | |
a26ca967 LB |
2406 | ret = vmw_view_id_val_add(sw_context, vmw_view_rt, |
2407 | cmd->body.renderTargetViewId); | |
2408 | ||
2409 | return PTR_ERR_OR_ZERO(ret); | |
d80efd5c TH |
2410 | } |
2411 | ||
2412 | /** | |
2cd80dbd | 2413 | * vmw_cmd_dx_clear_depthstencil_view - Validate |
d80efd5c TH |
2414 | * SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW command |
2415 | * | |
2416 | * @dev_priv: Pointer to a device private struct. | |
2417 | * @sw_context: The software context being used for this batch. | |
2418 | * @header: Pointer to the command header in the command stream. | |
2419 | */ | |
2420 | static int vmw_cmd_dx_clear_depthstencil_view(struct vmw_private *dev_priv, | |
2421 | struct vmw_sw_context *sw_context, | |
2422 | SVGA3dCmdHeader *header) | |
2423 | { | |
d01316d0 DR |
2424 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdDXClearDepthStencilView) = |
2425 | container_of(header, typeof(*cmd), header); | |
a26ca967 LB |
2426 | struct vmw_resource *ret; |
2427 | ||
2428 | ret = vmw_view_id_val_add(sw_context, vmw_view_ds, | |
2429 | cmd->body.depthStencilViewId); | |
d80efd5c | 2430 | |
a26ca967 | 2431 | return PTR_ERR_OR_ZERO(ret); |
d80efd5c TH |
2432 | } |
2433 | ||
2434 | static int vmw_cmd_dx_view_define(struct vmw_private *dev_priv, | |
2435 | struct vmw_sw_context *sw_context, | |
2436 | SVGA3dCmdHeader *header) | |
2437 | { | |
6f74fd91 | 2438 | struct vmw_ctx_validation_info *ctx_node = VMW_GET_CTX_NODE(sw_context); |
9c079b8c | 2439 | struct vmw_resource *srf; |
d80efd5c TH |
2440 | struct vmw_resource *res; |
2441 | enum vmw_view_type view_type; | |
2442 | int ret; | |
2443 | /* | |
680360a4 DR |
2444 | * This is based on the fact that all affected define commands have the |
2445 | * same initial command body layout. | |
d80efd5c TH |
2446 | */ |
2447 | struct { | |
2448 | SVGA3dCmdHeader header; | |
2449 | uint32 defined_id; | |
2450 | uint32 sid; | |
2451 | } *cmd; | |
2452 | ||
6f74fd91 | 2453 | if (!ctx_node) |
d80efd5c | 2454 | return -EINVAL; |
d80efd5c TH |
2455 | |
2456 | view_type = vmw_view_cmd_to_type(header->id); | |
0d9cac0c DC |
2457 | if (view_type == vmw_view_max) |
2458 | return -EINVAL; | |
680360a4 | 2459 | |
d80efd5c | 2460 | cmd = container_of(header, typeof(*cmd), header); |
bcd6aa7b MM |
2461 | if (unlikely(cmd->sid == SVGA3D_INVALID_ID)) { |
2462 | VMW_DEBUG_USER("Invalid surface id.\n"); | |
2463 | return -EINVAL; | |
2464 | } | |
d80efd5c | 2465 | ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, |
a9f58c45 | 2466 | VMW_RES_DIRTY_NONE, user_surface_converter, |
9c079b8c | 2467 | &cmd->sid, &srf); |
d80efd5c TH |
2468 | if (unlikely(ret != 0)) |
2469 | return ret; | |
2470 | ||
9c079b8c | 2471 | res = vmw_context_cotable(ctx_node->ctx, vmw_view_cotables[view_type]); |
517621b7 ZR |
2472 | if (IS_ERR_OR_NULL(res)) |
2473 | return res ? PTR_ERR(res) : -EINVAL; | |
d80efd5c | 2474 | ret = vmw_cotable_notify(res, cmd->defined_id); |
d80efd5c TH |
2475 | if (unlikely(ret != 0)) |
2476 | return ret; | |
2477 | ||
680360a4 DR |
2478 | return vmw_view_add(sw_context->man, ctx_node->ctx, srf, view_type, |
2479 | cmd->defined_id, header, | |
d80efd5c TH |
2480 | header->size + sizeof(*header), |
2481 | &sw_context->staged_cmd_res); | |
2482 | } | |
2483 | ||
2f633e5e | 2484 | /** |
680360a4 | 2485 | * vmw_cmd_dx_set_so_targets - Validate SVGA_3D_CMD_DX_SET_SOTARGETS command. |
2f633e5e CL |
2486 | * |
2487 | * @dev_priv: Pointer to a device private struct. | |
2488 | * @sw_context: The software context being used for this batch. | |
2489 | * @header: Pointer to the command header in the command stream. | |
2490 | */ | |
2491 | static int vmw_cmd_dx_set_so_targets(struct vmw_private *dev_priv, | |
2492 | struct vmw_sw_context *sw_context, | |
2493 | SVGA3dCmdHeader *header) | |
2494 | { | |
6f74fd91 | 2495 | struct vmw_ctx_validation_info *ctx_node = VMW_GET_CTX_NODE(sw_context); |
403fef50 | 2496 | struct vmw_ctx_bindinfo_so_target binding; |
9c079b8c | 2497 | struct vmw_resource *res; |
2f633e5e CL |
2498 | struct { |
2499 | SVGA3dCmdHeader header; | |
2500 | SVGA3dCmdDXSetSOTargets body; | |
2501 | SVGA3dSoTarget targets[]; | |
2502 | } *cmd; | |
2503 | int i, ret, num; | |
2504 | ||
6f74fd91 | 2505 | if (!ctx_node) |
2f633e5e | 2506 | return -EINVAL; |
2f633e5e CL |
2507 | |
2508 | cmd = container_of(header, typeof(*cmd), header); | |
680360a4 | 2509 | num = (cmd->header.size - sizeof(cmd->body)) / sizeof(SVGA3dSoTarget); |
2f633e5e CL |
2510 | |
2511 | if (num > SVGA3D_DX_MAX_SOTARGETS) { | |
5724f899 | 2512 | VMW_DEBUG_USER("Invalid DX SO binding.\n"); |
2f633e5e CL |
2513 | return -EINVAL; |
2514 | } | |
2515 | ||
2516 | for (i = 0; i < num; i++) { | |
2517 | ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, | |
a9f58c45 | 2518 | VMW_RES_DIRTY_SET, |
2f633e5e | 2519 | user_surface_converter, |
9c079b8c | 2520 | &cmd->targets[i].sid, &res); |
2f633e5e CL |
2521 | if (unlikely(ret != 0)) |
2522 | return ret; | |
2523 | ||
9c079b8c TH |
2524 | binding.bi.ctx = ctx_node->ctx; |
2525 | binding.bi.res = res; | |
ed2684e7 | 2526 | binding.bi.bt = vmw_ctx_binding_so_target; |
2f633e5e CL |
2527 | binding.offset = cmd->targets[i].offset; |
2528 | binding.size = cmd->targets[i].sizeInBytes; | |
2529 | binding.slot = i; | |
2530 | ||
680360a4 | 2531 | vmw_binding_add(ctx_node->staged, &binding.bi, 0, binding.slot); |
2f633e5e CL |
2532 | } |
2533 | ||
2534 | return 0; | |
2535 | } | |
2536 | ||
d80efd5c TH |
2537 | static int vmw_cmd_dx_so_define(struct vmw_private *dev_priv, |
2538 | struct vmw_sw_context *sw_context, | |
2539 | SVGA3dCmdHeader *header) | |
2540 | { | |
6f74fd91 | 2541 | struct vmw_ctx_validation_info *ctx_node = VMW_GET_CTX_NODE(sw_context); |
d80efd5c TH |
2542 | struct vmw_resource *res; |
2543 | /* | |
2544 | * This is based on the fact that all affected define commands have | |
2545 | * the same initial command body layout. | |
2546 | */ | |
2547 | struct { | |
2548 | SVGA3dCmdHeader header; | |
2549 | uint32 defined_id; | |
2550 | } *cmd; | |
2551 | enum vmw_so_type so_type; | |
2552 | int ret; | |
2553 | ||
6f74fd91 | 2554 | if (!ctx_node) |
d80efd5c | 2555 | return -EINVAL; |
d80efd5c TH |
2556 | |
2557 | so_type = vmw_so_cmd_to_type(header->id); | |
9c079b8c | 2558 | res = vmw_context_cotable(ctx_node->ctx, vmw_so_cotables[so_type]); |
517621b7 ZR |
2559 | if (IS_ERR_OR_NULL(res)) |
2560 | return res ? PTR_ERR(res) : -EINVAL; | |
d80efd5c TH |
2561 | cmd = container_of(header, typeof(*cmd), header); |
2562 | ret = vmw_cotable_notify(res, cmd->defined_id); | |
d80efd5c TH |
2563 | |
2564 | return ret; | |
2565 | } | |
2566 | ||
2567 | /** | |
680360a4 DR |
2568 | * vmw_cmd_dx_check_subresource - Validate SVGA_3D_CMD_DX_[X]_SUBRESOURCE |
2569 | * command | |
d80efd5c TH |
2570 | * |
2571 | * @dev_priv: Pointer to a device private struct. | |
2572 | * @sw_context: The software context being used for this batch. | |
2573 | * @header: Pointer to the command header in the command stream. | |
2574 | */ | |
2575 | static int vmw_cmd_dx_check_subresource(struct vmw_private *dev_priv, | |
2576 | struct vmw_sw_context *sw_context, | |
2577 | SVGA3dCmdHeader *header) | |
2578 | { | |
2579 | struct { | |
2580 | SVGA3dCmdHeader header; | |
2581 | union { | |
2582 | SVGA3dCmdDXReadbackSubResource r_body; | |
2583 | SVGA3dCmdDXInvalidateSubResource i_body; | |
2584 | SVGA3dCmdDXUpdateSubResource u_body; | |
2585 | SVGA3dSurfaceId sid; | |
2586 | }; | |
2587 | } *cmd; | |
2588 | ||
2589 | BUILD_BUG_ON(offsetof(typeof(*cmd), r_body.sid) != | |
2590 | offsetof(typeof(*cmd), sid)); | |
2591 | BUILD_BUG_ON(offsetof(typeof(*cmd), i_body.sid) != | |
2592 | offsetof(typeof(*cmd), sid)); | |
2593 | BUILD_BUG_ON(offsetof(typeof(*cmd), u_body.sid) != | |
2594 | offsetof(typeof(*cmd), sid)); | |
2595 | ||
2596 | cmd = container_of(header, typeof(*cmd), header); | |
d80efd5c | 2597 | return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, |
a9f58c45 | 2598 | VMW_RES_DIRTY_NONE, user_surface_converter, |
d80efd5c TH |
2599 | &cmd->sid, NULL); |
2600 | } | |
2601 | ||
2602 | static int vmw_cmd_dx_cid_check(struct vmw_private *dev_priv, | |
2603 | struct vmw_sw_context *sw_context, | |
2604 | SVGA3dCmdHeader *header) | |
2605 | { | |
6f74fd91 | 2606 | struct vmw_ctx_validation_info *ctx_node = VMW_GET_CTX_NODE(sw_context); |
d80efd5c | 2607 | |
6f74fd91 | 2608 | if (!ctx_node) |
d80efd5c | 2609 | return -EINVAL; |
d80efd5c TH |
2610 | |
2611 | return 0; | |
2612 | } | |
2613 | ||
2614 | /** | |
680360a4 DR |
2615 | * vmw_cmd_dx_view_remove - validate a view remove command and schedule the view |
2616 | * resource for removal. | |
d80efd5c TH |
2617 | * |
2618 | * @dev_priv: Pointer to a device private struct. | |
2619 | * @sw_context: The software context being used for this batch. | |
2620 | * @header: Pointer to the command header in the command stream. | |
2621 | * | |
680360a4 DR |
2622 | * Check that the view exists, and if it was not created using this command |
2623 | * batch, conditionally make this command a NOP. | |
d80efd5c TH |
2624 | */ |
2625 | static int vmw_cmd_dx_view_remove(struct vmw_private *dev_priv, | |
2626 | struct vmw_sw_context *sw_context, | |
2627 | SVGA3dCmdHeader *header) | |
2628 | { | |
6f74fd91 | 2629 | struct vmw_ctx_validation_info *ctx_node = VMW_GET_CTX_NODE(sw_context); |
d80efd5c TH |
2630 | struct { |
2631 | SVGA3dCmdHeader header; | |
2632 | union vmw_view_destroy body; | |
2633 | } *cmd = container_of(header, typeof(*cmd), header); | |
2634 | enum vmw_view_type view_type = vmw_view_cmd_to_type(header->id); | |
2635 | struct vmw_resource *view; | |
2636 | int ret; | |
2637 | ||
6f74fd91 | 2638 | if (!ctx_node) |
d80efd5c | 2639 | return -EINVAL; |
d80efd5c | 2640 | |
680360a4 DR |
2641 | ret = vmw_view_remove(sw_context->man, cmd->body.view_id, view_type, |
2642 | &sw_context->staged_cmd_res, &view); | |
d80efd5c TH |
2643 | if (ret || !view) |
2644 | return ret; | |
2645 | ||
2646 | /* | |
a1944030 TH |
2647 | * If the view wasn't created during this command batch, it might |
2648 | * have been removed due to a context swapout, so add a | |
2649 | * relocation to conditionally make this command a NOP to avoid | |
2650 | * device errors. | |
d80efd5c | 2651 | */ |
680360a4 | 2652 | return vmw_resource_relocation_add(sw_context, view, |
a1944030 TH |
2653 | vmw_ptr_diff(sw_context->buf_start, |
2654 | &cmd->header.id), | |
2655 | vmw_res_rel_cond_nop); | |
d80efd5c TH |
2656 | } |
2657 | ||
2658 | /** | |
680360a4 | 2659 | * vmw_cmd_dx_define_shader - Validate SVGA_3D_CMD_DX_DEFINE_SHADER command |
d80efd5c TH |
2660 | * |
2661 | * @dev_priv: Pointer to a device private struct. | |
2662 | * @sw_context: The software context being used for this batch. | |
2663 | * @header: Pointer to the command header in the command stream. | |
2664 | */ | |
2665 | static int vmw_cmd_dx_define_shader(struct vmw_private *dev_priv, | |
2666 | struct vmw_sw_context *sw_context, | |
2667 | SVGA3dCmdHeader *header) | |
2668 | { | |
6f74fd91 | 2669 | struct vmw_ctx_validation_info *ctx_node = VMW_GET_CTX_NODE(sw_context); |
d80efd5c | 2670 | struct vmw_resource *res; |
d01316d0 DR |
2671 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdDXDefineShader) = |
2672 | container_of(header, typeof(*cmd), header); | |
d80efd5c TH |
2673 | int ret; |
2674 | ||
6f74fd91 | 2675 | if (!ctx_node) |
d80efd5c | 2676 | return -EINVAL; |
d80efd5c | 2677 | |
9c079b8c | 2678 | res = vmw_context_cotable(ctx_node->ctx, SVGA_COTABLE_DXSHADER); |
517621b7 ZR |
2679 | if (IS_ERR_OR_NULL(res)) |
2680 | return res ? PTR_ERR(res) : -EINVAL; | |
d80efd5c | 2681 | ret = vmw_cotable_notify(res, cmd->body.shaderId); |
d80efd5c TH |
2682 | if (ret) |
2683 | return ret; | |
2684 | ||
9c079b8c | 2685 | return vmw_dx_shader_add(sw_context->man, ctx_node->ctx, |
d80efd5c TH |
2686 | cmd->body.shaderId, cmd->body.type, |
2687 | &sw_context->staged_cmd_res); | |
2688 | } | |
2689 | ||
2690 | /** | |
680360a4 | 2691 | * vmw_cmd_dx_destroy_shader - Validate SVGA_3D_CMD_DX_DESTROY_SHADER command |
d80efd5c TH |
2692 | * |
2693 | * @dev_priv: Pointer to a device private struct. | |
2694 | * @sw_context: The software context being used for this batch. | |
2695 | * @header: Pointer to the command header in the command stream. | |
2696 | */ | |
2697 | static int vmw_cmd_dx_destroy_shader(struct vmw_private *dev_priv, | |
2698 | struct vmw_sw_context *sw_context, | |
2699 | SVGA3dCmdHeader *header) | |
2700 | { | |
6f74fd91 | 2701 | struct vmw_ctx_validation_info *ctx_node = VMW_GET_CTX_NODE(sw_context); |
d01316d0 DR |
2702 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdDXDestroyShader) = |
2703 | container_of(header, typeof(*cmd), header); | |
d80efd5c TH |
2704 | int ret; |
2705 | ||
6f74fd91 | 2706 | if (!ctx_node) |
d80efd5c | 2707 | return -EINVAL; |
d80efd5c TH |
2708 | |
2709 | ret = vmw_shader_remove(sw_context->man, cmd->body.shaderId, 0, | |
2710 | &sw_context->staged_cmd_res); | |
d80efd5c TH |
2711 | |
2712 | return ret; | |
2713 | } | |
2714 | ||
2715 | /** | |
680360a4 | 2716 | * vmw_cmd_dx_bind_shader - Validate SVGA_3D_CMD_DX_BIND_SHADER command |
d80efd5c TH |
2717 | * |
2718 | * @dev_priv: Pointer to a device private struct. | |
2719 | * @sw_context: The software context being used for this batch. | |
2720 | * @header: Pointer to the command header in the command stream. | |
2721 | */ | |
2722 | static int vmw_cmd_dx_bind_shader(struct vmw_private *dev_priv, | |
2723 | struct vmw_sw_context *sw_context, | |
2724 | SVGA3dCmdHeader *header) | |
2725 | { | |
9c079b8c | 2726 | struct vmw_resource *ctx; |
d80efd5c | 2727 | struct vmw_resource *res; |
d01316d0 DR |
2728 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdDXBindShader) = |
2729 | container_of(header, typeof(*cmd), header); | |
d80efd5c TH |
2730 | int ret; |
2731 | ||
2732 | if (cmd->body.cid != SVGA3D_INVALID_ID) { | |
2733 | ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context, | |
a9f58c45 TH |
2734 | VMW_RES_DIRTY_SET, |
2735 | user_context_converter, &cmd->body.cid, | |
2736 | &ctx); | |
d80efd5c TH |
2737 | if (ret) |
2738 | return ret; | |
2739 | } else { | |
6f74fd91 DR |
2740 | struct vmw_ctx_validation_info *ctx_node = |
2741 | VMW_GET_CTX_NODE(sw_context); | |
2742 | ||
2743 | if (!ctx_node) | |
d80efd5c | 2744 | return -EINVAL; |
6f74fd91 DR |
2745 | |
2746 | ctx = ctx_node->ctx; | |
d80efd5c TH |
2747 | } |
2748 | ||
680360a4 | 2749 | res = vmw_shader_lookup(vmw_context_res_man(ctx), cmd->body.shid, 0); |
d80efd5c | 2750 | if (IS_ERR(res)) { |
5724f899 | 2751 | VMW_DEBUG_USER("Could not find shader to bind.\n"); |
d80efd5c TH |
2752 | return PTR_ERR(res); |
2753 | } | |
2754 | ||
a309c719 ZR |
2755 | ret = vmw_execbuf_res_val_add(sw_context, res, VMW_RES_DIRTY_NONE, |
2756 | vmw_val_add_flag_noctx); | |
d80efd5c | 2757 | if (ret) { |
5724f899 | 2758 | VMW_DEBUG_USER("Error creating resource validation node.\n"); |
508108ea | 2759 | return ret; |
d80efd5c TH |
2760 | } |
2761 | ||
508108ea TH |
2762 | return vmw_cmd_res_switch_backup(dev_priv, sw_context, res, |
2763 | &cmd->body.mobid, | |
2764 | cmd->body.offsetInBytes); | |
d80efd5c TH |
2765 | } |
2766 | ||
f3b33550 | 2767 | /** |
680360a4 | 2768 | * vmw_cmd_dx_genmips - Validate SVGA_3D_CMD_DX_GENMIPS command |
f3b33550 CL |
2769 | * |
2770 | * @dev_priv: Pointer to a device private struct. | |
2771 | * @sw_context: The software context being used for this batch. | |
2772 | * @header: Pointer to the command header in the command stream. | |
2773 | */ | |
2774 | static int vmw_cmd_dx_genmips(struct vmw_private *dev_priv, | |
2775 | struct vmw_sw_context *sw_context, | |
2776 | SVGA3dCmdHeader *header) | |
2777 | { | |
d01316d0 DR |
2778 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdDXGenMips) = |
2779 | container_of(header, typeof(*cmd), header); | |
75156a88 TH |
2780 | struct vmw_resource *view; |
2781 | struct vmw_res_cache_entry *rcache; | |
a26ca967 | 2782 | |
75156a88 TH |
2783 | view = vmw_view_id_val_add(sw_context, vmw_view_sr, |
2784 | cmd->body.shaderResourceViewId); | |
2785 | if (IS_ERR(view)) | |
2786 | return PTR_ERR(view); | |
f3b33550 | 2787 | |
75156a88 TH |
2788 | /* |
2789 | * Normally the shader-resource view is not gpu-dirtying, but for | |
2790 | * this particular command it is... | |
2791 | * So mark the last looked-up surface, which is the surface | |
2792 | * the view points to, gpu-dirty. | |
2793 | */ | |
2794 | rcache = &sw_context->res_cache[vmw_res_surface]; | |
2795 | vmw_validation_res_set_dirty(sw_context->ctx, rcache->private, | |
2796 | VMW_RES_DIRTY_SET); | |
2797 | return 0; | |
f3b33550 CL |
2798 | } |
2799 | ||
1f982e4e | 2800 | /** |
680360a4 DR |
2801 | * vmw_cmd_dx_transfer_from_buffer - Validate |
2802 | * SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER command | |
1f982e4e CL |
2803 | * |
2804 | * @dev_priv: Pointer to a device private struct. | |
2805 | * @sw_context: The software context being used for this batch. | |
2806 | * @header: Pointer to the command header in the command stream. | |
2807 | */ | |
2808 | static int vmw_cmd_dx_transfer_from_buffer(struct vmw_private *dev_priv, | |
2809 | struct vmw_sw_context *sw_context, | |
2810 | SVGA3dCmdHeader *header) | |
2811 | { | |
d01316d0 DR |
2812 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdDXTransferFromBuffer) = |
2813 | container_of(header, typeof(*cmd), header); | |
1f982e4e CL |
2814 | int ret; |
2815 | ||
2816 | ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, | |
a9f58c45 | 2817 | VMW_RES_DIRTY_NONE, user_surface_converter, |
1f982e4e CL |
2818 | &cmd->body.srcSid, NULL); |
2819 | if (ret != 0) | |
2820 | return ret; | |
2821 | ||
2822 | return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, | |
a9f58c45 | 2823 | VMW_RES_DIRTY_SET, user_surface_converter, |
1f982e4e CL |
2824 | &cmd->body.destSid, NULL); |
2825 | } | |
2826 | ||
0d81d346 | 2827 | /** |
680360a4 | 2828 | * vmw_cmd_intra_surface_copy - Validate SVGA_3D_CMD_INTRA_SURFACE_COPY command |
0d81d346 NB |
2829 | * |
2830 | * @dev_priv: Pointer to a device private struct. | |
2831 | * @sw_context: The software context being used for this batch. | |
2832 | * @header: Pointer to the command header in the command stream. | |
2833 | */ | |
2834 | static int vmw_cmd_intra_surface_copy(struct vmw_private *dev_priv, | |
2835 | struct vmw_sw_context *sw_context, | |
2836 | SVGA3dCmdHeader *header) | |
2837 | { | |
d01316d0 DR |
2838 | VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdIntraSurfaceCopy) = |
2839 | container_of(header, typeof(*cmd), header); | |
0d81d346 NB |
2840 | |
2841 | if (!(dev_priv->capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY)) | |
2842 | return -EINVAL; | |
2843 | ||
2844 | return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, | |
a9f58c45 TH |
2845 | VMW_RES_DIRTY_SET, user_surface_converter, |
2846 | &cmd->body.surface.sid, NULL); | |
0d81d346 NB |
2847 | } |
2848 | ||
b6fad739 DR |
2849 | static int vmw_cmd_sm5(struct vmw_private *dev_priv, |
2850 | struct vmw_sw_context *sw_context, | |
2851 | SVGA3dCmdHeader *header) | |
2852 | { | |
2853 | if (!has_sm5_context(dev_priv)) | |
2854 | return -EINVAL; | |
2855 | ||
2856 | return 0; | |
2857 | } | |
2858 | ||
5e8ec0d9 DR |
2859 | static int vmw_cmd_sm5_view_define(struct vmw_private *dev_priv, |
2860 | struct vmw_sw_context *sw_context, | |
2861 | SVGA3dCmdHeader *header) | |
2862 | { | |
2863 | if (!has_sm5_context(dev_priv)) | |
2864 | return -EINVAL; | |
2865 | ||
2866 | return vmw_cmd_dx_view_define(dev_priv, sw_context, header); | |
2867 | } | |
2868 | ||
2869 | static int vmw_cmd_sm5_view_remove(struct vmw_private *dev_priv, | |
2870 | struct vmw_sw_context *sw_context, | |
2871 | SVGA3dCmdHeader *header) | |
2872 | { | |
2873 | if (!has_sm5_context(dev_priv)) | |
2874 | return -EINVAL; | |
2875 | ||
2876 | return vmw_cmd_dx_view_remove(dev_priv, sw_context, header); | |
2877 | } | |
2878 | ||
2879 | static int vmw_cmd_clear_uav_uint(struct vmw_private *dev_priv, | |
2880 | struct vmw_sw_context *sw_context, | |
2881 | SVGA3dCmdHeader *header) | |
2882 | { | |
2883 | struct { | |
2884 | SVGA3dCmdHeader header; | |
2885 | SVGA3dCmdDXClearUAViewUint body; | |
2886 | } *cmd = container_of(header, typeof(*cmd), header); | |
2887 | struct vmw_resource *ret; | |
2888 | ||
2889 | if (!has_sm5_context(dev_priv)) | |
2890 | return -EINVAL; | |
2891 | ||
2892 | ret = vmw_view_id_val_add(sw_context, vmw_view_ua, | |
2893 | cmd->body.uaViewId); | |
2894 | ||
2895 | return PTR_ERR_OR_ZERO(ret); | |
2896 | } | |
2897 | ||
2898 | static int vmw_cmd_clear_uav_float(struct vmw_private *dev_priv, | |
2899 | struct vmw_sw_context *sw_context, | |
2900 | SVGA3dCmdHeader *header) | |
2901 | { | |
2902 | struct { | |
2903 | SVGA3dCmdHeader header; | |
2904 | SVGA3dCmdDXClearUAViewFloat body; | |
2905 | } *cmd = container_of(header, typeof(*cmd), header); | |
2906 | struct vmw_resource *ret; | |
2907 | ||
2908 | if (!has_sm5_context(dev_priv)) | |
2909 | return -EINVAL; | |
2910 | ||
2911 | ret = vmw_view_id_val_add(sw_context, vmw_view_ua, | |
2912 | cmd->body.uaViewId); | |
2913 | ||
2914 | return PTR_ERR_OR_ZERO(ret); | |
2915 | } | |
2916 | ||
2917 | static int vmw_cmd_set_uav(struct vmw_private *dev_priv, | |
2918 | struct vmw_sw_context *sw_context, | |
2919 | SVGA3dCmdHeader *header) | |
2920 | { | |
2921 | struct { | |
2922 | SVGA3dCmdHeader header; | |
2923 | SVGA3dCmdDXSetUAViews body; | |
2924 | } *cmd = container_of(header, typeof(*cmd), header); | |
2925 | u32 num_uav = (cmd->header.size - sizeof(cmd->body)) / | |
2926 | sizeof(SVGA3dUAViewId); | |
2927 | int ret; | |
2928 | ||
2929 | if (!has_sm5_context(dev_priv)) | |
2930 | return -EINVAL; | |
2931 | ||
4fb9326b | 2932 | if (num_uav > vmw_max_num_uavs(dev_priv)) { |
5e8ec0d9 DR |
2933 | VMW_DEBUG_USER("Invalid UAV binding.\n"); |
2934 | return -EINVAL; | |
2935 | } | |
2936 | ||
2937 | ret = vmw_view_bindings_add(sw_context, vmw_view_ua, | |
2938 | vmw_ctx_binding_uav, 0, (void *)&cmd[1], | |
2939 | num_uav, 0); | |
2940 | if (ret) | |
2941 | return ret; | |
2942 | ||
2943 | vmw_binding_add_uav_index(sw_context->dx_ctx_node->staged, 0, | |
2944 | cmd->body.uavSpliceIndex); | |
2945 | ||
2946 | return ret; | |
2947 | } | |
2948 | ||
2949 | static int vmw_cmd_set_cs_uav(struct vmw_private *dev_priv, | |
2950 | struct vmw_sw_context *sw_context, | |
2951 | SVGA3dCmdHeader *header) | |
2952 | { | |
2953 | struct { | |
2954 | SVGA3dCmdHeader header; | |
2955 | SVGA3dCmdDXSetCSUAViews body; | |
2956 | } *cmd = container_of(header, typeof(*cmd), header); | |
2957 | u32 num_uav = (cmd->header.size - sizeof(cmd->body)) / | |
2958 | sizeof(SVGA3dUAViewId); | |
2959 | int ret; | |
2960 | ||
2961 | if (!has_sm5_context(dev_priv)) | |
2962 | return -EINVAL; | |
2963 | ||
4fb9326b | 2964 | if (num_uav > vmw_max_num_uavs(dev_priv)) { |
5e8ec0d9 DR |
2965 | VMW_DEBUG_USER("Invalid UAV binding.\n"); |
2966 | return -EINVAL; | |
2967 | } | |
2968 | ||
2969 | ret = vmw_view_bindings_add(sw_context, vmw_view_ua, | |
2970 | vmw_ctx_binding_cs_uav, 0, (void *)&cmd[1], | |
2971 | num_uav, 0); | |
2972 | if (ret) | |
2973 | return ret; | |
2974 | ||
2975 | vmw_binding_add_uav_index(sw_context->dx_ctx_node->staged, 1, | |
2976 | cmd->body.startIndex); | |
2977 | ||
2978 | return ret; | |
2979 | } | |
2980 | ||
e8bead9c DR |
2981 | static int vmw_cmd_dx_define_streamoutput(struct vmw_private *dev_priv, |
2982 | struct vmw_sw_context *sw_context, | |
2983 | SVGA3dCmdHeader *header) | |
2984 | { | |
2985 | struct vmw_ctx_validation_info *ctx_node = sw_context->dx_ctx_node; | |
2986 | struct vmw_resource *res; | |
2987 | struct { | |
2988 | SVGA3dCmdHeader header; | |
2989 | SVGA3dCmdDXDefineStreamOutputWithMob body; | |
2990 | } *cmd = container_of(header, typeof(*cmd), header); | |
2991 | int ret; | |
2992 | ||
2993 | if (!has_sm5_context(dev_priv)) | |
2994 | return -EINVAL; | |
2995 | ||
2996 | if (!ctx_node) { | |
2997 | DRM_ERROR("DX Context not set.\n"); | |
2998 | return -EINVAL; | |
2999 | } | |
3000 | ||
3001 | res = vmw_context_cotable(ctx_node->ctx, SVGA_COTABLE_STREAMOUTPUT); | |
517621b7 ZR |
3002 | if (IS_ERR_OR_NULL(res)) |
3003 | return res ? PTR_ERR(res) : -EINVAL; | |
e8bead9c DR |
3004 | ret = vmw_cotable_notify(res, cmd->body.soid); |
3005 | if (ret) | |
3006 | return ret; | |
3007 | ||
3008 | return vmw_dx_streamoutput_add(sw_context->man, ctx_node->ctx, | |
3009 | cmd->body.soid, | |
3010 | &sw_context->staged_cmd_res); | |
3011 | } | |
3012 | ||
3013 | static int vmw_cmd_dx_destroy_streamoutput(struct vmw_private *dev_priv, | |
3014 | struct vmw_sw_context *sw_context, | |
3015 | SVGA3dCmdHeader *header) | |
3016 | { | |
3017 | struct vmw_ctx_validation_info *ctx_node = sw_context->dx_ctx_node; | |
3018 | struct vmw_resource *res; | |
3019 | struct { | |
3020 | SVGA3dCmdHeader header; | |
3021 | SVGA3dCmdDXDestroyStreamOutput body; | |
3022 | } *cmd = container_of(header, typeof(*cmd), header); | |
3023 | ||
3024 | if (!ctx_node) { | |
3025 | DRM_ERROR("DX Context not set.\n"); | |
3026 | return -EINVAL; | |
3027 | } | |
3028 | ||
3029 | /* | |
3030 | * When device does not support SM5 then streamoutput with mob command is | |
3031 | * not available to user-space. Simply return in this case. | |
3032 | */ | |
3033 | if (!has_sm5_context(dev_priv)) | |
3034 | return 0; | |
3035 | ||
3036 | /* | |
3037 | * With SM5 capable device if lookup fails then user-space probably used | |
3038 | * old streamoutput define command. Return without an error. | |
3039 | */ | |
3040 | res = vmw_dx_streamoutput_lookup(vmw_context_res_man(ctx_node->ctx), | |
3041 | cmd->body.soid); | |
3042 | if (IS_ERR(res)) | |
3043 | return 0; | |
3044 | ||
3045 | return vmw_dx_streamoutput_remove(sw_context->man, cmd->body.soid, | |
3046 | &sw_context->staged_cmd_res); | |
3047 | } | |
3048 | ||
3049 | static int vmw_cmd_dx_bind_streamoutput(struct vmw_private *dev_priv, | |
3050 | struct vmw_sw_context *sw_context, | |
3051 | SVGA3dCmdHeader *header) | |
3052 | { | |
3053 | struct vmw_ctx_validation_info *ctx_node = sw_context->dx_ctx_node; | |
3054 | struct vmw_resource *res; | |
3055 | struct { | |
3056 | SVGA3dCmdHeader header; | |
3057 | SVGA3dCmdDXBindStreamOutput body; | |
3058 | } *cmd = container_of(header, typeof(*cmd), header); | |
3059 | int ret; | |
3060 | ||
3061 | if (!has_sm5_context(dev_priv)) | |
3062 | return -EINVAL; | |
3063 | ||
3064 | if (!ctx_node) { | |
3065 | DRM_ERROR("DX Context not set.\n"); | |
3066 | return -EINVAL; | |
3067 | } | |
3068 | ||
3069 | res = vmw_dx_streamoutput_lookup(vmw_context_res_man(ctx_node->ctx), | |
3070 | cmd->body.soid); | |
3071 | if (IS_ERR(res)) { | |
1ae96fce | 3072 | DRM_ERROR("Could not find streamoutput to bind.\n"); |
e8bead9c DR |
3073 | return PTR_ERR(res); |
3074 | } | |
3075 | ||
3076 | vmw_dx_streamoutput_set_size(res, cmd->body.sizeInBytes); | |
3077 | ||
a309c719 ZR |
3078 | ret = vmw_execbuf_res_val_add(sw_context, res, VMW_RES_DIRTY_NONE, |
3079 | vmw_val_add_flag_noctx); | |
e8bead9c DR |
3080 | if (ret) { |
3081 | DRM_ERROR("Error creating resource validation node.\n"); | |
3082 | return ret; | |
3083 | } | |
3084 | ||
3085 | return vmw_cmd_res_switch_backup(dev_priv, sw_context, res, | |
3086 | &cmd->body.mobid, | |
3087 | cmd->body.offsetInBytes); | |
3088 | } | |
3089 | ||
3090 | static int vmw_cmd_dx_set_streamoutput(struct vmw_private *dev_priv, | |
3091 | struct vmw_sw_context *sw_context, | |
3092 | SVGA3dCmdHeader *header) | |
3093 | { | |
3094 | struct vmw_ctx_validation_info *ctx_node = sw_context->dx_ctx_node; | |
3095 | struct vmw_resource *res; | |
3096 | struct vmw_ctx_bindinfo_so binding; | |
3097 | struct { | |
3098 | SVGA3dCmdHeader header; | |
3099 | SVGA3dCmdDXSetStreamOutput body; | |
3100 | } *cmd = container_of(header, typeof(*cmd), header); | |
3101 | int ret; | |
3102 | ||
3103 | if (!ctx_node) { | |
3104 | DRM_ERROR("DX Context not set.\n"); | |
3105 | return -EINVAL; | |
3106 | } | |
3107 | ||
3108 | if (cmd->body.soid == SVGA3D_INVALID_ID) | |
3109 | return 0; | |
3110 | ||
3111 | /* | |
3112 | * When device does not support SM5 then streamoutput with mob command is | |
3113 | * not available to user-space. Simply return in this case. | |
3114 | */ | |
3115 | if (!has_sm5_context(dev_priv)) | |
3116 | return 0; | |
3117 | ||
3118 | /* | |
3119 | * With SM5 capable device if lookup fails then user-space probably used | |
3120 | * old streamoutput define command. Return without an error. | |
3121 | */ | |
3122 | res = vmw_dx_streamoutput_lookup(vmw_context_res_man(ctx_node->ctx), | |
3123 | cmd->body.soid); | |
3124 | if (IS_ERR(res)) { | |
3125 | return 0; | |
3126 | } | |
3127 | ||
a309c719 ZR |
3128 | ret = vmw_execbuf_res_val_add(sw_context, res, VMW_RES_DIRTY_NONE, |
3129 | vmw_val_add_flag_noctx); | |
e8bead9c DR |
3130 | if (ret) { |
3131 | DRM_ERROR("Error creating resource validation node.\n"); | |
3132 | return ret; | |
3133 | } | |
3134 | ||
3135 | binding.bi.ctx = ctx_node->ctx; | |
3136 | binding.bi.res = res; | |
3137 | binding.bi.bt = vmw_ctx_binding_so; | |
3138 | binding.slot = 0; /* Only one SO set to context at a time. */ | |
3139 | ||
3140 | vmw_binding_add(sw_context->dx_ctx_node->staged, &binding.bi, 0, | |
3141 | binding.slot); | |
3142 | ||
3143 | return ret; | |
3144 | } | |
3145 | ||
b6fad739 DR |
3146 | static int vmw_cmd_indexed_instanced_indirect(struct vmw_private *dev_priv, |
3147 | struct vmw_sw_context *sw_context, | |
3148 | SVGA3dCmdHeader *header) | |
3149 | { | |
3150 | struct vmw_draw_indexed_instanced_indirect_cmd { | |
3151 | SVGA3dCmdHeader header; | |
3152 | SVGA3dCmdDXDrawIndexedInstancedIndirect body; | |
3153 | } *cmd = container_of(header, typeof(*cmd), header); | |
3154 | ||
3155 | if (!has_sm5_context(dev_priv)) | |
3156 | return -EINVAL; | |
3157 | ||
3158 | return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, | |
3159 | VMW_RES_DIRTY_NONE, user_surface_converter, | |
3160 | &cmd->body.argsBufferSid, NULL); | |
3161 | } | |
3162 | ||
3163 | static int vmw_cmd_instanced_indirect(struct vmw_private *dev_priv, | |
3164 | struct vmw_sw_context *sw_context, | |
3165 | SVGA3dCmdHeader *header) | |
3166 | { | |
3167 | struct vmw_draw_instanced_indirect_cmd { | |
3168 | SVGA3dCmdHeader header; | |
3169 | SVGA3dCmdDXDrawInstancedIndirect body; | |
3170 | } *cmd = container_of(header, typeof(*cmd), header); | |
3171 | ||
3172 | if (!has_sm5_context(dev_priv)) | |
3173 | return -EINVAL; | |
3174 | ||
3175 | return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, | |
3176 | VMW_RES_DIRTY_NONE, user_surface_converter, | |
3177 | &cmd->body.argsBufferSid, NULL); | |
3178 | } | |
3179 | ||
3180 | static int vmw_cmd_dispatch_indirect(struct vmw_private *dev_priv, | |
3181 | struct vmw_sw_context *sw_context, | |
3182 | SVGA3dCmdHeader *header) | |
3183 | { | |
3184 | struct vmw_dispatch_indirect_cmd { | |
3185 | SVGA3dCmdHeader header; | |
3186 | SVGA3dCmdDXDispatchIndirect body; | |
3187 | } *cmd = container_of(header, typeof(*cmd), header); | |
3188 | ||
3189 | if (!has_sm5_context(dev_priv)) | |
3190 | return -EINVAL; | |
3191 | ||
3192 | return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, | |
3193 | VMW_RES_DIRTY_NONE, user_surface_converter, | |
3194 | &cmd->body.argsBufferSid, NULL); | |
3195 | } | |
3196 | ||
d80efd5c TH |
3197 | static int vmw_cmd_check_not_3d(struct vmw_private *dev_priv, |
3198 | struct vmw_sw_context *sw_context, | |
3199 | void *buf, uint32_t *size) | |
3200 | { | |
3201 | uint32_t size_remaining = *size; | |
3202 | uint32_t cmd_id; | |
3203 | ||
3204 | cmd_id = ((uint32_t *)buf)[0]; | |
3205 | switch (cmd_id) { | |
3206 | case SVGA_CMD_UPDATE: | |
3207 | *size = sizeof(uint32_t) + sizeof(SVGAFifoCmdUpdate); | |
3208 | break; | |
3209 | case SVGA_CMD_DEFINE_GMRFB: | |
3210 | *size = sizeof(uint32_t) + sizeof(SVGAFifoCmdDefineGMRFB); | |
3211 | break; | |
3212 | case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: | |
3213 | *size = sizeof(uint32_t) + sizeof(SVGAFifoCmdBlitGMRFBToScreen); | |
3214 | break; | |
3215 | case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: | |
3216 | *size = sizeof(uint32_t) + sizeof(SVGAFifoCmdBlitGMRFBToScreen); | |
3217 | break; | |
3218 | default: | |
5724f899 | 3219 | VMW_DEBUG_USER("Unsupported SVGA command: %u.\n", cmd_id); |
d80efd5c TH |
3220 | return -EINVAL; |
3221 | } | |
3222 | ||
3223 | if (*size > size_remaining) { | |
5724f899 DR |
3224 | VMW_DEBUG_USER("Invalid SVGA command (size mismatch): %u.\n", |
3225 | cmd_id); | |
d80efd5c TH |
3226 | return -EINVAL; |
3227 | } | |
3228 | ||
3229 | if (unlikely(!sw_context->kernel)) { | |
5724f899 | 3230 | VMW_DEBUG_USER("Kernel only SVGA command: %u.\n", cmd_id); |
d80efd5c TH |
3231 | return -EPERM; |
3232 | } | |
3233 | ||
3234 | if (cmd_id == SVGA_CMD_DEFINE_GMRFB) | |
3235 | return vmw_cmd_check_define_gmrfb(dev_priv, sw_context, buf); | |
3236 | ||
3237 | return 0; | |
3238 | } | |
3239 | ||
3240 | static const struct vmw_cmd_entry vmw_cmd_entries[SVGA_3D_CMD_MAX] = { | |
3241 | VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DEFINE, &vmw_cmd_invalid, | |
3242 | false, false, false), | |
3243 | VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DESTROY, &vmw_cmd_invalid, | |
3244 | false, false, false), | |
3245 | VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_COPY, &vmw_cmd_surface_copy_check, | |
3246 | true, false, false), | |
3247 | VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_STRETCHBLT, &vmw_cmd_stretch_blt_check, | |
3248 | true, false, false), | |
3249 | VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DMA, &vmw_cmd_dma, | |
3250 | true, false, false), | |
3251 | VMW_CMD_DEF(SVGA_3D_CMD_CONTEXT_DEFINE, &vmw_cmd_invalid, | |
3252 | false, false, false), | |
3253 | VMW_CMD_DEF(SVGA_3D_CMD_CONTEXT_DESTROY, &vmw_cmd_invalid, | |
3254 | false, false, false), | |
3255 | VMW_CMD_DEF(SVGA_3D_CMD_SETTRANSFORM, &vmw_cmd_cid_check, | |
3256 | true, false, false), | |
3257 | VMW_CMD_DEF(SVGA_3D_CMD_SETZRANGE, &vmw_cmd_cid_check, | |
3258 | true, false, false), | |
3259 | VMW_CMD_DEF(SVGA_3D_CMD_SETRENDERSTATE, &vmw_cmd_cid_check, | |
3260 | true, false, false), | |
3261 | VMW_CMD_DEF(SVGA_3D_CMD_SETRENDERTARGET, | |
3262 | &vmw_cmd_set_render_target_check, true, false, false), | |
3263 | VMW_CMD_DEF(SVGA_3D_CMD_SETTEXTURESTATE, &vmw_cmd_tex_state, | |
3264 | true, false, false), | |
3265 | VMW_CMD_DEF(SVGA_3D_CMD_SETMATERIAL, &vmw_cmd_cid_check, | |
3266 | true, false, false), | |
3267 | VMW_CMD_DEF(SVGA_3D_CMD_SETLIGHTDATA, &vmw_cmd_cid_check, | |
3268 | true, false, false), | |
c373d4ea TH |
3269 | VMW_CMD_DEF(SVGA_3D_CMD_SETLIGHTENABLED, &vmw_cmd_cid_check, |
3270 | true, false, false), | |
3271 | VMW_CMD_DEF(SVGA_3D_CMD_SETVIEWPORT, &vmw_cmd_cid_check, | |
3272 | true, false, false), | |
3273 | VMW_CMD_DEF(SVGA_3D_CMD_SETCLIPPLANE, &vmw_cmd_cid_check, | |
3274 | true, false, false), | |
3275 | VMW_CMD_DEF(SVGA_3D_CMD_CLEAR, &vmw_cmd_cid_check, | |
3276 | true, false, false), | |
3277 | VMW_CMD_DEF(SVGA_3D_CMD_PRESENT, &vmw_cmd_present_check, | |
3278 | false, false, false), | |
d5bde956 TH |
3279 | VMW_CMD_DEF(SVGA_3D_CMD_SHADER_DEFINE, &vmw_cmd_shader_define, |
3280 | true, false, false), | |
3281 | VMW_CMD_DEF(SVGA_3D_CMD_SHADER_DESTROY, &vmw_cmd_shader_destroy, | |
3282 | true, false, false), | |
c373d4ea TH |
3283 | VMW_CMD_DEF(SVGA_3D_CMD_SET_SHADER, &vmw_cmd_set_shader, |
3284 | true, false, false), | |
0ccbbae4 TH |
3285 | VMW_CMD_DEF(SVGA_3D_CMD_SET_SHADER_CONST, &vmw_cmd_set_shader_const, |
3286 | true, false, false), | |
c373d4ea TH |
3287 | VMW_CMD_DEF(SVGA_3D_CMD_DRAW_PRIMITIVES, &vmw_cmd_draw, |
3288 | true, false, false), | |
3289 | VMW_CMD_DEF(SVGA_3D_CMD_SETSCISSORRECT, &vmw_cmd_cid_check, | |
3290 | true, false, false), | |
3291 | VMW_CMD_DEF(SVGA_3D_CMD_BEGIN_QUERY, &vmw_cmd_begin_query, | |
3292 | true, false, false), | |
3293 | VMW_CMD_DEF(SVGA_3D_CMD_END_QUERY, &vmw_cmd_end_query, | |
3294 | true, false, false), | |
3295 | VMW_CMD_DEF(SVGA_3D_CMD_WAIT_FOR_QUERY, &vmw_cmd_wait_query, | |
3296 | true, false, false), | |
3297 | VMW_CMD_DEF(SVGA_3D_CMD_PRESENT_READBACK, &vmw_cmd_ok, | |
3298 | true, false, false), | |
fb1d9738 | 3299 | VMW_CMD_DEF(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN, |
c373d4ea TH |
3300 | &vmw_cmd_blt_surf_screen_check, false, false, false), |
3301 | VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DEFINE_V2, &vmw_cmd_invalid, | |
3302 | false, false, false), | |
3303 | VMW_CMD_DEF(SVGA_3D_CMD_GENERATE_MIPMAPS, &vmw_cmd_invalid, | |
3304 | false, false, false), | |
3305 | VMW_CMD_DEF(SVGA_3D_CMD_ACTIVATE_SURFACE, &vmw_cmd_invalid, | |
3306 | false, false, false), | |
3307 | VMW_CMD_DEF(SVGA_3D_CMD_DEACTIVATE_SURFACE, &vmw_cmd_invalid, | |
3308 | false, false, false), | |
3309 | VMW_CMD_DEF(SVGA_3D_CMD_SCREEN_DMA, &vmw_cmd_invalid, | |
3310 | false, false, false), | |
dc75e733 | 3311 | VMW_CMD_DEF(SVGA_3D_CMD_DEAD1, &vmw_cmd_invalid, |
c373d4ea | 3312 | false, false, false), |
dc75e733 | 3313 | VMW_CMD_DEF(SVGA_3D_CMD_DEAD2, &vmw_cmd_invalid, |
c373d4ea | 3314 | false, false, false), |
3d143954 DR |
3315 | VMW_CMD_DEF(SVGA_3D_CMD_DEAD12, &vmw_cmd_invalid, false, false, false), |
3316 | VMW_CMD_DEF(SVGA_3D_CMD_DEAD13, &vmw_cmd_invalid, false, false, false), | |
3317 | VMW_CMD_DEF(SVGA_3D_CMD_DEAD14, &vmw_cmd_invalid, false, false, false), | |
3318 | VMW_CMD_DEF(SVGA_3D_CMD_DEAD15, &vmw_cmd_invalid, false, false, false), | |
3319 | VMW_CMD_DEF(SVGA_3D_CMD_DEAD16, &vmw_cmd_invalid, false, false, false), | |
3320 | VMW_CMD_DEF(SVGA_3D_CMD_DEAD17, &vmw_cmd_invalid, false, false, false), | |
c373d4ea TH |
3321 | VMW_CMD_DEF(SVGA_3D_CMD_SET_OTABLE_BASE, &vmw_cmd_invalid, |
3322 | false, false, true), | |
3323 | VMW_CMD_DEF(SVGA_3D_CMD_READBACK_OTABLE, &vmw_cmd_invalid, | |
3324 | false, false, true), | |
3325 | VMW_CMD_DEF(SVGA_3D_CMD_DEFINE_GB_MOB, &vmw_cmd_invalid, | |
3326 | false, false, true), | |
3327 | VMW_CMD_DEF(SVGA_3D_CMD_DESTROY_GB_MOB, &vmw_cmd_invalid, | |
3328 | false, false, true), | |
fd11a3c0 SY |
3329 | VMW_CMD_DEF(SVGA_3D_CMD_REDEFINE_GB_MOB64, &vmw_cmd_invalid, |
3330 | false, false, true), | |
c373d4ea TH |
3331 | VMW_CMD_DEF(SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING, &vmw_cmd_invalid, |
3332 | false, false, true), | |
3333 | VMW_CMD_DEF(SVGA_3D_CMD_DEFINE_GB_SURFACE, &vmw_cmd_invalid, | |
3334 | false, false, true), | |
3335 | VMW_CMD_DEF(SVGA_3D_CMD_DESTROY_GB_SURFACE, &vmw_cmd_invalid, | |
3336 | false, false, true), | |
3337 | VMW_CMD_DEF(SVGA_3D_CMD_BIND_GB_SURFACE, &vmw_cmd_bind_gb_surface, | |
3338 | true, false, true), | |
3339 | VMW_CMD_DEF(SVGA_3D_CMD_COND_BIND_GB_SURFACE, &vmw_cmd_invalid, | |
3340 | false, false, true), | |
3341 | VMW_CMD_DEF(SVGA_3D_CMD_UPDATE_GB_IMAGE, &vmw_cmd_update_gb_image, | |
3342 | true, false, true), | |
a97e2192 | 3343 | VMW_CMD_DEF(SVGA_3D_CMD_UPDATE_GB_SURFACE, |
c373d4ea | 3344 | &vmw_cmd_update_gb_surface, true, false, true), |
a97e2192 | 3345 | VMW_CMD_DEF(SVGA_3D_CMD_READBACK_GB_IMAGE, |
c373d4ea | 3346 | &vmw_cmd_readback_gb_image, true, false, true), |
a97e2192 | 3347 | VMW_CMD_DEF(SVGA_3D_CMD_READBACK_GB_SURFACE, |
c373d4ea | 3348 | &vmw_cmd_readback_gb_surface, true, false, true), |
a97e2192 | 3349 | VMW_CMD_DEF(SVGA_3D_CMD_INVALIDATE_GB_IMAGE, |
c373d4ea | 3350 | &vmw_cmd_invalidate_gb_image, true, false, true), |
a97e2192 | 3351 | VMW_CMD_DEF(SVGA_3D_CMD_INVALIDATE_GB_SURFACE, |
c373d4ea TH |
3352 | &vmw_cmd_invalidate_gb_surface, true, false, true), |
3353 | VMW_CMD_DEF(SVGA_3D_CMD_DEFINE_GB_CONTEXT, &vmw_cmd_invalid, | |
3354 | false, false, true), | |
3355 | VMW_CMD_DEF(SVGA_3D_CMD_DESTROY_GB_CONTEXT, &vmw_cmd_invalid, | |
3356 | false, false, true), | |
3357 | VMW_CMD_DEF(SVGA_3D_CMD_BIND_GB_CONTEXT, &vmw_cmd_invalid, | |
3358 | false, false, true), | |
3359 | VMW_CMD_DEF(SVGA_3D_CMD_READBACK_GB_CONTEXT, &vmw_cmd_invalid, | |
3360 | false, false, true), | |
3361 | VMW_CMD_DEF(SVGA_3D_CMD_INVALIDATE_GB_CONTEXT, &vmw_cmd_invalid, | |
3362 | false, false, true), | |
3363 | VMW_CMD_DEF(SVGA_3D_CMD_DEFINE_GB_SHADER, &vmw_cmd_invalid, | |
3364 | false, false, true), | |
3365 | VMW_CMD_DEF(SVGA_3D_CMD_BIND_GB_SHADER, &vmw_cmd_bind_gb_shader, | |
3366 | true, false, true), | |
3367 | VMW_CMD_DEF(SVGA_3D_CMD_DESTROY_GB_SHADER, &vmw_cmd_invalid, | |
3368 | false, false, true), | |
f2a0dcb1 | 3369 | VMW_CMD_DEF(SVGA_3D_CMD_SET_OTABLE_BASE64, &vmw_cmd_invalid, |
8ba07315 | 3370 | false, false, false), |
c373d4ea TH |
3371 | VMW_CMD_DEF(SVGA_3D_CMD_BEGIN_GB_QUERY, &vmw_cmd_begin_gb_query, |
3372 | true, false, true), | |
3373 | VMW_CMD_DEF(SVGA_3D_CMD_END_GB_QUERY, &vmw_cmd_end_gb_query, | |
3374 | true, false, true), | |
3375 | VMW_CMD_DEF(SVGA_3D_CMD_WAIT_FOR_GB_QUERY, &vmw_cmd_wait_gb_query, | |
3376 | true, false, true), | |
3377 | VMW_CMD_DEF(SVGA_3D_CMD_NOP, &vmw_cmd_ok, | |
3378 | true, false, true), | |
5f55be5f TH |
3379 | VMW_CMD_DEF(SVGA_3D_CMD_NOP_ERROR, &vmw_cmd_ok, |
3380 | true, false, true), | |
c373d4ea TH |
3381 | VMW_CMD_DEF(SVGA_3D_CMD_ENABLE_GART, &vmw_cmd_invalid, |
3382 | false, false, true), | |
3383 | VMW_CMD_DEF(SVGA_3D_CMD_DISABLE_GART, &vmw_cmd_invalid, | |
3384 | false, false, true), | |
3385 | VMW_CMD_DEF(SVGA_3D_CMD_MAP_MOB_INTO_GART, &vmw_cmd_invalid, | |
3386 | false, false, true), | |
3387 | VMW_CMD_DEF(SVGA_3D_CMD_UNMAP_GART_RANGE, &vmw_cmd_invalid, | |
3388 | false, false, true), | |
3389 | VMW_CMD_DEF(SVGA_3D_CMD_DEFINE_GB_SCREENTARGET, &vmw_cmd_invalid, | |
3390 | false, false, true), | |
3391 | VMW_CMD_DEF(SVGA_3D_CMD_DESTROY_GB_SCREENTARGET, &vmw_cmd_invalid, | |
3392 | false, false, true), | |
3393 | VMW_CMD_DEF(SVGA_3D_CMD_BIND_GB_SCREENTARGET, &vmw_cmd_invalid, | |
3394 | false, false, true), | |
3395 | VMW_CMD_DEF(SVGA_3D_CMD_UPDATE_GB_SCREENTARGET, &vmw_cmd_invalid, | |
3396 | false, false, true), | |
3397 | VMW_CMD_DEF(SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL, &vmw_cmd_invalid, | |
3398 | false, false, true), | |
3399 | VMW_CMD_DEF(SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL, &vmw_cmd_invalid, | |
3400 | false, false, true), | |
3401 | VMW_CMD_DEF(SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE, &vmw_cmd_cid_check, | |
d80efd5c TH |
3402 | true, false, true), |
3403 | VMW_CMD_DEF(SVGA_3D_CMD_GB_SCREEN_DMA, &vmw_cmd_invalid, | |
3404 | false, false, true), | |
3405 | VMW_CMD_DEF(SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH, &vmw_cmd_invalid, | |
3406 | false, false, true), | |
3407 | VMW_CMD_DEF(SVGA_3D_CMD_GB_MOB_FENCE, &vmw_cmd_invalid, | |
3408 | false, false, true), | |
3409 | VMW_CMD_DEF(SVGA_3D_CMD_DEFINE_GB_SURFACE_V2, &vmw_cmd_invalid, | |
3410 | false, false, true), | |
3411 | ||
680360a4 | 3412 | /* SM commands */ |
d80efd5c TH |
3413 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DEFINE_CONTEXT, &vmw_cmd_invalid, |
3414 | false, false, true), | |
3415 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DESTROY_CONTEXT, &vmw_cmd_invalid, | |
3416 | false, false, true), | |
3417 | VMW_CMD_DEF(SVGA_3D_CMD_DX_BIND_CONTEXT, &vmw_cmd_invalid, | |
3418 | false, false, true), | |
3419 | VMW_CMD_DEF(SVGA_3D_CMD_DX_READBACK_CONTEXT, &vmw_cmd_invalid, | |
3420 | false, false, true), | |
3421 | VMW_CMD_DEF(SVGA_3D_CMD_DX_INVALIDATE_CONTEXT, &vmw_cmd_invalid, | |
3422 | false, false, true), | |
3423 | VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER, | |
3424 | &vmw_cmd_dx_set_single_constant_buffer, true, false, true), | |
3425 | VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_SHADER_RESOURCES, | |
3426 | &vmw_cmd_dx_set_shader_res, true, false, true), | |
3427 | VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_SHADER, &vmw_cmd_dx_set_shader, | |
3428 | true, false, true), | |
2f633e5e CL |
3429 | VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_SAMPLERS, &vmw_cmd_dx_cid_check, |
3430 | true, false, true), | |
3431 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DRAW, &vmw_cmd_dx_cid_check, | |
3432 | true, false, true), | |
3433 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DRAW_INDEXED, &vmw_cmd_dx_cid_check, | |
d80efd5c | 3434 | true, false, true), |
2f633e5e | 3435 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DRAW_INSTANCED, &vmw_cmd_dx_cid_check, |
d80efd5c | 3436 | true, false, true), |
2f633e5e CL |
3437 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED, |
3438 | &vmw_cmd_dx_cid_check, true, false, true), | |
3439 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DRAW_AUTO, &vmw_cmd_dx_cid_check, | |
d80efd5c TH |
3440 | true, false, true), |
3441 | VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS, | |
3442 | &vmw_cmd_dx_set_vertex_buffers, true, false, true), | |
3443 | VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_INDEX_BUFFER, | |
3444 | &vmw_cmd_dx_set_index_buffer, true, false, true), | |
3445 | VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_RENDERTARGETS, | |
3446 | &vmw_cmd_dx_set_rendertargets, true, false, true), | |
3447 | VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_BLEND_STATE, &vmw_cmd_dx_cid_check, | |
3448 | true, false, true), | |
d80efd5c | 3449 | VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE, |
2f633e5e CL |
3450 | &vmw_cmd_dx_cid_check, true, false, true), |
3451 | VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_RASTERIZER_STATE, | |
3452 | &vmw_cmd_dx_cid_check, true, false, true), | |
fd11a3c0 | 3453 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DEFINE_QUERY, &vmw_cmd_dx_define_query, |
d80efd5c | 3454 | true, false, true), |
e02e5884 | 3455 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DESTROY_QUERY, &vmw_cmd_dx_cid_check, |
d80efd5c | 3456 | true, false, true), |
fd11a3c0 | 3457 | VMW_CMD_DEF(SVGA_3D_CMD_DX_BIND_QUERY, &vmw_cmd_dx_bind_query, |
d80efd5c | 3458 | true, false, true), |
fd11a3c0 | 3459 | VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_QUERY_OFFSET, |
e02e5884 CL |
3460 | &vmw_cmd_dx_cid_check, true, false, true), |
3461 | VMW_CMD_DEF(SVGA_3D_CMD_DX_BEGIN_QUERY, &vmw_cmd_dx_cid_check, | |
d80efd5c | 3462 | true, false, true), |
e02e5884 | 3463 | VMW_CMD_DEF(SVGA_3D_CMD_DX_END_QUERY, &vmw_cmd_dx_cid_check, |
d80efd5c TH |
3464 | true, false, true), |
3465 | VMW_CMD_DEF(SVGA_3D_CMD_DX_READBACK_QUERY, &vmw_cmd_invalid, | |
3466 | true, false, true), | |
1883598d | 3467 | VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_PREDICATION, &vmw_cmd_dx_cid_check, |
d80efd5c TH |
3468 | true, false, true), |
3469 | VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_VIEWPORTS, &vmw_cmd_dx_cid_check, | |
3470 | true, false, true), | |
3471 | VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_SCISSORRECTS, &vmw_cmd_dx_cid_check, | |
3472 | true, false, true), | |
3473 | VMW_CMD_DEF(SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW, | |
3474 | &vmw_cmd_dx_clear_rendertarget_view, true, false, true), | |
3475 | VMW_CMD_DEF(SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW, | |
3476 | &vmw_cmd_dx_clear_depthstencil_view, true, false, true), | |
d80efd5c TH |
3477 | VMW_CMD_DEF(SVGA_3D_CMD_DX_PRED_COPY, &vmw_cmd_invalid, |
3478 | true, false, true), | |
f3b33550 | 3479 | VMW_CMD_DEF(SVGA_3D_CMD_DX_GENMIPS, &vmw_cmd_dx_genmips, |
d80efd5c TH |
3480 | true, false, true), |
3481 | VMW_CMD_DEF(SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE, | |
3482 | &vmw_cmd_dx_check_subresource, true, false, true), | |
3483 | VMW_CMD_DEF(SVGA_3D_CMD_DX_READBACK_SUBRESOURCE, | |
3484 | &vmw_cmd_dx_check_subresource, true, false, true), | |
3485 | VMW_CMD_DEF(SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE, | |
3486 | &vmw_cmd_dx_check_subresource, true, false, true), | |
3487 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW, | |
3488 | &vmw_cmd_dx_view_define, true, false, true), | |
3489 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW, | |
3490 | &vmw_cmd_dx_view_remove, true, false, true), | |
3491 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW, | |
3492 | &vmw_cmd_dx_view_define, true, false, true), | |
3493 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW, | |
3494 | &vmw_cmd_dx_view_remove, true, false, true), | |
3495 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW, | |
3496 | &vmw_cmd_dx_view_define, true, false, true), | |
3497 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW, | |
3498 | &vmw_cmd_dx_view_remove, true, false, true), | |
3499 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT, | |
3500 | &vmw_cmd_dx_so_define, true, false, true), | |
3501 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT, | |
3502 | &vmw_cmd_dx_cid_check, true, false, true), | |
3503 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DEFINE_BLEND_STATE, | |
3504 | &vmw_cmd_dx_so_define, true, false, true), | |
3505 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DESTROY_BLEND_STATE, | |
3506 | &vmw_cmd_dx_cid_check, true, false, true), | |
3507 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE, | |
3508 | &vmw_cmd_dx_so_define, true, false, true), | |
3509 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE, | |
3510 | &vmw_cmd_dx_cid_check, true, false, true), | |
3511 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE, | |
3512 | &vmw_cmd_dx_so_define, true, false, true), | |
3513 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE, | |
3514 | &vmw_cmd_dx_cid_check, true, false, true), | |
3515 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE, | |
3516 | &vmw_cmd_dx_so_define, true, false, true), | |
3517 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE, | |
3518 | &vmw_cmd_dx_cid_check, true, false, true), | |
3519 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DEFINE_SHADER, | |
3520 | &vmw_cmd_dx_define_shader, true, false, true), | |
3521 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DESTROY_SHADER, | |
3522 | &vmw_cmd_dx_destroy_shader, true, false, true), | |
3523 | VMW_CMD_DEF(SVGA_3D_CMD_DX_BIND_SHADER, | |
3524 | &vmw_cmd_dx_bind_shader, true, false, true), | |
3525 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT, | |
3526 | &vmw_cmd_dx_so_define, true, false, true), | |
3527 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT, | |
e8bead9c DR |
3528 | &vmw_cmd_dx_destroy_streamoutput, true, false, true), |
3529 | VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_STREAMOUTPUT, | |
3530 | &vmw_cmd_dx_set_streamoutput, true, false, true), | |
2f633e5e CL |
3531 | VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_SOTARGETS, |
3532 | &vmw_cmd_dx_set_so_targets, true, false, true), | |
d80efd5c TH |
3533 | VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_INPUT_LAYOUT, |
3534 | &vmw_cmd_dx_cid_check, true, false, true), | |
3535 | VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_TOPOLOGY, | |
3536 | &vmw_cmd_dx_cid_check, true, false, true), | |
0fca749e NB |
3537 | VMW_CMD_DEF(SVGA_3D_CMD_DX_BUFFER_COPY, |
3538 | &vmw_cmd_buffer_copy_check, true, false, true), | |
3539 | VMW_CMD_DEF(SVGA_3D_CMD_DX_PRED_COPY_REGION, | |
3540 | &vmw_cmd_pred_copy_check, true, false, true), | |
1f982e4e CL |
3541 | VMW_CMD_DEF(SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER, |
3542 | &vmw_cmd_dx_transfer_from_buffer, | |
3543 | true, false, true), | |
bf625870 RS |
3544 | VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET, |
3545 | &vmw_cmd_dx_set_constant_buffer_offset, | |
3546 | true, false, true), | |
3547 | VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET, | |
3548 | &vmw_cmd_dx_set_constant_buffer_offset, | |
3549 | true, false, true), | |
3550 | VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET, | |
3551 | &vmw_cmd_dx_set_constant_buffer_offset, | |
3552 | true, false, true), | |
3553 | VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET, | |
3554 | &vmw_cmd_dx_set_constant_buffer_offset, | |
3555 | true, false, true), | |
3556 | VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET, | |
3557 | &vmw_cmd_dx_set_constant_buffer_offset, | |
3558 | true, false, true), | |
3559 | VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET, | |
3560 | &vmw_cmd_dx_set_constant_buffer_offset, | |
3561 | true, false, true), | |
0d81d346 NB |
3562 | VMW_CMD_DEF(SVGA_3D_CMD_INTRA_SURFACE_COPY, &vmw_cmd_intra_surface_copy, |
3563 | true, false, true), | |
5e8ec0d9 DR |
3564 | |
3565 | /* | |
3566 | * SM5 commands | |
3567 | */ | |
3568 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DEFINE_UA_VIEW, &vmw_cmd_sm5_view_define, | |
3569 | true, false, true), | |
3570 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DESTROY_UA_VIEW, &vmw_cmd_sm5_view_remove, | |
3571 | true, false, true), | |
3572 | VMW_CMD_DEF(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT, &vmw_cmd_clear_uav_uint, | |
3573 | true, false, true), | |
3574 | VMW_CMD_DEF(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT, | |
3575 | &vmw_cmd_clear_uav_float, true, false, true), | |
3576 | VMW_CMD_DEF(SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT, &vmw_cmd_invalid, true, | |
3577 | false, true), | |
3578 | VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_UA_VIEWS, &vmw_cmd_set_uav, true, false, | |
3579 | true), | |
b6fad739 DR |
3580 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT, |
3581 | &vmw_cmd_indexed_instanced_indirect, true, false, true), | |
3582 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT, | |
3583 | &vmw_cmd_instanced_indirect, true, false, true), | |
3584 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DISPATCH, &vmw_cmd_sm5, true, false, true), | |
3585 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DISPATCH_INDIRECT, | |
3586 | &vmw_cmd_dispatch_indirect, true, false, true), | |
5e8ec0d9 DR |
3587 | VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_CS_UA_VIEWS, &vmw_cmd_set_cs_uav, true, |
3588 | false, true), | |
b6fad739 DR |
3589 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2, |
3590 | &vmw_cmd_sm5_view_define, true, false, true), | |
e8bead9c DR |
3591 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB, |
3592 | &vmw_cmd_dx_define_streamoutput, true, false, true), | |
3593 | VMW_CMD_DEF(SVGA_3D_CMD_DX_BIND_STREAMOUTPUT, | |
3594 | &vmw_cmd_dx_bind_streamoutput, true, false, true), | |
853369df RS |
3595 | VMW_CMD_DEF(SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE_V2, |
3596 | &vmw_cmd_dx_so_define, true, false, true), | |
f3e17b42 IF |
3597 | VMW_CMD_DEF(SVGA_3D_CMD_DEFINE_GB_SURFACE_V4, |
3598 | &vmw_cmd_invalid, false, false, true), | |
fb1d9738 JB |
3599 | }; |
3600 | ||
65b97a2b TH |
3601 | bool vmw_cmd_describe(const void *buf, u32 *size, char const **cmd) |
3602 | { | |
3603 | u32 cmd_id = ((u32 *) buf)[0]; | |
3604 | ||
3605 | if (cmd_id >= SVGA_CMD_MAX) { | |
3606 | SVGA3dCmdHeader *header = (SVGA3dCmdHeader *) buf; | |
3607 | const struct vmw_cmd_entry *entry; | |
3608 | ||
3609 | *size = header->size + sizeof(SVGA3dCmdHeader); | |
3610 | cmd_id = header->id; | |
3611 | if (cmd_id >= SVGA_3D_CMD_MAX) | |
3612 | return false; | |
3613 | ||
3614 | cmd_id -= SVGA_3D_CMD_BASE; | |
3615 | entry = &vmw_cmd_entries[cmd_id]; | |
3616 | *cmd = entry->cmd_name; | |
3617 | return true; | |
3618 | } | |
3619 | ||
3620 | switch (cmd_id) { | |
3621 | case SVGA_CMD_UPDATE: | |
3622 | *cmd = "SVGA_CMD_UPDATE"; | |
3623 | *size = sizeof(u32) + sizeof(SVGAFifoCmdUpdate); | |
3624 | break; | |
3625 | case SVGA_CMD_DEFINE_GMRFB: | |
3626 | *cmd = "SVGA_CMD_DEFINE_GMRFB"; | |
3627 | *size = sizeof(u32) + sizeof(SVGAFifoCmdDefineGMRFB); | |
3628 | break; | |
3629 | case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: | |
3630 | *cmd = "SVGA_CMD_BLIT_GMRFB_TO_SCREEN"; | |
3631 | *size = sizeof(u32) + sizeof(SVGAFifoCmdBlitGMRFBToScreen); | |
3632 | break; | |
3633 | case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: | |
3634 | *cmd = "SVGA_CMD_BLIT_SCREEN_TO_GMRFB"; | |
3635 | *size = sizeof(u32) + sizeof(SVGAFifoCmdBlitGMRFBToScreen); | |
3636 | break; | |
3637 | default: | |
3638 | *cmd = "UNKNOWN"; | |
3639 | *size = 0; | |
3640 | return false; | |
3641 | } | |
3642 | ||
3643 | return true; | |
3644 | } | |
3645 | ||
fb1d9738 | 3646 | static int vmw_cmd_check(struct vmw_private *dev_priv, |
680360a4 DR |
3647 | struct vmw_sw_context *sw_context, void *buf, |
3648 | uint32_t *size) | |
fb1d9738 JB |
3649 | { |
3650 | uint32_t cmd_id; | |
7a73ba74 | 3651 | uint32_t size_remaining = *size; |
fb1d9738 JB |
3652 | SVGA3dCmdHeader *header = (SVGA3dCmdHeader *) buf; |
3653 | int ret; | |
c373d4ea TH |
3654 | const struct vmw_cmd_entry *entry; |
3655 | bool gb = dev_priv->capabilities & SVGA_CAP_GBOBJECTS; | |
fb1d9738 | 3656 | |
b9eb1a61 | 3657 | cmd_id = ((uint32_t *)buf)[0]; |
4084fb89 JB |
3658 | /* Handle any none 3D commands */ |
3659 | if (unlikely(cmd_id < SVGA_CMD_MAX)) | |
3660 | return vmw_cmd_check_not_3d(dev_priv, sw_context, buf, size); | |
3661 | ||
fb1d9738 | 3662 | |
b9eb1a61 TH |
3663 | cmd_id = header->id; |
3664 | *size = header->size + sizeof(SVGA3dCmdHeader); | |
fb1d9738 JB |
3665 | |
3666 | cmd_id -= SVGA_3D_CMD_BASE; | |
7a73ba74 | 3667 | if (unlikely(*size > size_remaining)) |
c373d4ea | 3668 | goto out_invalid; |
7a73ba74 | 3669 | |
fb1d9738 | 3670 | if (unlikely(cmd_id >= SVGA_3D_CMD_MAX - SVGA_3D_CMD_BASE)) |
c373d4ea TH |
3671 | goto out_invalid; |
3672 | ||
3673 | entry = &vmw_cmd_entries[cmd_id]; | |
36e952c1 TH |
3674 | if (unlikely(!entry->func)) |
3675 | goto out_invalid; | |
3676 | ||
c373d4ea TH |
3677 | if (unlikely(!entry->user_allow && !sw_context->kernel)) |
3678 | goto out_privileged; | |
3679 | ||
3680 | if (unlikely(entry->gb_disable && gb)) | |
3681 | goto out_old; | |
3682 | ||
3683 | if (unlikely(entry->gb_enable && !gb)) | |
3684 | goto out_new; | |
fb1d9738 | 3685 | |
c373d4ea | 3686 | ret = entry->func(dev_priv, sw_context, header); |
45399b11 DR |
3687 | if (unlikely(ret != 0)) { |
3688 | VMW_DEBUG_USER("SVGA3D command: %d failed with error %d\n", | |
3689 | cmd_id + SVGA_3D_CMD_BASE, ret); | |
3690 | return ret; | |
3691 | } | |
fb1d9738 JB |
3692 | |
3693 | return 0; | |
c373d4ea | 3694 | out_invalid: |
5724f899 DR |
3695 | VMW_DEBUG_USER("Invalid SVGA3D command: %d\n", |
3696 | cmd_id + SVGA_3D_CMD_BASE); | |
c373d4ea TH |
3697 | return -EINVAL; |
3698 | out_privileged: | |
5724f899 DR |
3699 | VMW_DEBUG_USER("Privileged SVGA3D command: %d\n", |
3700 | cmd_id + SVGA_3D_CMD_BASE); | |
c373d4ea TH |
3701 | return -EPERM; |
3702 | out_old: | |
5724f899 DR |
3703 | VMW_DEBUG_USER("Deprecated (disallowed) SVGA3D command: %d\n", |
3704 | cmd_id + SVGA_3D_CMD_BASE); | |
c373d4ea TH |
3705 | return -EINVAL; |
3706 | out_new: | |
5724f899 DR |
3707 | VMW_DEBUG_USER("SVGA3D command: %d not supported by virtual device.\n", |
3708 | cmd_id + SVGA_3D_CMD_BASE); | |
fb1d9738 JB |
3709 | return -EINVAL; |
3710 | } | |
3711 | ||
3712 | static int vmw_cmd_check_all(struct vmw_private *dev_priv, | |
680360a4 | 3713 | struct vmw_sw_context *sw_context, void *buf, |
be38ab6e | 3714 | uint32_t size) |
fb1d9738 JB |
3715 | { |
3716 | int32_t cur_size = size; | |
3717 | int ret; | |
3718 | ||
c0951b79 TH |
3719 | sw_context->buf_start = buf; |
3720 | ||
fb1d9738 | 3721 | while (cur_size > 0) { |
7a73ba74 | 3722 | size = cur_size; |
fb1d9738 JB |
3723 | ret = vmw_cmd_check(dev_priv, sw_context, buf, &size); |
3724 | if (unlikely(ret != 0)) | |
3725 | return ret; | |
3726 | buf = (void *)((unsigned long) buf + size); | |
3727 | cur_size -= size; | |
3728 | } | |
3729 | ||
3730 | if (unlikely(cur_size != 0)) { | |
5724f899 | 3731 | VMW_DEBUG_USER("Command verifier out of sync.\n"); |
fb1d9738 JB |
3732 | return -EINVAL; |
3733 | } | |
3734 | ||
3735 | return 0; | |
3736 | } | |
3737 | ||
3738 | static void vmw_free_relocations(struct vmw_sw_context *sw_context) | |
3739 | { | |
fc18afcf | 3740 | /* Memory is validation context memory, so no need to free it */ |
fc18afcf | 3741 | INIT_LIST_HEAD(&sw_context->bo_relocations); |
fb1d9738 JB |
3742 | } |
3743 | ||
3744 | static void vmw_apply_relocations(struct vmw_sw_context *sw_context) | |
3745 | { | |
fb1d9738 | 3746 | struct vmw_relocation *reloc; |
fb1d9738 JB |
3747 | struct ttm_buffer_object *bo; |
3748 | ||
fc18afcf | 3749 | list_for_each_entry(reloc, &sw_context->bo_relocations, head) { |
668b2066 | 3750 | bo = &reloc->vbo->tbo; |
d3116756 | 3751 | switch (bo->resource->mem_type) { |
c0951b79 | 3752 | case TTM_PL_VRAM: |
d3116756 | 3753 | reloc->location->offset += bo->resource->start << PAGE_SHIFT; |
135cba0d | 3754 | reloc->location->gmrId = SVGA_GMR_FRAMEBUFFER; |
c0951b79 TH |
3755 | break; |
3756 | case VMW_PL_GMR: | |
d3116756 | 3757 | reloc->location->gmrId = bo->resource->start; |
c0951b79 | 3758 | break; |
ddcda24e | 3759 | case VMW_PL_MOB: |
d3116756 | 3760 | *reloc->mob_loc = bo->resource->start; |
ddcda24e | 3761 | break; |
c0951b79 TH |
3762 | default: |
3763 | BUG(); | |
3764 | } | |
fb1d9738 JB |
3765 | } |
3766 | vmw_free_relocations(sw_context); | |
3767 | } | |
3768 | ||
be38ab6e TH |
3769 | static int vmw_resize_cmd_bounce(struct vmw_sw_context *sw_context, |
3770 | uint32_t size) | |
3771 | { | |
3772 | if (likely(sw_context->cmd_bounce_size >= size)) | |
3773 | return 0; | |
3774 | ||
3775 | if (sw_context->cmd_bounce_size == 0) | |
3776 | sw_context->cmd_bounce_size = VMWGFX_CMD_BOUNCE_INIT_SIZE; | |
3777 | ||
3778 | while (sw_context->cmd_bounce_size < size) { | |
3779 | sw_context->cmd_bounce_size = | |
3780 | PAGE_ALIGN(sw_context->cmd_bounce_size + | |
3781 | (sw_context->cmd_bounce_size >> 1)); | |
3782 | } | |
3783 | ||
0bc32997 | 3784 | vfree(sw_context->cmd_bounce); |
be38ab6e TH |
3785 | sw_context->cmd_bounce = vmalloc(sw_context->cmd_bounce_size); |
3786 | ||
3787 | if (sw_context->cmd_bounce == NULL) { | |
5724f899 | 3788 | VMW_DEBUG_USER("Failed to allocate command bounce buffer.\n"); |
be38ab6e TH |
3789 | sw_context->cmd_bounce_size = 0; |
3790 | return -ENOMEM; | |
3791 | } | |
3792 | ||
3793 | return 0; | |
3794 | } | |
3795 | ||
7450bf76 | 3796 | /* |
ae2a1040 TH |
3797 | * vmw_execbuf_fence_commands - create and submit a command stream fence |
3798 | * | |
3799 | * Creates a fence object and submits a command stream marker. | |
3800 | * If this fails for some reason, We sync the fifo and return NULL. | |
3801 | * It is then safe to fence buffers with a NULL pointer. | |
6070e9fa | 3802 | * |
680360a4 DR |
3803 | * If @p_handle is not NULL @file_priv must also not be NULL. Creates a |
3804 | * userspace handle if @p_handle is not NULL, otherwise not. | |
ae2a1040 TH |
3805 | */ |
3806 | ||
3807 | int vmw_execbuf_fence_commands(struct drm_file *file_priv, | |
3808 | struct vmw_private *dev_priv, | |
3809 | struct vmw_fence_obj **p_fence, | |
3810 | uint32_t *p_handle) | |
3811 | { | |
3812 | uint32_t sequence; | |
3813 | int ret; | |
3814 | bool synced = false; | |
3815 | ||
6070e9fa JB |
3816 | /* p_handle implies file_priv. */ |
3817 | BUG_ON(p_handle != NULL && file_priv == NULL); | |
ae2a1040 | 3818 | |
8426ed9c | 3819 | ret = vmw_cmd_send_fence(dev_priv, &sequence); |
ae2a1040 | 3820 | if (unlikely(ret != 0)) { |
5724f899 | 3821 | VMW_DEBUG_USER("Fence submission error. Syncing.\n"); |
ae2a1040 TH |
3822 | synced = true; |
3823 | } | |
3824 | ||
3825 | if (p_handle != NULL) | |
3826 | ret = vmw_user_fence_create(file_priv, dev_priv->fman, | |
c060a4e1 | 3827 | sequence, p_fence, p_handle); |
ae2a1040 | 3828 | else |
c060a4e1 | 3829 | ret = vmw_fence_create(dev_priv->fman, sequence, p_fence); |
ae2a1040 TH |
3830 | |
3831 | if (unlikely(ret != 0 && !synced)) { | |
680360a4 DR |
3832 | (void) vmw_fallback_wait(dev_priv, false, false, sequence, |
3833 | false, VMW_FENCE_WAIT_TIMEOUT); | |
ae2a1040 TH |
3834 | *p_fence = NULL; |
3835 | } | |
3836 | ||
728354c0 | 3837 | return ret; |
ae2a1040 TH |
3838 | } |
3839 | ||
8bf445ce | 3840 | /** |
680360a4 | 3841 | * vmw_execbuf_copy_fence_user - copy fence object information to user-space. |
8bf445ce TH |
3842 | * |
3843 | * @dev_priv: Pointer to a vmw_private struct. | |
3844 | * @vmw_fp: Pointer to the struct vmw_fpriv representing the calling file. | |
3845 | * @ret: Return value from fence object creation. | |
680360a4 DR |
3846 | * @user_fence_rep: User space address of a struct drm_vmw_fence_rep to which |
3847 | * the information should be copied. | |
8bf445ce TH |
3848 | * @fence: Pointer to the fenc object. |
3849 | * @fence_handle: User-space fence handle. | |
c906965d | 3850 | * @out_fence_fd: exported file descriptor for the fence. -1 if not used |
8bf445ce | 3851 | * |
680360a4 DR |
3852 | * This function copies fence information to user-space. If copying fails, the |
3853 | * user-space struct drm_vmw_fence_rep::error member is hopefully left | |
3854 | * untouched, and if it's preloaded with an -EFAULT by user-space, the error | |
3855 | * will hopefully be detected. | |
3856 | * | |
3857 | * Also if copying fails, user-space will be unable to signal the fence object | |
3858 | * so we wait for it immediately, and then unreference the user-space reference. | |
8bf445ce | 3859 | */ |
a0f90c88 | 3860 | int |
8bf445ce | 3861 | vmw_execbuf_copy_fence_user(struct vmw_private *dev_priv, |
680360a4 | 3862 | struct vmw_fpriv *vmw_fp, int ret, |
8bf445ce | 3863 | struct drm_vmw_fence_rep __user *user_fence_rep, |
680360a4 | 3864 | struct vmw_fence_obj *fence, uint32_t fence_handle, |
a0f90c88 | 3865 | int32_t out_fence_fd) |
8bf445ce TH |
3866 | { |
3867 | struct drm_vmw_fence_rep fence_rep; | |
3868 | ||
3869 | if (user_fence_rep == NULL) | |
a0f90c88 | 3870 | return 0; |
8bf445ce | 3871 | |
80d9b24a DC |
3872 | memset(&fence_rep, 0, sizeof(fence_rep)); |
3873 | ||
8bf445ce | 3874 | fence_rep.error = ret; |
c906965d | 3875 | fence_rep.fd = out_fence_fd; |
8bf445ce TH |
3876 | if (ret == 0) { |
3877 | BUG_ON(fence == NULL); | |
3878 | ||
3879 | fence_rep.handle = fence_handle; | |
2298e804 | 3880 | fence_rep.seqno = fence->base.seqno; |
2cd80dbd | 3881 | vmw_update_seqno(dev_priv); |
8bf445ce TH |
3882 | fence_rep.passed_seqno = dev_priv->last_read_seqno; |
3883 | } | |
3884 | ||
3885 | /* | |
680360a4 DR |
3886 | * copy_to_user errors will be detected by user space not seeing |
3887 | * fence_rep::error filled in. Typically user-space would have pre-set | |
3888 | * that member to -EFAULT. | |
8bf445ce TH |
3889 | */ |
3890 | ret = copy_to_user(user_fence_rep, &fence_rep, | |
3891 | sizeof(fence_rep)); | |
3892 | ||
3893 | /* | |
680360a4 DR |
3894 | * User-space lost the fence object. We need to sync and unreference the |
3895 | * handle. | |
8bf445ce TH |
3896 | */ |
3897 | if (unlikely(ret != 0) && (fence_rep.error == 0)) { | |
8afa13a0 | 3898 | ttm_ref_object_base_unref(vmw_fp->tfile, fence_handle); |
5724f899 | 3899 | VMW_DEBUG_USER("Fence copy error. Syncing.\n"); |
c060a4e1 | 3900 | (void) vmw_fence_obj_wait(fence, false, false, |
8bf445ce TH |
3901 | VMW_FENCE_WAIT_TIMEOUT); |
3902 | } | |
a0f90c88 MK |
3903 | |
3904 | return ret ? -EFAULT : 0; | |
8bf445ce TH |
3905 | } |
3906 | ||
3eab3d9e | 3907 | /** |
680360a4 | 3908 | * vmw_execbuf_submit_fifo - Patch a command batch and submit it using the fifo. |
3eab3d9e TH |
3909 | * |
3910 | * @dev_priv: Pointer to a device private structure. | |
3911 | * @kernel_commands: Pointer to the unpatched command batch. | |
3912 | * @command_size: Size of the unpatched command batch. | |
3913 | * @sw_context: Structure holding the relocation lists. | |
3914 | * | |
680360a4 DR |
3915 | * Side effects: If this function returns 0, then the command batch pointed to |
3916 | * by @kernel_commands will have been modified. | |
3eab3d9e TH |
3917 | */ |
3918 | static int vmw_execbuf_submit_fifo(struct vmw_private *dev_priv, | |
680360a4 | 3919 | void *kernel_commands, u32 command_size, |
3eab3d9e TH |
3920 | struct vmw_sw_context *sw_context) |
3921 | { | |
d80efd5c | 3922 | void *cmd; |
3eab3d9e | 3923 | |
d80efd5c | 3924 | if (sw_context->dx_ctx_node) |
8426ed9c | 3925 | cmd = VMW_CMD_CTX_RESERVE(dev_priv, command_size, |
9c079b8c | 3926 | sw_context->dx_ctx_node->ctx->id); |
d80efd5c | 3927 | else |
8426ed9c | 3928 | cmd = VMW_CMD_RESERVE(dev_priv, command_size); |
11c45419 DR |
3929 | |
3930 | if (!cmd) | |
3eab3d9e | 3931 | return -ENOMEM; |
18e4a466 | 3932 | |
3eab3d9e TH |
3933 | vmw_apply_relocations(sw_context); |
3934 | memcpy(cmd, kernel_commands, command_size); | |
3935 | vmw_resource_relocations_apply(cmd, &sw_context->res_relocations); | |
3936 | vmw_resource_relocations_free(&sw_context->res_relocations); | |
8426ed9c | 3937 | vmw_cmd_commit(dev_priv, command_size); |
3eab3d9e TH |
3938 | |
3939 | return 0; | |
3940 | } | |
3941 | ||
3942 | /** | |
680360a4 DR |
3943 | * vmw_execbuf_submit_cmdbuf - Patch a command batch and submit it using the |
3944 | * command buffer manager. | |
3eab3d9e TH |
3945 | * |
3946 | * @dev_priv: Pointer to a device private structure. | |
3947 | * @header: Opaque handle to the command buffer allocation. | |
3948 | * @command_size: Size of the unpatched command batch. | |
3949 | * @sw_context: Structure holding the relocation lists. | |
3950 | * | |
680360a4 DR |
3951 | * Side effects: If this function returns 0, then the command buffer represented |
3952 | * by @header will have been modified. | |
3eab3d9e TH |
3953 | */ |
3954 | static int vmw_execbuf_submit_cmdbuf(struct vmw_private *dev_priv, | |
3955 | struct vmw_cmdbuf_header *header, | |
3956 | u32 command_size, | |
3957 | struct vmw_sw_context *sw_context) | |
3958 | { | |
9c079b8c | 3959 | u32 id = ((sw_context->dx_ctx_node) ? sw_context->dx_ctx_node->ctx->id : |
d80efd5c | 3960 | SVGA3D_INVALID_ID); |
680360a4 DR |
3961 | void *cmd = vmw_cmdbuf_reserve(dev_priv->cman, command_size, id, false, |
3962 | header); | |
3eab3d9e TH |
3963 | |
3964 | vmw_apply_relocations(sw_context); | |
3965 | vmw_resource_relocations_apply(cmd, &sw_context->res_relocations); | |
3966 | vmw_resource_relocations_free(&sw_context->res_relocations); | |
3967 | vmw_cmdbuf_commit(dev_priv->cman, command_size, header, false); | |
3968 | ||
3969 | return 0; | |
3970 | } | |
3971 | ||
3972 | /** | |
3973 | * vmw_execbuf_cmdbuf - Prepare, if possible, a user-space command batch for | |
3974 | * submission using a command buffer. | |
3975 | * | |
3976 | * @dev_priv: Pointer to a device private structure. | |
3977 | * @user_commands: User-space pointer to the commands to be submitted. | |
3978 | * @command_size: Size of the unpatched command batch. | |
3979 | * @header: Out parameter returning the opaque pointer to the command buffer. | |
3980 | * | |
3981 | * This function checks whether we can use the command buffer manager for | |
680360a4 DR |
3982 | * submission and if so, creates a command buffer of suitable size and copies |
3983 | * the user data into that buffer. | |
3eab3d9e TH |
3984 | * |
3985 | * On successful return, the function returns a pointer to the data in the | |
3986 | * command buffer and *@header is set to non-NULL. | |
680360a4 | 3987 | * |
7450bf76 LJ |
3988 | * @kernel_commands: If command buffers could not be used, the function will |
3989 | * return the value of @kernel_commands on function call. That value may be | |
3990 | * NULL. In that case, the value of *@header will be set to NULL. | |
680360a4 | 3991 | * |
3eab3d9e TH |
3992 | * If an error is encountered, the function will return a pointer error value. |
3993 | * If the function is interrupted by a signal while sleeping, it will return | |
3994 | * -ERESTARTSYS casted to a pointer error value. | |
3995 | */ | |
b9eb1a61 TH |
3996 | static void *vmw_execbuf_cmdbuf(struct vmw_private *dev_priv, |
3997 | void __user *user_commands, | |
680360a4 | 3998 | void *kernel_commands, u32 command_size, |
b9eb1a61 | 3999 | struct vmw_cmdbuf_header **header) |
3eab3d9e TH |
4000 | { |
4001 | size_t cmdbuf_size; | |
4002 | int ret; | |
4003 | ||
4004 | *header = NULL; | |
3eab3d9e | 4005 | if (command_size > SVGA_CB_MAX_SIZE) { |
5724f899 | 4006 | VMW_DEBUG_USER("Command buffer is too large.\n"); |
3eab3d9e TH |
4007 | return ERR_PTR(-EINVAL); |
4008 | } | |
4009 | ||
51ab70be TH |
4010 | if (!dev_priv->cman || kernel_commands) |
4011 | return kernel_commands; | |
4012 | ||
3eab3d9e TH |
4013 | /* If possible, add a little space for fencing. */ |
4014 | cmdbuf_size = command_size + 512; | |
4015 | cmdbuf_size = min_t(size_t, cmdbuf_size, SVGA_CB_MAX_SIZE); | |
680360a4 DR |
4016 | kernel_commands = vmw_cmdbuf_alloc(dev_priv->cman, cmdbuf_size, true, |
4017 | header); | |
3eab3d9e TH |
4018 | if (IS_ERR(kernel_commands)) |
4019 | return kernel_commands; | |
4020 | ||
680360a4 | 4021 | ret = copy_from_user(kernel_commands, user_commands, command_size); |
3eab3d9e | 4022 | if (ret) { |
5724f899 | 4023 | VMW_DEBUG_USER("Failed copying commands.\n"); |
3eab3d9e TH |
4024 | vmw_cmdbuf_header_free(*header); |
4025 | *header = NULL; | |
4026 | return ERR_PTR(-EFAULT); | |
4027 | } | |
4028 | ||
4029 | return kernel_commands; | |
4030 | } | |
18e4a466 | 4031 | |
d80efd5c TH |
4032 | static int vmw_execbuf_tie_context(struct vmw_private *dev_priv, |
4033 | struct vmw_sw_context *sw_context, | |
4034 | uint32_t handle) | |
4035 | { | |
d80efd5c TH |
4036 | struct vmw_resource *res; |
4037 | int ret; | |
e8c66efb | 4038 | unsigned int size; |
d80efd5c TH |
4039 | |
4040 | if (handle == SVGA3D_INVALID_ID) | |
4041 | return 0; | |
4042 | ||
e8c66efb TH |
4043 | size = vmw_execbuf_res_size(dev_priv, vmw_res_dx_context); |
4044 | ret = vmw_validation_preload_res(sw_context->ctx, size); | |
4045 | if (ret) | |
4046 | return ret; | |
4047 | ||
a309c719 | 4048 | ret = vmw_user_resource_lookup_handle |
e8c66efb | 4049 | (dev_priv, sw_context->fp->tfile, handle, |
a309c719 ZR |
4050 | user_context_converter, &res); |
4051 | if (ret != 0) { | |
5724f899 DR |
4052 | VMW_DEBUG_USER("Could not find or user DX context 0x%08x.\n", |
4053 | (unsigned int) handle); | |
a309c719 | 4054 | return ret; |
d80efd5c TH |
4055 | } |
4056 | ||
a309c719 ZR |
4057 | ret = vmw_execbuf_res_val_add(sw_context, res, VMW_RES_DIRTY_SET, |
4058 | vmw_val_add_flag_none); | |
4059 | if (unlikely(ret != 0)) { | |
4060 | vmw_resource_unreference(&res); | |
e8c66efb | 4061 | return ret; |
a309c719 | 4062 | } |
d80efd5c | 4063 | |
9c079b8c | 4064 | sw_context->dx_ctx_node = vmw_execbuf_info_from_res(sw_context, res); |
d80efd5c | 4065 | sw_context->man = vmw_context_res_man(res); |
e8c66efb | 4066 | |
a309c719 | 4067 | vmw_resource_unreference(&res); |
e8c66efb | 4068 | return 0; |
d80efd5c TH |
4069 | } |
4070 | ||
0039a3b3 IF |
4071 | /* |
4072 | * DMA fence callback to remove a seqno_waiter | |
4073 | */ | |
4074 | struct seqno_waiter_rm_context { | |
4075 | struct dma_fence_cb base; | |
4076 | struct vmw_private *dev_priv; | |
4077 | }; | |
4078 | ||
4079 | static void seqno_waiter_rm_cb(struct dma_fence *f, struct dma_fence_cb *cb) | |
4080 | { | |
4081 | struct seqno_waiter_rm_context *ctx = | |
4082 | container_of(cb, struct seqno_waiter_rm_context, base); | |
4083 | ||
4084 | vmw_seqno_waiter_remove(ctx->dev_priv); | |
4085 | kfree(ctx); | |
4086 | } | |
4087 | ||
922ade0d TH |
4088 | int vmw_execbuf_process(struct drm_file *file_priv, |
4089 | struct vmw_private *dev_priv, | |
680360a4 DR |
4090 | void __user *user_commands, void *kernel_commands, |
4091 | uint32_t command_size, uint64_t throttle_us, | |
d80efd5c | 4092 | uint32_t dx_context_handle, |
bb1bd2f4 | 4093 | struct drm_vmw_fence_rep __user *user_fence_rep, |
680360a4 | 4094 | struct vmw_fence_obj **out_fence, uint32_t flags) |
fb1d9738 | 4095 | { |
fb1d9738 | 4096 | struct vmw_sw_context *sw_context = &dev_priv->ctx; |
bb1bd2f4 | 4097 | struct vmw_fence_obj *fence = NULL; |
3eab3d9e | 4098 | struct vmw_cmdbuf_header *header; |
a5020f4f | 4099 | uint32_t handle = 0; |
922ade0d | 4100 | int ret; |
c906965d SY |
4101 | int32_t out_fence_fd = -1; |
4102 | struct sync_file *sync_file = NULL; | |
9e931f2e | 4103 | DECLARE_VAL_CONTEXT(val_ctx, sw_context, 1); |
c906965d SY |
4104 | |
4105 | if (flags & DRM_VMW_EXECBUF_FLAG_EXPORT_FENCE_FD) { | |
4106 | out_fence_fd = get_unused_fd_flags(O_CLOEXEC); | |
4107 | if (out_fence_fd < 0) { | |
5724f899 | 4108 | VMW_DEBUG_USER("Failed to get a fence fd.\n"); |
c906965d SY |
4109 | return out_fence_fd; |
4110 | } | |
4111 | } | |
fb1d9738 | 4112 | |
2f633e5e | 4113 | if (throttle_us) { |
359dc60d | 4114 | VMW_DEBUG_USER("Throttling is no longer supported.\n"); |
3eab3d9e | 4115 | } |
2f633e5e | 4116 | |
3eab3d9e TH |
4117 | kernel_commands = vmw_execbuf_cmdbuf(dev_priv, user_commands, |
4118 | kernel_commands, command_size, | |
4119 | &header); | |
c906965d SY |
4120 | if (IS_ERR(kernel_commands)) { |
4121 | ret = PTR_ERR(kernel_commands); | |
4122 | goto out_free_fence_fd; | |
4123 | } | |
3eab3d9e | 4124 | |
922ade0d | 4125 | ret = mutex_lock_interruptible(&dev_priv->cmdbuf_mutex); |
3eab3d9e TH |
4126 | if (ret) { |
4127 | ret = -ERESTARTSYS; | |
4128 | goto out_free_header; | |
4129 | } | |
fb1d9738 | 4130 | |
3eab3d9e | 4131 | sw_context->kernel = false; |
922ade0d | 4132 | if (kernel_commands == NULL) { |
922ade0d TH |
4133 | ret = vmw_resize_cmd_bounce(sw_context, command_size); |
4134 | if (unlikely(ret != 0)) | |
4135 | goto out_unlock; | |
fb1d9738 | 4136 | |
680360a4 DR |
4137 | ret = copy_from_user(sw_context->cmd_bounce, user_commands, |
4138 | command_size); | |
922ade0d TH |
4139 | if (unlikely(ret != 0)) { |
4140 | ret = -EFAULT; | |
5724f899 | 4141 | VMW_DEBUG_USER("Failed copying commands.\n"); |
922ade0d TH |
4142 | goto out_unlock; |
4143 | } | |
680360a4 | 4144 | |
922ade0d | 4145 | kernel_commands = sw_context->cmd_bounce; |
680360a4 | 4146 | } else if (!header) { |
922ade0d | 4147 | sw_context->kernel = true; |
680360a4 | 4148 | } |
fb1d9738 | 4149 | |
8afa13a0 | 4150 | sw_context->filp = file_priv; |
d5bde956 | 4151 | sw_context->fp = vmw_fpriv(file_priv); |
9c079b8c | 4152 | INIT_LIST_HEAD(&sw_context->ctx_list); |
e2fa3a76 | 4153 | sw_context->cur_query_bo = dev_priv->pinned_bo; |
c0951b79 TH |
4154 | sw_context->last_query_ctx = NULL; |
4155 | sw_context->needs_post_query_barrier = false; | |
d80efd5c | 4156 | sw_context->dx_ctx_node = NULL; |
fd11a3c0 SY |
4157 | sw_context->dx_query_mob = NULL; |
4158 | sw_context->dx_query_ctx = NULL; | |
c0951b79 | 4159 | memset(sw_context->res_cache, 0, sizeof(sw_context->res_cache)); |
c0951b79 | 4160 | INIT_LIST_HEAD(&sw_context->res_relocations); |
fc18afcf | 4161 | INIT_LIST_HEAD(&sw_context->bo_relocations); |
680360a4 | 4162 | |
d80efd5c TH |
4163 | if (sw_context->staged_bindings) |
4164 | vmw_binding_state_reset(sw_context->staged_bindings); | |
4165 | ||
18e4a466 | 4166 | INIT_LIST_HEAD(&sw_context->staged_cmd_res); |
9c079b8c | 4167 | sw_context->ctx = &val_ctx; |
d80efd5c | 4168 | ret = vmw_execbuf_tie_context(dev_priv, sw_context, dx_context_handle); |
9c079b8c | 4169 | if (unlikely(ret != 0)) |
d80efd5c | 4170 | goto out_err_nores; |
d80efd5c | 4171 | |
922ade0d TH |
4172 | ret = vmw_cmd_check_all(dev_priv, sw_context, kernel_commands, |
4173 | command_size); | |
2f633e5e CL |
4174 | if (unlikely(ret != 0)) |
4175 | goto out_err_nores; | |
4176 | ||
c0951b79 TH |
4177 | ret = vmw_resources_reserve(sw_context); |
4178 | if (unlikely(ret != 0)) | |
cf5e3413 | 4179 | goto out_err_nores; |
c0951b79 | 4180 | |
9c079b8c | 4181 | ret = vmw_validation_bo_reserve(&val_ctx, true); |
fb1d9738 | 4182 | if (unlikely(ret != 0)) |
d80efd5c | 4183 | goto out_err_nores; |
fb1d9738 | 4184 | |
9c079b8c | 4185 | ret = vmw_validation_bo_validate(&val_ctx, true); |
fb1d9738 JB |
4186 | if (unlikely(ret != 0)) |
4187 | goto out_err; | |
4188 | ||
9c079b8c | 4189 | ret = vmw_validation_res_validate(&val_ctx, true); |
c0951b79 TH |
4190 | if (unlikely(ret != 0)) |
4191 | goto out_err; | |
680360a4 | 4192 | |
9c079b8c | 4193 | vmw_validation_drop_ht(&val_ctx); |
1925d456 | 4194 | |
173fb7d4 TH |
4195 | ret = mutex_lock_interruptible(&dev_priv->binding_mutex); |
4196 | if (unlikely(ret != 0)) { | |
4197 | ret = -ERESTARTSYS; | |
4198 | goto out_err; | |
4199 | } | |
4200 | ||
30f82d81 TH |
4201 | if (dev_priv->has_mob) { |
4202 | ret = vmw_rebind_contexts(sw_context); | |
4203 | if (unlikely(ret != 0)) | |
b2ad9881 | 4204 | goto out_unlock_binding; |
30f82d81 TH |
4205 | } |
4206 | ||
3eab3d9e TH |
4207 | if (!header) { |
4208 | ret = vmw_execbuf_submit_fifo(dev_priv, kernel_commands, | |
4209 | command_size, sw_context); | |
4210 | } else { | |
4211 | ret = vmw_execbuf_submit_cmdbuf(dev_priv, header, command_size, | |
4212 | sw_context); | |
4213 | header = NULL; | |
1925d456 | 4214 | } |
d80efd5c | 4215 | mutex_unlock(&dev_priv->binding_mutex); |
3eab3d9e | 4216 | if (ret) |
d80efd5c | 4217 | goto out_err; |
fb1d9738 | 4218 | |
e2fa3a76 | 4219 | vmw_query_bo_switch_commit(dev_priv, sw_context); |
680360a4 | 4220 | ret = vmw_execbuf_fence_commands(file_priv, dev_priv, &fence, |
ae2a1040 | 4221 | (user_fence_rep) ? &handle : NULL); |
fb1d9738 JB |
4222 | /* |
4223 | * This error is harmless, because if fence submission fails, | |
ae2a1040 TH |
4224 | * vmw_fifo_send_fence will sync. The error will be propagated to |
4225 | * user-space in @fence_rep | |
fb1d9738 | 4226 | */ |
fb1d9738 | 4227 | if (ret != 0) |
5724f899 | 4228 | VMW_DEBUG_USER("Fence submission error. Syncing.\n"); |
fb1d9738 | 4229 | |
9c079b8c TH |
4230 | vmw_execbuf_bindings_commit(sw_context, false); |
4231 | vmw_bind_dx_query_mob(sw_context); | |
4232 | vmw_validation_res_unreserve(&val_ctx, false); | |
173fb7d4 | 4233 | |
9c079b8c | 4234 | vmw_validation_bo_fence(sw_context->ctx, fence); |
fb1d9738 | 4235 | |
680360a4 | 4236 | if (unlikely(dev_priv->pinned_bo != NULL && !dev_priv->query_cid_valid)) |
c0951b79 TH |
4237 | __vmw_execbuf_release_pinned_bo(dev_priv, fence); |
4238 | ||
c906965d | 4239 | /* |
680360a4 DR |
4240 | * If anything fails here, give up trying to export the fence and do a |
4241 | * sync since the user mode will not be able to sync the fence itself. | |
4242 | * This ensures we are still functionally correct. | |
c906965d SY |
4243 | */ |
4244 | if (flags & DRM_VMW_EXECBUF_FLAG_EXPORT_FENCE_FD) { | |
4245 | ||
4246 | sync_file = sync_file_create(&fence->base); | |
4247 | if (!sync_file) { | |
5724f899 | 4248 | VMW_DEBUG_USER("Sync file create failed for fence\n"); |
c906965d SY |
4249 | put_unused_fd(out_fence_fd); |
4250 | out_fence_fd = -1; | |
4251 | ||
4252 | (void) vmw_fence_obj_wait(fence, false, false, | |
4253 | VMW_FENCE_WAIT_TIMEOUT); | |
a0f90c88 MK |
4254 | } |
4255 | } | |
4256 | ||
4257 | ret = vmw_execbuf_copy_fence_user(dev_priv, vmw_fpriv(file_priv), ret, | |
4258 | user_fence_rep, fence, handle, out_fence_fd); | |
4259 | ||
4260 | if (sync_file) { | |
4261 | if (ret) { | |
4262 | /* usercopy of fence failed, put the file object */ | |
4263 | fput(sync_file->file); | |
4264 | put_unused_fd(out_fence_fd); | |
c906965d SY |
4265 | } else { |
4266 | /* Link the fence with the FD created earlier */ | |
4267 | fd_install(out_fence_fd, sync_file->file); | |
0039a3b3 IF |
4268 | struct seqno_waiter_rm_context *ctx = |
4269 | kmalloc(sizeof(*ctx), GFP_KERNEL); | |
4270 | ctx->dev_priv = dev_priv; | |
4271 | vmw_seqno_waiter_add(dev_priv); | |
4272 | if (dma_fence_add_callback(&fence->base, &ctx->base, | |
4273 | seqno_waiter_rm_cb) < 0) { | |
4274 | vmw_seqno_waiter_remove(dev_priv); | |
4275 | kfree(ctx); | |
4276 | } | |
c906965d SY |
4277 | } |
4278 | } | |
4279 | ||
bb1bd2f4 JB |
4280 | /* Don't unreference when handing fence out */ |
4281 | if (unlikely(out_fence != NULL)) { | |
4282 | *out_fence = fence; | |
4283 | fence = NULL; | |
4284 | } else if (likely(fence != NULL)) { | |
ae2a1040 | 4285 | vmw_fence_obj_unreference(&fence); |
bb1bd2f4 | 4286 | } |
fb1d9738 | 4287 | |
18e4a466 | 4288 | vmw_cmdbuf_res_commit(&sw_context->staged_cmd_res); |
922ade0d | 4289 | mutex_unlock(&dev_priv->cmdbuf_mutex); |
c0951b79 TH |
4290 | |
4291 | /* | |
680360a4 DR |
4292 | * Unreference resources outside of the cmdbuf_mutex to avoid deadlocks |
4293 | * in resource destruction paths. | |
c0951b79 | 4294 | */ |
9c079b8c | 4295 | vmw_validation_unref_lists(&val_ctx); |
c0951b79 | 4296 | |
a0f90c88 | 4297 | return ret; |
922ade0d | 4298 | |
173fb7d4 TH |
4299 | out_unlock_binding: |
4300 | mutex_unlock(&dev_priv->binding_mutex); | |
fb1d9738 | 4301 | out_err: |
9c079b8c | 4302 | vmw_validation_bo_backoff(&val_ctx); |
cf5e3413 | 4303 | out_err_nores: |
9c079b8c TH |
4304 | vmw_execbuf_bindings_commit(sw_context, true); |
4305 | vmw_validation_res_unreserve(&val_ctx, true); | |
cf5e3413 TH |
4306 | vmw_resource_relocations_free(&sw_context->res_relocations); |
4307 | vmw_free_relocations(sw_context); | |
680360a4 | 4308 | if (unlikely(dev_priv->pinned_bo != NULL && !dev_priv->query_cid_valid)) |
c0951b79 | 4309 | __vmw_execbuf_release_pinned_bo(dev_priv, NULL); |
fb1d9738 | 4310 | out_unlock: |
18e4a466 | 4311 | vmw_cmdbuf_res_revert(&sw_context->staged_cmd_res); |
9c079b8c TH |
4312 | vmw_validation_drop_ht(&val_ctx); |
4313 | WARN_ON(!list_empty(&sw_context->ctx_list)); | |
fb1d9738 | 4314 | mutex_unlock(&dev_priv->cmdbuf_mutex); |
c0951b79 TH |
4315 | |
4316 | /* | |
680360a4 DR |
4317 | * Unreference resources outside of the cmdbuf_mutex to avoid deadlocks |
4318 | * in resource destruction paths. | |
c0951b79 | 4319 | */ |
9c079b8c | 4320 | vmw_validation_unref_lists(&val_ctx); |
3eab3d9e TH |
4321 | out_free_header: |
4322 | if (header) | |
4323 | vmw_cmdbuf_header_free(header); | |
c906965d SY |
4324 | out_free_fence_fd: |
4325 | if (out_fence_fd >= 0) | |
4326 | put_unused_fd(out_fence_fd); | |
c0951b79 | 4327 | |
922ade0d TH |
4328 | return ret; |
4329 | } | |
4330 | ||
e2fa3a76 TH |
4331 | /** |
4332 | * vmw_execbuf_unpin_panic - Idle the fifo and unpin the query buffer. | |
4333 | * | |
4334 | * @dev_priv: The device private structure. | |
4335 | * | |
680360a4 DR |
4336 | * This function is called to idle the fifo and unpin the query buffer if the |
4337 | * normal way to do this hits an error, which should typically be extremely | |
4338 | * rare. | |
e2fa3a76 TH |
4339 | */ |
4340 | static void vmw_execbuf_unpin_panic(struct vmw_private *dev_priv) | |
4341 | { | |
5724f899 | 4342 | VMW_DEBUG_USER("Can't unpin query buffer. Trying to recover.\n"); |
e2fa3a76 TH |
4343 | |
4344 | (void) vmw_fallback_wait(dev_priv, false, true, 0, false, 10*HZ); | |
459d0fa7 TH |
4345 | vmw_bo_pin_reserved(dev_priv->pinned_bo, false); |
4346 | if (dev_priv->dummy_query_bo_pinned) { | |
4347 | vmw_bo_pin_reserved(dev_priv->dummy_query_bo, false); | |
4348 | dev_priv->dummy_query_bo_pinned = false; | |
4349 | } | |
e2fa3a76 TH |
4350 | } |
4351 | ||
4352 | ||
4353 | /** | |
680360a4 DR |
4354 | * __vmw_execbuf_release_pinned_bo - Flush queries and unpin the pinned query |
4355 | * bo. | |
e2fa3a76 TH |
4356 | * |
4357 | * @dev_priv: The device private structure. | |
680360a4 DR |
4358 | * @fence: If non-NULL should point to a struct vmw_fence_obj issued _after_ a |
4359 | * query barrier that flushes all queries touching the current buffer pointed to | |
4360 | * by @dev_priv->pinned_bo | |
e2fa3a76 | 4361 | * |
680360a4 DR |
4362 | * This function should be used to unpin the pinned query bo, or as a query |
4363 | * barrier when we need to make sure that all queries have finished before the | |
4364 | * next fifo command. (For example on hardware context destructions where the | |
4365 | * hardware may otherwise leak unfinished queries). | |
e2fa3a76 | 4366 | * |
680360a4 DR |
4367 | * This function does not return any failure codes, but make attempts to do safe |
4368 | * unpinning in case of errors. | |
e2fa3a76 | 4369 | * |
680360a4 DR |
4370 | * The function will synchronize on the previous query barrier, and will thus |
4371 | * not finish until that barrier has executed. | |
c0951b79 | 4372 | * |
680360a4 DR |
4373 | * the @dev_priv->cmdbuf_mutex needs to be held by the current thread before |
4374 | * calling this function. | |
e2fa3a76 | 4375 | */ |
c0951b79 TH |
4376 | void __vmw_execbuf_release_pinned_bo(struct vmw_private *dev_priv, |
4377 | struct vmw_fence_obj *fence) | |
e2fa3a76 TH |
4378 | { |
4379 | int ret = 0; | |
c0951b79 | 4380 | struct vmw_fence_obj *lfence = NULL; |
9c079b8c | 4381 | DECLARE_VAL_CONTEXT(val_ctx, NULL, 0); |
e2fa3a76 TH |
4382 | |
4383 | if (dev_priv->pinned_bo == NULL) | |
4384 | goto out_unlock; | |
4385 | ||
39985eea ZR |
4386 | vmw_bo_placement_set(dev_priv->pinned_bo, |
4387 | VMW_BO_DOMAIN_GMR | VMW_BO_DOMAIN_VRAM, | |
4388 | VMW_BO_DOMAIN_GMR | VMW_BO_DOMAIN_VRAM); | |
4389 | ret = vmw_validation_add_bo(&val_ctx, dev_priv->pinned_bo); | |
9c079b8c TH |
4390 | if (ret) |
4391 | goto out_no_reserve; | |
e2fa3a76 | 4392 | |
39985eea ZR |
4393 | vmw_bo_placement_set(dev_priv->dummy_query_bo, |
4394 | VMW_BO_DOMAIN_GMR | VMW_BO_DOMAIN_VRAM, | |
4395 | VMW_BO_DOMAIN_GMR | VMW_BO_DOMAIN_VRAM); | |
4396 | ret = vmw_validation_add_bo(&val_ctx, dev_priv->dummy_query_bo); | |
9c079b8c TH |
4397 | if (ret) |
4398 | goto out_no_reserve; | |
e2fa3a76 | 4399 | |
9c079b8c TH |
4400 | ret = vmw_validation_bo_reserve(&val_ctx, false); |
4401 | if (ret) | |
e2fa3a76 | 4402 | goto out_no_reserve; |
e2fa3a76 | 4403 | |
c0951b79 TH |
4404 | if (dev_priv->query_cid_valid) { |
4405 | BUG_ON(fence != NULL); | |
8426ed9c | 4406 | ret = vmw_cmd_emit_dummy_query(dev_priv, dev_priv->query_cid); |
9c079b8c | 4407 | if (ret) |
c0951b79 | 4408 | goto out_no_emit; |
c0951b79 | 4409 | dev_priv->query_cid_valid = false; |
e2fa3a76 TH |
4410 | } |
4411 | ||
459d0fa7 TH |
4412 | vmw_bo_pin_reserved(dev_priv->pinned_bo, false); |
4413 | if (dev_priv->dummy_query_bo_pinned) { | |
4414 | vmw_bo_pin_reserved(dev_priv->dummy_query_bo, false); | |
4415 | dev_priv->dummy_query_bo_pinned = false; | |
4416 | } | |
c0951b79 TH |
4417 | if (fence == NULL) { |
4418 | (void) vmw_execbuf_fence_commands(NULL, dev_priv, &lfence, | |
4419 | NULL); | |
4420 | fence = lfence; | |
4421 | } | |
9c079b8c | 4422 | vmw_validation_bo_fence(&val_ctx, fence); |
c0951b79 TH |
4423 | if (lfence != NULL) |
4424 | vmw_fence_obj_unreference(&lfence); | |
e2fa3a76 | 4425 | |
9c079b8c | 4426 | vmw_validation_unref_lists(&val_ctx); |
f1d34bfd | 4427 | vmw_bo_unreference(&dev_priv->pinned_bo); |
680360a4 | 4428 | |
e2fa3a76 | 4429 | out_unlock: |
e2fa3a76 | 4430 | return; |
e2fa3a76 | 4431 | out_no_emit: |
9c079b8c | 4432 | vmw_validation_bo_backoff(&val_ctx); |
e2fa3a76 | 4433 | out_no_reserve: |
9c079b8c TH |
4434 | vmw_validation_unref_lists(&val_ctx); |
4435 | vmw_execbuf_unpin_panic(dev_priv); | |
f1d34bfd | 4436 | vmw_bo_unreference(&dev_priv->pinned_bo); |
c0951b79 TH |
4437 | } |
4438 | ||
4439 | /** | |
680360a4 | 4440 | * vmw_execbuf_release_pinned_bo - Flush queries and unpin the pinned query bo. |
c0951b79 TH |
4441 | * |
4442 | * @dev_priv: The device private structure. | |
4443 | * | |
680360a4 DR |
4444 | * This function should be used to unpin the pinned query bo, or as a query |
4445 | * barrier when we need to make sure that all queries have finished before the | |
4446 | * next fifo command. (For example on hardware context destructions where the | |
4447 | * hardware may otherwise leak unfinished queries). | |
c0951b79 | 4448 | * |
680360a4 DR |
4449 | * This function does not return any failure codes, but make attempts to do safe |
4450 | * unpinning in case of errors. | |
c0951b79 | 4451 | * |
680360a4 DR |
4452 | * The function will synchronize on the previous query barrier, and will thus |
4453 | * not finish until that barrier has executed. | |
c0951b79 TH |
4454 | */ |
4455 | void vmw_execbuf_release_pinned_bo(struct vmw_private *dev_priv) | |
4456 | { | |
4457 | mutex_lock(&dev_priv->cmdbuf_mutex); | |
4458 | if (dev_priv->query_cid_valid) | |
4459 | __vmw_execbuf_release_pinned_bo(dev_priv, NULL); | |
e2fa3a76 TH |
4460 | mutex_unlock(&dev_priv->cmdbuf_mutex); |
4461 | } | |
4462 | ||
cbfbe47f EV |
4463 | int vmw_execbuf_ioctl(struct drm_device *dev, void *data, |
4464 | struct drm_file *file_priv) | |
922ade0d TH |
4465 | { |
4466 | struct vmw_private *dev_priv = vmw_priv(dev); | |
cbfbe47f | 4467 | struct drm_vmw_execbuf_arg *arg = data; |
922ade0d | 4468 | int ret; |
58585116 | 4469 | struct dma_fence *in_fence = NULL; |
d80efd5c | 4470 | |
7a7a933e MK |
4471 | MKS_STAT_TIME_DECL(MKSSTAT_KERN_EXECBUF); |
4472 | MKS_STAT_TIME_PUSH(MKSSTAT_KERN_EXECBUF); | |
4473 | ||
922ade0d | 4474 | /* |
680360a4 | 4475 | * Extend the ioctl argument while maintaining backwards compatibility: |
cbfbe47f EV |
4476 | * We take different code paths depending on the value of arg->version. |
4477 | * | |
4478 | * Note: The ioctl argument is extended and zeropadded by core DRM. | |
922ade0d | 4479 | */ |
cbfbe47f EV |
4480 | if (unlikely(arg->version > DRM_VMW_EXECBUF_VERSION || |
4481 | arg->version == 0)) { | |
5724f899 | 4482 | VMW_DEBUG_USER("Incorrect execbuf version.\n"); |
7a7a933e MK |
4483 | ret = -EINVAL; |
4484 | goto mksstats_out; | |
922ade0d TH |
4485 | } |
4486 | ||
cbfbe47f | 4487 | switch (arg->version) { |
d80efd5c | 4488 | case 1: |
cbfbe47f EV |
4489 | /* For v1 core DRM have extended + zeropadded the data */ |
4490 | arg->context_handle = (uint32_t) -1; | |
d80efd5c TH |
4491 | break; |
4492 | case 2: | |
d80efd5c | 4493 | default: |
cbfbe47f | 4494 | /* For v2 and later core DRM would have correctly copied it */ |
d80efd5c TH |
4495 | break; |
4496 | } | |
4497 | ||
58585116 | 4498 | /* If imported a fence FD from elsewhere, then wait on it */ |
cbfbe47f EV |
4499 | if (arg->flags & DRM_VMW_EXECBUF_FLAG_IMPORT_FENCE_FD) { |
4500 | in_fence = sync_file_get_fence(arg->imported_fence_fd); | |
58585116 SY |
4501 | |
4502 | if (!in_fence) { | |
5724f899 | 4503 | VMW_DEBUG_USER("Cannot get imported fence\n"); |
7a7a933e MK |
4504 | ret = -EINVAL; |
4505 | goto mksstats_out; | |
58585116 SY |
4506 | } |
4507 | ||
3f1a31ff | 4508 | ret = dma_fence_wait(in_fence, true); |
58585116 SY |
4509 | if (ret) |
4510 | goto out; | |
4511 | } | |
4512 | ||
922ade0d | 4513 | ret = vmw_execbuf_process(file_priv, dev_priv, |
cbfbe47f EV |
4514 | (void __user *)(unsigned long)arg->commands, |
4515 | NULL, arg->command_size, arg->throttle_us, | |
4516 | arg->context_handle, | |
4517 | (void __user *)(unsigned long)arg->fence_rep, | |
4518 | NULL, arg->flags); | |
680360a4 | 4519 | |
922ade0d | 4520 | if (unlikely(ret != 0)) |
58585116 | 4521 | goto out; |
922ade0d | 4522 | |
58585116 SY |
4523 | out: |
4524 | if (in_fence) | |
4525 | dma_fence_put(in_fence); | |
7a7a933e MK |
4526 | |
4527 | mksstats_out: | |
4528 | MKS_STAT_TIME_POP(MKSSTAT_KERN_EXECBUF); | |
58585116 | 4529 | return ret; |
fb1d9738 | 4530 | } |