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lguest: Read offset of device_cap later
[linux-2.6-block.git] / drivers / gpu / drm / vmwgfx / vmwgfx_drv.c
CommitLineData
fb1d9738
JB		 1/**************************************************************************
2 *
f9217913 3 * Copyright © 2009-2016 VMware, Inc., Palo Alto, CA., USA
fb1d9738
JB		 4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
e0cd3608 27#include <linux/module.h>
96c5d076 28#include <linux/console.h>
fb1d9738 29
760285e7 30#include <drm/drmP.h>
fb1d9738 31#include "vmwgfx_drv.h"
d80efd5c 32#include "vmwgfx_binding.h"
760285e7
DH		 33#include <drm/ttm/ttm_placement.h>
34#include <drm/ttm/ttm_bo_driver.h>
35#include <drm/ttm/ttm_object.h>
36#include <drm/ttm/ttm_module.h>
d92d9851 37#include <linux/dma_remapping.h>
fb1d9738
JB		 38
39#define VMWGFX_DRIVER_NAME "vmwgfx"
40#define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
41#define VMWGFX_CHIP_SVGAII 0
42#define VMW_FB_RESERVATION 0
43
eb4f923b
JB		 44#define VMW_MIN_INITIAL_WIDTH 800
45#define VMW_MIN_INITIAL_HEIGHT 600
46
f9217913
SY		 47#ifndef VMWGFX_GIT_VERSION
48#define VMWGFX_GIT_VERSION "Unknown"
49#endif
50
51#define VMWGFX_REPO "In Tree"
52
eb4f923b 53
fb1d9738
JB		 54/**
55 * Fully encoded drm commands. Might move to vmw_drm.h
56 */
57
58#define DRM_IOCTL_VMW_GET_PARAM \
59 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
60 struct drm_vmw_getparam_arg)
61#define DRM_IOCTL_VMW_ALLOC_DMABUF \
62 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
63 union drm_vmw_alloc_dmabuf_arg)
64#define DRM_IOCTL_VMW_UNREF_DMABUF \
65 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
66 struct drm_vmw_unref_dmabuf_arg)
67#define DRM_IOCTL_VMW_CURSOR_BYPASS \
68 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
69 struct drm_vmw_cursor_bypass_arg)
70
71#define DRM_IOCTL_VMW_CONTROL_STREAM \
72 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
73 struct drm_vmw_control_stream_arg)
74#define DRM_IOCTL_VMW_CLAIM_STREAM \
75 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
76 struct drm_vmw_stream_arg)
77#define DRM_IOCTL_VMW_UNREF_STREAM \
78 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
79 struct drm_vmw_stream_arg)
80
81#define DRM_IOCTL_VMW_CREATE_CONTEXT \
82 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
83 struct drm_vmw_context_arg)
84#define DRM_IOCTL_VMW_UNREF_CONTEXT \
85 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
86 struct drm_vmw_context_arg)
87#define DRM_IOCTL_VMW_CREATE_SURFACE \
88 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
89 union drm_vmw_surface_create_arg)
90#define DRM_IOCTL_VMW_UNREF_SURFACE \
91 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
92 struct drm_vmw_surface_arg)
93#define DRM_IOCTL_VMW_REF_SURFACE \
94 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
95 union drm_vmw_surface_reference_arg)
96#define DRM_IOCTL_VMW_EXECBUF \
97 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
98 struct drm_vmw_execbuf_arg)
ae2a1040
TH		 99#define DRM_IOCTL_VMW_GET_3D_CAP \
100 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
101 struct drm_vmw_get_3d_cap_arg)
fb1d9738
JB		 102#define DRM_IOCTL_VMW_FENCE_WAIT \
103 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
104 struct drm_vmw_fence_wait_arg)
ae2a1040
TH		 105#define DRM_IOCTL_VMW_FENCE_SIGNALED \
106 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
107 struct drm_vmw_fence_signaled_arg)
108#define DRM_IOCTL_VMW_FENCE_UNREF \
109 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
110 struct drm_vmw_fence_arg)
57c5ee79
TH		 111#define DRM_IOCTL_VMW_FENCE_EVENT \
112 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
113 struct drm_vmw_fence_event_arg)
2fcd5a73
JB		 114#define DRM_IOCTL_VMW_PRESENT \
115 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
116 struct drm_vmw_present_arg)
117#define DRM_IOCTL_VMW_PRESENT_READBACK \
118 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
119 struct drm_vmw_present_readback_arg)
cd2b89e7
TH		 120#define DRM_IOCTL_VMW_UPDATE_LAYOUT \
121 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
122 struct drm_vmw_update_layout_arg)
c74c162f
TH		 123#define DRM_IOCTL_VMW_CREATE_SHADER \
124 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \
125 struct drm_vmw_shader_create_arg)
126#define DRM_IOCTL_VMW_UNREF_SHADER \
127 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \
128 struct drm_vmw_shader_arg)
a97e2192
TH		 129#define DRM_IOCTL_VMW_GB_SURFACE_CREATE \
130 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \
131 union drm_vmw_gb_surface_create_arg)
132#define DRM_IOCTL_VMW_GB_SURFACE_REF \
133 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \
134 union drm_vmw_gb_surface_reference_arg)
1d7a5cbf
TH		 135#define DRM_IOCTL_VMW_SYNCCPU \
136 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \
137 struct drm_vmw_synccpu_arg)
d80efd5c
TH		 138#define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \
139 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \
140 struct drm_vmw_context_arg)
fb1d9738
JB		 141
142/**
143 * The core DRM version of this macro doesn't account for
144 * DRM_COMMAND_BASE.
145 */
146
147#define VMW_IOCTL_DEF(ioctl, func, flags) \
7e7392a6 148 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func}
fb1d9738
JB		 149
150/**
151 * Ioctl definitions.
152 */
153
baa70943 154static const struct drm_ioctl_desc vmw_ioctls[] = {
1b2f1489 155 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
f8c47144 156 DRM_AUTH | DRM_RENDER_ALLOW),
1b2f1489 157 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
f8c47144 158 DRM_AUTH | DRM_RENDER_ALLOW),
1b2f1489 159 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
f8c47144 160 DRM_RENDER_ALLOW),
1b2f1489 161 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
e1f78003 162 vmw_kms_cursor_bypass_ioctl,
f8c47144 163 DRM_MASTER | DRM_CONTROL_ALLOW),
fb1d9738 164
1b2f1489 165 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
f8c47144 166 DRM_MASTER | DRM_CONTROL_ALLOW),
1b2f1489 167 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
f8c47144 168 DRM_MASTER | DRM_CONTROL_ALLOW),
1b2f1489 169 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
f8c47144 170 DRM_MASTER | DRM_CONTROL_ALLOW),
fb1d9738 171
1b2f1489 172 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
f8c47144 173 DRM_AUTH | DRM_RENDER_ALLOW),
1b2f1489 174 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
f8c47144 175 DRM_RENDER_ALLOW),
1b2f1489 176 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
f8c47144 177 DRM_AUTH | DRM_RENDER_ALLOW),
1b2f1489 178 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
f8c47144 179 DRM_RENDER_ALLOW),
1b2f1489 180 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
f8c47144
DV		 181 DRM_AUTH | DRM_RENDER_ALLOW),
182 VMW_IOCTL_DEF(VMW_EXECBUF, NULL, DRM_AUTH |
d80efd5c 183 DRM_RENDER_ALLOW),
ae2a1040 184 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
f8c47144 185 DRM_RENDER_ALLOW),
ae2a1040
TH		 186 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
187 vmw_fence_obj_signaled_ioctl,
f8c47144 188 DRM_RENDER_ALLOW),
ae2a1040 189 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
f8c47144 190 DRM_RENDER_ALLOW),
03f80263 191 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl,
f8c47144 192 DRM_AUTH | DRM_RENDER_ALLOW),
f63f6a59 193 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
f8c47144 194 DRM_AUTH | DRM_RENDER_ALLOW),
2fcd5a73
JB		 195
196 /* these allow direct access to the framebuffers mark as master only */
197 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
f8c47144 198 DRM_MASTER | DRM_AUTH),
2fcd5a73
JB		 199 VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
200 vmw_present_readback_ioctl,
f8c47144 201 DRM_MASTER | DRM_AUTH),
cd2b89e7
TH		 202 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
203 vmw_kms_update_layout_ioctl,
b0dc6d43 204 DRM_MASTER | DRM_CONTROL_ALLOW),
c74c162f
TH		 205 VMW_IOCTL_DEF(VMW_CREATE_SHADER,
206 vmw_shader_define_ioctl,
f8c47144 207 DRM_AUTH | DRM_RENDER_ALLOW),
c74c162f
TH		 208 VMW_IOCTL_DEF(VMW_UNREF_SHADER,
209 vmw_shader_destroy_ioctl,
f8c47144 210 DRM_RENDER_ALLOW),
a97e2192
TH		 211 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
212 vmw_gb_surface_define_ioctl,
f8c47144 213 DRM_AUTH | DRM_RENDER_ALLOW),
a97e2192
TH		 214 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
215 vmw_gb_surface_reference_ioctl,
f8c47144 216 DRM_AUTH | DRM_RENDER_ALLOW),
1d7a5cbf
TH		 217 VMW_IOCTL_DEF(VMW_SYNCCPU,
218 vmw_user_dmabuf_synccpu_ioctl,
f8c47144 219 DRM_RENDER_ALLOW),
d80efd5c
TH		 220 VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT,
221 vmw_extended_context_define_ioctl,
f8c47144 222 DRM_AUTH | DRM_RENDER_ALLOW),
fb1d9738
JB		 223};
224
225static struct pci_device_id vmw_pci_id_list[] = {
226 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
227 {0, 0, 0}
228};
c4903429 229MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
fb1d9738 230
5d2afab9 231static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
d92d9851
TH		 232static int vmw_force_iommu;
233static int vmw_restrict_iommu;
234static int vmw_force_coherent;
0d00c488 235static int vmw_restrict_dma_mask;
fb1d9738
JB		 236
237static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
238static void vmw_master_init(struct vmw_master *);
d9f36a00
TH		 239static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
240 void *ptr);
fb1d9738 241
30c78bb8
TH		 242MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
243module_param_named(enable_fbdev, enable_fbdev, int, 0600);
d92d9851
TH		 244MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
245module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
246MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
247module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
248MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
249module_param_named(force_coherent, vmw_force_coherent, int, 0600);
0d00c488
TH		 250MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
251module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
d92d9851 252
30c78bb8 253
fb1d9738
JB		 254static void vmw_print_capabilities(uint32_t capabilities)
255{
256 DRM_INFO("Capabilities:\n");
257 if (capabilities & SVGA_CAP_RECT_COPY)
258 DRM_INFO(" Rect copy.\n");
259 if (capabilities & SVGA_CAP_CURSOR)
260 DRM_INFO(" Cursor.\n");
261 if (capabilities & SVGA_CAP_CURSOR_BYPASS)
262 DRM_INFO(" Cursor bypass.\n");
263 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
264 DRM_INFO(" Cursor bypass 2.\n");
265 if (capabilities & SVGA_CAP_8BIT_EMULATION)
266 DRM_INFO(" 8bit emulation.\n");
267 if (capabilities & SVGA_CAP_ALPHA_CURSOR)
268 DRM_INFO(" Alpha cursor.\n");
269 if (capabilities & SVGA_CAP_3D)
270 DRM_INFO(" 3D.\n");
271 if (capabilities & SVGA_CAP_EXTENDED_FIFO)
272 DRM_INFO(" Extended Fifo.\n");
273 if (capabilities & SVGA_CAP_MULTIMON)
274 DRM_INFO(" Multimon.\n");
275 if (capabilities & SVGA_CAP_PITCHLOCK)
276 DRM_INFO(" Pitchlock.\n");
277 if (capabilities & SVGA_CAP_IRQMASK)
278 DRM_INFO(" Irq mask.\n");
279 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
280 DRM_INFO(" Display Topology.\n");
281 if (capabilities & SVGA_CAP_GMR)
282 DRM_INFO(" GMR.\n");
283 if (capabilities & SVGA_CAP_TRACES)
284 DRM_INFO(" Traces.\n");
dcca2862
TH		 285 if (capabilities & SVGA_CAP_GMR2)
286 DRM_INFO(" GMR2.\n");
287 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
288 DRM_INFO(" Screen Object 2.\n");
c1234db7
TH		 289 if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
290 DRM_INFO(" Command Buffers.\n");
291 if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
292 DRM_INFO(" Command Buffers 2.\n");
293 if (capabilities & SVGA_CAP_GBOBJECTS)
294 DRM_INFO(" Guest Backed Resources.\n");
8ce75f8a
SY		 295 if (capabilities & SVGA_CAP_DX)
296 DRM_INFO(" DX Features.\n");
fb1d9738
JB		 297}
298
e2fa3a76 299/**
4b9e45e6 300 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
e2fa3a76 301 *
4b9e45e6 302 * @dev_priv: A device private structure.
e2fa3a76 303 *
4b9e45e6
TH		 304 * This function creates a small buffer object that holds the query
305 * result for dummy queries emitted as query barriers.
306 * The function will then map the first page and initialize a pending
307 * occlusion query result structure, Finally it will unmap the buffer.
308 * No interruptible waits are done within this function.
e2fa3a76 309 *
4b9e45e6 310 * Returns an error if bo creation or initialization fails.
e2fa3a76 311 */
4b9e45e6 312static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
e2fa3a76 313{
4b9e45e6 314 int ret;
459d0fa7 315 struct vmw_dma_buffer *vbo;
e2fa3a76
TH		 316 struct ttm_bo_kmap_obj map;
317 volatile SVGA3dQueryResult *result;
318 bool dummy;
e2fa3a76 319
4b9e45e6 320 /*
459d0fa7 321 * Create the vbo as pinned, so that a tryreserve will
4b9e45e6
TH		 322 * immediately succeed. This is because we're the only
323 * user of the bo currently.
324 */
459d0fa7
TH		 325 vbo = kzalloc(sizeof(*vbo), GFP_KERNEL);
326 if (!vbo)
327 return -ENOMEM;
4b9e45e6 328
459d0fa7
TH		 329 ret = vmw_dmabuf_init(dev_priv, vbo, PAGE_SIZE,
330 &vmw_sys_ne_placement, false,
331 &vmw_dmabuf_bo_free);
e2fa3a76 332 if (unlikely(ret != 0))
4b9e45e6
TH		 333 return ret;
334
dfd5e50e 335 ret = ttm_bo_reserve(&vbo->base, false, true, NULL);
4b9e45e6 336 BUG_ON(ret != 0);
459d0fa7 337 vmw_bo_pin_reserved(vbo, true);
e2fa3a76 338
459d0fa7 339 ret = ttm_bo_kmap(&vbo->base, 0, 1, &map);
e2fa3a76
TH		 340 if (likely(ret == 0)) {
341 result = ttm_kmap_obj_virtual(&map, &dummy);
342 result->totalSize = sizeof(*result);
343 result->state = SVGA3D_QUERYSTATE_PENDING;
344 result->result32 = 0xff;
345 ttm_bo_kunmap(&map);
4b9e45e6 346 }
459d0fa7
TH		 347 vmw_bo_pin_reserved(vbo, false);
348 ttm_bo_unreserve(&vbo->base);
e2fa3a76 349
4b9e45e6
TH		 350 if (unlikely(ret != 0)) {
351 DRM_ERROR("Dummy query buffer map failed.\n");
459d0fa7 352 vmw_dmabuf_unreference(&vbo);
4b9e45e6 353 } else
459d0fa7 354 dev_priv->dummy_query_bo = vbo;
e2fa3a76 355
4b9e45e6 356 return ret;
e2fa3a76
TH		 357}
358
153b3d5b
TH		 359/**
360 * vmw_request_device_late - Perform late device setup
361 *
362 * @dev_priv: Pointer to device private.
363 *
364 * This function performs setup of otables and enables large command
365 * buffer submission. These tasks are split out to a separate function
366 * because it reverts vmw_release_device_early and is intended to be used
367 * by an error path in the hibernation code.
368 */
369static int vmw_request_device_late(struct vmw_private *dev_priv)
fb1d9738
JB		 370{
371 int ret;
372
3530bdc3
TH		 373 if (dev_priv->has_mob) {
374 ret = vmw_otables_setup(dev_priv);
375 if (unlikely(ret != 0)) {
376 DRM_ERROR("Unable to initialize "
377 "guest Memory OBjects.\n");
153b3d5b 378 return ret;
3530bdc3
TH		 379 }
380 }
153b3d5b 381
3eab3d9e
TH		 382 if (dev_priv->cman) {
383 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman,
384 256*4096, 2*4096);
385 if (ret) {
386 struct vmw_cmdbuf_man *man = dev_priv->cman;
387
388 dev_priv->cman = NULL;
389 vmw_cmdbuf_man_destroy(man);
390 }
391 }
392
153b3d5b
TH		 393 return 0;
394}
395
fb1d9738
JB		 396static int vmw_request_device(struct vmw_private *dev_priv)
397{
398 int ret;
399
fb1d9738
JB		 400 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
401 if (unlikely(ret != 0)) {
402 DRM_ERROR("Unable to initialize FIFO.\n");
403 return ret;
404 }
ae2a1040 405 vmw_fence_fifo_up(dev_priv->fman);
3eab3d9e 406 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv);
d80efd5c 407 if (IS_ERR(dev_priv->cman)) {
3eab3d9e 408 dev_priv->cman = NULL;
d80efd5c 409 dev_priv->has_dx = false;
3530bdc3 410 }
153b3d5b
TH		 411
412 ret = vmw_request_device_late(dev_priv);
413 if (ret)
414 goto out_no_mob;
415
e2fa3a76
TH		 416 ret = vmw_dummy_query_bo_create(dev_priv);
417 if (unlikely(ret != 0))
418 goto out_no_query_bo;
fb1d9738
JB		 419
420 return 0;
e2fa3a76
TH		 421
422out_no_query_bo:
3eab3d9e
TH		 423 if (dev_priv->cman)
424 vmw_cmdbuf_remove_pool(dev_priv->cman);
153b3d5b
TH		 425 if (dev_priv->has_mob) {
426 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
3530bdc3 427 vmw_otables_takedown(dev_priv);
153b3d5b 428 }
3eab3d9e
TH		 429 if (dev_priv->cman)
430 vmw_cmdbuf_man_destroy(dev_priv->cman);
3530bdc3 431out_no_mob:
e2fa3a76
TH		 432 vmw_fence_fifo_down(dev_priv->fman);
433 vmw_fifo_release(dev_priv, &dev_priv->fifo);
434 return ret;
fb1d9738
JB		 435}
436
153b3d5b
TH		 437/**
438 * vmw_release_device_early - Early part of fifo takedown.
439 *
440 * @dev_priv: Pointer to device private struct.
441 *
442 * This is the first part of command submission takedown, to be called before
443 * buffer management is taken down.
444 */
445static void vmw_release_device_early(struct vmw_private *dev_priv)
fb1d9738 446{
e2fa3a76
TH		 447 /*
448 * Previous destructions should've released
449 * the pinned bo.
450 */
451
452 BUG_ON(dev_priv->pinned_bo != NULL);
453
459d0fa7 454 vmw_dmabuf_unreference(&dev_priv->dummy_query_bo);
3eab3d9e
TH		 455 if (dev_priv->cman)
456 vmw_cmdbuf_remove_pool(dev_priv->cman);
30c78bb8 457
153b3d5b
TH		 458 if (dev_priv->has_mob) {
459 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
3530bdc3 460 vmw_otables_takedown(dev_priv);
30c78bb8 461 }
fb1d9738
JB		 462}
463
05730b32 464/**
153b3d5b
TH		 465 * vmw_release_device_late - Late part of fifo takedown.
466 *
467 * @dev_priv: Pointer to device private struct.
468 *
469 * This is the last part of the command submission takedown, to be called when
470 * command submission is no longer needed. It may wait on pending fences.
05730b32 471 */
153b3d5b 472static void vmw_release_device_late(struct vmw_private *dev_priv)
30c78bb8 473{
153b3d5b 474 vmw_fence_fifo_down(dev_priv->fman);
3eab3d9e
TH		 475 if (dev_priv->cman)
476 vmw_cmdbuf_man_destroy(dev_priv->cman);
30c78bb8 477
153b3d5b 478 vmw_fifo_release(dev_priv, &dev_priv->fifo);
30c78bb8
TH		 479}
480
eb4f923b
JB		 481/**
482 * Sets the initial_[width|height] fields on the given vmw_private.
483 *
484 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
67d4a87b
TH		 485 * clamping the value to fb_max_[width|height] fields and the
486 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
487 * If the values appear to be invalid, set them to
eb4f923b
JB		 488 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
489 */
490static void vmw_get_initial_size(struct vmw_private *dev_priv)
491{
492 uint32_t width;
493 uint32_t height;
494
495 width = vmw_read(dev_priv, SVGA_REG_WIDTH);
496 height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
497
498 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
eb4f923b 499 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
67d4a87b
TH		 500
501 if (width > dev_priv->fb_max_width ||
502 height > dev_priv->fb_max_height) {
503
504 /*
505 * This is a host error and shouldn't occur.
506 */
507
508 width = VMW_MIN_INITIAL_WIDTH;
509 height = VMW_MIN_INITIAL_HEIGHT;
510 }
eb4f923b
JB		 511
512 dev_priv->initial_width = width;
513 dev_priv->initial_height = height;
514}
515
d92d9851
TH		 516/**
517 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
518 * system.
519 *
520 * @dev_priv: Pointer to a struct vmw_private
521 *
522 * This functions tries to determine the IOMMU setup and what actions
523 * need to be taken by the driver to make system pages visible to the
524 * device.
525 * If this function decides that DMA is not possible, it returns -EINVAL.
526 * The driver may then try to disable features of the device that require
527 * DMA.
528 */
529static int vmw_dma_select_mode(struct vmw_private *dev_priv)
530{
d92d9851
TH		 531 static const char *names[vmw_dma_map_max] = {
532 [vmw_dma_phys] = "Using physical TTM page addresses.",
533 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
534 [vmw_dma_map_populate] = "Keeping DMA mappings.",
535 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
e14cd953
TH		 536#ifdef CONFIG_X86
537 const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev);
d92d9851
TH		 538
539#ifdef CONFIG_INTEL_IOMMU
540 if (intel_iommu_enabled) {
541 dev_priv->map_mode = vmw_dma_map_populate;
542 goto out_fixup;
543 }
544#endif
545
546 if (!(vmw_force_iommu || vmw_force_coherent)) {
547 dev_priv->map_mode = vmw_dma_phys;
548 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
549 return 0;
550 }
551
552 dev_priv->map_mode = vmw_dma_map_populate;
553
554 if (dma_ops->sync_single_for_cpu)
555 dev_priv->map_mode = vmw_dma_alloc_coherent;
556#ifdef CONFIG_SWIOTLB
557 if (swiotlb_nr_tbl() == 0)
558 dev_priv->map_mode = vmw_dma_map_populate;
559#endif
560
21136946 561#ifdef CONFIG_INTEL_IOMMU
d92d9851 562out_fixup:
21136946 563#endif
d92d9851
TH		 564 if (dev_priv->map_mode == vmw_dma_map_populate &&
565 vmw_restrict_iommu)
566 dev_priv->map_mode = vmw_dma_map_bind;
567
568 if (vmw_force_coherent)
569 dev_priv->map_mode = vmw_dma_alloc_coherent;
570
571#if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU)
572 /*
573 * No coherent page pool
574 */
575 if (dev_priv->map_mode == vmw_dma_alloc_coherent)
576 return -EINVAL;
577#endif
578
e14cd953
TH		 579#else /* CONFIG_X86 */
580 dev_priv->map_mode = vmw_dma_map_populate;
581#endif /* CONFIG_X86 */
582
d92d9851
TH		 583 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
584
585 return 0;
586}
587
0d00c488
TH		 588/**
589 * vmw_dma_masks - set required page- and dma masks
590 *
591 * @dev: Pointer to struct drm-device
592 *
593 * With 32-bit we can only handle 32 bit PFNs. Optionally set that
594 * restriction also for 64-bit systems.
595 */
596#ifdef CONFIG_INTEL_IOMMU
597static int vmw_dma_masks(struct vmw_private *dev_priv)
598{
599 struct drm_device *dev = dev_priv->dev;
600
601 if (intel_iommu_enabled &&
602 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
603 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
604 return dma_set_mask(dev->dev, DMA_BIT_MASK(44));
605 }
606 return 0;
607}
608#else
609static int vmw_dma_masks(struct vmw_private *dev_priv)
610{
611 return 0;
612}
613#endif
614
fb1d9738
JB		 615static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
616{
617 struct vmw_private *dev_priv;
618 int ret;
c188660f 619 uint32_t svga_id;
c0951b79 620 enum vmw_res_type i;
d92d9851 621 bool refuse_dma = false;
f9217913 622 char host_log[100] = {0};
fb1d9738
JB		 623
624 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
625 if (unlikely(dev_priv == NULL)) {
626 DRM_ERROR("Failed allocating a device private struct.\n");
627 return -ENOMEM;
628 }
fb1d9738 629
466e69b8
DA		 630 pci_set_master(dev->pdev);
631
fb1d9738
JB		 632 dev_priv->dev = dev;
633 dev_priv->vmw_chipset = chipset;
6bcd8d3c 634 dev_priv->last_read_seqno = (uint32_t) -100;
fb1d9738 635 mutex_init(&dev_priv->cmdbuf_mutex);
30c78bb8 636 mutex_init(&dev_priv->release_mutex);
173fb7d4 637 mutex_init(&dev_priv->binding_mutex);
93cd1681 638 mutex_init(&dev_priv->global_kms_state_mutex);
fb1d9738 639 rwlock_init(&dev_priv->resource_lock);
294adf7d 640 ttm_lock_init(&dev_priv->reservation_sem);
496eb6fd
TH		 641 spin_lock_init(&dev_priv->hw_lock);
642 spin_lock_init(&dev_priv->waiter_lock);
643 spin_lock_init(&dev_priv->cap_lock);
153b3d5b 644 spin_lock_init(&dev_priv->svga_lock);
c0951b79
TH		 645
646 for (i = vmw_res_context; i < vmw_res_max; ++i) {
647 idr_init(&dev_priv->res_idr[i]);
648 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
649 }
650
fb1d9738
JB		 651 mutex_init(&dev_priv->init_mutex);
652 init_waitqueue_head(&dev_priv->fence_queue);
653 init_waitqueue_head(&dev_priv->fifo_queue);
4f73a96b 654 dev_priv->fence_queue_waiters = 0;
d2e8851a 655 dev_priv->fifo_queue_waiters = 0;
c0951b79 656
5bb39e81 657 dev_priv->used_memory_size = 0;
fb1d9738
JB		 658
659 dev_priv->io_start = pci_resource_start(dev->pdev, 0);
660 dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
661 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
662
30c78bb8
TH		 663 dev_priv->enable_fb = enable_fbdev;
664
c188660f
PH		 665 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
666 svga_id = vmw_read(dev_priv, SVGA_REG_ID);
667 if (svga_id != SVGA_ID_2) {
668 ret = -ENOSYS;
49625904 669 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
c188660f
PH		 670 goto out_err0;
671 }
672
fb1d9738 673 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
d92d9851
TH		 674 ret = vmw_dma_select_mode(dev_priv);
675 if (unlikely(ret != 0)) {
676 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
677 refuse_dma = true;
678 }
fb1d9738 679
5bb39e81
TH		 680 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
681 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
682 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
683 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
eb4f923b
JB		 684
685 vmw_get_initial_size(dev_priv);
686
0d00c488 687 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
fb1d9738
JB		 688 dev_priv->max_gmr_ids =
689 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
fb17f189
TH		 690 dev_priv->max_gmr_pages =
691 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
692 dev_priv->memory_size =
693 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
5bb39e81
TH		 694 dev_priv->memory_size -= dev_priv->vram_size;
695 } else {
696 /*
697 * An arbitrary limit of 512MiB on surface
698 * memory. But all HWV8 hardware supports GMR2.
699 */
700 dev_priv->memory_size = 512*1024*1024;
fb17f189 701 }
6da768aa 702 dev_priv->max_mob_pages = 0;
857aea1c 703 dev_priv->max_mob_size = 0;
6da768aa
TH		 704 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
705 uint64_t mem_size =
706 vmw_read(dev_priv,
707 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
708
709 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
afb0e50f
TH		 710 dev_priv->prim_bb_mem =
711 vmw_read(dev_priv,
712 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
857aea1c
CL		 713 dev_priv->max_mob_size =
714 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
35c05125
SY		 715 dev_priv->stdu_max_width =
716 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH);
717 dev_priv->stdu_max_height =
718 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT);
719
720 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
721 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
722 dev_priv->texture_max_width = vmw_read(dev_priv,
723 SVGA_REG_DEV_CAP);
724 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
725 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
726 dev_priv->texture_max_height = vmw_read(dev_priv,
727 SVGA_REG_DEV_CAP);
df45e9d4
TH		 728 } else {
729 dev_priv->texture_max_width = 8192;
730 dev_priv->texture_max_height = 8192;
afb0e50f 731 dev_priv->prim_bb_mem = dev_priv->vram_size;
df45e9d4
TH		 732 }
733
35c05125 734 vmw_print_capabilities(dev_priv->capabilities);
fb1d9738 735
0d00c488 736 ret = vmw_dma_masks(dev_priv);
496eb6fd 737 if (unlikely(ret != 0))
0d00c488
TH		 738 goto out_err0;
739
0d00c488 740 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
fb1d9738
JB		 741 DRM_INFO("Max GMR ids is %u\n",
742 (unsigned)dev_priv->max_gmr_ids);
fb17f189
TH		 743 DRM_INFO("Max number of GMR pages is %u\n",
744 (unsigned)dev_priv->max_gmr_pages);
5bb39e81
TH		 745 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
746 (unsigned)dev_priv->memory_size / 1024);
fb17f189 747 }
bc2d6508
TH		 748 DRM_INFO("Maximum display memory size is %u kiB\n",
749 dev_priv->prim_bb_mem / 1024);
fb1d9738
JB		 750 DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
751 dev_priv->vram_start, dev_priv->vram_size / 1024);
752 DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
753 dev_priv->mmio_start, dev_priv->mmio_size / 1024);
754
755 ret = vmw_ttm_global_init(dev_priv);
756 if (unlikely(ret != 0))
757 goto out_err0;
758
759
760 vmw_master_init(&dev_priv->fbdev_master);
761 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
762 dev_priv->active_master = &dev_priv->fbdev_master;
763
b76ff5ea
TH		 764 dev_priv->mmio_virt = memremap(dev_priv->mmio_start,
765 dev_priv->mmio_size, MEMREMAP_WB);
fb1d9738
JB		 766
767 if (unlikely(dev_priv->mmio_virt == NULL)) {
768 ret = -ENOMEM;
769 DRM_ERROR("Failed mapping MMIO.\n");
770 goto out_err3;
771 }
772
d7e1958d
JB		 773 /* Need mmio memory to check for fifo pitchlock cap. */
774 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
775 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
776 !vmw_fifo_have_pitchlock(dev_priv)) {
777 ret = -ENOSYS;
778 DRM_ERROR("Hardware has no pitchlock\n");
779 goto out_err4;
780 }
781
fb1d9738 782 dev_priv->tdev = ttm_object_device_init
69977ff5 783 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops);
fb1d9738
JB		 784
785 if (unlikely(dev_priv->tdev == NULL)) {
786 DRM_ERROR("Unable to initialize TTM object management.\n");
787 ret = -ENOMEM;
788 goto out_err4;
789 }
790
791 dev->dev_private = dev_priv;
792
fb1d9738
JB		 793 ret = pci_request_regions(dev->pdev, "vmwgfx probe");
794 dev_priv->stealth = (ret != 0);
795 if (dev_priv->stealth) {
796 /**
797 * Request at least the mmio PCI resource.
798 */
799
800 DRM_INFO("It appears like vesafb is loaded. "
f2d12b8e 801 "Ignore above error if any.\n");
fb1d9738
JB		 802 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
803 if (unlikely(ret != 0)) {
804 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
805 goto out_no_device;
806 }
fb1d9738 807 }
ae2a1040 808
506ff75c 809 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
bb0f1b5c 810 ret = drm_irq_install(dev, dev->pdev->irq);
506ff75c
TH		 811 if (ret != 0) {
812 DRM_ERROR("Failed installing irq: %d\n", ret);
813 goto out_no_irq;
814 }
815 }
816
ae2a1040 817 dev_priv->fman = vmw_fence_manager_init(dev_priv);
14bbf20c
WY		 818 if (unlikely(dev_priv->fman == NULL)) {
819 ret = -ENOMEM;
ae2a1040 820 goto out_no_fman;
14bbf20c 821 }
56d1c78d 822
153b3d5b
TH		 823 ret = ttm_bo_device_init(&dev_priv->bdev,
824 dev_priv->bo_global_ref.ref.object,
825 &vmw_bo_driver,
826 dev->anon_inode->i_mapping,
827 VMWGFX_FILE_PAGE_OFFSET,
828 false);
829 if (unlikely(ret != 0)) {
830 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
831 goto out_no_bdev;
832 }
3458390b 833
153b3d5b
TH		 834 /*
835 * Enable VRAM, but initially don't use it until SVGA is enabled and
836 * unhidden.
837 */
3458390b
TH		 838 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
839 (dev_priv->vram_size >> PAGE_SHIFT));
840 if (unlikely(ret != 0)) {
841 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
842 goto out_no_vram;
843 }
153b3d5b 844 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
3458390b
TH		 845
846 dev_priv->has_gmr = true;
847 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
848 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
849 VMW_PL_GMR) != 0) {
850 DRM_INFO("No GMR memory available. "
851 "Graphics memory resources are very limited.\n");
852 dev_priv->has_gmr = false;
853 }
854
855 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
856 dev_priv->has_mob = true;
857 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB,
858 VMW_PL_MOB) != 0) {
859 DRM_INFO("No MOB memory available. "
860 "3D will be disabled.\n");
861 dev_priv->has_mob = false;
862 }
863 }
864
d80efd5c
TH		 865 if (dev_priv->has_mob) {
866 spin_lock(&dev_priv->cap_lock);
867 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DX);
868 dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP);
869 spin_unlock(&dev_priv->cap_lock);
870 }
871
56d1c78d 872
7a1c2f6c
TH		 873 ret = vmw_kms_init(dev_priv);
874 if (unlikely(ret != 0))
875 goto out_no_kms;
f2d12b8e 876 vmw_overlay_init(dev_priv);
56d1c78d 877
153b3d5b
TH		 878 ret = vmw_request_device(dev_priv);
879 if (ret)
880 goto out_no_fifo;
881
d80efd5c
TH		 882 DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no.");
883
f9217913
SY		 884 snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s",
885 VMWGFX_REPO, VMWGFX_GIT_VERSION);
886 vmw_host_log(host_log);
887
888 memset(host_log, 0, sizeof(host_log));
889 snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d",
890 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR,
891 VMWGFX_DRIVER_PATCHLEVEL);
892 vmw_host_log(host_log);
893
30c78bb8 894 if (dev_priv->enable_fb) {
153b3d5b
TH		 895 vmw_fifo_resource_inc(dev_priv);
896 vmw_svga_enable(dev_priv);
30c78bb8 897 vmw_fb_init(dev_priv);
7a1c2f6c
TH		 898 }
899
d9f36a00
TH		 900 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
901 register_pm_notifier(&dev_priv->pm_nb);
902
fb1d9738
JB		 903 return 0;
904
506ff75c 905out_no_fifo:
56d1c78d
JB		 906 vmw_overlay_close(dev_priv);
907 vmw_kms_close(dev_priv);
908out_no_kms:
3458390b
TH		 909 if (dev_priv->has_mob)
910 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
911 if (dev_priv->has_gmr)
912 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
913 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
914out_no_vram:
153b3d5b
TH		 915 (void)ttm_bo_device_release(&dev_priv->bdev);
916out_no_bdev:
ae2a1040
TH		 917 vmw_fence_manager_takedown(dev_priv->fman);
918out_no_fman:
506ff75c
TH		 919 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
920 drm_irq_uninstall(dev_priv->dev);
921out_no_irq:
30c78bb8
TH		 922 if (dev_priv->stealth)
923 pci_release_region(dev->pdev, 2);
924 else
925 pci_release_regions(dev->pdev);
fb1d9738 926out_no_device:
fb1d9738
JB		 927 ttm_object_device_release(&dev_priv->tdev);
928out_err4:
b76ff5ea 929 memunmap(dev_priv->mmio_virt);
fb1d9738 930out_err3:
fb1d9738
JB		 931 vmw_ttm_global_release(dev_priv);
932out_err0:
c0951b79
TH		 933 for (i = vmw_res_context; i < vmw_res_max; ++i)
934 idr_destroy(&dev_priv->res_idr[i]);
935
d80efd5c
TH		 936 if (dev_priv->ctx.staged_bindings)
937 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
fb1d9738
JB		 938 kfree(dev_priv);
939 return ret;
940}
941
942static int vmw_driver_unload(struct drm_device *dev)
943{
944 struct vmw_private *dev_priv = vmw_priv(dev);
c0951b79 945 enum vmw_res_type i;
fb1d9738 946
d9f36a00
TH		 947 unregister_pm_notifier(&dev_priv->pm_nb);
948
c0951b79
TH		 949 if (dev_priv->ctx.res_ht_initialized)
950 drm_ht_remove(&dev_priv->ctx.res_ht);
a3a1a667 951 vfree(dev_priv->ctx.cmd_bounce);
30c78bb8 952 if (dev_priv->enable_fb) {
05c95018 953 vmw_fb_off(dev_priv);
30c78bb8 954 vmw_fb_close(dev_priv);
153b3d5b
TH		 955 vmw_fifo_resource_dec(dev_priv);
956 vmw_svga_disable(dev_priv);
30c78bb8 957 }
153b3d5b 958
f2d12b8e
TH		 959 vmw_kms_close(dev_priv);
960 vmw_overlay_close(dev_priv);
3458390b 961
3458390b
TH		 962 if (dev_priv->has_gmr)
963 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
964 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
965
153b3d5b
TH		 966 vmw_release_device_early(dev_priv);
967 if (dev_priv->has_mob)
968 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
969 (void) ttm_bo_device_release(&dev_priv->bdev);
970 vmw_release_device_late(dev_priv);
ae2a1040 971 vmw_fence_manager_takedown(dev_priv->fman);
506ff75c
TH		 972 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
973 drm_irq_uninstall(dev_priv->dev);
f2d12b8e 974 if (dev_priv->stealth)
fb1d9738 975 pci_release_region(dev->pdev, 2);
f2d12b8e
TH		 976 else
977 pci_release_regions(dev->pdev);
978
fb1d9738 979 ttm_object_device_release(&dev_priv->tdev);
b76ff5ea 980 memunmap(dev_priv->mmio_virt);
d80efd5c
TH		 981 if (dev_priv->ctx.staged_bindings)
982 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
fb1d9738 983 vmw_ttm_global_release(dev_priv);
c0951b79
TH		 984
985 for (i = vmw_res_context; i < vmw_res_max; ++i)
986 idr_destroy(&dev_priv->res_idr[i]);
fb1d9738
JB		 987
988 kfree(dev_priv);
989
990 return 0;
991}
992
993static void vmw_postclose(struct drm_device *dev,
994 struct drm_file *file_priv)
995{
996 struct vmw_fpriv *vmw_fp;
997
998 vmw_fp = vmw_fpriv(file_priv);
c4249855
TH		 999
1000 if (vmw_fp->locked_master) {
1001 struct vmw_master *vmaster =
1002 vmw_master(vmw_fp->locked_master);
1003
1004 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1005 ttm_vt_unlock(&vmaster->lock);
fb1d9738 1006 drm_master_put(&vmw_fp->locked_master);
c4249855
TH		 1007 }
1008
1009 ttm_object_file_release(&vmw_fp->tfile);
fb1d9738
JB		 1010 kfree(vmw_fp);
1011}
1012
1013static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1014{
1015 struct vmw_private *dev_priv = vmw_priv(dev);
1016 struct vmw_fpriv *vmw_fp;
1017 int ret = -ENOMEM;
1018
1019 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
1020 if (unlikely(vmw_fp == NULL))
1021 return ret;
1022
1023 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
1024 if (unlikely(vmw_fp->tfile == NULL))
1025 goto out_no_tfile;
1026
1027 file_priv->driver_priv = vmw_fp;
fb1d9738
JB		 1028
1029 return 0;
1030
1031out_no_tfile:
1032 kfree(vmw_fp);
1033 return ret;
1034}
1035
64190bde
TH		 1036static struct vmw_master *vmw_master_check(struct drm_device *dev,
1037 struct drm_file *file_priv,
1038 unsigned int flags)
1039{
1040 int ret;
1041 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1042 struct vmw_master *vmaster;
1043
1044 if (file_priv->minor->type != DRM_MINOR_LEGACY ||
1045 !(flags & DRM_AUTH))
1046 return NULL;
1047
1048 ret = mutex_lock_interruptible(&dev->master_mutex);
1049 if (unlikely(ret != 0))
1050 return ERR_PTR(-ERESTARTSYS);
1051
7963e9db 1052 if (file_priv->is_master) {
64190bde
TH		 1053 mutex_unlock(&dev->master_mutex);
1054 return NULL;
1055 }
1056
1057 /*
aa3469ce
TH		 1058 * Check if we were previously master, but now dropped. In that
1059 * case, allow at least render node functionality.
64190bde
TH		 1060 */
1061 if (vmw_fp->locked_master) {
1062 mutex_unlock(&dev->master_mutex);
aa3469ce
TH		 1063
1064 if (flags & DRM_RENDER_ALLOW)
1065 return NULL;
1066
64190bde
TH		 1067 DRM_ERROR("Dropped master trying to access ioctl that "
1068 "requires authentication.\n");
1069 return ERR_PTR(-EACCES);
1070 }
1071 mutex_unlock(&dev->master_mutex);
1072
64190bde
TH		 1073 /*
1074 * Take the TTM lock. Possibly sleep waiting for the authenticating
1075 * master to become master again, or for a SIGTERM if the
1076 * authenticating master exits.
1077 */
1078 vmaster = vmw_master(file_priv->master);
1079 ret = ttm_read_lock(&vmaster->lock, true);
1080 if (unlikely(ret != 0))
1081 vmaster = ERR_PTR(ret);
1082
1083 return vmaster;
1084}
1085
1086static long vmw_generic_ioctl(struct file *filp, unsigned int cmd,
1087 unsigned long arg,
1088 long (*ioctl_func)(struct file *, unsigned int,
1089 unsigned long))
fb1d9738
JB		 1090{
1091 struct drm_file *file_priv = filp->private_data;
1092 struct drm_device *dev = file_priv->minor->dev;
1093 unsigned int nr = DRM_IOCTL_NR(cmd);
64190bde
TH		 1094 struct vmw_master *vmaster;
1095 unsigned int flags;
1096 long ret;
fb1d9738
JB		 1097
1098 /*
e1f78003 1099 * Do extra checking on driver private ioctls.
fb1d9738
JB		 1100 */
1101
1102 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1103 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
baa70943 1104 const struct drm_ioctl_desc *ioctl =
64190bde 1105 &vmw_ioctls[nr - DRM_COMMAND_BASE];
fb1d9738 1106
d80efd5c
TH		 1107 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) {
1108 ret = (long) drm_ioctl_permit(ioctl->flags, file_priv);
1109 if (unlikely(ret != 0))
1110 return ret;
1111
1112 if (unlikely((cmd & (IOC_IN | IOC_OUT)) != IOC_IN))
1113 goto out_io_encoding;
1114
1115 return (long) vmw_execbuf_ioctl(dev, arg, file_priv,
1116 _IOC_SIZE(cmd));
fb1d9738 1117 }
d80efd5c
TH		 1118
1119 if (unlikely(ioctl->cmd != cmd))
1120 goto out_io_encoding;
1121
64190bde
TH		 1122 flags = ioctl->flags;
1123 } else if (!drm_ioctl_flags(nr, &flags))
1124 return -EINVAL;
1125
1126 vmaster = vmw_master_check(dev, file_priv, flags);
55579cfe 1127 if (IS_ERR(vmaster)) {
e338c4c2
TH		 1128 ret = PTR_ERR(vmaster);
1129
1130 if (ret != -ERESTARTSYS)
1131 DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n",
1132 nr, ret);
1133 return ret;
fb1d9738
JB		 1134 }
1135
64190bde
TH		 1136 ret = ioctl_func(filp, cmd, arg);
1137 if (vmaster)
1138 ttm_read_unlock(&vmaster->lock);
1139
1140 return ret;
d80efd5c
TH		 1141
1142out_io_encoding:
1143 DRM_ERROR("Invalid command format, ioctl %d\n",
1144 nr - DRM_COMMAND_BASE);
1145
1146 return -EINVAL;
64190bde
TH		 1147}
1148
1149static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
1150 unsigned long arg)
1151{
1152 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl);
fb1d9738
JB		 1153}
1154
64190bde
TH		 1155#ifdef CONFIG_COMPAT
1156static long vmw_compat_ioctl(struct file *filp, unsigned int cmd,
1157 unsigned long arg)
1158{
1159 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl);
1160}
1161#endif
1162
fb1d9738
JB		 1163static void vmw_lastclose(struct drm_device *dev)
1164{
fb1d9738
JB		 1165}
1166
1167static void vmw_master_init(struct vmw_master *vmaster)
1168{
1169 ttm_lock_init(&vmaster->lock);
1170}
1171
1172static int vmw_master_create(struct drm_device *dev,
1173 struct drm_master *master)
1174{
1175 struct vmw_master *vmaster;
1176
fb1d9738
JB		 1177 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
1178 if (unlikely(vmaster == NULL))
1179 return -ENOMEM;
1180
3a939a5e 1181 vmw_master_init(vmaster);
fb1d9738
JB		 1182 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1183 master->driver_priv = vmaster;
1184
1185 return 0;
1186}
1187
1188static void vmw_master_destroy(struct drm_device *dev,
1189 struct drm_master *master)
1190{
1191 struct vmw_master *vmaster = vmw_master(master);
1192
fb1d9738
JB		 1193 master->driver_priv = NULL;
1194 kfree(vmaster);
1195}
1196
fb1d9738
JB		 1197static int vmw_master_set(struct drm_device *dev,
1198 struct drm_file *file_priv,
1199 bool from_open)
1200{
1201 struct vmw_private *dev_priv = vmw_priv(dev);
1202 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1203 struct vmw_master *active = dev_priv->active_master;
1204 struct vmw_master *vmaster = vmw_master(file_priv->master);
1205 int ret = 0;
1206
fb1d9738
JB		 1207 if (active) {
1208 BUG_ON(active != &dev_priv->fbdev_master);
1209 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
1210 if (unlikely(ret != 0))
153b3d5b 1211 return ret;
fb1d9738
JB		 1212
1213 ttm_lock_set_kill(&active->lock, true, SIGTERM);
fb1d9738
JB		 1214 dev_priv->active_master = NULL;
1215 }
1216
1217 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1218 if (!from_open) {
1219 ttm_vt_unlock(&vmaster->lock);
1220 BUG_ON(vmw_fp->locked_master != file_priv->master);
1221 drm_master_put(&vmw_fp->locked_master);
1222 }
1223
1224 dev_priv->active_master = vmaster;
5ea17348 1225 drm_sysfs_hotplug_event(dev);
fb1d9738
JB		 1226
1227 return 0;
fb1d9738
JB		 1228}
1229
1230static void vmw_master_drop(struct drm_device *dev,
1231 struct drm_file *file_priv,
1232 bool from_release)
1233{
1234 struct vmw_private *dev_priv = vmw_priv(dev);
1235 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1236 struct vmw_master *vmaster = vmw_master(file_priv->master);
1237 int ret;
1238
fb1d9738
JB		 1239 /**
1240 * Make sure the master doesn't disappear while we have
1241 * it locked.
1242 */
1243
1244 vmw_fp->locked_master = drm_master_get(file_priv->master);
1245 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
8fbf9d92 1246 vmw_kms_legacy_hotspot_clear(dev_priv);
fb1d9738
JB		 1247 if (unlikely((ret != 0))) {
1248 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1249 drm_master_put(&vmw_fp->locked_master);
1250 }
1251
c4249855 1252 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
fb1d9738 1253
153b3d5b
TH		 1254 if (!dev_priv->enable_fb)
1255 vmw_svga_disable(dev_priv);
30c78bb8 1256
fb1d9738
JB		 1257 dev_priv->active_master = &dev_priv->fbdev_master;
1258 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
1259 ttm_vt_unlock(&dev_priv->fbdev_master.lock);
1260
30c78bb8
TH		 1261 if (dev_priv->enable_fb)
1262 vmw_fb_on(dev_priv);
fb1d9738
JB		 1263}
1264
153b3d5b
TH		 1265/**
1266 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1267 *
1268 * @dev_priv: Pointer to device private struct.
1269 * Needs the reservation sem to be held in non-exclusive mode.
1270 */
b9eb1a61 1271static void __vmw_svga_enable(struct vmw_private *dev_priv)
153b3d5b
TH		 1272{
1273 spin_lock(&dev_priv->svga_lock);
1274 if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1275 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE);
1276 dev_priv->bdev.man[TTM_PL_VRAM].use_type = true;
1277 }
1278 spin_unlock(&dev_priv->svga_lock);
1279}
1280
1281/**
1282 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1283 *
1284 * @dev_priv: Pointer to device private struct.
1285 */
1286void vmw_svga_enable(struct vmw_private *dev_priv)
1287{
1288 ttm_read_lock(&dev_priv->reservation_sem, false);
1289 __vmw_svga_enable(dev_priv);
1290 ttm_read_unlock(&dev_priv->reservation_sem);
1291}
1292
1293/**
1294 * __vmw_svga_disable - Disable SVGA mode and use of VRAM.
1295 *
1296 * @dev_priv: Pointer to device private struct.
1297 * Needs the reservation sem to be held in exclusive mode.
1298 * Will not empty VRAM. VRAM must be emptied by caller.
1299 */
b9eb1a61 1300static void __vmw_svga_disable(struct vmw_private *dev_priv)
153b3d5b
TH		 1301{
1302 spin_lock(&dev_priv->svga_lock);
1303 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1304 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
1305 vmw_write(dev_priv, SVGA_REG_ENABLE,
8ce75f8a
SY		 1306 SVGA_REG_ENABLE_HIDE |
1307 SVGA_REG_ENABLE_ENABLE);
153b3d5b
TH		 1308 }
1309 spin_unlock(&dev_priv->svga_lock);
1310}
1311
1312/**
1313 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo
1314 * running.
1315 *
1316 * @dev_priv: Pointer to device private struct.
1317 * Will empty VRAM.
1318 */
1319void vmw_svga_disable(struct vmw_private *dev_priv)
1320{
1321 ttm_write_lock(&dev_priv->reservation_sem, false);
1322 spin_lock(&dev_priv->svga_lock);
1323 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1324 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
153b3d5b
TH		 1325 spin_unlock(&dev_priv->svga_lock);
1326 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM))
1327 DRM_ERROR("Failed evicting VRAM buffers.\n");
8ce75f8a
SY		 1328 vmw_write(dev_priv, SVGA_REG_ENABLE,
1329 SVGA_REG_ENABLE_HIDE |
1330 SVGA_REG_ENABLE_ENABLE);
153b3d5b
TH		 1331 } else
1332 spin_unlock(&dev_priv->svga_lock);
1333 ttm_write_unlock(&dev_priv->reservation_sem);
1334}
fb1d9738
JB		 1335
1336static void vmw_remove(struct pci_dev *pdev)
1337{
1338 struct drm_device *dev = pci_get_drvdata(pdev);
1339
fd3e4d6e 1340 pci_disable_device(pdev);
fb1d9738
JB		 1341 drm_put_dev(dev);
1342}
1343
d9f36a00
TH		 1344static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1345 void *ptr)
1346{
1347 struct vmw_private *dev_priv =
1348 container_of(nb, struct vmw_private, pm_nb);
d9f36a00
TH		 1349
1350 switch (val) {
1351 case PM_HIBERNATION_PREPARE:
a278724a
TH		 1352 if (dev_priv->enable_fb)
1353 vmw_fb_off(dev_priv);
294adf7d 1354 ttm_suspend_lock(&dev_priv->reservation_sem);
d9f36a00 1355
153b3d5b 1356 /*
d9f36a00
TH		 1357 * This empties VRAM and unbinds all GMR bindings.
1358 * Buffer contents is moved to swappable memory.
1359 */
c0951b79
TH		 1360 vmw_execbuf_release_pinned_bo(dev_priv);
1361 vmw_resource_evict_all(dev_priv);
153b3d5b 1362 vmw_release_device_early(dev_priv);
d9f36a00 1363 ttm_bo_swapout_all(&dev_priv->bdev);
153b3d5b 1364 vmw_fence_fifo_down(dev_priv->fman);
d9f36a00
TH		 1365 break;
1366 case PM_POST_HIBERNATION:
094e0fa8 1367 case PM_POST_RESTORE:
153b3d5b 1368 vmw_fence_fifo_up(dev_priv->fman);
294adf7d 1369 ttm_suspend_unlock(&dev_priv->reservation_sem);
a278724a
TH		 1370 if (dev_priv->enable_fb)
1371 vmw_fb_on(dev_priv);
d9f36a00
TH		 1372 break;
1373 case PM_RESTORE_PREPARE:
1374 break;
d9f36a00
TH		 1375 default:
1376 break;
1377 }
1378 return 0;
1379}
1380
7fbd721a 1381static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
d9f36a00 1382{
094e0fa8
TH		 1383 struct drm_device *dev = pci_get_drvdata(pdev);
1384 struct vmw_private *dev_priv = vmw_priv(dev);
1385
153b3d5b 1386 if (dev_priv->refuse_hibernation)
094e0fa8 1387 return -EBUSY;
094e0fa8 1388
d9f36a00
TH		 1389 pci_save_state(pdev);
1390 pci_disable_device(pdev);
1391 pci_set_power_state(pdev, PCI_D3hot);
1392 return 0;
1393}
1394
7fbd721a 1395static int vmw_pci_resume(struct pci_dev *pdev)
d9f36a00
TH		 1396{
1397 pci_set_power_state(pdev, PCI_D0);
1398 pci_restore_state(pdev);
1399 return pci_enable_device(pdev);
1400}
1401
7fbd721a
TH		 1402static int vmw_pm_suspend(struct device *kdev)
1403{
1404 struct pci_dev *pdev = to_pci_dev(kdev);
1405 struct pm_message dummy;
1406
1407 dummy.event = 0;
1408
1409 return vmw_pci_suspend(pdev, dummy);
1410}
1411
1412static int vmw_pm_resume(struct device *kdev)
1413{
1414 struct pci_dev *pdev = to_pci_dev(kdev);
1415
1416 return vmw_pci_resume(pdev);
1417}
1418
153b3d5b 1419static int vmw_pm_freeze(struct device *kdev)
7fbd721a
TH		 1420{
1421 struct pci_dev *pdev = to_pci_dev(kdev);
1422 struct drm_device *dev = pci_get_drvdata(pdev);
1423 struct vmw_private *dev_priv = vmw_priv(dev);
1424
7fbd721a
TH		 1425 dev_priv->suspended = true;
1426 if (dev_priv->enable_fb)
153b3d5b 1427 vmw_fifo_resource_dec(dev_priv);
7fbd721a 1428
153b3d5b
TH		 1429 if (atomic_read(&dev_priv->num_fifo_resources) != 0) {
1430 DRM_ERROR("Can't hibernate while 3D resources are active.\n");
7fbd721a 1431 if (dev_priv->enable_fb)
153b3d5b
TH		 1432 vmw_fifo_resource_inc(dev_priv);
1433 WARN_ON(vmw_request_device_late(dev_priv));
7fbd721a
TH		 1434 dev_priv->suspended = false;
1435 return -EBUSY;
1436 }
1437
153b3d5b
TH		 1438 if (dev_priv->enable_fb)
1439 __vmw_svga_disable(dev_priv);
1440
1441 vmw_release_device_late(dev_priv);
1442
7fbd721a
TH		 1443 return 0;
1444}
1445
153b3d5b 1446static int vmw_pm_restore(struct device *kdev)
7fbd721a
TH		 1447{
1448 struct pci_dev *pdev = to_pci_dev(kdev);
1449 struct drm_device *dev = pci_get_drvdata(pdev);
1450 struct vmw_private *dev_priv = vmw_priv(dev);
153b3d5b 1451 int ret;
7fbd721a 1452
95e8f6a2
TH		 1453 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
1454 (void) vmw_read(dev_priv, SVGA_REG_ID);
95e8f6a2 1455
7fbd721a 1456 if (dev_priv->enable_fb)
153b3d5b
TH		 1457 vmw_fifo_resource_inc(dev_priv);
1458
1459 ret = vmw_request_device(dev_priv);
1460 if (ret)
1461 return ret;
1462
1463 if (dev_priv->enable_fb)
1464 __vmw_svga_enable(dev_priv);
7fbd721a
TH		 1465
1466 dev_priv->suspended = false;
153b3d5b
TH		 1467
1468 return 0;
7fbd721a
TH		 1469}
1470
1471static const struct dev_pm_ops vmw_pm_ops = {
153b3d5b
TH		 1472 .freeze = vmw_pm_freeze,
1473 .thaw = vmw_pm_restore,
1474 .restore = vmw_pm_restore,
7fbd721a
TH		 1475 .suspend = vmw_pm_suspend,
1476 .resume = vmw_pm_resume,
1477};
1478
e08e96de
AV		 1479static const struct file_operations vmwgfx_driver_fops = {
1480 .owner = THIS_MODULE,
1481 .open = drm_open,
1482 .release = drm_release,
1483 .unlocked_ioctl = vmw_unlocked_ioctl,
1484 .mmap = vmw_mmap,
1485 .poll = vmw_fops_poll,
1486 .read = vmw_fops_read,
e08e96de 1487#if defined(CONFIG_COMPAT)
64190bde 1488 .compat_ioctl = vmw_compat_ioctl,
e08e96de
AV		 1489#endif
1490 .llseek = noop_llseek,
1491};
1492
fb1d9738
JB		 1493static struct drm_driver driver = {
1494 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
03f80263 1495 DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER,
fb1d9738
JB		 1496 .load = vmw_driver_load,
1497 .unload = vmw_driver_unload,
fb1d9738
JB		 1498 .lastclose = vmw_lastclose,
1499 .irq_preinstall = vmw_irq_preinstall,
1500 .irq_postinstall = vmw_irq_postinstall,
1501 .irq_uninstall = vmw_irq_uninstall,
1502 .irq_handler = vmw_irq_handler,
7a1c2f6c 1503 .get_vblank_counter = vmw_get_vblank_counter,
1c482ab3
JB		 1504 .enable_vblank = vmw_enable_vblank,
1505 .disable_vblank = vmw_disable_vblank,
fb1d9738 1506 .ioctls = vmw_ioctls,
f95aeb17 1507 .num_ioctls = ARRAY_SIZE(vmw_ioctls),
fb1d9738
JB		 1508 .master_create = vmw_master_create,
1509 .master_destroy = vmw_master_destroy,
1510 .master_set = vmw_master_set,
1511 .master_drop = vmw_master_drop,
1512 .open = vmw_driver_open,
1513 .postclose = vmw_postclose,
915b4d11 1514 .set_busid = drm_pci_set_busid,
5e1782d2
DA		 1515
1516 .dumb_create = vmw_dumb_create,
1517 .dumb_map_offset = vmw_dumb_map_offset,
1518 .dumb_destroy = vmw_dumb_destroy,
1519
69977ff5
TH		 1520 .prime_fd_to_handle = vmw_prime_fd_to_handle,
1521 .prime_handle_to_fd = vmw_prime_handle_to_fd,
1522
e08e96de 1523 .fops = &vmwgfx_driver_fops,
fb1d9738
JB		 1524 .name = VMWGFX_DRIVER_NAME,
1525 .desc = VMWGFX_DRIVER_DESC,
1526 .date = VMWGFX_DRIVER_DATE,
1527 .major = VMWGFX_DRIVER_MAJOR,
1528 .minor = VMWGFX_DRIVER_MINOR,
1529 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1530};
1531
8410ea3b
DA		 1532static struct pci_driver vmw_pci_driver = {
1533 .name = VMWGFX_DRIVER_NAME,
1534 .id_table = vmw_pci_id_list,
1535 .probe = vmw_probe,
1536 .remove = vmw_remove,
1537 .driver = {
1538 .pm = &vmw_pm_ops
1539 }
1540};
1541
fb1d9738
JB		 1542static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1543{
dcdb1674 1544 return drm_get_pci_dev(pdev, ent, &driver);
fb1d9738
JB		 1545}
1546
1547static int __init vmwgfx_init(void)
1548{
1549 int ret;
96c5d076 1550
96c5d076
RC		 1551 if (vgacon_text_force())
1552 return -EINVAL;
96c5d076 1553
8410ea3b 1554 ret = drm_pci_init(&driver, &vmw_pci_driver);
fb1d9738
JB		 1555 if (ret)
1556 DRM_ERROR("Failed initializing DRM.\n");
1557 return ret;
1558}
1559
1560static void __exit vmwgfx_exit(void)
1561{
8410ea3b 1562 drm_pci_exit(&driver, &vmw_pci_driver);
fb1d9738
JB		 1563}
1564
1565module_init(vmwgfx_init);
1566module_exit(vmwgfx_exit);
1567
1568MODULE_AUTHOR("VMware Inc. and others");
1569MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1570MODULE_LICENSE("GPL and additional rights");
73558ead
TH		 1571MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1572 __stringify(VMWGFX_DRIVER_MINOR) "."
1573 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1574 "0");
Linux 6.x block layer and io_uring tree(s)