drm/vkms: Use drmm_crtc_init_with_planes()
[linux-2.6-block.git] / drivers / gpu / drm / vkms / vkms_crtc.c
CommitLineData
7fd56e02 1// SPDX-License-Identifier: GPL-2.0+
854502fa 2
d71cbff1
DV
3#include <linux/dma-fence.h>
4
8b186587 5#include <drm/drm_atomic.h>
854502fa 6#include <drm/drm_atomic_helper.h>
fcd70cd3 7#include <drm/drm_probe_helper.h>
ce672a1b
SR
8#include <drm/drm_vblank.h>
9
10#include "vkms_drv.h"
854502fa 11
ba420afa 12static enum hrtimer_restart vkms_vblank_simulate(struct hrtimer *timer)
3a070992 13{
ba420afa
SM
14 struct vkms_output *output = container_of(timer, struct vkms_output,
15 vblank_hrtimer);
3a070992 16 struct drm_crtc *crtc = &output->crtc;
8b186587 17 struct vkms_crtc_state *state;
09ef09b4 18 u64 ret_overrun;
d71cbff1
DV
19 bool ret, fence_cookie;
20
21 fence_cookie = dma_fence_begin_signalling();
3a070992 22
7355965d
DV
23 ret_overrun = hrtimer_forward_now(&output->vblank_hrtimer,
24 output->period_ns);
b4142fc4
DV
25 if (ret_overrun != 1)
26 pr_warn("%s: vblank timer overrun\n", __func__);
7355965d 27
88ad7f3a 28 spin_lock(&output->lock);
3a070992
RS
29 ret = drm_crtc_handle_vblank(crtc);
30 if (!ret)
31 DRM_ERROR("vkms failure on handling vblank");
32
a4e7e98e 33 state = output->composer_state;
88ad7f3a
DV
34 spin_unlock(&output->lock);
35
a4e7e98e 36 if (state && output->composer_enabled) {
0ca33adb
HM
37 u64 frame = drm_crtc_accurate_vblank_count(crtc);
38
a4e7e98e 39 /* update frame_start only if a queued vkms_composer_worker()
0ca33adb
HM
40 * has read the data
41 */
a4e7e98e 42 spin_lock(&output->composer_lock);
18d0952a 43 if (!state->crc_pending)
0ca33adb 44 state->frame_start = frame;
18d0952a
DV
45 else
46 DRM_DEBUG_DRIVER("crc worker falling behind, frame_start: %llu, frame_end: %llu\n",
47 state->frame_start, frame);
48 state->frame_end = frame;
49 state->crc_pending = true;
a4e7e98e 50 spin_unlock(&output->composer_lock);
0ca33adb 51
a4e7e98e 52 ret = queue_work(output->composer_workq, &state->composer_work);
0ca33adb 53 if (!ret)
a4e7e98e 54 DRM_DEBUG_DRIVER("Composer worker already queued\n");
6c234fe3
HM
55 }
56
d71cbff1
DV
57 dma_fence_end_signalling(fence_cookie);
58
3a070992
RS
59 return HRTIMER_RESTART;
60}
61
62static int vkms_enable_vblank(struct drm_crtc *crtc)
63{
64 struct drm_device *dev = crtc->dev;
65 unsigned int pipe = drm_crtc_index(crtc);
66 struct drm_vblank_crtc *vblank = &dev->vblank[pipe];
67 struct vkms_output *out = drm_crtc_to_vkms_output(crtc);
68
69 drm_calc_timestamping_constants(crtc, &crtc->mode);
70
71 hrtimer_init(&out->vblank_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
72 out->vblank_hrtimer.function = &vkms_vblank_simulate;
73 out->period_ns = ktime_set(0, vblank->framedur_ns);
74 hrtimer_start(&out->vblank_hrtimer, out->period_ns, HRTIMER_MODE_REL);
75
76 return 0;
77}
78
79static void vkms_disable_vblank(struct drm_crtc *crtc)
80{
81 struct vkms_output *out = drm_crtc_to_vkms_output(crtc);
82
83 hrtimer_cancel(&out->vblank_hrtimer);
84}
85
dc3260d0
TZ
86static bool vkms_get_vblank_timestamp(struct drm_crtc *crtc,
87 int *max_error, ktime_t *vblank_time,
88 bool in_vblank_irq)
3a070992 89{
dc3260d0
TZ
90 struct drm_device *dev = crtc->dev;
91 unsigned int pipe = crtc->index;
3a070992
RS
92 struct vkms_device *vkmsdev = drm_device_to_vkms_device(dev);
93 struct vkms_output *output = &vkmsdev->output;
7355965d 94 struct drm_vblank_crtc *vblank = &dev->vblank[pipe];
3a070992 95
05ca5302
SY
96 if (!READ_ONCE(vblank->enabled)) {
97 *vblank_time = ktime_get();
98 return true;
99 }
100
88ad7f3a 101 *vblank_time = READ_ONCE(output->vblank_hrtimer.node.expires);
3a070992 102
7355965d
DV
103 if (WARN_ON(*vblank_time == vblank->time))
104 return true;
105
106 /*
107 * To prevent races we roll the hrtimer forward before we do any
108 * interrupt processing - this is how real hw works (the interrupt is
109 * only generated after all the vblank registers are updated) and what
110 * the vblank core expects. Therefore we need to always correct the
111 * timestampe by one frame.
112 */
113 *vblank_time -= output->period_ns;
def35e7c 114
3a070992
RS
115 return true;
116}
117
dfb9f5ca
HM
118static struct drm_crtc_state *
119vkms_atomic_crtc_duplicate_state(struct drm_crtc *crtc)
120{
121 struct vkms_crtc_state *vkms_state;
122
123 if (WARN_ON(!crtc->state))
124 return NULL;
125
126 vkms_state = kzalloc(sizeof(*vkms_state), GFP_KERNEL);
127 if (!vkms_state)
128 return NULL;
129
130 __drm_atomic_helper_crtc_duplicate_state(crtc, &vkms_state->base);
131
a4e7e98e 132 INIT_WORK(&vkms_state->composer_work, vkms_composer_worker);
6c234fe3 133
dfb9f5ca
HM
134 return &vkms_state->base;
135}
136
137static void vkms_atomic_crtc_destroy_state(struct drm_crtc *crtc,
138 struct drm_crtc_state *state)
139{
6c234fe3 140 struct vkms_crtc_state *vkms_state = to_vkms_crtc_state(state);
dfb9f5ca
HM
141
142 __drm_atomic_helper_crtc_destroy_state(state);
6c234fe3 143
a4e7e98e 144 WARN_ON(work_pending(&vkms_state->composer_work));
8b186587
DV
145 kfree(vkms_state->active_planes);
146 kfree(vkms_state);
dfb9f5ca
HM
147}
148
7a34d9c4
ML
149static void vkms_atomic_crtc_reset(struct drm_crtc *crtc)
150{
151 struct vkms_crtc_state *vkms_state =
152 kzalloc(sizeof(*vkms_state), GFP_KERNEL);
153
154 if (crtc->state)
155 vkms_atomic_crtc_destroy_state(crtc, crtc->state);
156
157 __drm_atomic_helper_crtc_reset(crtc, &vkms_state->base);
158 if (vkms_state)
a4e7e98e 159 INIT_WORK(&vkms_state->composer_work, vkms_composer_worker);
7a34d9c4
ML
160}
161
854502fa
RS
162static const struct drm_crtc_funcs vkms_crtc_funcs = {
163 .set_config = drm_atomic_helper_set_config,
854502fa 164 .page_flip = drm_atomic_helper_page_flip,
dfb9f5ca
HM
165 .reset = vkms_atomic_crtc_reset,
166 .atomic_duplicate_state = vkms_atomic_crtc_duplicate_state,
167 .atomic_destroy_state = vkms_atomic_crtc_destroy_state,
3a070992
RS
168 .enable_vblank = vkms_enable_vblank,
169 .disable_vblank = vkms_disable_vblank,
dc3260d0 170 .get_vblank_timestamp = vkms_get_vblank_timestamp,
c936843f 171 .get_crc_sources = vkms_get_crc_sources,
6c234fe3 172 .set_crc_source = vkms_set_crc_source,
af697933 173 .verify_crc_source = vkms_verify_crc_source,
3a070992
RS
174};
175
8b186587 176static int vkms_crtc_atomic_check(struct drm_crtc *crtc,
29b77ad7 177 struct drm_atomic_state *state)
8b186587 178{
29b77ad7
MR
179 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
180 crtc);
181 struct vkms_crtc_state *vkms_state = to_vkms_crtc_state(crtc_state);
8b186587
DV
182 struct drm_plane *plane;
183 struct drm_plane_state *plane_state;
184 int i = 0, ret;
185
186 if (vkms_state->active_planes)
187 return 0;
188
29b77ad7 189 ret = drm_atomic_add_affected_planes(crtc_state->state, crtc);
8b186587
DV
190 if (ret < 0)
191 return ret;
192
29b77ad7
MR
193 drm_for_each_plane_mask(plane, crtc->dev, crtc_state->plane_mask) {
194 plane_state = drm_atomic_get_existing_plane_state(crtc_state->state,
8b186587
DV
195 plane);
196 WARN_ON(!plane_state);
197
198 if (!plane_state->visible)
199 continue;
200
201 i++;
202 }
203
204 vkms_state->active_planes = kcalloc(i, sizeof(plane), GFP_KERNEL);
205 if (!vkms_state->active_planes)
206 return -ENOMEM;
207 vkms_state->num_active_planes = i;
208
209 i = 0;
29b77ad7
MR
210 drm_for_each_plane_mask(plane, crtc->dev, crtc_state->plane_mask) {
211 plane_state = drm_atomic_get_existing_plane_state(crtc_state->state,
8b186587
DV
212 plane);
213
214 if (!plane_state->visible)
215 continue;
216
217 vkms_state->active_planes[i++] =
218 to_vkms_plane_state(plane_state);
219 }
220
221 return 0;
222}
223
3a070992 224static void vkms_crtc_atomic_enable(struct drm_crtc *crtc,
351f950d 225 struct drm_atomic_state *state)
3a070992
RS
226{
227 drm_crtc_vblank_on(crtc);
228}
229
230static void vkms_crtc_atomic_disable(struct drm_crtc *crtc,
351f950d 231 struct drm_atomic_state *state)
3a070992
RS
232{
233 drm_crtc_vblank_off(crtc);
234}
235
6c234fe3 236static void vkms_crtc_atomic_begin(struct drm_crtc *crtc,
f6ebe9f9 237 struct drm_atomic_state *state)
6c234fe3
HM
238{
239 struct vkms_output *vkms_output = drm_crtc_to_vkms_output(crtc);
240
241 /* This lock is held across the atomic commit to block vblank timer
a4e7e98e 242 * from scheduling vkms_composer_worker until the composer is updated
6c234fe3
HM
243 */
244 spin_lock_irq(&vkms_output->lock);
245}
246
3a070992 247static void vkms_crtc_atomic_flush(struct drm_crtc *crtc,
f6ebe9f9 248 struct drm_atomic_state *state)
3a070992 249{
6c234fe3 250 struct vkms_output *vkms_output = drm_crtc_to_vkms_output(crtc);
3a070992
RS
251
252 if (crtc->state->event) {
1c305e13 253 spin_lock(&crtc->dev->event_lock);
3a070992
RS
254
255 if (drm_crtc_vblank_get(crtc) != 0)
256 drm_crtc_send_vblank_event(crtc, crtc->state->event);
257 else
258 drm_crtc_arm_vblank_event(crtc, crtc->state->event);
259
1c305e13 260 spin_unlock(&crtc->dev->event_lock);
3a070992
RS
261
262 crtc->state->event = NULL;
263 }
6c234fe3 264
a4e7e98e 265 vkms_output->composer_state = to_vkms_crtc_state(crtc->state);
8b186587 266
6c234fe3 267 spin_unlock_irq(&vkms_output->lock);
3a070992
RS
268}
269
270static const struct drm_crtc_helper_funcs vkms_crtc_helper_funcs = {
8b186587 271 .atomic_check = vkms_crtc_atomic_check,
6c234fe3 272 .atomic_begin = vkms_crtc_atomic_begin,
3a070992
RS
273 .atomic_flush = vkms_crtc_atomic_flush,
274 .atomic_enable = vkms_crtc_atomic_enable,
275 .atomic_disable = vkms_crtc_atomic_disable,
854502fa
RS
276};
277
278int vkms_crtc_init(struct drm_device *dev, struct drm_crtc *crtc,
279 struct drm_plane *primary, struct drm_plane *cursor)
280{
6c234fe3 281 struct vkms_output *vkms_out = drm_crtc_to_vkms_output(crtc);
854502fa
RS
282 int ret;
283
99cc528e
MC
284 ret = drmm_crtc_init_with_planes(dev, crtc, primary, cursor,
285 &vkms_crtc_funcs, NULL);
854502fa
RS
286 if (ret) {
287 DRM_ERROR("Failed to init CRTC\n");
288 return ret;
289 }
290
3a070992
RS
291 drm_crtc_helper_add(crtc, &vkms_crtc_helper_funcs);
292
6c234fe3 293 spin_lock_init(&vkms_out->lock);
a4e7e98e 294 spin_lock_init(&vkms_out->composer_lock);
6c234fe3 295
a4e7e98e
RS
296 vkms_out->composer_workq = alloc_ordered_workqueue("vkms_composer", 0);
297 if (!vkms_out->composer_workq)
208c6e8c 298 return -ENOMEM;
6c234fe3 299
854502fa
RS
300 return ret;
301}