[linux-2.6-block.git] / drivers / gpu / drm / virtio / virtgpu_drv.h

/*
 * Copyright (C) 2015 Red Hat, Inc.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sublicense, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial
 * portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef VIRTIO_DRV_H
#define VIRTIO_DRV_H

#include <linux/virtio.h>
#include <linux/virtio_ids.h>
#include <linux/virtio_config.h>
#include <linux/virtio_gpu.h>

#include <drm/drmP.h>
#include <drm/drm_gem.h>
#include <drm/drm_atomic.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_encoder.h>
#include <drm/drm_fb_helper.h>
#include <drm/ttm/ttm_bo_api.h>
#include <drm/ttm/ttm_bo_driver.h>
#include <drm/ttm/ttm_placement.h>
#include <drm/ttm/ttm_module.h>

#define DRIVER_NAME "virtio_gpu"
#define DRIVER_DESC "virtio GPU"
#define DRIVER_DATE "0"

#define DRIVER_MAJOR 0
#define DRIVER_MINOR 1
#define DRIVER_PATCHLEVEL 0

/* virtgpu_drm_bus.c */
int drm_virtio_init(struct drm_driver *driver, struct virtio_device *vdev);

struct virtio_gpu_object {
	struct drm_gem_object gem_base;
	uint32_t hw_res_handle;

	struct sg_table *pages;
	uint32_t mapped;
	void *vmap;
	bool dumb;
	struct ttm_place                placement_code;
	struct ttm_placement		placement;
	struct ttm_buffer_object	tbo;
	struct ttm_bo_kmap_obj		kmap;
	bool created;
};
#define gem_to_virtio_gpu_obj(gobj) \
	container_of((gobj), struct virtio_gpu_object, gem_base)

struct virtio_gpu_vbuffer;
struct virtio_gpu_device;

typedef void (*virtio_gpu_resp_cb)(struct virtio_gpu_device *vgdev,
				   struct virtio_gpu_vbuffer *vbuf);

struct virtio_gpu_fence_driver {
	atomic64_t       last_seq;
	uint64_t         sync_seq;
	uint64_t         context;
	struct list_head fences;
	spinlock_t       lock;
};

struct virtio_gpu_fence {
	struct dma_fence f;
	struct virtio_gpu_fence_driver *drv;
	struct list_head node;
	uint64_t seq;
};
#define to_virtio_fence(x) \
	container_of(x, struct virtio_gpu_fence, f)

struct virtio_gpu_vbuffer {
	char *buf;
	int size;

	void *data_buf;
	uint32_t data_size;

	char *resp_buf;
	int resp_size;

	virtio_gpu_resp_cb resp_cb;

	struct list_head list;
};

struct virtio_gpu_output {
	int index;
	struct drm_crtc crtc;
	struct drm_connector conn;
	struct drm_encoder enc;
	struct virtio_gpu_display_one info;
	struct virtio_gpu_update_cursor cursor;
	struct edid *edid;
	int cur_x;
	int cur_y;
	bool enabled;
};
#define drm_crtc_to_virtio_gpu_output(x) \
	container_of(x, struct virtio_gpu_output, crtc)
#define drm_connector_to_virtio_gpu_output(x) \
	container_of(x, struct virtio_gpu_output, conn)
#define drm_encoder_to_virtio_gpu_output(x) \
	container_of(x, struct virtio_gpu_output, enc)

struct virtio_gpu_framebuffer {
	struct drm_framebuffer base;
	int x1, y1, x2, y2; /* dirty rect */
	spinlock_t dirty_lock;
	uint32_t hw_res_handle;
	struct virtio_gpu_fence *fence;
};
#define to_virtio_gpu_framebuffer(x) \
	container_of(x, struct virtio_gpu_framebuffer, base)

struct virtio_gpu_fbdev {
	struct drm_fb_helper           helper;
	struct virtio_gpu_framebuffer  vgfb;
	struct virtio_gpu_device       *vgdev;
	struct delayed_work            work;
};

struct virtio_gpu_mman {
	struct ttm_bo_device		bdev;
};

struct virtio_gpu_fbdev;

struct virtio_gpu_queue {
	struct virtqueue *vq;
	spinlock_t qlock;
	wait_queue_head_t ack_queue;
	struct work_struct dequeue_work;
};

struct virtio_gpu_drv_capset {
	uint32_t id;
	uint32_t max_version;
	uint32_t max_size;
};

struct virtio_gpu_drv_cap_cache {
	struct list_head head;
	void *caps_cache;
	uint32_t id;
	uint32_t version;
	uint32_t size;
	atomic_t is_valid;
};

struct virtio_gpu_device {
	struct device *dev;
	struct drm_device *ddev;

	struct virtio_device *vdev;

	struct virtio_gpu_mman mman;

	/* pointer to fbdev info structure */
	struct virtio_gpu_fbdev *vgfbdev;
	struct virtio_gpu_output outputs[VIRTIO_GPU_MAX_SCANOUTS];
	uint32_t num_scanouts;

	struct virtio_gpu_queue ctrlq;
	struct virtio_gpu_queue cursorq;
	struct kmem_cache *vbufs;
	bool vqs_ready;

	struct ida	resource_ida;

	wait_queue_head_t resp_wq;
	/* current display info */
	spinlock_t display_info_lock;
	bool display_info_pending;

	struct virtio_gpu_fence_driver fence_drv;

	struct ida	ctx_id_ida;

	bool has_virgl_3d;
	bool has_edid;

	struct work_struct config_changed_work;

	struct virtio_gpu_drv_capset *capsets;
	uint32_t num_capsets;
	struct list_head cap_cache;
};

struct virtio_gpu_fpriv {
	uint32_t ctx_id;
};

/* virtio_ioctl.c */
#define DRM_VIRTIO_NUM_IOCTLS 10
extern struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS];

/* virtio_kms.c */
int virtio_gpu_driver_load(struct drm_device *dev, unsigned long flags);
void virtio_gpu_driver_unload(struct drm_device *dev);
int virtio_gpu_driver_open(struct drm_device *dev, struct drm_file *file);
void virtio_gpu_driver_postclose(struct drm_device *dev, struct drm_file *file);

/* virtio_gem.c */
void virtio_gpu_gem_free_object(struct drm_gem_object *gem_obj);
int virtio_gpu_gem_init(struct virtio_gpu_device *vgdev);
void virtio_gpu_gem_fini(struct virtio_gpu_device *vgdev);
int virtio_gpu_gem_create(struct drm_file *file,
			  struct drm_device *dev,
			  uint64_t size,
			  struct drm_gem_object **obj_p,
			  uint32_t *handle_p);
int virtio_gpu_gem_object_open(struct drm_gem_object *obj,
			       struct drm_file *file);
void virtio_gpu_gem_object_close(struct drm_gem_object *obj,
				 struct drm_file *file);
struct virtio_gpu_object *virtio_gpu_alloc_object(struct drm_device *dev,
						  size_t size, bool kernel,
						  bool pinned);
int virtio_gpu_mode_dumb_create(struct drm_file *file_priv,
				struct drm_device *dev,
				struct drm_mode_create_dumb *args);
int virtio_gpu_mode_dumb_mmap(struct drm_file *file_priv,
			      struct drm_device *dev,
			      uint32_t handle, uint64_t *offset_p);

/* virtio_fb */
#define VIRTIO_GPUFB_CONN_LIMIT 1
int virtio_gpu_fbdev_init(struct virtio_gpu_device *vgdev);
void virtio_gpu_fbdev_fini(struct virtio_gpu_device *vgdev);
int virtio_gpu_surface_dirty(struct virtio_gpu_framebuffer *qfb,
			     struct drm_clip_rect *clips,
			     unsigned int num_clips);
/* virtio vg */
int virtio_gpu_alloc_vbufs(struct virtio_gpu_device *vgdev);
void virtio_gpu_free_vbufs(struct virtio_gpu_device *vgdev);
void virtio_gpu_cmd_create_resource(struct virtio_gpu_device *vgdev,
				    struct virtio_gpu_object *bo,
				    uint32_t format,
				    uint32_t width,
				    uint32_t height);
void virtio_gpu_cmd_unref_resource(struct virtio_gpu_device *vgdev,
				   uint32_t resource_id);
void virtio_gpu_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev,
					struct virtio_gpu_object *bo,
					uint64_t offset,
					__le32 width, __le32 height,
					__le32 x, __le32 y,
					struct virtio_gpu_fence *fence);
void virtio_gpu_cmd_resource_flush(struct virtio_gpu_device *vgdev,
				   uint32_t resource_id,
				   uint32_t x, uint32_t y,
				   uint32_t width, uint32_t height);
void virtio_gpu_cmd_set_scanout(struct virtio_gpu_device *vgdev,
				uint32_t scanout_id, uint32_t resource_id,
				uint32_t width, uint32_t height,
				uint32_t x, uint32_t y);
int virtio_gpu_object_attach(struct virtio_gpu_device *vgdev,
			     struct virtio_gpu_object *obj,
			     struct virtio_gpu_fence *fence);
void virtio_gpu_object_detach(struct virtio_gpu_device *vgdev,
			      struct virtio_gpu_object *obj);
int virtio_gpu_attach_status_page(struct virtio_gpu_device *vgdev);
int virtio_gpu_detach_status_page(struct virtio_gpu_device *vgdev);
void virtio_gpu_cursor_ping(struct virtio_gpu_device *vgdev,
			    struct virtio_gpu_output *output);
int virtio_gpu_cmd_get_display_info(struct virtio_gpu_device *vgdev);
int virtio_gpu_cmd_get_capset_info(struct virtio_gpu_device *vgdev, int idx);
int virtio_gpu_cmd_get_capset(struct virtio_gpu_device *vgdev,
			      int idx, int version,
			      struct virtio_gpu_drv_cap_cache **cache_p);
int virtio_gpu_cmd_get_edids(struct virtio_gpu_device *vgdev);
void virtio_gpu_cmd_context_create(struct virtio_gpu_device *vgdev, uint32_t id,
				   uint32_t nlen, const char *name);
void virtio_gpu_cmd_context_destroy(struct virtio_gpu_device *vgdev,
				    uint32_t id);
void virtio_gpu_cmd_context_attach_resource(struct virtio_gpu_device *vgdev,
					    uint32_t ctx_id,
					    uint32_t resource_id);
void virtio_gpu_cmd_context_detach_resource(struct virtio_gpu_device *vgdev,
					    uint32_t ctx_id,
					    uint32_t resource_id);
void virtio_gpu_cmd_submit(struct virtio_gpu_device *vgdev,
			   void *data, uint32_t data_size,
			   uint32_t ctx_id, struct virtio_gpu_fence *fence);
void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev,
					  uint32_t resource_id, uint32_t ctx_id,
					  uint64_t offset, uint32_t level,
					  struct virtio_gpu_box *box,
					  struct virtio_gpu_fence *fence);
void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,
					struct virtio_gpu_object *bo,
					uint32_t ctx_id,
					uint64_t offset, uint32_t level,
					struct virtio_gpu_box *box,
					struct virtio_gpu_fence *fence);
void
virtio_gpu_cmd_resource_create_3d(struct virtio_gpu_device *vgdev,
				  struct virtio_gpu_object *bo,
				  struct virtio_gpu_resource_create_3d *rc_3d);
void virtio_gpu_ctrl_ack(struct virtqueue *vq);
void virtio_gpu_cursor_ack(struct virtqueue *vq);
void virtio_gpu_fence_ack(struct virtqueue *vq);
void virtio_gpu_dequeue_ctrl_func(struct work_struct *work);
void virtio_gpu_dequeue_cursor_func(struct work_struct *work);
void virtio_gpu_dequeue_fence_func(struct work_struct *work);

/* virtio_gpu_display.c */
int virtio_gpu_framebuffer_init(struct drm_device *dev,
				struct virtio_gpu_framebuffer *vgfb,
				const struct drm_mode_fb_cmd2 *mode_cmd,
				struct drm_gem_object *obj);
int virtio_gpu_modeset_init(struct virtio_gpu_device *vgdev);
void virtio_gpu_modeset_fini(struct virtio_gpu_device *vgdev);

/* virtio_gpu_plane.c */
uint32_t virtio_gpu_translate_format(uint32_t drm_fourcc);
struct drm_plane *virtio_gpu_plane_init(struct virtio_gpu_device *vgdev,
					enum drm_plane_type type,
					int index);

/* virtio_gpu_ttm.c */
int virtio_gpu_ttm_init(struct virtio_gpu_device *vgdev);
void virtio_gpu_ttm_fini(struct virtio_gpu_device *vgdev);
int virtio_gpu_mmap(struct file *filp, struct vm_area_struct *vma);

/* virtio_gpu_fence.c */
struct virtio_gpu_fence *virtio_gpu_fence_alloc(
	struct virtio_gpu_device *vgdev);
void virtio_gpu_fence_cleanup(struct virtio_gpu_fence *fence);
int virtio_gpu_fence_emit(struct virtio_gpu_device *vgdev,
			  struct virtio_gpu_ctrl_hdr *cmd_hdr,
			  struct virtio_gpu_fence *fence);
void virtio_gpu_fence_event_process(struct virtio_gpu_device *vdev,
				    u64 last_seq);

/* virtio_gpu_object */
int virtio_gpu_object_create(struct virtio_gpu_device *vgdev,
			     unsigned long size, bool kernel, bool pinned,
			     struct virtio_gpu_object **bo_ptr);
void virtio_gpu_object_kunmap(struct virtio_gpu_object *bo);
int virtio_gpu_object_kmap(struct virtio_gpu_object *bo);
int virtio_gpu_object_get_sg_table(struct virtio_gpu_device *qdev,
				   struct virtio_gpu_object *bo);
void virtio_gpu_object_free_sg_table(struct virtio_gpu_object *bo);
int virtio_gpu_object_wait(struct virtio_gpu_object *bo, bool no_wait);

/* virtgpu_prime.c */
int virtgpu_gem_prime_pin(struct drm_gem_object *obj);
void virtgpu_gem_prime_unpin(struct drm_gem_object *obj);
void *virtgpu_gem_prime_vmap(struct drm_gem_object *obj);
void virtgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
int virtgpu_gem_prime_mmap(struct drm_gem_object *obj,
			   struct vm_area_struct *vma);

static inline struct virtio_gpu_object*
virtio_gpu_object_ref(struct virtio_gpu_object *bo)
{
	ttm_bo_get(&bo->tbo);
	return bo;
}

static inline void virtio_gpu_object_unref(struct virtio_gpu_object **bo)
{
	struct ttm_buffer_object *tbo;

	if ((*bo) == NULL)
		return;
	tbo = &((*bo)->tbo);
	ttm_bo_put(tbo);
	*bo = NULL;
}

static inline u64 virtio_gpu_object_mmap_offset(struct virtio_gpu_object *bo)
{
	return drm_vma_node_offset_addr(&bo->tbo.vma_node);
}

static inline int virtio_gpu_object_reserve(struct virtio_gpu_object *bo,
					 bool no_wait)
{
	int r;

	r = ttm_bo_reserve(&bo->tbo, true, no_wait, NULL);
	if (unlikely(r != 0)) {
		if (r != -ERESTARTSYS) {
			struct virtio_gpu_device *qdev =
				bo->gem_base.dev->dev_private;
			dev_err(qdev->dev, "%p reserve failed\n", bo);
		}
		return r;
	}
	return 0;
}

static inline void virtio_gpu_object_unreserve(struct virtio_gpu_object *bo)
{
	ttm_bo_unreserve(&bo->tbo);
}

/* virgl debufs */
int virtio_gpu_debugfs_init(struct drm_minor *minor);

#endif
Commit	Line	Data
dc5698e8 DA	1	/*
	2	* Copyright (C) 2015 Red Hat, Inc.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining
	6	* a copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sublicense, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* The above copyright notice and this permission notice (including the
	14	* next paragraph) shall be included in all copies or substantial
	15	* portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	18	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	19	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
	20	* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
	21	* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
	22	* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
	23	* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	24	*/
	25
	26	#ifndef VIRTIO_DRV_H
	27	#define VIRTIO_DRV_H
	28
	29	#include <linux/virtio.h>
	30	#include <linux/virtio_ids.h>
	31	#include <linux/virtio_config.h>
	32	#include <linux/virtio_gpu.h>
	33
	34	#include <drm/drmP.h>
	35	#include <drm/drm_gem.h>
e7cf0963	36	#include <drm/drm_atomic.h>
dc5698e8	37	#include <drm/drm_crtc_helper.h>
9338203c	38	#include <drm/drm_encoder.h>
8f44ca22	39	#include <drm/drm_fb_helper.h>
ff67a25d MY	40	#include <drm/ttm/ttm_bo_api.h>
	41	#include <drm/ttm/ttm_bo_driver.h>
	42	#include <drm/ttm/ttm_placement.h>
	43	#include <drm/ttm/ttm_module.h>
dc5698e8 DA	44
	45	#define DRIVER_NAME "virtio_gpu"
	46	#define DRIVER_DESC "virtio GPU"
	47	#define DRIVER_DATE "0"
	48
	49	#define DRIVER_MAJOR 0
68629652 GP	50	#define DRIVER_MINOR 1
68629652 GP	51	#define DRIVER_PATCHLEVEL 0
dc5698e8 DA	52
dc5698e8 DA	53	/* virtgpu_drm_bus.c */
dc5698e8 DA	54	int drm_virtio_init(struct drm_driver driver, struct virtio_device vdev);
	55
	56	struct virtio_gpu_object {
	57	struct drm_gem_object gem_base;
	58	uint32_t hw_res_handle;
	59
	60	struct sg_table *pages;
a3b815f0	61	uint32_t mapped;
dc5698e8 DA	62	void *vmap;
	63	bool dumb;
	64	struct ttm_place placement_code;
	65	struct ttm_placement placement;
	66	struct ttm_buffer_object tbo;
	67	struct ttm_bo_kmap_obj kmap;
23c897d7	68	bool created;
dc5698e8 DA	69	};
	70	#define gem_to_virtio_gpu_obj(gobj) \
	71	container_of((gobj), struct virtio_gpu_object, gem_base)
	72
	73	struct virtio_gpu_vbuffer;
	74	struct virtio_gpu_device;
	75
	76	typedef void (virtio_gpu_resp_cb)(struct virtio_gpu_device vgdev,
	77	struct virtio_gpu_vbuffer *vbuf);
	78
	79	struct virtio_gpu_fence_driver {
	80	atomic64_t last_seq;
	81	uint64_t sync_seq;
30b9c96c	82	uint64_t context;
dc5698e8 DA	83	struct list_head fences;
	84	spinlock_t lock;
	85	};
	86
	87	struct virtio_gpu_fence {
f54d1867	88	struct dma_fence f;
dc5698e8 DA	89	struct virtio_gpu_fence_driver *drv;
	90	struct list_head node;
	91	uint64_t seq;
	92	};
	93	#define to_virtio_fence(x) \
	94	container_of(x, struct virtio_gpu_fence, f)
	95
	96	struct virtio_gpu_vbuffer {
	97	char *buf;
	98	int size;
	99
	100	void *data_buf;
	101	uint32_t data_size;
	102
	103	char *resp_buf;
	104	int resp_size;
	105
	106	virtio_gpu_resp_cb resp_cb;
	107
	108	struct list_head list;
	109	};
	110
	111	struct virtio_gpu_output {
	112	int index;
	113	struct drm_crtc crtc;
	114	struct drm_connector conn;
	115	struct drm_encoder enc;
	116	struct virtio_gpu_display_one info;
	117	struct virtio_gpu_update_cursor cursor;
b4b01b49	118	struct edid *edid;
dc5698e8 DA	119	int cur_x;
dc5698e8 DA	120	int cur_y;
6c19787e	121	bool enabled;
dc5698e8 DA	122	};
	123	#define drm_crtc_to_virtio_gpu_output(x) \
	124	container_of(x, struct virtio_gpu_output, crtc)
	125	#define drm_connector_to_virtio_gpu_output(x) \
	126	container_of(x, struct virtio_gpu_output, conn)
	127	#define drm_encoder_to_virtio_gpu_output(x) \
	128	container_of(x, struct virtio_gpu_output, enc)
	129
	130	struct virtio_gpu_framebuffer {
	131	struct drm_framebuffer base;
dc5698e8 DA	132	int x1, y1, x2, y2; /* dirty rect */
	133	spinlock_t dirty_lock;
	134	uint32_t hw_res_handle;
9fdd90c0	135	struct virtio_gpu_fence *fence;
dc5698e8 DA	136	};
	137	#define to_virtio_gpu_framebuffer(x) \
	138	container_of(x, struct virtio_gpu_framebuffer, base)
	139
8f44ca22 JA	140	struct virtio_gpu_fbdev {
	141	struct drm_fb_helper helper;
	142	struct virtio_gpu_framebuffer vgfb;
	143	struct virtio_gpu_device *vgdev;
	144	struct delayed_work work;
	145	};
	146
dc5698e8	147	struct virtio_gpu_mman {
dc5698e8 DA	148	struct ttm_bo_device bdev;
	149	};
	150
	151	struct virtio_gpu_fbdev;
	152
	153	struct virtio_gpu_queue {
	154	struct virtqueue *vq;
	155	spinlock_t qlock;
	156	wait_queue_head_t ack_queue;
	157	struct work_struct dequeue_work;
	158	};
	159
62fb7a5e GH	160	struct virtio_gpu_drv_capset {
	161	uint32_t id;
	162	uint32_t max_version;
	163	uint32_t max_size;
	164	};
	165
	166	struct virtio_gpu_drv_cap_cache {
	167	struct list_head head;
	168	void *caps_cache;
	169	uint32_t id;
	170	uint32_t version;
	171	uint32_t size;
	172	atomic_t is_valid;
	173	};
	174
dc5698e8 DA	175	struct virtio_gpu_device {
	176	struct device *dev;
	177	struct drm_device *ddev;
	178
	179	struct virtio_device *vdev;
	180
	181	struct virtio_gpu_mman mman;
	182
	183	/* pointer to fbdev info structure */
	184	struct virtio_gpu_fbdev *vgfbdev;
	185	struct virtio_gpu_output outputs[VIRTIO_GPU_MAX_SCANOUTS];
	186	uint32_t num_scanouts;
	187
	188	struct virtio_gpu_queue ctrlq;
	189	struct virtio_gpu_queue cursorq;
f5985bf9	190	struct kmem_cache *vbufs;
dc5698e8 DA	191	bool vqs_ready;
dc5698e8 DA	192
1938d1ae	193	struct ida resource_ida;
dc5698e8 DA	194
	195	wait_queue_head_t resp_wq;
	196	/* current display info */
	197	spinlock_t display_info_lock;
441012af	198	bool display_info_pending;
dc5698e8 DA	199
	200	struct virtio_gpu_fence_driver fence_drv;
	201
1938d1ae	202	struct ida ctx_id_ida;
dc5698e8	203
62fb7a5e	204	bool has_virgl_3d;
b4b01b49	205	bool has_edid;
62fb7a5e	206
dc5698e8	207	struct work_struct config_changed_work;
62fb7a5e GH	208
	209	struct virtio_gpu_drv_capset *capsets;
	210	uint32_t num_capsets;
	211	struct list_head cap_cache;
dc5698e8 DA	212	};
	213
	214	struct virtio_gpu_fpriv {
	215	uint32_t ctx_id;
	216	};
	217
	218	/* virtio_ioctl.c */
	219	#define DRM_VIRTIO_NUM_IOCTLS 10
	220	extern struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS];
	221
	222	/* virtio_kms.c */
	223	int virtio_gpu_driver_load(struct drm_device *dev, unsigned long flags);
11b3c20b	224	void virtio_gpu_driver_unload(struct drm_device *dev);
62fb7a5e GH	225	int virtio_gpu_driver_open(struct drm_device dev, struct drm_file file);
62fb7a5e GH	226	void virtio_gpu_driver_postclose(struct drm_device dev, struct drm_file file);
dc5698e8 DA	227
	228	/* virtio_gem.c */
	229	void virtio_gpu_gem_free_object(struct drm_gem_object *gem_obj);
	230	int virtio_gpu_gem_init(struct virtio_gpu_device *vgdev);
	231	void virtio_gpu_gem_fini(struct virtio_gpu_device *vgdev);
	232	int virtio_gpu_gem_create(struct drm_file *file,
	233	struct drm_device *dev,
	234	uint64_t size,
	235	struct drm_gem_object **obj_p,
	236	uint32_t *handle_p);
62fb7a5e GH	237	int virtio_gpu_gem_object_open(struct drm_gem_object *obj,
	238	struct drm_file *file);
	239	void virtio_gpu_gem_object_close(struct drm_gem_object *obj,
	240	struct drm_file *file);
dc5698e8 DA	241	struct virtio_gpu_object virtio_gpu_alloc_object(struct drm_device dev,
	242	size_t size, bool kernel,
	243	bool pinned);
	244	int virtio_gpu_mode_dumb_create(struct drm_file *file_priv,
	245	struct drm_device *dev,
	246	struct drm_mode_create_dumb *args);
dc5698e8 DA	247	int virtio_gpu_mode_dumb_mmap(struct drm_file *file_priv,
	248	struct drm_device *dev,
	249	uint32_t handle, uint64_t *offset_p);
	250
	251	/* virtio_fb */
	252	#define VIRTIO_GPUFB_CONN_LIMIT 1
	253	int virtio_gpu_fbdev_init(struct virtio_gpu_device *vgdev);
	254	void virtio_gpu_fbdev_fini(struct virtio_gpu_device *vgdev);
	255	int virtio_gpu_surface_dirty(struct virtio_gpu_framebuffer *qfb,
	256	struct drm_clip_rect *clips,
dc31b3b7	257	unsigned int num_clips);
dc5698e8 DA	258	/* virtio vg */
	259	int virtio_gpu_alloc_vbufs(struct virtio_gpu_device *vgdev);
	260	void virtio_gpu_free_vbufs(struct virtio_gpu_device *vgdev);
dc5698e8	261	void virtio_gpu_cmd_create_resource(struct virtio_gpu_device *vgdev,
23c897d7	262	struct virtio_gpu_object *bo,
dc5698e8 DA	263	uint32_t format,
	264	uint32_t width,
	265	uint32_t height);
	266	void virtio_gpu_cmd_unref_resource(struct virtio_gpu_device *vgdev,
	267	uint32_t resource_id);
	268	void virtio_gpu_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev,
af334c5d GH	269	struct virtio_gpu_object *bo,
af334c5d GH	270	uint64_t offset,
dc5698e8 DA	271	__le32 width, __le32 height,
dc5698e8 DA	272	__le32 x, __le32 y,
4d55fd66	273	struct virtio_gpu_fence *fence);
dc5698e8 DA	274	void virtio_gpu_cmd_resource_flush(struct virtio_gpu_device *vgdev,
	275	uint32_t resource_id,
	276	uint32_t x, uint32_t y,
	277	uint32_t width, uint32_t height);
	278	void virtio_gpu_cmd_set_scanout(struct virtio_gpu_device *vgdev,
	279	uint32_t scanout_id, uint32_t resource_id,
	280	uint32_t width, uint32_t height,
	281	uint32_t x, uint32_t y);
	282	int virtio_gpu_object_attach(struct virtio_gpu_device *vgdev,
	283	struct virtio_gpu_object *obj,
4d55fd66	284	struct virtio_gpu_fence *fence);
b3f13ec9 GH	285	void virtio_gpu_object_detach(struct virtio_gpu_device *vgdev,
b3f13ec9 GH	286	struct virtio_gpu_object *obj);
dc5698e8 DA	287	int virtio_gpu_attach_status_page(struct virtio_gpu_device *vgdev);
	288	int virtio_gpu_detach_status_page(struct virtio_gpu_device *vgdev);
	289	void virtio_gpu_cursor_ping(struct virtio_gpu_device *vgdev,
	290	struct virtio_gpu_output *output);
	291	int virtio_gpu_cmd_get_display_info(struct virtio_gpu_device *vgdev);
62fb7a5e GH	292	int virtio_gpu_cmd_get_capset_info(struct virtio_gpu_device *vgdev, int idx);
	293	int virtio_gpu_cmd_get_capset(struct virtio_gpu_device *vgdev,
	294	int idx, int version,
	295	struct virtio_gpu_drv_cap_cache **cache_p);
b4b01b49	296	int virtio_gpu_cmd_get_edids(struct virtio_gpu_device *vgdev);
62fb7a5e GH	297	void virtio_gpu_cmd_context_create(struct virtio_gpu_device *vgdev, uint32_t id,
	298	uint32_t nlen, const char *name);
	299	void virtio_gpu_cmd_context_destroy(struct virtio_gpu_device *vgdev,
	300	uint32_t id);
	301	void virtio_gpu_cmd_context_attach_resource(struct virtio_gpu_device *vgdev,
	302	uint32_t ctx_id,
	303	uint32_t resource_id);
	304	void virtio_gpu_cmd_context_detach_resource(struct virtio_gpu_device *vgdev,
	305	uint32_t ctx_id,
	306	uint32_t resource_id);
	307	void virtio_gpu_cmd_submit(struct virtio_gpu_device *vgdev,
	308	void *data, uint32_t data_size,
4d55fd66	309	uint32_t ctx_id, struct virtio_gpu_fence *fence);
62fb7a5e GH	310	void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev,
	311	uint32_t resource_id, uint32_t ctx_id,
	312	uint64_t offset, uint32_t level,
	313	struct virtio_gpu_box *box,
4d55fd66	314	struct virtio_gpu_fence *fence);
62fb7a5e	315	void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,
af334c5d GH	316	struct virtio_gpu_object *bo,
af334c5d GH	317	uint32_t ctx_id,
62fb7a5e GH	318	uint64_t offset, uint32_t level,
62fb7a5e GH	319	struct virtio_gpu_box *box,
4d55fd66	320	struct virtio_gpu_fence *fence);
62fb7a5e GH	321	void
62fb7a5e GH	322	virtio_gpu_cmd_resource_create_3d(struct virtio_gpu_device *vgdev,
23c897d7	323	struct virtio_gpu_object *bo,
d7a86dff	324	struct virtio_gpu_resource_create_3d *rc_3d);
dc5698e8 DA	325	void virtio_gpu_ctrl_ack(struct virtqueue *vq);
dc5698e8 DA	326	void virtio_gpu_cursor_ack(struct virtqueue *vq);
62fb7a5e	327	void virtio_gpu_fence_ack(struct virtqueue *vq);
dc5698e8 DA	328	void virtio_gpu_dequeue_ctrl_func(struct work_struct *work);
dc5698e8 DA	329	void virtio_gpu_dequeue_cursor_func(struct work_struct *work);
62fb7a5e	330	void virtio_gpu_dequeue_fence_func(struct work_struct *work);
dc5698e8 DA	331
	332	/* virtio_gpu_display.c */
	333	int virtio_gpu_framebuffer_init(struct drm_device *dev,
	334	struct virtio_gpu_framebuffer *vgfb,
1eb83451	335	const struct drm_mode_fb_cmd2 *mode_cmd,
dc5698e8 DA	336	struct drm_gem_object *obj);
	337	int virtio_gpu_modeset_init(struct virtio_gpu_device *vgdev);
	338	void virtio_gpu_modeset_fini(struct virtio_gpu_device *vgdev);
	339
	340	/* virtio_gpu_plane.c */
d519cb76	341	uint32_t virtio_gpu_translate_format(uint32_t drm_fourcc);
dc5698e8	342	struct drm_plane virtio_gpu_plane_init(struct virtio_gpu_device vgdev,
bbbed888	343	enum drm_plane_type type,
dc5698e8 DA	344	int index);
	345
	346	/* virtio_gpu_ttm.c */
	347	int virtio_gpu_ttm_init(struct virtio_gpu_device *vgdev);
	348	void virtio_gpu_ttm_fini(struct virtio_gpu_device *vgdev);
	349	int virtio_gpu_mmap(struct file filp, struct vm_area_struct vma);
	350
	351	/* virtio_gpu_fence.c */
9fdd90c0 RF	352	struct virtio_gpu_fence *virtio_gpu_fence_alloc(
	353	struct virtio_gpu_device *vgdev);
	354	void virtio_gpu_fence_cleanup(struct virtio_gpu_fence *fence);
dc5698e8 DA	355	int virtio_gpu_fence_emit(struct virtio_gpu_device *vgdev,
dc5698e8 DA	356	struct virtio_gpu_ctrl_hdr *cmd_hdr,
4d55fd66	357	struct virtio_gpu_fence *fence);
dc5698e8 DA	358	void virtio_gpu_fence_event_process(struct virtio_gpu_device *vdev,
	359	u64 last_seq);
	360
	361	/* virtio_gpu_object */
	362	int virtio_gpu_object_create(struct virtio_gpu_device *vgdev,
	363	unsigned long size, bool kernel, bool pinned,
	364	struct virtio_gpu_object **bo_ptr);
02c87cab	365	void virtio_gpu_object_kunmap(struct virtio_gpu_object *bo);
a20c4173	366	int virtio_gpu_object_kmap(struct virtio_gpu_object *bo);
dc5698e8 DA	367	int virtio_gpu_object_get_sg_table(struct virtio_gpu_device *qdev,
	368	struct virtio_gpu_object *bo);
	369	void virtio_gpu_object_free_sg_table(struct virtio_gpu_object *bo);
	370	int virtio_gpu_object_wait(struct virtio_gpu_object *bo, bool no_wait);
	371
11a8f280 DA	372	/* virtgpu_prime.c */
	373	int virtgpu_gem_prime_pin(struct drm_gem_object *obj);
	374	void virtgpu_gem_prime_unpin(struct drm_gem_object *obj);
11a8f280 DA	375	void virtgpu_gem_prime_vmap(struct drm_gem_object obj);
	376	void virtgpu_gem_prime_vunmap(struct drm_gem_object obj, void vaddr);
	377	int virtgpu_gem_prime_mmap(struct drm_gem_object *obj,
1858b856	378	struct vm_area_struct *vma);
11a8f280	379
dc5698e8 DA	380	static inline struct virtio_gpu_object*
	381	virtio_gpu_object_ref(struct virtio_gpu_object *bo)
	382	{
94f4a127	383	ttm_bo_get(&bo->tbo);
dc5698e8 DA	384	return bo;
	385	}
	386
	387	static inline void virtio_gpu_object_unref(struct virtio_gpu_object **bo)
	388	{
	389	struct ttm_buffer_object *tbo;
	390
	391	if ((*bo) == NULL)
	392	return;
	393	tbo = &((*bo)->tbo);
0e7a3d4b TZ	394	ttm_bo_put(tbo);
0e7a3d4b TZ	395	*bo = NULL;
dc5698e8 DA	396	}
	397
	398	static inline u64 virtio_gpu_object_mmap_offset(struct virtio_gpu_object *bo)
	399	{
	400	return drm_vma_node_offset_addr(&bo->tbo.vma_node);
	401	}
	402
	403	static inline int virtio_gpu_object_reserve(struct virtio_gpu_object *bo,
	404	bool no_wait)
	405	{
	406	int r;
	407
dfd5e50e	408	r = ttm_bo_reserve(&bo->tbo, true, no_wait, NULL);
dc5698e8 DA	409	if (unlikely(r != 0)) {
	410	if (r != -ERESTARTSYS) {
	411	struct virtio_gpu_device *qdev =
	412	bo->gem_base.dev->dev_private;
	413	dev_err(qdev->dev, "%p reserve failed\n", bo);
	414	}
	415	return r;
	416	}
	417	return 0;
	418	}
	419
	420	static inline void virtio_gpu_object_unreserve(struct virtio_gpu_object *bo)
	421	{
	422	ttm_bo_unreserve(&bo->tbo);
	423	}
	424
	425	/* virgl debufs */
	426	int virtio_gpu_debugfs_init(struct drm_minor *minor);
dc5698e8 DA	427
dc5698e8 DA	428	#endif