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22f579c6 DA |
1 | /* via_irq.c |
2 | * | |
3 | * Copyright 2004 BEAM Ltd. | |
4 | * Copyright 2002 Tungsten Graphics, Inc. | |
5 | * Copyright 2005 Thomas Hellstrom. | |
6 | * All Rights Reserved. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the "Software"), | |
10 | * to deal in the Software without restriction, including without limitation | |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
12 | * and/or sell copies of the Software, and to permit persons to whom the | |
13 | * Software is furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the next | |
16 | * paragraph) shall be included in all copies or substantial portions of the | |
17 | * Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
22 | * BEAM LTD, TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
23 | * DAMAGES OR | |
24 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
25 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
26 | * DEALINGS IN THE SOFTWARE. | |
27 | * | |
28 | * Authors: | |
29 | * Terry Barnaby <terry1@beam.ltd.uk> | |
30 | * Keith Whitwell <keith@tungstengraphics.com> | |
31 | * Thomas Hellstrom <unichrome@shipmail.org> | |
32 | * | |
33 | * This code provides standard DRM access to the Via Unichrome / Pro Vertical blank | |
34 | * interrupt, as well as an infrastructure to handle other interrupts of the chip. | |
35 | * The refresh rate is also calculated for video playback sync purposes. | |
36 | */ | |
37 | ||
760285e7 DH |
38 | #include <drm/drmP.h> |
39 | #include <drm/via_drm.h> | |
22f579c6 DA |
40 | #include "via_drv.h" |
41 | ||
42 | #define VIA_REG_INTERRUPT 0x200 | |
43 | ||
44 | /* VIA_REG_INTERRUPT */ | |
0a3e67a4 | 45 | #define VIA_IRQ_GLOBAL (1 << 31) |
22f579c6 DA |
46 | #define VIA_IRQ_VBLANK_ENABLE (1 << 19) |
47 | #define VIA_IRQ_VBLANK_PENDING (1 << 3) | |
48 | #define VIA_IRQ_HQV0_ENABLE (1 << 11) | |
49 | #define VIA_IRQ_HQV1_ENABLE (1 << 25) | |
50 | #define VIA_IRQ_HQV0_PENDING (1 << 9) | |
51 | #define VIA_IRQ_HQV1_PENDING (1 << 10) | |
92514243 DA |
52 | #define VIA_IRQ_DMA0_DD_ENABLE (1 << 20) |
53 | #define VIA_IRQ_DMA0_TD_ENABLE (1 << 21) | |
54 | #define VIA_IRQ_DMA1_DD_ENABLE (1 << 22) | |
55 | #define VIA_IRQ_DMA1_TD_ENABLE (1 << 23) | |
56 | #define VIA_IRQ_DMA0_DD_PENDING (1 << 4) | |
57 | #define VIA_IRQ_DMA0_TD_PENDING (1 << 5) | |
58 | #define VIA_IRQ_DMA1_DD_PENDING (1 << 6) | |
59 | #define VIA_IRQ_DMA1_TD_PENDING (1 << 7) | |
60 | ||
22f579c6 DA |
61 | |
62 | /* | |
63 | * Device-specific IRQs go here. This type might need to be extended with | |
64 | * the register if there are multiple IRQ control registers. | |
b5e89ed5 | 65 | * Currently we activate the HQV interrupts of Unichrome Pro group A. |
22f579c6 DA |
66 | */ |
67 | ||
68 | static maskarray_t via_pro_group_a_irqs[] = { | |
b5e89ed5 | 69 | {VIA_IRQ_HQV0_ENABLE, VIA_IRQ_HQV0_PENDING, 0x000003D0, 0x00008010, |
0a3e67a4 | 70 | 0x00000000 }, |
b5e89ed5 | 71 | {VIA_IRQ_HQV1_ENABLE, VIA_IRQ_HQV1_PENDING, 0x000013D0, 0x00008010, |
0a3e67a4 | 72 | 0x00000000 }, |
92514243 DA |
73 | {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0, |
74 | VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008}, | |
75 | {VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1, | |
76 | VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008}, | |
b5e89ed5 | 77 | }; |
0a3e67a4 | 78 | static int via_num_pro_group_a = ARRAY_SIZE(via_pro_group_a_irqs); |
92514243 | 79 | static int via_irqmap_pro_group_a[] = {0, 1, -1, 2, -1, 3}; |
b5e89ed5 | 80 | |
92514243 DA |
81 | static maskarray_t via_unichrome_irqs[] = { |
82 | {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0, | |
83 | VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008}, | |
84 | {VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1, | |
85 | VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008} | |
86 | }; | |
0a3e67a4 | 87 | static int via_num_unichrome = ARRAY_SIZE(via_unichrome_irqs); |
92514243 | 88 | static int via_irqmap_unichrome[] = {-1, -1, -1, 0, -1, 1}; |
b5e89ed5 | 89 | |
0a3e67a4 | 90 | |
b5e89ed5 | 91 | static unsigned time_diff(struct timeval *now, struct timeval *then) |
22f579c6 | 92 | { |
b5e89ed5 | 93 | return (now->tv_usec >= then->tv_usec) ? |
0a3e67a4 JB |
94 | now->tv_usec - then->tv_usec : |
95 | 1000000 - (then->tv_usec - now->tv_usec); | |
96 | } | |
97 | ||
98 | u32 via_get_vblank_counter(struct drm_device *dev, int crtc) | |
99 | { | |
100 | drm_via_private_t *dev_priv = dev->dev_private; | |
101 | if (crtc != 0) | |
102 | return 0; | |
103 | ||
104 | return atomic_read(&dev_priv->vbl_received); | |
22f579c6 DA |
105 | } |
106 | ||
107 | irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS) | |
108 | { | |
84b1fd10 | 109 | struct drm_device *dev = (struct drm_device *) arg; |
22f579c6 DA |
110 | drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; |
111 | u32 status; | |
112 | int handled = 0; | |
113 | struct timeval cur_vblank; | |
114 | drm_via_irq_t *cur_irq = dev_priv->via_irqs; | |
115 | int i; | |
116 | ||
117 | status = VIA_READ(VIA_REG_INTERRUPT); | |
118 | if (status & VIA_IRQ_VBLANK_PENDING) { | |
0a3e67a4 JB |
119 | atomic_inc(&dev_priv->vbl_received); |
120 | if (!(atomic_read(&dev_priv->vbl_received) & 0x0F)) { | |
22f579c6 | 121 | do_gettimeofday(&cur_vblank); |
b5e89ed5 DA |
122 | if (dev_priv->last_vblank_valid) { |
123 | dev_priv->usec_per_vblank = | |
0a3e67a4 JB |
124 | time_diff(&cur_vblank, |
125 | &dev_priv->last_vblank) >> 4; | |
22f579c6 DA |
126 | } |
127 | dev_priv->last_vblank = cur_vblank; | |
128 | dev_priv->last_vblank_valid = 1; | |
b5e89ed5 | 129 | } |
0a3e67a4 | 130 | if (!(atomic_read(&dev_priv->vbl_received) & 0xFF)) { |
22f579c6 | 131 | DRM_DEBUG("US per vblank is: %u\n", |
b5e89ed5 | 132 | dev_priv->usec_per_vblank); |
22f579c6 | 133 | } |
0a3e67a4 | 134 | drm_handle_vblank(dev, 0); |
22f579c6 DA |
135 | handled = 1; |
136 | } | |
22f579c6 | 137 | |
b5e89ed5 | 138 | for (i = 0; i < dev_priv->num_irqs; ++i) { |
22f579c6 | 139 | if (status & cur_irq->pending_mask) { |
b5e89ed5 DA |
140 | atomic_inc(&cur_irq->irq_received); |
141 | DRM_WAKEUP(&cur_irq->irq_queue); | |
22f579c6 | 142 | handled = 1; |
58c1e85a | 143 | if (dev_priv->irq_map[drm_via_irq_dma0_td] == i) |
92514243 | 144 | via_dmablit_handler(dev, 0, 1); |
58c1e85a | 145 | else if (dev_priv->irq_map[drm_via_irq_dma1_td] == i) |
92514243 | 146 | via_dmablit_handler(dev, 1, 1); |
22f579c6 DA |
147 | } |
148 | cur_irq++; | |
149 | } | |
b5e89ed5 | 150 | |
3ad2f3fb | 151 | /* Acknowledge interrupts */ |
22f579c6 DA |
152 | VIA_WRITE(VIA_REG_INTERRUPT, status); |
153 | ||
0a3e67a4 | 154 | |
22f579c6 DA |
155 | if (handled) |
156 | return IRQ_HANDLED; | |
157 | else | |
158 | return IRQ_NONE; | |
159 | } | |
160 | ||
58c1e85a | 161 | static __inline__ void viadrv_acknowledge_irqs(drm_via_private_t *dev_priv) |
22f579c6 DA |
162 | { |
163 | u32 status; | |
164 | ||
165 | if (dev_priv) { | |
3ad2f3fb | 166 | /* Acknowledge interrupts */ |
22f579c6 | 167 | status = VIA_READ(VIA_REG_INTERRUPT); |
b5e89ed5 | 168 | VIA_WRITE(VIA_REG_INTERRUPT, status | |
22f579c6 DA |
169 | dev_priv->irq_pending_mask); |
170 | } | |
171 | } | |
172 | ||
0a3e67a4 | 173 | int via_enable_vblank(struct drm_device *dev, int crtc) |
22f579c6 | 174 | { |
0a3e67a4 JB |
175 | drm_via_private_t *dev_priv = dev->dev_private; |
176 | u32 status; | |
22f579c6 | 177 | |
0a3e67a4 JB |
178 | if (crtc != 0) { |
179 | DRM_ERROR("%s: bad crtc %d\n", __func__, crtc); | |
22f579c6 DA |
180 | return -EINVAL; |
181 | } | |
182 | ||
0a3e67a4 | 183 | status = VIA_READ(VIA_REG_INTERRUPT); |
42dd8619 | 184 | VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_VBLANK_ENABLE); |
0a3e67a4 JB |
185 | |
186 | VIA_WRITE8(0x83d4, 0x11); | |
187 | VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30); | |
22f579c6 | 188 | |
0a3e67a4 JB |
189 | return 0; |
190 | } | |
22f579c6 | 191 | |
0a3e67a4 JB |
192 | void via_disable_vblank(struct drm_device *dev, int crtc) |
193 | { | |
194 | drm_via_private_t *dev_priv = dev->dev_private; | |
42dd8619 SF |
195 | u32 status; |
196 | ||
197 | status = VIA_READ(VIA_REG_INTERRUPT); | |
198 | VIA_WRITE(VIA_REG_INTERRUPT, status & ~VIA_IRQ_VBLANK_ENABLE); | |
b5e89ed5 | 199 | |
0a3e67a4 JB |
200 | VIA_WRITE8(0x83d4, 0x11); |
201 | VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30); | |
202 | ||
203 | if (crtc != 0) | |
204 | DRM_ERROR("%s: bad crtc %d\n", __func__, crtc); | |
22f579c6 DA |
205 | } |
206 | ||
ce60fe02 | 207 | static int |
58c1e85a | 208 | via_driver_irq_wait(struct drm_device *dev, unsigned int irq, int force_sequence, |
22f579c6 DA |
209 | unsigned int *sequence) |
210 | { | |
211 | drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; | |
212 | unsigned int cur_irq_sequence; | |
d253258c | 213 | drm_via_irq_t *cur_irq; |
22f579c6 | 214 | int ret = 0; |
86678dfd | 215 | maskarray_t *masks; |
92514243 | 216 | int real_irq; |
22f579c6 | 217 | |
3e684eae | 218 | DRM_DEBUG("\n"); |
22f579c6 DA |
219 | |
220 | if (!dev_priv) { | |
3e684eae | 221 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 222 | return -EINVAL; |
22f579c6 DA |
223 | } |
224 | ||
92514243 | 225 | if (irq >= drm_via_irq_num) { |
3e684eae | 226 | DRM_ERROR("Trying to wait on unknown irq %d\n", irq); |
20caafa6 | 227 | return -EINVAL; |
22f579c6 | 228 | } |
b5e89ed5 | 229 | |
92514243 DA |
230 | real_irq = dev_priv->irq_map[irq]; |
231 | ||
232 | if (real_irq < 0) { | |
3e684eae MN |
233 | DRM_ERROR("Video IRQ %d not available on this hardware.\n", |
234 | irq); | |
20caafa6 | 235 | return -EINVAL; |
92514243 | 236 | } |
86678dfd DA |
237 | |
238 | masks = dev_priv->irq_masks; | |
d253258c | 239 | cur_irq = dev_priv->via_irqs + real_irq; |
22f579c6 | 240 | |
92514243 | 241 | if (masks[real_irq][2] && !force_sequence) { |
22f579c6 | 242 | DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ, |
b5e89ed5 DA |
243 | ((VIA_READ(masks[irq][2]) & masks[irq][3]) == |
244 | masks[irq][4])); | |
22f579c6 DA |
245 | cur_irq_sequence = atomic_read(&cur_irq->irq_received); |
246 | } else { | |
247 | DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ, | |
b5e89ed5 DA |
248 | (((cur_irq_sequence = |
249 | atomic_read(&cur_irq->irq_received)) - | |
250 | *sequence) <= (1 << 23))); | |
22f579c6 DA |
251 | } |
252 | *sequence = cur_irq_sequence; | |
253 | return ret; | |
254 | } | |
255 | ||
0a3e67a4 | 256 | |
22f579c6 DA |
257 | /* |
258 | * drm_dma.h hooks | |
259 | */ | |
260 | ||
58c1e85a | 261 | void via_driver_irq_preinstall(struct drm_device *dev) |
22f579c6 DA |
262 | { |
263 | drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; | |
264 | u32 status; | |
d253258c | 265 | drm_via_irq_t *cur_irq; |
22f579c6 DA |
266 | int i; |
267 | ||
3e684eae | 268 | DRM_DEBUG("dev_priv: %p\n", dev_priv); |
22f579c6 | 269 | if (dev_priv) { |
d253258c | 270 | cur_irq = dev_priv->via_irqs; |
22f579c6 DA |
271 | |
272 | dev_priv->irq_enable_mask = VIA_IRQ_VBLANK_ENABLE; | |
273 | dev_priv->irq_pending_mask = VIA_IRQ_VBLANK_PENDING; | |
274 | ||
689692e7 TH |
275 | if (dev_priv->chipset == VIA_PRO_GROUP_A || |
276 | dev_priv->chipset == VIA_DX9_0) { | |
277 | dev_priv->irq_masks = via_pro_group_a_irqs; | |
278 | dev_priv->num_irqs = via_num_pro_group_a; | |
279 | dev_priv->irq_map = via_irqmap_pro_group_a; | |
280 | } else { | |
281 | dev_priv->irq_masks = via_unichrome_irqs; | |
282 | dev_priv->num_irqs = via_num_unichrome; | |
283 | dev_priv->irq_map = via_irqmap_unichrome; | |
284 | } | |
b5e89ed5 DA |
285 | |
286 | for (i = 0; i < dev_priv->num_irqs; ++i) { | |
22f579c6 | 287 | atomic_set(&cur_irq->irq_received, 0); |
b5e89ed5 | 288 | cur_irq->enable_mask = dev_priv->irq_masks[i][0]; |
22f579c6 | 289 | cur_irq->pending_mask = dev_priv->irq_masks[i][1]; |
b5e89ed5 | 290 | DRM_INIT_WAITQUEUE(&cur_irq->irq_queue); |
22f579c6 DA |
291 | dev_priv->irq_enable_mask |= cur_irq->enable_mask; |
292 | dev_priv->irq_pending_mask |= cur_irq->pending_mask; | |
293 | cur_irq++; | |
b5e89ed5 | 294 | |
22f579c6 DA |
295 | DRM_DEBUG("Initializing IRQ %d\n", i); |
296 | } | |
b5e89ed5 DA |
297 | |
298 | dev_priv->last_vblank_valid = 0; | |
22f579c6 | 299 | |
92514243 | 300 | /* Clear VSync interrupt regs */ |
22f579c6 | 301 | status = VIA_READ(VIA_REG_INTERRUPT); |
b5e89ed5 | 302 | VIA_WRITE(VIA_REG_INTERRUPT, status & |
22f579c6 | 303 | ~(dev_priv->irq_enable_mask)); |
b5e89ed5 | 304 | |
22f579c6 DA |
305 | /* Clear bits if they're already high */ |
306 | viadrv_acknowledge_irqs(dev_priv); | |
307 | } | |
308 | } | |
309 | ||
0a3e67a4 | 310 | int via_driver_irq_postinstall(struct drm_device *dev) |
22f579c6 DA |
311 | { |
312 | drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; | |
313 | u32 status; | |
314 | ||
0a3e67a4 JB |
315 | DRM_DEBUG("via_driver_irq_postinstall\n"); |
316 | if (!dev_priv) | |
317 | return -EINVAL; | |
22f579c6 | 318 | |
0a3e67a4 JB |
319 | status = VIA_READ(VIA_REG_INTERRUPT); |
320 | VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_GLOBAL | |
321 | | dev_priv->irq_enable_mask); | |
22f579c6 | 322 | |
0a3e67a4 JB |
323 | /* Some magic, oh for some data sheets ! */ |
324 | VIA_WRITE8(0x83d4, 0x11); | |
325 | VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30); | |
b5e89ed5 | 326 | |
0a3e67a4 | 327 | return 0; |
22f579c6 DA |
328 | } |
329 | ||
58c1e85a | 330 | void via_driver_irq_uninstall(struct drm_device *dev) |
22f579c6 DA |
331 | { |
332 | drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; | |
333 | u32 status; | |
334 | ||
3e684eae | 335 | DRM_DEBUG("\n"); |
22f579c6 DA |
336 | if (dev_priv) { |
337 | ||
338 | /* Some more magic, oh for some data sheets ! */ | |
339 | ||
340 | VIA_WRITE8(0x83d4, 0x11); | |
341 | VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30); | |
342 | ||
343 | status = VIA_READ(VIA_REG_INTERRUPT); | |
b5e89ed5 | 344 | VIA_WRITE(VIA_REG_INTERRUPT, status & |
22f579c6 DA |
345 | ~(VIA_IRQ_VBLANK_ENABLE | dev_priv->irq_enable_mask)); |
346 | } | |
347 | } | |
348 | ||
c153f45f | 349 | int via_wait_irq(struct drm_device *dev, void *data, struct drm_file *file_priv) |
22f579c6 | 350 | { |
c153f45f | 351 | drm_via_irqwait_t *irqwait = data; |
22f579c6 DA |
352 | struct timeval now; |
353 | int ret = 0; | |
354 | drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; | |
355 | drm_via_irq_t *cur_irq = dev_priv->via_irqs; | |
356 | int force_sequence; | |
357 | ||
c153f45f | 358 | if (irqwait->request.irq >= dev_priv->num_irqs) { |
3e684eae | 359 | DRM_ERROR("Trying to wait on unknown irq %d\n", |
c153f45f | 360 | irqwait->request.irq); |
20caafa6 | 361 | return -EINVAL; |
22f579c6 DA |
362 | } |
363 | ||
c153f45f | 364 | cur_irq += irqwait->request.irq; |
22f579c6 | 365 | |
c153f45f | 366 | switch (irqwait->request.type & ~VIA_IRQ_FLAGS_MASK) { |
22f579c6 | 367 | case VIA_IRQ_RELATIVE: |
0a3e67a4 JB |
368 | irqwait->request.sequence += |
369 | atomic_read(&cur_irq->irq_received); | |
c153f45f | 370 | irqwait->request.type &= ~_DRM_VBLANK_RELATIVE; |
22f579c6 DA |
371 | case VIA_IRQ_ABSOLUTE: |
372 | break; | |
373 | default: | |
20caafa6 | 374 | return -EINVAL; |
22f579c6 DA |
375 | } |
376 | ||
c153f45f | 377 | if (irqwait->request.type & VIA_IRQ_SIGNAL) { |
3e684eae | 378 | DRM_ERROR("Signals on Via IRQs not implemented yet.\n"); |
20caafa6 | 379 | return -EINVAL; |
22f579c6 DA |
380 | } |
381 | ||
c153f45f | 382 | force_sequence = (irqwait->request.type & VIA_IRQ_FORCE_SEQUENCE); |
22f579c6 | 383 | |
c153f45f EA |
384 | ret = via_driver_irq_wait(dev, irqwait->request.irq, force_sequence, |
385 | &irqwait->request.sequence); | |
22f579c6 | 386 | do_gettimeofday(&now); |
c153f45f EA |
387 | irqwait->reply.tval_sec = now.tv_sec; |
388 | irqwait->reply.tval_usec = now.tv_usec; | |
22f579c6 DA |
389 | |
390 | return ret; | |
391 | } |