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drm/vc4: prepare for CEC support
[linux-block.git] / drivers / gpu / drm / vc4 / vc4_hdmi.c
CommitLineData
c8b75bca
EA		 1/*
2 * Copyright (C) 2015 Broadcom
3 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20/**
21 * DOC: VC4 Falcon HDMI module
22 *
f6c01530
EA		 23 * The HDMI core has a state machine and a PHY. On BCM2835, most of
24 * the unit operates off of the HSM clock from CPRMAN. It also
25 * internally uses the PLLH_PIX clock for the PHY.
26 *
27 * HDMI infoframes are kept within a small packet ram, where each
28 * packet can be individually enabled for including in a frame.
29 *
30 * HDMI audio is implemented entirely within the HDMI IP block. A
31 * register in the HDMI encoder takes SPDIF frames from the DMA engine
32 * and transfers them over an internal MAI (multi-channel audio
33 * interconnect) bus to the encoder side for insertion into the video
34 * blank regions.
35 *
36 * The driver's HDMI encoder does not yet support power management.
37 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
38 * continuously running, and only the HDMI logic and packet ram are
39 * powered off/on at disable/enable time.
40 *
41 * The driver does not yet support CEC control, though the HDMI
42 * encoder block has CEC support.
c8b75bca
EA		 43 */
44
b7e8e25b
MY		 45#include <drm/drm_atomic_helper.h>
46#include <drm/drm_crtc_helper.h>
47#include <drm/drm_edid.h>
48#include <linux/clk.h>
49#include <linux/component.h>
50#include <linux/i2c.h>
51#include <linux/of_address.h>
52#include <linux/of_gpio.h>
53#include <linux/of_platform.h>
54#include <linux/pm_runtime.h>
55#include <linux/rational.h>
56#include <sound/dmaengine_pcm.h>
57#include <sound/pcm_drm_eld.h>
58#include <sound/pcm_params.h>
59#include <sound/soc.h>
c8b75bca
EA		 60#include "vc4_drv.h"
61#include "vc4_regs.h"
62
bb7d7856
EA		 63/* HDMI audio information */
64struct vc4_hdmi_audio {
65 struct snd_soc_card card;
66 struct snd_soc_dai_link link;
67 int samplerate;
68 int channels;
69 struct snd_dmaengine_dai_dma_data dma_data;
70 struct snd_pcm_substream *substream;
71};
72
c8b75bca
EA		 73/* General HDMI hardware state. */
74struct vc4_hdmi {
75 struct platform_device *pdev;
76
77 struct drm_encoder *encoder;
78 struct drm_connector *connector;
79
bb7d7856
EA		 80 struct vc4_hdmi_audio audio;
81
c8b75bca
EA		 82 struct i2c_adapter *ddc;
83 void __iomem *hdmicore_regs;
84 void __iomem *hd_regs;
85 int hpd_gpio;
0b06e0a7 86 bool hpd_active_low;
c8b75bca
EA		 87
88 struct clk *pixel_clock;
89 struct clk *hsm_clock;
90};
91
92#define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset)
93#define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset)
94#define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset)
95#define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset)
96
97/* VC4 HDMI encoder KMS struct */
98struct vc4_hdmi_encoder {
99 struct vc4_encoder base;
100 bool hdmi_monitor;
21317b3f
EA		 101 bool limited_rgb_range;
102 bool rgb_range_selectable;
c8b75bca
EA		 103};
104
105static inline struct vc4_hdmi_encoder *
106to_vc4_hdmi_encoder(struct drm_encoder *encoder)
107{
108 return container_of(encoder, struct vc4_hdmi_encoder, base.base);
109}
110
111/* VC4 HDMI connector KMS struct */
112struct vc4_hdmi_connector {
113 struct drm_connector base;
114
115 /* Since the connector is attached to just the one encoder,
116 * this is the reference to it so we can do the best_encoder()
117 * hook.
118 */
119 struct drm_encoder *encoder;
120};
121
122static inline struct vc4_hdmi_connector *
123to_vc4_hdmi_connector(struct drm_connector *connector)
124{
125 return container_of(connector, struct vc4_hdmi_connector, base);
126}
127
128#define HDMI_REG(reg) { reg, #reg }
129static const struct {
130 u32 reg;
131 const char *name;
132} hdmi_regs[] = {
133 HDMI_REG(VC4_HDMI_CORE_REV),
134 HDMI_REG(VC4_HDMI_SW_RESET_CONTROL),
135 HDMI_REG(VC4_HDMI_HOTPLUG_INT),
136 HDMI_REG(VC4_HDMI_HOTPLUG),
bb7d7856
EA		 137 HDMI_REG(VC4_HDMI_MAI_CHANNEL_MAP),
138 HDMI_REG(VC4_HDMI_MAI_CONFIG),
139 HDMI_REG(VC4_HDMI_MAI_FORMAT),
140 HDMI_REG(VC4_HDMI_AUDIO_PACKET_CONFIG),
936f1a53 141 HDMI_REG(VC4_HDMI_RAM_PACKET_CONFIG),
c8b75bca
EA		 142 HDMI_REG(VC4_HDMI_HORZA),
143 HDMI_REG(VC4_HDMI_HORZB),
144 HDMI_REG(VC4_HDMI_FIFO_CTL),
145 HDMI_REG(VC4_HDMI_SCHEDULER_CONTROL),
146 HDMI_REG(VC4_HDMI_VERTA0),
147 HDMI_REG(VC4_HDMI_VERTA1),
148 HDMI_REG(VC4_HDMI_VERTB0),
149 HDMI_REG(VC4_HDMI_VERTB1),
150 HDMI_REG(VC4_HDMI_TX_PHY_RESET_CTL),
bb7d7856 151 HDMI_REG(VC4_HDMI_TX_PHY_CTL0),
c8b75bca
EA		 152};
153
154static const struct {
155 u32 reg;
156 const char *name;
157} hd_regs[] = {
158 HDMI_REG(VC4_HD_M_CTL),
159 HDMI_REG(VC4_HD_MAI_CTL),
bb7d7856
EA		 160 HDMI_REG(VC4_HD_MAI_THR),
161 HDMI_REG(VC4_HD_MAI_FMT),
162 HDMI_REG(VC4_HD_MAI_SMP),
c8b75bca
EA		 163 HDMI_REG(VC4_HD_VID_CTL),
164 HDMI_REG(VC4_HD_CSC_CTL),
165 HDMI_REG(VC4_HD_FRAME_COUNT),
166};
167
168#ifdef CONFIG_DEBUG_FS
169int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
170{
171 struct drm_info_node *node = (struct drm_info_node *)m->private;
172 struct drm_device *dev = node->minor->dev;
173 struct vc4_dev *vc4 = to_vc4_dev(dev);
174 int i;
175
176 for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) {
177 seq_printf(m, "%s (0x%04x): 0x%08x\n",
178 hdmi_regs[i].name, hdmi_regs[i].reg,
179 HDMI_READ(hdmi_regs[i].reg));
180 }
181
182 for (i = 0; i < ARRAY_SIZE(hd_regs); i++) {
183 seq_printf(m, "%s (0x%04x): 0x%08x\n",
184 hd_regs[i].name, hd_regs[i].reg,
185 HD_READ(hd_regs[i].reg));
186 }
187
188 return 0;
189}
190#endif /* CONFIG_DEBUG_FS */
191
192static void vc4_hdmi_dump_regs(struct drm_device *dev)
193{
194 struct vc4_dev *vc4 = to_vc4_dev(dev);
195 int i;
196
197 for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) {
198 DRM_INFO("0x%04x (%s): 0x%08x\n",
199 hdmi_regs[i].reg, hdmi_regs[i].name,
200 HDMI_READ(hdmi_regs[i].reg));
201 }
202 for (i = 0; i < ARRAY_SIZE(hd_regs); i++) {
203 DRM_INFO("0x%04x (%s): 0x%08x\n",
204 hd_regs[i].reg, hd_regs[i].name,
205 HD_READ(hd_regs[i].reg));
206 }
207}
208
209static enum drm_connector_status
210vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
211{
212 struct drm_device *dev = connector->dev;
213 struct vc4_dev *vc4 = to_vc4_dev(dev);
214
215 if (vc4->hdmi->hpd_gpio) {
0b06e0a7
EA		 216 if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^
217 vc4->hdmi->hpd_active_low)
c8b75bca
EA		 218 return connector_status_connected;
219 else
220 return connector_status_disconnected;
221 }
222
9d44abbb
EA		 223 if (drm_probe_ddc(vc4->hdmi->ddc))
224 return connector_status_connected;
225
c8b75bca
EA		 226 if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED)
227 return connector_status_connected;
228 else
229 return connector_status_disconnected;
230}
231
232static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
233{
234 drm_connector_unregister(connector);
235 drm_connector_cleanup(connector);
236}
237
238static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
239{
240 struct vc4_hdmi_connector *vc4_connector =
241 to_vc4_hdmi_connector(connector);
242 struct drm_encoder *encoder = vc4_connector->encoder;
243 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
244 struct drm_device *dev = connector->dev;
245 struct vc4_dev *vc4 = to_vc4_dev(dev);
246 int ret = 0;
247 struct edid *edid;
248
249 edid = drm_get_edid(connector, vc4->hdmi->ddc);
250 if (!edid)
251 return -ENODEV;
252
253 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
21317b3f
EA		 254
255 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
256 vc4_encoder->rgb_range_selectable =
257 drm_rgb_quant_range_selectable(edid);
258 }
259
c8b75bca
EA		 260 drm_mode_connector_update_edid_property(connector, edid);
261 ret = drm_add_edid_modes(connector, edid);
bb7d7856 262 drm_edid_to_eld(connector, edid);
c8b75bca
EA		 263
264 return ret;
265}
266
c8b75bca
EA		 267static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
268 .dpms = drm_atomic_helper_connector_dpms,
269 .detect = vc4_hdmi_connector_detect,
682e62c4 270 .fill_modes = drm_helper_probe_single_connector_modes,
c8b75bca
EA		 271 .destroy = vc4_hdmi_connector_destroy,
272 .reset = drm_atomic_helper_connector_reset,
273 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
274 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
275};
276
277static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
278 .get_modes = vc4_hdmi_connector_get_modes,
c8b75bca
EA		 279};
280
281static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev,
282 struct drm_encoder *encoder)
283{
284 struct drm_connector *connector = NULL;
285 struct vc4_hdmi_connector *hdmi_connector;
286 int ret = 0;
287
288 hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector),
289 GFP_KERNEL);
290 if (!hdmi_connector) {
291 ret = -ENOMEM;
292 goto fail;
293 }
294 connector = &hdmi_connector->base;
295
296 hdmi_connector->encoder = encoder;
297
298 drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs,
299 DRM_MODE_CONNECTOR_HDMIA);
300 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
301
302 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
303 DRM_CONNECTOR_POLL_DISCONNECT);
304
acc1be1d 305 connector->interlace_allowed = 1;
c8b75bca
EA		 306 connector->doublescan_allowed = 0;
307
308 drm_mode_connector_attach_encoder(connector, encoder);
309
310 return connector;
311
312 fail:
313 if (connector)
314 vc4_hdmi_connector_destroy(connector);
315
316 return ERR_PTR(ret);
317}
318
319static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder)
320{
321 drm_encoder_cleanup(encoder);
322}
323
324static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
325 .destroy = vc4_hdmi_encoder_destroy,
326};
327
21317b3f
EA		 328static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
329 enum hdmi_infoframe_type type)
330{
331 struct drm_device *dev = encoder->dev;
332 struct vc4_dev *vc4 = to_vc4_dev(dev);
333 u32 packet_id = type - 0x80;
334
335 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
336 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
337
338 return wait_for(!(HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) &
339 BIT(packet_id)), 100);
340}
341
342static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
343 union hdmi_infoframe *frame)
344{
345 struct drm_device *dev = encoder->dev;
346 struct vc4_dev *vc4 = to_vc4_dev(dev);
347 u32 packet_id = frame->any.type - 0x80;
bb7d7856 348 u32 packet_reg = VC4_HDMI_RAM_PACKET(packet_id);
21317b3f
EA		 349 uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
350 ssize_t len, i;
351 int ret;
352
353 WARN_ONCE(!(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
354 VC4_HDMI_RAM_PACKET_ENABLE),
355 "Packet RAM has to be on to store the packet.");
356
357 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
358 if (len < 0)
359 return;
360
361 ret = vc4_hdmi_stop_packet(encoder, frame->any.type);
362 if (ret) {
363 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
364 return;
365 }
366
367 for (i = 0; i < len; i += 7) {
368 HDMI_WRITE(packet_reg,
369 buffer[i + 0] << 0 |
370 buffer[i + 1] << 8 |
371 buffer[i + 2] << 16);
372 packet_reg += 4;
373
374 HDMI_WRITE(packet_reg,
375 buffer[i + 3] << 0 |
376 buffer[i + 4] << 8 |
377 buffer[i + 5] << 16 |
378 buffer[i + 6] << 24);
379 packet_reg += 4;
380 }
381
382 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
383 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
384 ret = wait_for((HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) &
385 BIT(packet_id)), 100);
386 if (ret)
387 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
388}
389
390static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
391{
392 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
393 struct drm_crtc *crtc = encoder->crtc;
394 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
395 union hdmi_infoframe frame;
396 int ret;
397
0c1f528c 398 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode, false);
21317b3f
EA		 399 if (ret < 0) {
400 DRM_ERROR("couldn't fill AVI infoframe\n");
401 return;
402 }
403
779c4c28 404 drm_hdmi_avi_infoframe_quant_range(&frame.avi, mode,
a2ce26f8
VS		 405 vc4_encoder->limited_rgb_range ?
406 HDMI_QUANTIZATION_RANGE_LIMITED :
407 HDMI_QUANTIZATION_RANGE_FULL,
408 vc4_encoder->rgb_range_selectable);
21317b3f
EA		 409
410 vc4_hdmi_write_infoframe(encoder, &frame);
411}
412
413static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
414{
415 union hdmi_infoframe frame;
416 int ret;
417
418 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
419 if (ret < 0) {
420 DRM_ERROR("couldn't fill SPD infoframe\n");
421 return;
422 }
423
424 frame.spd.sdi = HDMI_SPD_SDI_PC;
425
426 vc4_hdmi_write_infoframe(encoder, &frame);
427}
428
bb7d7856
EA		 429static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
430{
431 struct drm_device *drm = encoder->dev;
432 struct vc4_dev *vc4 = drm->dev_private;
433 struct vc4_hdmi *hdmi = vc4->hdmi;
434 union hdmi_infoframe frame;
435 int ret;
436
437 ret = hdmi_audio_infoframe_init(&frame.audio);
438
439 frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
440 frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
441 frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
442 frame.audio.channels = hdmi->audio.channels;
443
444 vc4_hdmi_write_infoframe(encoder, &frame);
445}
446
21317b3f
EA		 447static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
448{
449 vc4_hdmi_set_avi_infoframe(encoder);
450 vc4_hdmi_set_spd_infoframe(encoder);
451}
452
4f6e3d66
BB		 453static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
454{
455 struct drm_device *dev = encoder->dev;
456 struct vc4_dev *vc4 = to_vc4_dev(dev);
457 struct vc4_hdmi *hdmi = vc4->hdmi;
458 int ret;
459
460 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 0);
461
462 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
463 HD_WRITE(VC4_HD_VID_CTL,
464 HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
465
4f6e3d66
BB		 466 clk_disable_unprepare(hdmi->pixel_clock);
467
468 ret = pm_runtime_put(&hdmi->pdev->dev);
469 if (ret < 0)
470 DRM_ERROR("Failed to release power domain: %d\n", ret);
471}
472
473static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
c8b75bca 474{
4f6e3d66 475 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
6e1cbbad 476 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
c8b75bca
EA		 477 struct drm_device *dev = encoder->dev;
478 struct vc4_dev *vc4 = to_vc4_dev(dev);
4f6e3d66 479 struct vc4_hdmi *hdmi = vc4->hdmi;
c8b75bca
EA		 480 bool debug_dump_regs = false;
481 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
482 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
682e62c4 483 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
dfccd937 484 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
682e62c4 485 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
c8b75bca 486 VC4_HDMI_VERTA_VSP) |
682e62c4 487 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
c8b75bca 488 VC4_HDMI_VERTA_VFP) |
682e62c4 489 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
c8b75bca 490 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
682e62c4 491 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
c8b75bca 492 VC4_HDMI_VERTB_VBP));
682e62c4
EA		 493 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
494 VC4_SET_FIELD(mode->crtc_vtotal -
495 mode->crtc_vsync_end -
496 interlaced,
497 VC4_HDMI_VERTB_VBP));
6e1cbbad 498 u32 csc_ctl;
4f6e3d66
BB		 499 int ret;
500
501 ret = pm_runtime_get_sync(&hdmi->pdev->dev);
502 if (ret < 0) {
503 DRM_ERROR("Failed to retain power domain: %d\n", ret);
504 return;
505 }
506
4f6e3d66
BB		 507 ret = clk_set_rate(hdmi->pixel_clock,
508 mode->clock * 1000 *
509 ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1));
510 if (ret) {
511 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
512 return;
513 }
514
515 ret = clk_prepare_enable(hdmi->pixel_clock);
516 if (ret) {
517 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
518 return;
519 }
520
4f6e3d66
BB		 521 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL,
522 VC4_HDMI_SW_RESET_HDMI |
523 VC4_HDMI_SW_RESET_FORMAT_DETECT);
524
525 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0);
526
527 /* PHY should be in reset, like
528 * vc4_hdmi_encoder_disable() does.
529 */
530 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
531
532 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0);
c8b75bca
EA		 533
534 if (debug_dump_regs) {
535 DRM_INFO("HDMI regs before:\n");
536 vc4_hdmi_dump_regs(dev);
537 }
538
539 HD_WRITE(VC4_HD_VID_CTL, 0);
540
c8b75bca
EA		 541 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
542 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
543 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
544 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
545
546 HDMI_WRITE(VC4_HDMI_HORZA,
547 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
548 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
dfccd937
EA		 549 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
550 VC4_HDMI_HORZA_HAP));
c8b75bca
EA		 551
552 HDMI_WRITE(VC4_HDMI_HORZB,
dfccd937
EA		 553 VC4_SET_FIELD((mode->htotal -
554 mode->hsync_end) * pixel_rep,
c8b75bca 555 VC4_HDMI_HORZB_HBP) |
dfccd937
EA		 556 VC4_SET_FIELD((mode->hsync_end -
557 mode->hsync_start) * pixel_rep,
c8b75bca 558 VC4_HDMI_HORZB_HSP) |
dfccd937
EA		 559 VC4_SET_FIELD((mode->hsync_start -
560 mode->hdisplay) * pixel_rep,
c8b75bca
EA		 561 VC4_HDMI_HORZB_HFP));
562
563 HDMI_WRITE(VC4_HDMI_VERTA0, verta);
564 HDMI_WRITE(VC4_HDMI_VERTA1, verta);
565
682e62c4 566 HDMI_WRITE(VC4_HDMI_VERTB0, vertb_even);
c8b75bca
EA		 567 HDMI_WRITE(VC4_HDMI_VERTB1, vertb);
568
569 HD_WRITE(VC4_HD_VID_CTL,
570 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
571 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
572
6e1cbbad
EA		 573 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
574 VC4_HD_CSC_CTL_ORDER);
575
c8127cf0
VS		 576 if (vc4_encoder->hdmi_monitor &&
577 drm_default_rgb_quant_range(mode) ==
578 HDMI_QUANTIZATION_RANGE_LIMITED) {
6e1cbbad 579 /* CEA VICs other than #1 requre limited range RGB
21317b3f
EA		 580 * output unless overridden by an AVI infoframe.
581 * Apply a colorspace conversion to squash 0-255 down
582 * to 16-235. The matrix here is:
6e1cbbad
EA		 583 *
584 * [ 0 0 0.8594 16]
585 * [ 0 0.8594 0 16]
586 * [ 0.8594 0 0 16]
587 * [ 0 0 0 1]
588 */
589 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
590 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
591 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
592 VC4_HD_CSC_CTL_MODE);
593
594 HD_WRITE(VC4_HD_CSC_12_11, (0x000 << 16) | 0x000);
595 HD_WRITE(VC4_HD_CSC_14_13, (0x100 << 16) | 0x6e0);
596 HD_WRITE(VC4_HD_CSC_22_21, (0x6e0 << 16) | 0x000);
597 HD_WRITE(VC4_HD_CSC_24_23, (0x100 << 16) | 0x000);
598 HD_WRITE(VC4_HD_CSC_32_31, (0x000 << 16) | 0x6e0);
599 HD_WRITE(VC4_HD_CSC_34_33, (0x100 << 16) | 0x000);
21317b3f
EA		 600 vc4_encoder->limited_rgb_range = true;
601 } else {
602 vc4_encoder->limited_rgb_range = false;
6e1cbbad
EA		 603 }
604
c8b75bca 605 /* The RGB order applies even when CSC is disabled. */
6e1cbbad 606 HD_WRITE(VC4_HD_CSC_CTL, csc_ctl);
c8b75bca
EA		 607
608 HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
609
610 if (debug_dump_regs) {
611 DRM_INFO("HDMI regs after:\n");
612 vc4_hdmi_dump_regs(dev);
613 }
c8b75bca
EA		 614
615 HD_WRITE(VC4_HD_VID_CTL,
616 HD_READ(VC4_HD_VID_CTL) |
617 VC4_HD_VID_CTL_ENABLE |
618 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
619 VC4_HD_VID_CTL_FRAME_COUNTER_RESET);
620
621 if (vc4_encoder->hdmi_monitor) {
622 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
623 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
624 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
625
626 ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
2b29bf16 627 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
c8b75bca
EA		 628 WARN_ONCE(ret, "Timeout waiting for "
629 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
630 } else {
631 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
632 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
633 ~(VC4_HDMI_RAM_PACKET_ENABLE));
634 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
635 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
636 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
637
638 ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
2b29bf16 639 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
c8b75bca
EA		 640 WARN_ONCE(ret, "Timeout waiting for "
641 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
642 }
643
644 if (vc4_encoder->hdmi_monitor) {
645 u32 drift;
646
647 WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
648 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
649 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
650 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
651 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
652
21317b3f
EA		 653 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
654 VC4_HDMI_RAM_PACKET_ENABLE);
655
656 vc4_hdmi_set_infoframes(encoder);
c8b75bca
EA		 657
658 drift = HDMI_READ(VC4_HDMI_FIFO_CTL);
659 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
660
661 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
662 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
663 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
664 drift | VC4_HDMI_FIFO_CTL_RECENTER);
665 udelay(1000);
666 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
667 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
668 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
669 drift | VC4_HDMI_FIFO_CTL_RECENTER);
670
671 ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) &
672 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
673 WARN_ONCE(ret, "Timeout waiting for "
674 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
675 }
676}
677
678static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
c8b75bca
EA		 679 .disable = vc4_hdmi_encoder_disable,
680 .enable = vc4_hdmi_encoder_enable,
681};
682
bb7d7856
EA		 683/* HDMI audio codec callbacks */
684static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *hdmi)
685{
686 struct drm_device *drm = hdmi->encoder->dev;
687 struct vc4_dev *vc4 = to_vc4_dev(drm);
688 u32 hsm_clock = clk_get_rate(hdmi->hsm_clock);
689 unsigned long n, m;
690
691 rational_best_approximation(hsm_clock, hdmi->audio.samplerate,
692 VC4_HD_MAI_SMP_N_MASK >>
693 VC4_HD_MAI_SMP_N_SHIFT,
694 (VC4_HD_MAI_SMP_M_MASK >>
695 VC4_HD_MAI_SMP_M_SHIFT) + 1,
696 &n, &m);
697
698 HD_WRITE(VC4_HD_MAI_SMP,
699 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
700 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
701}
702
703static void vc4_hdmi_set_n_cts(struct vc4_hdmi *hdmi)
704{
705 struct drm_encoder *encoder = hdmi->encoder;
706 struct drm_crtc *crtc = encoder->crtc;
707 struct drm_device *drm = encoder->dev;
708 struct vc4_dev *vc4 = to_vc4_dev(drm);
709 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
710 u32 samplerate = hdmi->audio.samplerate;
711 u32 n, cts;
712 u64 tmp;
713
714 n = 128 * samplerate / 1000;
715 tmp = (u64)(mode->clock * 1000) * n;
716 do_div(tmp, 128 * samplerate);
717 cts = tmp;
718
719 HDMI_WRITE(VC4_HDMI_CRP_CFG,
720 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
721 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
722
723 /*
724 * We could get slightly more accurate clocks in some cases by
725 * providing a CTS_1 value. The two CTS values are alternated
726 * between based on the period fields
727 */
728 HDMI_WRITE(VC4_HDMI_CTS_0, cts);
729 HDMI_WRITE(VC4_HDMI_CTS_1, cts);
730}
731
732static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
733{
734 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
735
736 return snd_soc_card_get_drvdata(card);
737}
738
739static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream,
740 struct snd_soc_dai *dai)
741{
742 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
743 struct drm_encoder *encoder = hdmi->encoder;
744 struct vc4_dev *vc4 = to_vc4_dev(encoder->dev);
745 int ret;
746
747 if (hdmi->audio.substream && hdmi->audio.substream != substream)
748 return -EINVAL;
749
750 hdmi->audio.substream = substream;
751
752 /*
753 * If the HDMI encoder hasn't probed, or the encoder is
754 * currently in DVI mode, treat the codec dai as missing.
755 */
756 if (!encoder->crtc || !(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
757 VC4_HDMI_RAM_PACKET_ENABLE))
758 return -ENODEV;
759
760 ret = snd_pcm_hw_constraint_eld(substream->runtime,
761 hdmi->connector->eld);
762 if (ret)
763 return ret;
764
765 return 0;
766}
767
768static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
769{
770 return 0;
771}
772
773static void vc4_hdmi_audio_reset(struct vc4_hdmi *hdmi)
774{
775 struct drm_encoder *encoder = hdmi->encoder;
776 struct drm_device *drm = encoder->dev;
777 struct device *dev = &hdmi->pdev->dev;
778 struct vc4_dev *vc4 = to_vc4_dev(drm);
779 int ret;
780
781 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO);
782 if (ret)
783 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
784
785 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_RESET);
786 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
787 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
788}
789
790static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream,
791 struct snd_soc_dai *dai)
792{
793 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
794
795 if (substream != hdmi->audio.substream)
796 return;
797
798 vc4_hdmi_audio_reset(hdmi);
799
800 hdmi->audio.substream = NULL;
801}
802
803/* HDMI audio codec callbacks */
804static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
805 struct snd_pcm_hw_params *params,
806 struct snd_soc_dai *dai)
807{
808 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
809 struct drm_encoder *encoder = hdmi->encoder;
810 struct drm_device *drm = encoder->dev;
811 struct device *dev = &hdmi->pdev->dev;
812 struct vc4_dev *vc4 = to_vc4_dev(drm);
813 u32 audio_packet_config, channel_mask;
814 u32 channel_map, i;
815
816 if (substream != hdmi->audio.substream)
817 return -EINVAL;
818
819 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
820 params_rate(params), params_width(params),
821 params_channels(params));
822
823 hdmi->audio.channels = params_channels(params);
824 hdmi->audio.samplerate = params_rate(params);
825
826 HD_WRITE(VC4_HD_MAI_CTL,
827 VC4_HD_MAI_CTL_RESET |
828 VC4_HD_MAI_CTL_FLUSH |
829 VC4_HD_MAI_CTL_DLATE |
830 VC4_HD_MAI_CTL_ERRORE |
831 VC4_HD_MAI_CTL_ERRORF);
832
833 vc4_hdmi_audio_set_mai_clock(hdmi);
834
835 audio_packet_config =
836 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
837 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
838 VC4_SET_FIELD(0xf, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
839
840 channel_mask = GENMASK(hdmi->audio.channels - 1, 0);
841 audio_packet_config |= VC4_SET_FIELD(channel_mask,
842 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
843
844 /* Set the MAI threshold. This logic mimics the firmware's. */
845 if (hdmi->audio.samplerate > 96000) {
846 HD_WRITE(VC4_HD_MAI_THR,
847 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) |
848 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
849 } else if (hdmi->audio.samplerate > 48000) {
850 HD_WRITE(VC4_HD_MAI_THR,
851 VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) |
852 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
853 } else {
854 HD_WRITE(VC4_HD_MAI_THR,
855 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
856 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
857 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
858 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
859 }
860
861 HDMI_WRITE(VC4_HDMI_MAI_CONFIG,
862 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
863 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
864
865 channel_map = 0;
866 for (i = 0; i < 8; i++) {
867 if (channel_mask & BIT(i))
868 channel_map |= i << (3 * i);
869 }
870
871 HDMI_WRITE(VC4_HDMI_MAI_CHANNEL_MAP, channel_map);
872 HDMI_WRITE(VC4_HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
873 vc4_hdmi_set_n_cts(hdmi);
874
875 return 0;
876}
877
878static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
879 struct snd_soc_dai *dai)
880{
881 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
882 struct drm_encoder *encoder = hdmi->encoder;
883 struct drm_device *drm = encoder->dev;
884 struct vc4_dev *vc4 = to_vc4_dev(drm);
885
886 switch (cmd) {
887 case SNDRV_PCM_TRIGGER_START:
888 vc4_hdmi_set_audio_infoframe(encoder);
889 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0,
890 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) &
891 ~VC4_HDMI_TX_PHY_RNG_PWRDN);
892 HD_WRITE(VC4_HD_MAI_CTL,
893 VC4_SET_FIELD(hdmi->audio.channels,
894 VC4_HD_MAI_CTL_CHNUM) |
895 VC4_HD_MAI_CTL_ENABLE);
896 break;
897 case SNDRV_PCM_TRIGGER_STOP:
898 HD_WRITE(VC4_HD_MAI_CTL,
899 VC4_HD_MAI_CTL_DLATE |
900 VC4_HD_MAI_CTL_ERRORE |
901 VC4_HD_MAI_CTL_ERRORF);
902 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0,
903 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) |
904 VC4_HDMI_TX_PHY_RNG_PWRDN);
905 break;
906 default:
907 break;
908 }
909
910 return 0;
911}
912
913static inline struct vc4_hdmi *
914snd_component_to_hdmi(struct snd_soc_component *component)
915{
916 struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
917
918 return snd_soc_card_get_drvdata(card);
919}
920
921static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol,
922 struct snd_ctl_elem_info *uinfo)
923{
924 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
925 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component);
926
927 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
928 uinfo->count = sizeof(hdmi->connector->eld);
929
930 return 0;
931}
932
933static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol,
934 struct snd_ctl_elem_value *ucontrol)
935{
936 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
937 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component);
938
939 memcpy(ucontrol->value.bytes.data, hdmi->connector->eld,
940 sizeof(hdmi->connector->eld));
941
942 return 0;
943}
944
945static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = {
946 {
947 .access = SNDRV_CTL_ELEM_ACCESS_READ |
948 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
949 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
950 .name = "ELD",
951 .info = vc4_hdmi_audio_eld_ctl_info,
952 .get = vc4_hdmi_audio_eld_ctl_get,
953 },
954};
955
956static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = {
957 SND_SOC_DAPM_OUTPUT("TX"),
958};
959
960static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = {
961 { "TX", NULL, "Playback" },
962};
963
964static const struct snd_soc_codec_driver vc4_hdmi_audio_codec_drv = {
965 .component_driver = {
966 .controls = vc4_hdmi_audio_controls,
967 .num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls),
968 .dapm_widgets = vc4_hdmi_audio_widgets,
969 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets),
970 .dapm_routes = vc4_hdmi_audio_routes,
971 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes),
972 },
973};
974
975static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = {
976 .startup = vc4_hdmi_audio_startup,
977 .shutdown = vc4_hdmi_audio_shutdown,
978 .hw_params = vc4_hdmi_audio_hw_params,
979 .set_fmt = vc4_hdmi_audio_set_fmt,
980 .trigger = vc4_hdmi_audio_trigger,
981};
982
983static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = {
984 .name = "vc4-hdmi-hifi",
985 .playback = {
986 .stream_name = "Playback",
987 .channels_min = 2,
988 .channels_max = 8,
989 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
990 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
991 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
992 SNDRV_PCM_RATE_192000,
993 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
994 },
995};
996
997static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
998 .name = "vc4-hdmi-cpu-dai-component",
999};
1000
1001static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1002{
1003 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
1004
1005 snd_soc_dai_init_dma_data(dai, &hdmi->audio.dma_data, NULL);
1006
1007 return 0;
1008}
1009
1010static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1011 .name = "vc4-hdmi-cpu-dai",
1012 .probe = vc4_hdmi_audio_cpu_dai_probe,
1013 .playback = {
1014 .stream_name = "Playback",
1015 .channels_min = 1,
1016 .channels_max = 8,
1017 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1018 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1019 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1020 SNDRV_PCM_RATE_192000,
1021 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1022 },
1023 .ops = &vc4_hdmi_audio_dai_ops,
1024};
1025
1026static const struct snd_dmaengine_pcm_config pcm_conf = {
1027 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1028 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1029};
1030
1031static int vc4_hdmi_audio_init(struct vc4_hdmi *hdmi)
1032{
1033 struct snd_soc_dai_link *dai_link = &hdmi->audio.link;
1034 struct snd_soc_card *card = &hdmi->audio.card;
1035 struct device *dev = &hdmi->pdev->dev;
1036 const __be32 *addr;
1037 int ret;
1038
1039 if (!of_find_property(dev->of_node, "dmas", NULL)) {
1040 dev_warn(dev,
1041 "'dmas' DT property is missing, no HDMI audio\n");
1042 return 0;
1043 }
1044
1045 /*
1046 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1047 * the bus address specified in the DT, because the physical address
1048 * (the one returned by platform_get_resource()) is not appropriate
1049 * for DMA transfers.
1050 * This VC/MMU should probably be exposed to avoid this kind of hacks.
1051 */
1052 addr = of_get_address(dev->of_node, 1, NULL, NULL);
1053 hdmi->audio.dma_data.addr = be32_to_cpup(addr) + VC4_HD_MAI_DATA;
1054 hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1055 hdmi->audio.dma_data.maxburst = 2;
1056
1057 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1058 if (ret) {
1059 dev_err(dev, "Could not register PCM component: %d\n", ret);
1060 return ret;
1061 }
1062
1063 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1064 &vc4_hdmi_audio_cpu_dai_drv, 1);
1065 if (ret) {
1066 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1067 return ret;
1068 }
1069
1070 /* register codec and codec dai */
1071 ret = snd_soc_register_codec(dev, &vc4_hdmi_audio_codec_drv,
1072 &vc4_hdmi_audio_codec_dai_drv, 1);
1073 if (ret) {
1074 dev_err(dev, "Could not register codec: %d\n", ret);
1075 return ret;
1076 }
1077
1078 dai_link->name = "MAI";
1079 dai_link->stream_name = "MAI PCM";
1080 dai_link->codec_dai_name = vc4_hdmi_audio_codec_dai_drv.name;
1081 dai_link->cpu_dai_name = dev_name(dev);
1082 dai_link->codec_name = dev_name(dev);
1083 dai_link->platform_name = dev_name(dev);
1084
1085 card->dai_link = dai_link;
1086 card->num_links = 1;
1087 card->name = "vc4-hdmi";
1088 card->dev = dev;
1089
1090 /*
1091 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1092 * stores a pointer to the snd card object in dev->driver_data. This
1093 * means we cannot use it for something else. The hdmi back-pointer is
1094 * now stored in card->drvdata and should be retrieved with
1095 * snd_soc_card_get_drvdata() if needed.
1096 */
1097 snd_soc_card_set_drvdata(card, hdmi);
1098 ret = devm_snd_soc_register_card(dev, card);
1099 if (ret) {
1100 dev_err(dev, "Could not register sound card: %d\n", ret);
1101 goto unregister_codec;
1102 }
1103
1104 return 0;
1105
1106unregister_codec:
1107 snd_soc_unregister_codec(dev);
1108
1109 return ret;
1110}
1111
1112static void vc4_hdmi_audio_cleanup(struct vc4_hdmi *hdmi)
1113{
1114 struct device *dev = &hdmi->pdev->dev;
1115
1116 /*
1117 * If drvdata is not set this means the audio card was not
1118 * registered, just skip codec unregistration in this case.
1119 */
1120 if (dev_get_drvdata(dev))
1121 snd_soc_unregister_codec(dev);
1122}
1123
c8b75bca
EA		 1124static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
1125{
1126 struct platform_device *pdev = to_platform_device(dev);
1127 struct drm_device *drm = dev_get_drvdata(master);
1128 struct vc4_dev *vc4 = drm->dev_private;
1129 struct vc4_hdmi *hdmi;
1130 struct vc4_hdmi_encoder *vc4_hdmi_encoder;
1131 struct device_node *ddc_node;
1132 u32 value;
1133 int ret;
1134
1135 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1136 if (!hdmi)
1137 return -ENOMEM;
1138
1139 vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder),
1140 GFP_KERNEL);
1141 if (!vc4_hdmi_encoder)
1142 return -ENOMEM;
1143 vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI;
1144 hdmi->encoder = &vc4_hdmi_encoder->base.base;
1145
1146 hdmi->pdev = pdev;
1147 hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1148 if (IS_ERR(hdmi->hdmicore_regs))
1149 return PTR_ERR(hdmi->hdmicore_regs);
1150
1151 hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1152 if (IS_ERR(hdmi->hd_regs))
1153 return PTR_ERR(hdmi->hd_regs);
1154
c8b75bca
EA		 1155 hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1156 if (IS_ERR(hdmi->pixel_clock)) {
1157 DRM_ERROR("Failed to get pixel clock\n");
1158 return PTR_ERR(hdmi->pixel_clock);
1159 }
1160 hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1161 if (IS_ERR(hdmi->hsm_clock)) {
1162 DRM_ERROR("Failed to get HDMI state machine clock\n");
1163 return PTR_ERR(hdmi->hsm_clock);
1164 }
1165
027a6976
PC		 1166 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
1167 if (!ddc_node) {
1168 DRM_ERROR("Failed to find ddc node in device tree\n");
1169 return -ENODEV;
1170 }
1171
c8b75bca 1172 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
027a6976 1173 of_node_put(ddc_node);
c8b75bca
EA		 1174 if (!hdmi->ddc) {
1175 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
1176 return -EPROBE_DEFER;
1177 }
1178
10ee275c
HV		 1179 /* This is the rate that is set by the firmware. The number
1180 * needs to be a bit higher than the pixel clock rate
1181 * (generally 148.5Mhz).
1182 */
1183 ret = clk_set_rate(hdmi->hsm_clock, 163682864);
1184 if (ret) {
1185 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1186 goto err_put_i2c;
1187 }
1188
1189 ret = clk_prepare_enable(hdmi->hsm_clock);
1190 if (ret) {
1191 DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n",
1192 ret);
1193 goto err_put_i2c;
1194 }
1195
c8b75bca
EA		 1196 /* Only use the GPIO HPD pin if present in the DT, otherwise
1197 * we'll use the HDMI core's register.
1198 */
1199 if (of_find_property(dev->of_node, "hpd-gpios", &value)) {
0b06e0a7
EA		 1200 enum of_gpio_flags hpd_gpio_flags;
1201
1202 hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
1203 "hpd-gpios", 0,
1204 &hpd_gpio_flags);
c8b75bca
EA		 1205 if (hdmi->hpd_gpio < 0) {
1206 ret = hdmi->hpd_gpio;
10ee275c 1207 goto err_unprepare_hsm;
c8b75bca 1208 }
0b06e0a7
EA		 1209
1210 hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
c8b75bca
EA		 1211 }
1212
1213 vc4->hdmi = hdmi;
1214
10ee275c
HV		 1215 /* HDMI core must be enabled. */
1216 if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) {
1217 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST);
1218 udelay(1);
1219 HD_WRITE(VC4_HD_M_CTL, 0);
1220
1221 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE);
1222 }
4f6e3d66 1223 pm_runtime_enable(dev);
c8b75bca
EA		 1224
1225 drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs,
13a3d91f 1226 DRM_MODE_ENCODER_TMDS, NULL);
c8b75bca
EA		 1227 drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs);
1228
1229 hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder);
1230 if (IS_ERR(hdmi->connector)) {
1231 ret = PTR_ERR(hdmi->connector);
1232 goto err_destroy_encoder;
1233 }
1234
bb7d7856
EA		 1235 ret = vc4_hdmi_audio_init(hdmi);
1236 if (ret)
1237 goto err_destroy_encoder;
1238
c8b75bca
EA		 1239 return 0;
1240
1241err_destroy_encoder:
1242 vc4_hdmi_encoder_destroy(hdmi->encoder);
10ee275c
HV		 1243err_unprepare_hsm:
1244 clk_disable_unprepare(hdmi->hsm_clock);
4f6e3d66 1245 pm_runtime_disable(dev);
c8b75bca 1246err_put_i2c:
58839803 1247 put_device(&hdmi->ddc->dev);
c8b75bca
EA		 1248
1249 return ret;
1250}
1251
1252static void vc4_hdmi_unbind(struct device *dev, struct device *master,
1253 void *data)
1254{
1255 struct drm_device *drm = dev_get_drvdata(master);
1256 struct vc4_dev *vc4 = drm->dev_private;
1257 struct vc4_hdmi *hdmi = vc4->hdmi;
1258
bb7d7856
EA		 1259 vc4_hdmi_audio_cleanup(hdmi);
1260
c8b75bca
EA		 1261 vc4_hdmi_connector_destroy(hdmi->connector);
1262 vc4_hdmi_encoder_destroy(hdmi->encoder);
1263
10ee275c 1264 clk_disable_unprepare(hdmi->hsm_clock);
4f6e3d66
BB		 1265 pm_runtime_disable(dev);
1266
c8b75bca
EA		 1267 put_device(&hdmi->ddc->dev);
1268
1269 vc4->hdmi = NULL;
1270}
1271
1272static const struct component_ops vc4_hdmi_ops = {
1273 .bind = vc4_hdmi_bind,
1274 .unbind = vc4_hdmi_unbind,
1275};
1276
1277static int vc4_hdmi_dev_probe(struct platform_device *pdev)
1278{
1279 return component_add(&pdev->dev, &vc4_hdmi_ops);
1280}
1281
1282static int vc4_hdmi_dev_remove(struct platform_device *pdev)
1283{
1284 component_del(&pdev->dev, &vc4_hdmi_ops);
1285 return 0;
1286}
1287
1288static const struct of_device_id vc4_hdmi_dt_match[] = {
1289 { .compatible = "brcm,bcm2835-hdmi" },
1290 {}
1291};
1292
1293struct platform_driver vc4_hdmi_driver = {
1294 .probe = vc4_hdmi_dev_probe,
1295 .remove = vc4_hdmi_dev_remove,
1296 .driver = {
1297 .name = "vc4_hdmi",
1298 .of_match_table = vc4_hdmi_dt_match,
1299 },
1300};
Linux 6.x block layer and io_uring tree(s)