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c8b75bca EA |
1 | /* |
2 | * Copyright (C) 2015 Broadcom | |
3 | * Copyright (c) 2014 The Linux Foundation. All rights reserved. | |
4 | * Copyright (C) 2013 Red Hat | |
5 | * Author: Rob Clark <robdclark@gmail.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | /** | |
21 | * DOC: VC4 Falcon HDMI module | |
22 | * | |
23 | * The HDMI core has a state machine and a PHY. Most of the unit | |
24 | * operates off of the HSM clock from CPRMAN. It also internally uses | |
25 | * the PLLH_PIX clock for the PHY. | |
26 | */ | |
27 | ||
28 | #include "drm_atomic_helper.h" | |
29 | #include "drm_crtc_helper.h" | |
30 | #include "drm_edid.h" | |
31 | #include "linux/clk.h" | |
32 | #include "linux/component.h" | |
33 | #include "linux/i2c.h" | |
34 | #include "linux/of_gpio.h" | |
35 | #include "linux/of_platform.h" | |
36 | #include "vc4_drv.h" | |
37 | #include "vc4_regs.h" | |
38 | ||
39 | /* General HDMI hardware state. */ | |
40 | struct vc4_hdmi { | |
41 | struct platform_device *pdev; | |
42 | ||
43 | struct drm_encoder *encoder; | |
44 | struct drm_connector *connector; | |
45 | ||
46 | struct i2c_adapter *ddc; | |
47 | void __iomem *hdmicore_regs; | |
48 | void __iomem *hd_regs; | |
49 | int hpd_gpio; | |
50 | ||
51 | struct clk *pixel_clock; | |
52 | struct clk *hsm_clock; | |
53 | }; | |
54 | ||
55 | #define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset) | |
56 | #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset) | |
57 | #define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset) | |
58 | #define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset) | |
59 | ||
60 | /* VC4 HDMI encoder KMS struct */ | |
61 | struct vc4_hdmi_encoder { | |
62 | struct vc4_encoder base; | |
63 | bool hdmi_monitor; | |
64 | }; | |
65 | ||
66 | static inline struct vc4_hdmi_encoder * | |
67 | to_vc4_hdmi_encoder(struct drm_encoder *encoder) | |
68 | { | |
69 | return container_of(encoder, struct vc4_hdmi_encoder, base.base); | |
70 | } | |
71 | ||
72 | /* VC4 HDMI connector KMS struct */ | |
73 | struct vc4_hdmi_connector { | |
74 | struct drm_connector base; | |
75 | ||
76 | /* Since the connector is attached to just the one encoder, | |
77 | * this is the reference to it so we can do the best_encoder() | |
78 | * hook. | |
79 | */ | |
80 | struct drm_encoder *encoder; | |
81 | }; | |
82 | ||
83 | static inline struct vc4_hdmi_connector * | |
84 | to_vc4_hdmi_connector(struct drm_connector *connector) | |
85 | { | |
86 | return container_of(connector, struct vc4_hdmi_connector, base); | |
87 | } | |
88 | ||
89 | #define HDMI_REG(reg) { reg, #reg } | |
90 | static const struct { | |
91 | u32 reg; | |
92 | const char *name; | |
93 | } hdmi_regs[] = { | |
94 | HDMI_REG(VC4_HDMI_CORE_REV), | |
95 | HDMI_REG(VC4_HDMI_SW_RESET_CONTROL), | |
96 | HDMI_REG(VC4_HDMI_HOTPLUG_INT), | |
97 | HDMI_REG(VC4_HDMI_HOTPLUG), | |
936f1a53 | 98 | HDMI_REG(VC4_HDMI_RAM_PACKET_CONFIG), |
c8b75bca EA |
99 | HDMI_REG(VC4_HDMI_HORZA), |
100 | HDMI_REG(VC4_HDMI_HORZB), | |
101 | HDMI_REG(VC4_HDMI_FIFO_CTL), | |
102 | HDMI_REG(VC4_HDMI_SCHEDULER_CONTROL), | |
103 | HDMI_REG(VC4_HDMI_VERTA0), | |
104 | HDMI_REG(VC4_HDMI_VERTA1), | |
105 | HDMI_REG(VC4_HDMI_VERTB0), | |
106 | HDMI_REG(VC4_HDMI_VERTB1), | |
107 | HDMI_REG(VC4_HDMI_TX_PHY_RESET_CTL), | |
108 | }; | |
109 | ||
110 | static const struct { | |
111 | u32 reg; | |
112 | const char *name; | |
113 | } hd_regs[] = { | |
114 | HDMI_REG(VC4_HD_M_CTL), | |
115 | HDMI_REG(VC4_HD_MAI_CTL), | |
116 | HDMI_REG(VC4_HD_VID_CTL), | |
117 | HDMI_REG(VC4_HD_CSC_CTL), | |
118 | HDMI_REG(VC4_HD_FRAME_COUNT), | |
119 | }; | |
120 | ||
121 | #ifdef CONFIG_DEBUG_FS | |
122 | int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) | |
123 | { | |
124 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
125 | struct drm_device *dev = node->minor->dev; | |
126 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
127 | int i; | |
128 | ||
129 | for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) { | |
130 | seq_printf(m, "%s (0x%04x): 0x%08x\n", | |
131 | hdmi_regs[i].name, hdmi_regs[i].reg, | |
132 | HDMI_READ(hdmi_regs[i].reg)); | |
133 | } | |
134 | ||
135 | for (i = 0; i < ARRAY_SIZE(hd_regs); i++) { | |
136 | seq_printf(m, "%s (0x%04x): 0x%08x\n", | |
137 | hd_regs[i].name, hd_regs[i].reg, | |
138 | HD_READ(hd_regs[i].reg)); | |
139 | } | |
140 | ||
141 | return 0; | |
142 | } | |
143 | #endif /* CONFIG_DEBUG_FS */ | |
144 | ||
145 | static void vc4_hdmi_dump_regs(struct drm_device *dev) | |
146 | { | |
147 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
148 | int i; | |
149 | ||
150 | for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) { | |
151 | DRM_INFO("0x%04x (%s): 0x%08x\n", | |
152 | hdmi_regs[i].reg, hdmi_regs[i].name, | |
153 | HDMI_READ(hdmi_regs[i].reg)); | |
154 | } | |
155 | for (i = 0; i < ARRAY_SIZE(hd_regs); i++) { | |
156 | DRM_INFO("0x%04x (%s): 0x%08x\n", | |
157 | hd_regs[i].reg, hd_regs[i].name, | |
158 | HD_READ(hd_regs[i].reg)); | |
159 | } | |
160 | } | |
161 | ||
162 | static enum drm_connector_status | |
163 | vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) | |
164 | { | |
165 | struct drm_device *dev = connector->dev; | |
166 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
167 | ||
168 | if (vc4->hdmi->hpd_gpio) { | |
0e60eab5 | 169 | if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio)) |
c8b75bca EA |
170 | return connector_status_connected; |
171 | else | |
172 | return connector_status_disconnected; | |
173 | } | |
174 | ||
175 | if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) | |
176 | return connector_status_connected; | |
177 | else | |
178 | return connector_status_disconnected; | |
179 | } | |
180 | ||
181 | static void vc4_hdmi_connector_destroy(struct drm_connector *connector) | |
182 | { | |
183 | drm_connector_unregister(connector); | |
184 | drm_connector_cleanup(connector); | |
185 | } | |
186 | ||
187 | static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) | |
188 | { | |
189 | struct vc4_hdmi_connector *vc4_connector = | |
190 | to_vc4_hdmi_connector(connector); | |
191 | struct drm_encoder *encoder = vc4_connector->encoder; | |
192 | struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); | |
193 | struct drm_device *dev = connector->dev; | |
194 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
195 | int ret = 0; | |
196 | struct edid *edid; | |
197 | ||
198 | edid = drm_get_edid(connector, vc4->hdmi->ddc); | |
199 | if (!edid) | |
200 | return -ENODEV; | |
201 | ||
202 | vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid); | |
203 | drm_mode_connector_update_edid_property(connector, edid); | |
204 | ret = drm_add_edid_modes(connector, edid); | |
205 | ||
206 | return ret; | |
207 | } | |
208 | ||
209 | static struct drm_encoder * | |
210 | vc4_hdmi_connector_best_encoder(struct drm_connector *connector) | |
211 | { | |
212 | struct vc4_hdmi_connector *hdmi_connector = | |
213 | to_vc4_hdmi_connector(connector); | |
214 | return hdmi_connector->encoder; | |
215 | } | |
216 | ||
217 | static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { | |
218 | .dpms = drm_atomic_helper_connector_dpms, | |
219 | .detect = vc4_hdmi_connector_detect, | |
220 | .fill_modes = drm_helper_probe_single_connector_modes, | |
221 | .destroy = vc4_hdmi_connector_destroy, | |
222 | .reset = drm_atomic_helper_connector_reset, | |
223 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, | |
224 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, | |
225 | }; | |
226 | ||
227 | static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { | |
228 | .get_modes = vc4_hdmi_connector_get_modes, | |
229 | .best_encoder = vc4_hdmi_connector_best_encoder, | |
230 | }; | |
231 | ||
232 | static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev, | |
233 | struct drm_encoder *encoder) | |
234 | { | |
235 | struct drm_connector *connector = NULL; | |
236 | struct vc4_hdmi_connector *hdmi_connector; | |
237 | int ret = 0; | |
238 | ||
239 | hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector), | |
240 | GFP_KERNEL); | |
241 | if (!hdmi_connector) { | |
242 | ret = -ENOMEM; | |
243 | goto fail; | |
244 | } | |
245 | connector = &hdmi_connector->base; | |
246 | ||
247 | hdmi_connector->encoder = encoder; | |
248 | ||
249 | drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs, | |
250 | DRM_MODE_CONNECTOR_HDMIA); | |
251 | drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); | |
252 | ||
253 | connector->polled = (DRM_CONNECTOR_POLL_CONNECT | | |
254 | DRM_CONNECTOR_POLL_DISCONNECT); | |
255 | ||
256 | connector->interlace_allowed = 0; | |
257 | connector->doublescan_allowed = 0; | |
258 | ||
259 | drm_mode_connector_attach_encoder(connector, encoder); | |
260 | ||
261 | return connector; | |
262 | ||
263 | fail: | |
264 | if (connector) | |
265 | vc4_hdmi_connector_destroy(connector); | |
266 | ||
267 | return ERR_PTR(ret); | |
268 | } | |
269 | ||
270 | static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder) | |
271 | { | |
272 | drm_encoder_cleanup(encoder); | |
273 | } | |
274 | ||
275 | static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = { | |
276 | .destroy = vc4_hdmi_encoder_destroy, | |
277 | }; | |
278 | ||
279 | static void vc4_hdmi_encoder_mode_set(struct drm_encoder *encoder, | |
280 | struct drm_display_mode *unadjusted_mode, | |
281 | struct drm_display_mode *mode) | |
282 | { | |
283 | struct drm_device *dev = encoder->dev; | |
284 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
285 | bool debug_dump_regs = false; | |
286 | bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; | |
287 | bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; | |
288 | u32 vactive = (mode->vdisplay >> | |
289 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0)); | |
290 | u32 verta = (VC4_SET_FIELD(mode->vsync_end - mode->vsync_start, | |
291 | VC4_HDMI_VERTA_VSP) | | |
292 | VC4_SET_FIELD(mode->vsync_start - mode->vdisplay, | |
293 | VC4_HDMI_VERTA_VFP) | | |
294 | VC4_SET_FIELD(vactive, VC4_HDMI_VERTA_VAL)); | |
295 | u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | | |
296 | VC4_SET_FIELD(mode->vtotal - mode->vsync_end, | |
297 | VC4_HDMI_VERTB_VBP)); | |
298 | ||
299 | if (debug_dump_regs) { | |
300 | DRM_INFO("HDMI regs before:\n"); | |
301 | vc4_hdmi_dump_regs(dev); | |
302 | } | |
303 | ||
304 | HD_WRITE(VC4_HD_VID_CTL, 0); | |
305 | ||
306 | clk_set_rate(vc4->hdmi->pixel_clock, mode->clock * 1000); | |
307 | ||
308 | HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, | |
309 | HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | | |
310 | VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | | |
311 | VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); | |
312 | ||
313 | HDMI_WRITE(VC4_HDMI_HORZA, | |
314 | (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | | |
315 | (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | | |
316 | VC4_SET_FIELD(mode->hdisplay, VC4_HDMI_HORZA_HAP)); | |
317 | ||
318 | HDMI_WRITE(VC4_HDMI_HORZB, | |
319 | VC4_SET_FIELD(mode->htotal - mode->hsync_end, | |
320 | VC4_HDMI_HORZB_HBP) | | |
321 | VC4_SET_FIELD(mode->hsync_end - mode->hsync_start, | |
322 | VC4_HDMI_HORZB_HSP) | | |
323 | VC4_SET_FIELD(mode->hsync_start - mode->hdisplay, | |
324 | VC4_HDMI_HORZB_HFP)); | |
325 | ||
326 | HDMI_WRITE(VC4_HDMI_VERTA0, verta); | |
327 | HDMI_WRITE(VC4_HDMI_VERTA1, verta); | |
328 | ||
329 | HDMI_WRITE(VC4_HDMI_VERTB0, vertb); | |
330 | HDMI_WRITE(VC4_HDMI_VERTB1, vertb); | |
331 | ||
332 | HD_WRITE(VC4_HD_VID_CTL, | |
333 | (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | | |
334 | (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); | |
335 | ||
336 | /* The RGB order applies even when CSC is disabled. */ | |
337 | HD_WRITE(VC4_HD_CSC_CTL, VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, | |
338 | VC4_HD_CSC_CTL_ORDER)); | |
339 | ||
340 | HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); | |
341 | ||
342 | if (debug_dump_regs) { | |
343 | DRM_INFO("HDMI regs after:\n"); | |
344 | vc4_hdmi_dump_regs(dev); | |
345 | } | |
346 | } | |
347 | ||
348 | static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) | |
349 | { | |
350 | struct drm_device *dev = encoder->dev; | |
351 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
352 | ||
353 | HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16); | |
354 | HD_WRITE(VC4_HD_VID_CTL, | |
355 | HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); | |
356 | } | |
357 | ||
358 | static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) | |
359 | { | |
360 | struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); | |
361 | struct drm_device *dev = encoder->dev; | |
362 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
363 | int ret; | |
364 | ||
365 | HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0); | |
366 | ||
367 | HD_WRITE(VC4_HD_VID_CTL, | |
368 | HD_READ(VC4_HD_VID_CTL) | | |
369 | VC4_HD_VID_CTL_ENABLE | | |
370 | VC4_HD_VID_CTL_UNDERFLOW_ENABLE | | |
371 | VC4_HD_VID_CTL_FRAME_COUNTER_RESET); | |
372 | ||
373 | if (vc4_encoder->hdmi_monitor) { | |
374 | HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, | |
375 | HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | | |
376 | VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); | |
377 | ||
378 | ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & | |
379 | VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1); | |
380 | WARN_ONCE(ret, "Timeout waiting for " | |
381 | "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); | |
382 | } else { | |
383 | HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, | |
384 | HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & | |
385 | ~(VC4_HDMI_RAM_PACKET_ENABLE)); | |
386 | HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, | |
387 | HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & | |
388 | ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); | |
389 | ||
390 | ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & | |
391 | VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1); | |
392 | WARN_ONCE(ret, "Timeout waiting for " | |
393 | "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); | |
394 | } | |
395 | ||
396 | if (vc4_encoder->hdmi_monitor) { | |
397 | u32 drift; | |
398 | ||
399 | WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & | |
400 | VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); | |
401 | HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, | |
402 | HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | | |
403 | VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); | |
404 | ||
405 | /* XXX: Set HDMI_RAM_PACKET_CONFIG (1 << 16) and set | |
406 | * up the infoframe. | |
407 | */ | |
408 | ||
409 | drift = HDMI_READ(VC4_HDMI_FIFO_CTL); | |
410 | drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; | |
411 | ||
412 | HDMI_WRITE(VC4_HDMI_FIFO_CTL, | |
413 | drift & ~VC4_HDMI_FIFO_CTL_RECENTER); | |
414 | HDMI_WRITE(VC4_HDMI_FIFO_CTL, | |
415 | drift | VC4_HDMI_FIFO_CTL_RECENTER); | |
416 | udelay(1000); | |
417 | HDMI_WRITE(VC4_HDMI_FIFO_CTL, | |
418 | drift & ~VC4_HDMI_FIFO_CTL_RECENTER); | |
419 | HDMI_WRITE(VC4_HDMI_FIFO_CTL, | |
420 | drift | VC4_HDMI_FIFO_CTL_RECENTER); | |
421 | ||
422 | ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) & | |
423 | VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); | |
424 | WARN_ONCE(ret, "Timeout waiting for " | |
425 | "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); | |
426 | } | |
427 | } | |
428 | ||
429 | static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { | |
430 | .mode_set = vc4_hdmi_encoder_mode_set, | |
431 | .disable = vc4_hdmi_encoder_disable, | |
432 | .enable = vc4_hdmi_encoder_enable, | |
433 | }; | |
434 | ||
435 | static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) | |
436 | { | |
437 | struct platform_device *pdev = to_platform_device(dev); | |
438 | struct drm_device *drm = dev_get_drvdata(master); | |
439 | struct vc4_dev *vc4 = drm->dev_private; | |
440 | struct vc4_hdmi *hdmi; | |
441 | struct vc4_hdmi_encoder *vc4_hdmi_encoder; | |
442 | struct device_node *ddc_node; | |
443 | u32 value; | |
444 | int ret; | |
445 | ||
446 | hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); | |
447 | if (!hdmi) | |
448 | return -ENOMEM; | |
449 | ||
450 | vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder), | |
451 | GFP_KERNEL); | |
452 | if (!vc4_hdmi_encoder) | |
453 | return -ENOMEM; | |
454 | vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI; | |
455 | hdmi->encoder = &vc4_hdmi_encoder->base.base; | |
456 | ||
457 | hdmi->pdev = pdev; | |
458 | hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); | |
459 | if (IS_ERR(hdmi->hdmicore_regs)) | |
460 | return PTR_ERR(hdmi->hdmicore_regs); | |
461 | ||
462 | hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); | |
463 | if (IS_ERR(hdmi->hd_regs)) | |
464 | return PTR_ERR(hdmi->hd_regs); | |
465 | ||
466 | ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); | |
467 | if (!ddc_node) { | |
468 | DRM_ERROR("Failed to find ddc node in device tree\n"); | |
469 | return -ENODEV; | |
470 | } | |
471 | ||
472 | hdmi->pixel_clock = devm_clk_get(dev, "pixel"); | |
473 | if (IS_ERR(hdmi->pixel_clock)) { | |
474 | DRM_ERROR("Failed to get pixel clock\n"); | |
475 | return PTR_ERR(hdmi->pixel_clock); | |
476 | } | |
477 | hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); | |
478 | if (IS_ERR(hdmi->hsm_clock)) { | |
479 | DRM_ERROR("Failed to get HDMI state machine clock\n"); | |
480 | return PTR_ERR(hdmi->hsm_clock); | |
481 | } | |
482 | ||
483 | hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); | |
484 | if (!hdmi->ddc) { | |
485 | DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); | |
486 | return -EPROBE_DEFER; | |
487 | } | |
488 | ||
489 | /* Enable the clocks at startup. We can't quite recover from | |
490 | * turning off the pixel clock during disable/enables yet, so | |
491 | * it's always running. | |
492 | */ | |
493 | ret = clk_prepare_enable(hdmi->pixel_clock); | |
494 | if (ret) { | |
495 | DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); | |
496 | goto err_put_i2c; | |
497 | } | |
498 | ||
851479ad EA |
499 | /* This is the rate that is set by the firmware. The number |
500 | * needs to be a bit higher than the pixel clock rate | |
501 | * (generally 148.5Mhz). | |
502 | */ | |
503 | ret = clk_set_rate(hdmi->hsm_clock, 163682864); | |
504 | if (ret) { | |
505 | DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); | |
506 | goto err_unprepare_pix; | |
507 | } | |
508 | ||
c8b75bca EA |
509 | ret = clk_prepare_enable(hdmi->hsm_clock); |
510 | if (ret) { | |
511 | DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n", | |
512 | ret); | |
513 | goto err_unprepare_pix; | |
514 | } | |
515 | ||
516 | /* Only use the GPIO HPD pin if present in the DT, otherwise | |
517 | * we'll use the HDMI core's register. | |
518 | */ | |
519 | if (of_find_property(dev->of_node, "hpd-gpios", &value)) { | |
520 | hdmi->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0); | |
521 | if (hdmi->hpd_gpio < 0) { | |
522 | ret = hdmi->hpd_gpio; | |
523 | goto err_unprepare_hsm; | |
524 | } | |
525 | } | |
526 | ||
527 | vc4->hdmi = hdmi; | |
528 | ||
529 | /* HDMI core must be enabled. */ | |
851479ad EA |
530 | if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) { |
531 | HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST); | |
532 | udelay(1); | |
533 | HD_WRITE(VC4_HD_M_CTL, 0); | |
534 | ||
535 | HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE); | |
536 | ||
537 | HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, | |
538 | VC4_HDMI_SW_RESET_HDMI | | |
539 | VC4_HDMI_SW_RESET_FORMAT_DETECT); | |
540 | ||
541 | HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0); | |
542 | ||
543 | /* PHY should be in reset, like | |
544 | * vc4_hdmi_encoder_disable() does. | |
545 | */ | |
546 | HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16); | |
547 | } | |
c8b75bca EA |
548 | |
549 | drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs, | |
13a3d91f | 550 | DRM_MODE_ENCODER_TMDS, NULL); |
c8b75bca EA |
551 | drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs); |
552 | ||
553 | hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder); | |
554 | if (IS_ERR(hdmi->connector)) { | |
555 | ret = PTR_ERR(hdmi->connector); | |
556 | goto err_destroy_encoder; | |
557 | } | |
558 | ||
559 | return 0; | |
560 | ||
561 | err_destroy_encoder: | |
562 | vc4_hdmi_encoder_destroy(hdmi->encoder); | |
563 | err_unprepare_hsm: | |
564 | clk_disable_unprepare(hdmi->hsm_clock); | |
565 | err_unprepare_pix: | |
566 | clk_disable_unprepare(hdmi->pixel_clock); | |
567 | err_put_i2c: | |
568 | put_device(&vc4->hdmi->ddc->dev); | |
569 | ||
570 | return ret; | |
571 | } | |
572 | ||
573 | static void vc4_hdmi_unbind(struct device *dev, struct device *master, | |
574 | void *data) | |
575 | { | |
576 | struct drm_device *drm = dev_get_drvdata(master); | |
577 | struct vc4_dev *vc4 = drm->dev_private; | |
578 | struct vc4_hdmi *hdmi = vc4->hdmi; | |
579 | ||
580 | vc4_hdmi_connector_destroy(hdmi->connector); | |
581 | vc4_hdmi_encoder_destroy(hdmi->encoder); | |
582 | ||
583 | clk_disable_unprepare(hdmi->pixel_clock); | |
584 | clk_disable_unprepare(hdmi->hsm_clock); | |
585 | put_device(&hdmi->ddc->dev); | |
586 | ||
587 | vc4->hdmi = NULL; | |
588 | } | |
589 | ||
590 | static const struct component_ops vc4_hdmi_ops = { | |
591 | .bind = vc4_hdmi_bind, | |
592 | .unbind = vc4_hdmi_unbind, | |
593 | }; | |
594 | ||
595 | static int vc4_hdmi_dev_probe(struct platform_device *pdev) | |
596 | { | |
597 | return component_add(&pdev->dev, &vc4_hdmi_ops); | |
598 | } | |
599 | ||
600 | static int vc4_hdmi_dev_remove(struct platform_device *pdev) | |
601 | { | |
602 | component_del(&pdev->dev, &vc4_hdmi_ops); | |
603 | return 0; | |
604 | } | |
605 | ||
606 | static const struct of_device_id vc4_hdmi_dt_match[] = { | |
607 | { .compatible = "brcm,bcm2835-hdmi" }, | |
608 | {} | |
609 | }; | |
610 | ||
611 | struct platform_driver vc4_hdmi_driver = { | |
612 | .probe = vc4_hdmi_dev_probe, | |
613 | .remove = vc4_hdmi_dev_remove, | |
614 | .driver = { | |
615 | .name = "vc4_hdmi", | |
616 | .of_match_table = vc4_hdmi_dt_match, | |
617 | }, | |
618 | }; |