[linux-2.6-block.git] / drivers / gpu / drm / vc4 / vc4_crtc.c

/*
 * Copyright (C) 2015 Broadcom
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/**
 * DOC: VC4 CRTC module
 *
 * In VC4, the Pixel Valve is what most closely corresponds to the
 * DRM's concept of a CRTC.  The PV generates video timings from the
 * output's clock plus its configuration.  It pulls scaled pixels from
 * the HVS at that timing, and feeds it to the encoder.
 *
 * However, the DRM CRTC also collects the configuration of all the
 * DRM planes attached to it.  As a result, this file also manages
 * setup of the VC4 HVS's display elements on the CRTC.
 *
 * The 2835 has 3 different pixel valves.  pv0 in the audio power
 * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI.  pv2 in the
 * image domain can feed either HDMI or the SDTV controller.  The
 * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
 * SDTV, etc.) according to which output type is chosen in the mux.
 *
 * For power management, the pixel valve's registers are all clocked
 * by the AXI clock, while the timings and FIFOs make use of the
 * output-specific clock.  Since the encoders also directly consume
 * the CPRMAN clocks, and know what timings they need, they are the
 * ones that set the clock.
 */

#include "drm_atomic.h"
#include "drm_atomic_helper.h"
#include "drm_crtc_helper.h"
#include "linux/clk.h"
#include "linux/component.h"
#include "linux/of_device.h"
#include "vc4_drv.h"
#include "vc4_regs.h"

struct vc4_crtc {
	struct drm_crtc base;
	const struct vc4_crtc_data *data;
	void __iomem *regs;

	/* Which HVS channel we're using for our CRTC. */
	int channel;

	/* Pointer to the actual hardware display list memory for the
	 * crtc.
	 */
	u32 __iomem *dlist;

	u32 dlist_size; /* in dwords */

	struct drm_pending_vblank_event *event;
};

static inline struct vc4_crtc *
to_vc4_crtc(struct drm_crtc *crtc)
{
	return (struct vc4_crtc *)crtc;
}

struct vc4_crtc_data {
	/* Which channel of the HVS this pixelvalve sources from. */
	int hvs_channel;

	enum vc4_encoder_type encoder0_type;
	enum vc4_encoder_type encoder1_type;
};

#define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
#define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))

#define CRTC_REG(reg) { reg, #reg }
static const struct {
	u32 reg;
	const char *name;
} crtc_regs[] = {
	CRTC_REG(PV_CONTROL),
	CRTC_REG(PV_V_CONTROL),
	CRTC_REG(PV_VSYNCD),
	CRTC_REG(PV_HORZA),
	CRTC_REG(PV_HORZB),
	CRTC_REG(PV_VERTA),
	CRTC_REG(PV_VERTB),
	CRTC_REG(PV_VERTA_EVEN),
	CRTC_REG(PV_VERTB_EVEN),
	CRTC_REG(PV_INTEN),
	CRTC_REG(PV_INTSTAT),
	CRTC_REG(PV_STAT),
	CRTC_REG(PV_HACT_ACT),
};

static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
		DRM_INFO("0x%04x (%s): 0x%08x\n",
			 crtc_regs[i].reg, crtc_regs[i].name,
			 CRTC_READ(crtc_regs[i].reg));
	}
}

#ifdef CONFIG_DEBUG_FS
int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused)
{
	struct drm_info_node *node = (struct drm_info_node *)m->private;
	struct drm_device *dev = node->minor->dev;
	int crtc_index = (uintptr_t)node->info_ent->data;
	struct drm_crtc *crtc;
	struct vc4_crtc *vc4_crtc;
	int i;

	i = 0;
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		if (i == crtc_index)
			break;
		i++;
	}
	if (!crtc)
		return 0;
	vc4_crtc = to_vc4_crtc(crtc);

	for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
		seq_printf(m, "%s (0x%04x): 0x%08x\n",
			   crtc_regs[i].name, crtc_regs[i].reg,
			   CRTC_READ(crtc_regs[i].reg));
	}

	return 0;
}
#endif

static void vc4_crtc_destroy(struct drm_crtc *crtc)
{
	drm_crtc_cleanup(crtc);
}

static u32 vc4_get_fifo_full_level(u32 format)
{
	static const u32 fifo_len_bytes = 64;
	static const u32 hvs_latency_pix = 6;

	switch (format) {
	case PV_CONTROL_FORMAT_DSIV_16:
	case PV_CONTROL_FORMAT_DSIC_16:
		return fifo_len_bytes - 2 * hvs_latency_pix;
	case PV_CONTROL_FORMAT_DSIV_18:
		return fifo_len_bytes - 14;
	case PV_CONTROL_FORMAT_24:
	case PV_CONTROL_FORMAT_DSIV_24:
	default:
		return fifo_len_bytes - 3 * hvs_latency_pix;
	}
}

/*
 * Returns the clock select bit for the connector attached to the
 * CRTC.
 */
static int vc4_get_clock_select(struct drm_crtc *crtc)
{
	struct drm_connector *connector;

	drm_for_each_connector(connector, crtc->dev) {
		if (connector->state->crtc == crtc) {
			struct drm_encoder *encoder = connector->encoder;
			struct vc4_encoder *vc4_encoder =
				to_vc4_encoder(encoder);

			return vc4_encoder->clock_select;
		}
	}

	return -1;
}

static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
	struct drm_crtc_state *state = crtc->state;
	struct drm_display_mode *mode = &state->adjusted_mode;
	bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
	u32 vactive = (mode->vdisplay >> (interlace ? 1 : 0));
	u32 format = PV_CONTROL_FORMAT_24;
	bool debug_dump_regs = false;
	int clock_select = vc4_get_clock_select(crtc);

	if (debug_dump_regs) {
		DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
		vc4_crtc_dump_regs(vc4_crtc);
	}

	/* Reset the PV fifo. */
	CRTC_WRITE(PV_CONTROL, 0);
	CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
	CRTC_WRITE(PV_CONTROL, 0);

	CRTC_WRITE(PV_HORZA,
		   VC4_SET_FIELD(mode->htotal - mode->hsync_end,
				 PV_HORZA_HBP) |
		   VC4_SET_FIELD(mode->hsync_end - mode->hsync_start,
				 PV_HORZA_HSYNC));
	CRTC_WRITE(PV_HORZB,
		   VC4_SET_FIELD(mode->hsync_start - mode->hdisplay,
				 PV_HORZB_HFP) |
		   VC4_SET_FIELD(mode->hdisplay, PV_HORZB_HACTIVE));

	if (interlace) {
		CRTC_WRITE(PV_VERTA_EVEN,
			   VC4_SET_FIELD(mode->vtotal - mode->vsync_end - 1,
					 PV_VERTA_VBP) |
			   VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,
					 PV_VERTA_VSYNC));
		CRTC_WRITE(PV_VERTB_EVEN,
			   VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
					 PV_VERTB_VFP) |
			   VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE));
	}

	CRTC_WRITE(PV_HACT_ACT, mode->hdisplay);

	CRTC_WRITE(PV_V_CONTROL,
		   PV_VCONTROL_CONTINUOUS |
		   (interlace ? PV_VCONTROL_INTERLACE : 0));

	CRTC_WRITE(PV_CONTROL,
		   VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
		   VC4_SET_FIELD(vc4_get_fifo_full_level(format),
				 PV_CONTROL_FIFO_LEVEL) |
		   PV_CONTROL_CLR_AT_START |
		   PV_CONTROL_TRIGGER_UNDERFLOW |
		   PV_CONTROL_WAIT_HSTART |
		   VC4_SET_FIELD(clock_select, PV_CONTROL_CLK_SELECT) |
		   PV_CONTROL_FIFO_CLR |
		   PV_CONTROL_EN);

	if (debug_dump_regs) {
		DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
		vc4_crtc_dump_regs(vc4_crtc);
	}
}

static void require_hvs_enabled(struct drm_device *dev)
{
	struct vc4_dev *vc4 = to_vc4_dev(dev);

	WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
		     SCALER_DISPCTRL_ENABLE);
}

static void vc4_crtc_disable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct vc4_dev *vc4 = to_vc4_dev(dev);
	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
	u32 chan = vc4_crtc->channel;
	int ret;
	require_hvs_enabled(dev);

	CRTC_WRITE(PV_V_CONTROL,
		   CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
	ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
	WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");

	if (HVS_READ(SCALER_DISPCTRLX(chan)) &
	    SCALER_DISPCTRLX_ENABLE) {
		HVS_WRITE(SCALER_DISPCTRLX(chan),
			  SCALER_DISPCTRLX_RESET);

		/* While the docs say that reset is self-clearing, it
		 * seems it doesn't actually.
		 */
		HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
	}

	/* Once we leave, the scaler should be disabled and its fifo empty. */

	WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);

	WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
				   SCALER_DISPSTATX_MODE) !=
		     SCALER_DISPSTATX_MODE_DISABLED);

	WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
		      (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
		     SCALER_DISPSTATX_EMPTY);
}

static void vc4_crtc_enable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct vc4_dev *vc4 = to_vc4_dev(dev);
	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
	struct drm_crtc_state *state = crtc->state;
	struct drm_display_mode *mode = &state->adjusted_mode;

	require_hvs_enabled(dev);

	/* Turn on the scaler, which will wait for vstart to start
	 * compositing.
	 */
	HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
		  VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
		  VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
		  SCALER_DISPCTRLX_ENABLE);

	/* Turn on the pixel valve, which will emit the vstart signal. */
	CRTC_WRITE(PV_V_CONTROL,
		   CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
}

static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
				 struct drm_crtc_state *state)
{
	struct drm_device *dev = crtc->dev;
	struct vc4_dev *vc4 = to_vc4_dev(dev);
	struct drm_plane *plane;
	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
	u32 dlist_count = 0;

	/* The pixelvalve can only feed one encoder (and encoders are
	 * 1:1 with connectors.)
	 */
	if (drm_atomic_connectors_for_crtc(state->state, crtc) > 1)
		return -EINVAL;

	drm_atomic_crtc_state_for_each_plane(plane, state) {
		struct drm_plane_state *plane_state =
			state->state->plane_states[drm_plane_index(plane)];

		/* plane might not have changed, in which case take
		 * current state:
		 */
		if (!plane_state)
			plane_state = plane->state;

		dlist_count += vc4_plane_dlist_size(plane_state);
	}

	dlist_count++; /* Account for SCALER_CTL0_END. */

	if (!vc4_crtc->dlist || dlist_count > vc4_crtc->dlist_size) {
		vc4_crtc->dlist = ((u32 __iomem *)vc4->hvs->dlist +
				   HVS_BOOTLOADER_DLIST_END);
		vc4_crtc->dlist_size = ((SCALER_DLIST_SIZE >> 2) -
					HVS_BOOTLOADER_DLIST_END);

		if (dlist_count > vc4_crtc->dlist_size) {
			DRM_DEBUG_KMS("dlist too large for CRTC (%d > %d).\n",
				      dlist_count, vc4_crtc->dlist_size);
			return -EINVAL;
		}
	}

	return 0;
}

static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
				  struct drm_crtc_state *old_state)
{
	struct drm_device *dev = crtc->dev;
	struct vc4_dev *vc4 = to_vc4_dev(dev);
	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
	struct drm_plane *plane;
	bool debug_dump_regs = false;
	u32 __iomem *dlist_next = vc4_crtc->dlist;

	if (debug_dump_regs) {
		DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
		vc4_hvs_dump_state(dev);
	}

	/* Copy all the active planes' dlist contents to the hardware dlist.
	 *
	 * XXX: If the new display list was large enough that it
	 * overlapped a currently-read display list, we need to do
	 * something like disable scanout before putting in the new
	 * list.  For now, we're safe because we only have the two
	 * planes.
	 */
	drm_atomic_crtc_for_each_plane(plane, crtc) {
		dlist_next += vc4_plane_write_dlist(plane, dlist_next);
	}

	if (dlist_next == vc4_crtc->dlist) {
		/* If no planes were enabled, use the SCALER_CTL0_END
		 * at the start of the display list memory (in the
		 * bootloader section).  We'll rewrite that
		 * SCALER_CTL0_END, just in case, though.
		 */
		writel(SCALER_CTL0_END, vc4->hvs->dlist);
		HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel), 0);
	} else {
		writel(SCALER_CTL0_END, dlist_next);
		dlist_next++;

		HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
			  (u32 __iomem *)vc4_crtc->dlist -
			  (u32 __iomem *)vc4->hvs->dlist);

		/* Make the next display list start after ours. */
		vc4_crtc->dlist_size -= (dlist_next - vc4_crtc->dlist);
		vc4_crtc->dlist = dlist_next;
	}

	if (debug_dump_regs) {
		DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
		vc4_hvs_dump_state(dev);
	}

	if (crtc->state->event) {
		unsigned long flags;

		crtc->state->event->pipe = drm_crtc_index(crtc);

		WARN_ON(drm_crtc_vblank_get(crtc) != 0);

		spin_lock_irqsave(&dev->event_lock, flags);
		vc4_crtc->event = crtc->state->event;
		spin_unlock_irqrestore(&dev->event_lock, flags);
		crtc->state->event = NULL;
	}
}

int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id)
{
	struct vc4_dev *vc4 = to_vc4_dev(dev);
	struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];

	CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);

	return 0;
}

void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id)
{
	struct vc4_dev *vc4 = to_vc4_dev(dev);
	struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];

	CRTC_WRITE(PV_INTEN, 0);
}

static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
{
	struct drm_crtc *crtc = &vc4_crtc->base;
	struct drm_device *dev = crtc->dev;
	unsigned long flags;

	spin_lock_irqsave(&dev->event_lock, flags);
	if (vc4_crtc->event) {
		drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
		vc4_crtc->event = NULL;
	}
	spin_unlock_irqrestore(&dev->event_lock, flags);
}

static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
{
	struct vc4_crtc *vc4_crtc = data;
	u32 stat = CRTC_READ(PV_INTSTAT);
	irqreturn_t ret = IRQ_NONE;

	if (stat & PV_INT_VFP_START) {
		CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
		drm_crtc_handle_vblank(&vc4_crtc->base);
		vc4_crtc_handle_page_flip(vc4_crtc);
		ret = IRQ_HANDLED;
	}

	return ret;
}

static const struct drm_crtc_funcs vc4_crtc_funcs = {
	.set_config = drm_atomic_helper_set_config,
	.destroy = vc4_crtc_destroy,
	.page_flip = drm_atomic_helper_page_flip,
	.set_property = NULL,
	.cursor_set = NULL, /* handled by drm_mode_cursor_universal */
	.cursor_move = NULL, /* handled by drm_mode_cursor_universal */
	.reset = drm_atomic_helper_crtc_reset,
	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
};

static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
	.mode_set_nofb = vc4_crtc_mode_set_nofb,
	.disable = vc4_crtc_disable,
	.enable = vc4_crtc_enable,
	.atomic_check = vc4_crtc_atomic_check,
	.atomic_flush = vc4_crtc_atomic_flush,
};

/* Frees the page flip event when the DRM device is closed with the
 * event still outstanding.
 */
void vc4_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
{
	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	unsigned long flags;

	spin_lock_irqsave(&dev->event_lock, flags);

	if (vc4_crtc->event && vc4_crtc->event->base.file_priv == file) {
		vc4_crtc->event->base.destroy(&vc4_crtc->event->base);
		drm_crtc_vblank_put(crtc);
		vc4_crtc->event = NULL;
	}

	spin_unlock_irqrestore(&dev->event_lock, flags);
}

static const struct vc4_crtc_data pv0_data = {
	.hvs_channel = 0,
	.encoder0_type = VC4_ENCODER_TYPE_DSI0,
	.encoder1_type = VC4_ENCODER_TYPE_DPI,
};

static const struct vc4_crtc_data pv1_data = {
	.hvs_channel = 2,
	.encoder0_type = VC4_ENCODER_TYPE_DSI1,
	.encoder1_type = VC4_ENCODER_TYPE_SMI,
};

static const struct vc4_crtc_data pv2_data = {
	.hvs_channel = 1,
	.encoder0_type = VC4_ENCODER_TYPE_VEC,
	.encoder1_type = VC4_ENCODER_TYPE_HDMI,
};

static const struct of_device_id vc4_crtc_dt_match[] = {
	{ .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
	{ .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
	{ .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
	{}
};

static void vc4_set_crtc_possible_masks(struct drm_device *drm,
					struct drm_crtc *crtc)
{
	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
	struct drm_encoder *encoder;

	drm_for_each_encoder(encoder, drm) {
		struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);

		if (vc4_encoder->type == vc4_crtc->data->encoder0_type) {
			vc4_encoder->clock_select = 0;
			encoder->possible_crtcs |= drm_crtc_mask(crtc);
		} else if (vc4_encoder->type == vc4_crtc->data->encoder1_type) {
			vc4_encoder->clock_select = 1;
			encoder->possible_crtcs |= drm_crtc_mask(crtc);
		}
	}
}

static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct drm_device *drm = dev_get_drvdata(master);
	struct vc4_dev *vc4 = to_vc4_dev(drm);
	struct vc4_crtc *vc4_crtc;
	struct drm_crtc *crtc;
	struct drm_plane *primary_plane, *cursor_plane;
	const struct of_device_id *match;
	int ret;

	vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
	if (!vc4_crtc)
		return -ENOMEM;
	crtc = &vc4_crtc->base;

	match = of_match_device(vc4_crtc_dt_match, dev);
	if (!match)
		return -ENODEV;
	vc4_crtc->data = match->data;

	vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
	if (IS_ERR(vc4_crtc->regs))
		return PTR_ERR(vc4_crtc->regs);

	/* For now, we create just the primary and the legacy cursor
	 * planes.  We should be able to stack more planes on easily,
	 * but to do that we would need to compute the bandwidth
	 * requirement of the plane configuration, and reject ones
	 * that will take too much.
	 */
	primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
	if (IS_ERR(primary_plane)) {
		dev_err(dev, "failed to construct primary plane\n");
		ret = PTR_ERR(primary_plane);
		goto err;
	}

	cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
	if (IS_ERR(cursor_plane)) {
		dev_err(dev, "failed to construct cursor plane\n");
		ret = PTR_ERR(cursor_plane);
		goto err_primary;
	}

	drm_crtc_init_with_planes(drm, crtc, primary_plane, cursor_plane,
				  &vc4_crtc_funcs);
	drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
	primary_plane->crtc = crtc;
	cursor_plane->crtc = crtc;
	vc4->crtc[drm_crtc_index(crtc)] = vc4_crtc;
	vc4_crtc->channel = vc4_crtc->data->hvs_channel;

	CRTC_WRITE(PV_INTEN, 0);
	CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
	ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
			       vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
	if (ret)
		goto err_cursor;

	vc4_set_crtc_possible_masks(drm, crtc);

	platform_set_drvdata(pdev, vc4_crtc);

	return 0;

err_cursor:
	cursor_plane->funcs->destroy(cursor_plane);
err_primary:
	primary_plane->funcs->destroy(primary_plane);
err:
	return ret;
}

static void vc4_crtc_unbind(struct device *dev, struct device *master,
			    void *data)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);

	vc4_crtc_destroy(&vc4_crtc->base);

	CRTC_WRITE(PV_INTEN, 0);

	platform_set_drvdata(pdev, NULL);
}

static const struct component_ops vc4_crtc_ops = {
	.bind   = vc4_crtc_bind,
	.unbind = vc4_crtc_unbind,
};

static int vc4_crtc_dev_probe(struct platform_device *pdev)
{
	return component_add(&pdev->dev, &vc4_crtc_ops);
}

static int vc4_crtc_dev_remove(struct platform_device *pdev)
{
	component_del(&pdev->dev, &vc4_crtc_ops);
	return 0;
}

struct platform_driver vc4_crtc_driver = {
	.probe = vc4_crtc_dev_probe,
	.remove = vc4_crtc_dev_remove,
	.driver = {
		.name = "vc4_crtc",
		.of_match_table = vc4_crtc_dt_match,
	},
};
Commit	Line	Data
c8b75bca EA	1	/*
	2	* Copyright (C) 2015 Broadcom
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
	9	/**
	10	* DOC: VC4 CRTC module
	11	*
	12	* In VC4, the Pixel Valve is what most closely corresponds to the
	13	* DRM's concept of a CRTC. The PV generates video timings from the
	14	* output's clock plus its configuration. It pulls scaled pixels from
	15	* the HVS at that timing, and feeds it to the encoder.
	16	*
	17	* However, the DRM CRTC also collects the configuration of all the
	18	* DRM planes attached to it. As a result, this file also manages
	19	* setup of the VC4 HVS's display elements on the CRTC.
	20	*
	21	* The 2835 has 3 different pixel valves. pv0 in the audio power
	22	* domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the
	23	* image domain can feed either HDMI or the SDTV controller. The
	24	* pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
	25	* SDTV, etc.) according to which output type is chosen in the mux.
	26	*
	27	* For power management, the pixel valve's registers are all clocked
	28	* by the AXI clock, while the timings and FIFOs make use of the
	29	* output-specific clock. Since the encoders also directly consume
	30	* the CPRMAN clocks, and know what timings they need, they are the
	31	* ones that set the clock.
	32	*/
	33
	34	#include "drm_atomic.h"
	35	#include "drm_atomic_helper.h"
	36	#include "drm_crtc_helper.h"
	37	#include "linux/clk.h"
	38	#include "linux/component.h"
	39	#include "linux/of_device.h"
	40	#include "vc4_drv.h"
	41	#include "vc4_regs.h"
	42
	43	struct vc4_crtc {
	44	struct drm_crtc base;
	45	const struct vc4_crtc_data *data;
	46	void __iomem *regs;
	47
	48	/* Which HVS channel we're using for our CRTC. */
	49	int channel;
	50
	51	/* Pointer to the actual hardware display list memory for the
	52	* crtc.
	53	*/
	54	u32 __iomem *dlist;
	55
	56	u32 dlist_size; /* in dwords */
	57
	58	struct drm_pending_vblank_event *event;
	59	};
	60
	61	static inline struct vc4_crtc *
	62	to_vc4_crtc(struct drm_crtc *crtc)
	63	{
	64	return (struct vc4_crtc *)crtc;
65	}
66
67	struct vc4_crtc_data {
68	/* Which channel of the HVS this pixelvalve sources from. */
69	int hvs_channel;
70
71	enum vc4_encoder_type encoder0_type;
72	enum vc4_encoder_type encoder1_type;
73	};
74
75	#define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
76	#define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
77
78	#define CRTC_REG(reg) { reg, #reg }
79	static const struct {
80	u32 reg;
81	const char *name;
82	} crtc_regs[] = {
83	CRTC_REG(PV_CONTROL),
84	CRTC_REG(PV_V_CONTROL),
85	CRTC_REG(PV_VSYNCD),
86	CRTC_REG(PV_HORZA),
87	CRTC_REG(PV_HORZB),
88	CRTC_REG(PV_VERTA),
89	CRTC_REG(PV_VERTB),
90	CRTC_REG(PV_VERTA_EVEN),
91	CRTC_REG(PV_VERTB_EVEN),
92	CRTC_REG(PV_INTEN),
93	CRTC_REG(PV_INTSTAT),
94	CRTC_REG(PV_STAT),
95	CRTC_REG(PV_HACT_ACT),
96	};
97
98	static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc)
99	{
100	int i;
101
102	for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
103	DRM_INFO("0x%04x (%s): 0x%08x\n",
104	crtc_regs[i].reg, crtc_regs[i].name,
105	CRTC_READ(crtc_regs[i].reg));
106	}
107	}
108
109	#ifdef CONFIG_DEBUG_FS
110	int vc4_crtc_debugfs_regs(struct seq_file m, void unused)
111	{
112	struct drm_info_node node = (struct drm_info_node )m->private;
113	struct drm_device *dev = node->minor->dev;
114	int crtc_index = (uintptr_t)node->info_ent->data;
115	struct drm_crtc *crtc;
116	struct vc4_crtc *vc4_crtc;
117	int i;
118
119	i = 0;
120	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
121	if (i == crtc_index)
122	break;
123	i++;
124	}
125	if (!crtc)
126	return 0;
127	vc4_crtc = to_vc4_crtc(crtc);
128
129	for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
130	seq_printf(m, "%s (0x%04x): 0x%08x\n",
131	crtc_regs[i].name, crtc_regs[i].reg,
132	CRTC_READ(crtc_regs[i].reg));
133	}
134
135	return 0;
136	}
137	#endif
138
139	static void vc4_crtc_destroy(struct drm_crtc *crtc)
140	{
141	drm_crtc_cleanup(crtc);
142	}
143
144	static u32 vc4_get_fifo_full_level(u32 format)
145	{
146	static const u32 fifo_len_bytes = 64;
147	static const u32 hvs_latency_pix = 6;
148
149	switch (format) {
150	case PV_CONTROL_FORMAT_DSIV_16:
151	case PV_CONTROL_FORMAT_DSIC_16:
152	return fifo_len_bytes - 2 * hvs_latency_pix;
153	case PV_CONTROL_FORMAT_DSIV_18:
154	return fifo_len_bytes - 14;
155	case PV_CONTROL_FORMAT_24:
156	case PV_CONTROL_FORMAT_DSIV_24:
157	default:
158	return fifo_len_bytes - 3 * hvs_latency_pix;
159	}
160	}
161
162	/*
163	* Returns the clock select bit for the connector attached to the
164	* CRTC.
165	*/
166	static int vc4_get_clock_select(struct drm_crtc *crtc)
167	{
168	struct drm_connector *connector;
169
170	drm_for_each_connector(connector, crtc->dev) {
2fa8e904	171	if (connector->state->crtc == crtc) {
c8b75bca EA	172	struct drm_encoder *encoder = connector->encoder;
	173	struct vc4_encoder *vc4_encoder =
	174	to_vc4_encoder(encoder);
	175
	176	return vc4_encoder->clock_select;
	177	}
	178	}
	179
	180	return -1;
	181	}
	182
	183	static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
	184	{
	185	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
	186	struct drm_crtc_state *state = crtc->state;
	187	struct drm_display_mode *mode = &state->adjusted_mode;
	188	bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
	189	u32 vactive = (mode->vdisplay >> (interlace ? 1 : 0));
	190	u32 format = PV_CONTROL_FORMAT_24;
	191	bool debug_dump_regs = false;
	192	int clock_select = vc4_get_clock_select(crtc);
	193
	194	if (debug_dump_regs) {
	195	DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
	196	vc4_crtc_dump_regs(vc4_crtc);
	197	}
	198
	199	/* Reset the PV fifo. */
	200	CRTC_WRITE(PV_CONTROL, 0);
	201	CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR \| PV_CONTROL_EN);
	202	CRTC_WRITE(PV_CONTROL, 0);
	203
	204	CRTC_WRITE(PV_HORZA,
	205	VC4_SET_FIELD(mode->htotal - mode->hsync_end,
	206	PV_HORZA_HBP) \|
	207	VC4_SET_FIELD(mode->hsync_end - mode->hsync_start,
	208	PV_HORZA_HSYNC));
	209	CRTC_WRITE(PV_HORZB,
	210	VC4_SET_FIELD(mode->hsync_start - mode->hdisplay,
	211	PV_HORZB_HFP) \|
	212	VC4_SET_FIELD(mode->hdisplay, PV_HORZB_HACTIVE));
	213
	214	if (interlace) {
	215	CRTC_WRITE(PV_VERTA_EVEN,
	216	VC4_SET_FIELD(mode->vtotal - mode->vsync_end - 1,
	217	PV_VERTA_VBP) \|
	218	VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,
	219	PV_VERTA_VSYNC));
	220	CRTC_WRITE(PV_VERTB_EVEN,
	221	VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
	222	PV_VERTB_VFP) \|
	223	VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE));
	224	}
	225
	226	CRTC_WRITE(PV_HACT_ACT, mode->hdisplay);
	227
	228	CRTC_WRITE(PV_V_CONTROL,
	229	PV_VCONTROL_CONTINUOUS \|
	230	(interlace ? PV_VCONTROL_INTERLACE : 0));
	231
	232	CRTC_WRITE(PV_CONTROL,
	233	VC4_SET_FIELD(format, PV_CONTROL_FORMAT) \|
	234	VC4_SET_FIELD(vc4_get_fifo_full_level(format),
	235	PV_CONTROL_FIFO_LEVEL) \|
236	PV_CONTROL_CLR_AT_START \|
237	PV_CONTROL_TRIGGER_UNDERFLOW \|
238	PV_CONTROL_WAIT_HSTART \|
239	VC4_SET_FIELD(clock_select, PV_CONTROL_CLK_SELECT) \|
240	PV_CONTROL_FIFO_CLR \|
241	PV_CONTROL_EN);
242
243	if (debug_dump_regs) {
244	DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
245	vc4_crtc_dump_regs(vc4_crtc);
246	}
247	}
248
249	static void require_hvs_enabled(struct drm_device *dev)
250	{
251	struct vc4_dev *vc4 = to_vc4_dev(dev);
252
253	WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
254	SCALER_DISPCTRL_ENABLE);
255	}
256
257	static void vc4_crtc_disable(struct drm_crtc *crtc)
258	{
259	struct drm_device *dev = crtc->dev;
260	struct vc4_dev *vc4 = to_vc4_dev(dev);
261	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
262	u32 chan = vc4_crtc->channel;
263	int ret;
264	require_hvs_enabled(dev);
265
266	CRTC_WRITE(PV_V_CONTROL,
267	CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
268	ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
269	WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
270
271	if (HVS_READ(SCALER_DISPCTRLX(chan)) &
272	SCALER_DISPCTRLX_ENABLE) {
273	HVS_WRITE(SCALER_DISPCTRLX(chan),
274	SCALER_DISPCTRLX_RESET);
275
276	/* While the docs say that reset is self-clearing, it
277	* seems it doesn't actually.
278	*/
279	HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
280	}
281
282	/* Once we leave, the scaler should be disabled and its fifo empty. */
283
284	WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
285
286	WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
287	SCALER_DISPSTATX_MODE) !=
288	SCALER_DISPSTATX_MODE_DISABLED);
289
290	WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
291	(SCALER_DISPSTATX_FULL \| SCALER_DISPSTATX_EMPTY)) !=
292	SCALER_DISPSTATX_EMPTY);
293	}
294
295	static void vc4_crtc_enable(struct drm_crtc *crtc)
296	{
297	struct drm_device *dev = crtc->dev;
298	struct vc4_dev *vc4 = to_vc4_dev(dev);
299	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
300	struct drm_crtc_state *state = crtc->state;
301	struct drm_display_mode *mode = &state->adjusted_mode;
302
303	require_hvs_enabled(dev);
304
305	/* Turn on the scaler, which will wait for vstart to start
306	* compositing.
307	*/
308	HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
309	VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) \|
310	VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) \|
311	SCALER_DISPCTRLX_ENABLE);
312
313	/* Turn on the pixel valve, which will emit the vstart signal. */
314	CRTC_WRITE(PV_V_CONTROL,
315	CRTC_READ(PV_V_CONTROL) \| PV_VCONTROL_VIDEN);
316	}
317
318	static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
319	struct drm_crtc_state *state)
320	{
321	struct drm_device *dev = crtc->dev;
322	struct vc4_dev *vc4 = to_vc4_dev(dev);
323	struct drm_plane *plane;
324	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
325	u32 dlist_count = 0;
326
327	/* The pixelvalve can only feed one encoder (and encoders are
328	* 1:1 with connectors.)
329	*/
330	if (drm_atomic_connectors_for_crtc(state->state, crtc) > 1)
331	return -EINVAL;
332
333	drm_atomic_crtc_state_for_each_plane(plane, state) {
334	struct drm_plane_state *plane_state =
335	state->state->plane_states[drm_plane_index(plane)];
336
337	/* plane might not have changed, in which case take
338	* current state:
339	*/
340	if (!plane_state)
341	plane_state = plane->state;
342
343	dlist_count += vc4_plane_dlist_size(plane_state);
344	}
345
346	dlist_count++; /* Account for SCALER_CTL0_END. */
347
348	if (!vc4_crtc->dlist \|\| dlist_count > vc4_crtc->dlist_size) {
349	vc4_crtc->dlist = ((u32 __iomem *)vc4->hvs->dlist +
350	HVS_BOOTLOADER_DLIST_END);
351	vc4_crtc->dlist_size = ((SCALER_DLIST_SIZE >> 2) -
352	HVS_BOOTLOADER_DLIST_END);
353
354	if (dlist_count > vc4_crtc->dlist_size) {
355	DRM_DEBUG_KMS("dlist too large for CRTC (%d > %d).\n",
356	dlist_count, vc4_crtc->dlist_size);
357	return -EINVAL;
358	}
359	}
360
361	return 0;
362	}
363
364	static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
365	struct drm_crtc_state *old_state)
366	{
367	struct drm_device *dev = crtc->dev;
368	struct vc4_dev *vc4 = to_vc4_dev(dev);
369	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
370	struct drm_plane *plane;
371	bool debug_dump_regs = false;
372	u32 __iomem *dlist_next = vc4_crtc->dlist;
373
374	if (debug_dump_regs) {
375	DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
376	vc4_hvs_dump_state(dev);
377	}
378
379	/* Copy all the active planes' dlist contents to the hardware dlist.
380	*
381	* XXX: If the new display list was large enough that it
382	* overlapped a currently-read display list, we need to do
383	* something like disable scanout before putting in the new
384	* list. For now, we're safe because we only have the two
385	* planes.
386	*/
387	drm_atomic_crtc_for_each_plane(plane, crtc) {
388	dlist_next += vc4_plane_write_dlist(plane, dlist_next);
389	}
390
391	if (dlist_next == vc4_crtc->dlist) {
392	/* If no planes were enabled, use the SCALER_CTL0_END
393	* at the start of the display list memory (in the
394	* bootloader section). We'll rewrite that
395	* SCALER_CTL0_END, just in case, though.
396	*/
397	writel(SCALER_CTL0_END, vc4->hvs->dlist);
398	HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel), 0);
399	} else {
400	writel(SCALER_CTL0_END, dlist_next);
401	dlist_next++;
402
403	HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
36f4f69a EA	404	(u32 __iomem *)vc4_crtc->dlist -
36f4f69a EA	405	(u32 __iomem *)vc4->hvs->dlist);
c8b75bca EA	406
	407	/* Make the next display list start after ours. */
	408	vc4_crtc->dlist_size -= (dlist_next - vc4_crtc->dlist);
	409	vc4_crtc->dlist = dlist_next;
	410	}
	411
	412	if (debug_dump_regs) {
	413	DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
	414	vc4_hvs_dump_state(dev);
	415	}
	416
	417	if (crtc->state->event) {
	418	unsigned long flags;
	419
	420	crtc->state->event->pipe = drm_crtc_index(crtc);
	421
	422	WARN_ON(drm_crtc_vblank_get(crtc) != 0);
	423
	424	spin_lock_irqsave(&dev->event_lock, flags);
	425	vc4_crtc->event = crtc->state->event;
	426	spin_unlock_irqrestore(&dev->event_lock, flags);
	427	crtc->state->event = NULL;
	428	}
	429	}
	430
1f43710a	431	int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id)
c8b75bca EA	432	{
	433	struct vc4_dev *vc4 = to_vc4_dev(dev);
	434	struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
	435
	436	CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
	437
	438	return 0;
	439	}
	440
1f43710a	441	void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id)
c8b75bca EA	442	{
	443	struct vc4_dev *vc4 = to_vc4_dev(dev);
	444	struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
	445
	446	CRTC_WRITE(PV_INTEN, 0);
	447	}
	448
	449	static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
	450	{
	451	struct drm_crtc *crtc = &vc4_crtc->base;
	452	struct drm_device *dev = crtc->dev;
	453	unsigned long flags;
	454
	455	spin_lock_irqsave(&dev->event_lock, flags);
	456	if (vc4_crtc->event) {
	457	drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
	458	vc4_crtc->event = NULL;
	459	}
	460	spin_unlock_irqrestore(&dev->event_lock, flags);
	461	}
	462
	463	static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
	464	{
	465	struct vc4_crtc *vc4_crtc = data;
	466	u32 stat = CRTC_READ(PV_INTSTAT);
	467	irqreturn_t ret = IRQ_NONE;
	468
	469	if (stat & PV_INT_VFP_START) {
	470	CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
	471	drm_crtc_handle_vblank(&vc4_crtc->base);
	472	vc4_crtc_handle_page_flip(vc4_crtc);
	473	ret = IRQ_HANDLED;
	474	}
	475
	476	return ret;
	477	}
	478
	479	static const struct drm_crtc_funcs vc4_crtc_funcs = {
	480	.set_config = drm_atomic_helper_set_config,
	481	.destroy = vc4_crtc_destroy,
	482	.page_flip = drm_atomic_helper_page_flip,
	483	.set_property = NULL,
	484	.cursor_set = NULL, /* handled by drm_mode_cursor_universal */
	485	.cursor_move = NULL, /* handled by drm_mode_cursor_universal */
	486	.reset = drm_atomic_helper_crtc_reset,
	487	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
	488	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
	489	};
	490
	491	static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
	492	.mode_set_nofb = vc4_crtc_mode_set_nofb,
	493	.disable = vc4_crtc_disable,
	494	.enable = vc4_crtc_enable,
	495	.atomic_check = vc4_crtc_atomic_check,
	496	.atomic_flush = vc4_crtc_atomic_flush,
	497	};
	498
	499	/* Frees the page flip event when the DRM device is closed with the
	500	* event still outstanding.
	501	*/
	502	void vc4_cancel_page_flip(struct drm_crtc crtc, struct drm_file file)
	503	{
	504	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
	505	struct drm_device *dev = crtc->dev;
506	unsigned long flags;
507
508	spin_lock_irqsave(&dev->event_lock, flags);
509
510	if (vc4_crtc->event && vc4_crtc->event->base.file_priv == file) {
511	vc4_crtc->event->base.destroy(&vc4_crtc->event->base);
512	drm_crtc_vblank_put(crtc);
513	vc4_crtc->event = NULL;
514	}
515
516	spin_unlock_irqrestore(&dev->event_lock, flags);
517	}
518
519	static const struct vc4_crtc_data pv0_data = {
520	.hvs_channel = 0,
521	.encoder0_type = VC4_ENCODER_TYPE_DSI0,
522	.encoder1_type = VC4_ENCODER_TYPE_DPI,
523	};
524
525	static const struct vc4_crtc_data pv1_data = {
526	.hvs_channel = 2,
527	.encoder0_type = VC4_ENCODER_TYPE_DSI1,
528	.encoder1_type = VC4_ENCODER_TYPE_SMI,
529	};
530
531	static const struct vc4_crtc_data pv2_data = {
532	.hvs_channel = 1,
533	.encoder0_type = VC4_ENCODER_TYPE_VEC,
534	.encoder1_type = VC4_ENCODER_TYPE_HDMI,
535	};
536
537	static const struct of_device_id vc4_crtc_dt_match[] = {
538	{ .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
539	{ .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
540	{ .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
541	{}
542	};
543
544	static void vc4_set_crtc_possible_masks(struct drm_device *drm,
545	struct drm_crtc *crtc)
546	{
547	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
548	struct drm_encoder *encoder;
549
550	drm_for_each_encoder(encoder, drm) {
551	struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
552
553	if (vc4_encoder->type == vc4_crtc->data->encoder0_type) {
554	vc4_encoder->clock_select = 0;
555	encoder->possible_crtcs \|= drm_crtc_mask(crtc);
556	} else if (vc4_encoder->type == vc4_crtc->data->encoder1_type) {
557	vc4_encoder->clock_select = 1;
558	encoder->possible_crtcs \|= drm_crtc_mask(crtc);
559	}
560	}
561	}
562
563	static int vc4_crtc_bind(struct device dev, struct device master, void *data)
564	{
565	struct platform_device *pdev = to_platform_device(dev);
566	struct drm_device *drm = dev_get_drvdata(master);
567	struct vc4_dev *vc4 = to_vc4_dev(drm);
568	struct vc4_crtc *vc4_crtc;
569	struct drm_crtc *crtc;
570	struct drm_plane primary_plane, cursor_plane;
571	const struct of_device_id *match;
572	int ret;
573
574	vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
575	if (!vc4_crtc)
576	return -ENOMEM;
577	crtc = &vc4_crtc->base;
578
579	match = of_match_device(vc4_crtc_dt_match, dev);
580	if (!match)
581	return -ENODEV;
582	vc4_crtc->data = match->data;
583
584	vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
585	if (IS_ERR(vc4_crtc->regs))
586	return PTR_ERR(vc4_crtc->regs);
587
588	/* For now, we create just the primary and the legacy cursor
589	* planes. We should be able to stack more planes on easily,
590	* but to do that we would need to compute the bandwidth
591	* requirement of the plane configuration, and reject ones
592	* that will take too much.
593	*/
594	primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
79513237	595	if (IS_ERR(primary_plane)) {
c8b75bca EA	596	dev_err(dev, "failed to construct primary plane\n");
	597	ret = PTR_ERR(primary_plane);
	598	goto err;
	599	}
	600
	601	cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
79513237	602	if (IS_ERR(cursor_plane)) {
c8b75bca EA	603	dev_err(dev, "failed to construct cursor plane\n");
	604	ret = PTR_ERR(cursor_plane);
	605	goto err_primary;
	606	}
	607
	608	drm_crtc_init_with_planes(drm, crtc, primary_plane, cursor_plane,
	609	&vc4_crtc_funcs);
	610	drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
	611	primary_plane->crtc = crtc;
	612	cursor_plane->crtc = crtc;
	613	vc4->crtc[drm_crtc_index(crtc)] = vc4_crtc;
	614	vc4_crtc->channel = vc4_crtc->data->hvs_channel;
	615
	616	CRTC_WRITE(PV_INTEN, 0);
	617	CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
	618	ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
	619	vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
	620	if (ret)
	621	goto err_cursor;
	622
	623	vc4_set_crtc_possible_masks(drm, crtc);
	624
	625	platform_set_drvdata(pdev, vc4_crtc);
	626
	627	return 0;
	628
	629	err_cursor:
	630	cursor_plane->funcs->destroy(cursor_plane);
	631	err_primary:
	632	primary_plane->funcs->destroy(primary_plane);
	633	err:
	634	return ret;
	635	}
	636
	637	static void vc4_crtc_unbind(struct device dev, struct device master,
	638	void *data)
	639	{
	640	struct platform_device *pdev = to_platform_device(dev);
	641	struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
	642
	643	vc4_crtc_destroy(&vc4_crtc->base);
	644
	645	CRTC_WRITE(PV_INTEN, 0);
	646
	647	platform_set_drvdata(pdev, NULL);
	648	}
	649
	650	static const struct component_ops vc4_crtc_ops = {
	651	.bind = vc4_crtc_bind,
	652	.unbind = vc4_crtc_unbind,
	653	};
	654
	655	static int vc4_crtc_dev_probe(struct platform_device *pdev)
	656	{
	657	return component_add(&pdev->dev, &vc4_crtc_ops);
	658	}
	659
	660	static int vc4_crtc_dev_remove(struct platform_device *pdev)
	661	{
	662	component_del(&pdev->dev, &vc4_crtc_ops);
	663	return 0;
	664	}
	665
	666	struct platform_driver vc4_crtc_driver = {
667	.probe = vc4_crtc_dev_probe,
668	.remove = vc4_crtc_dev_remove,
669	.driver = {
670	.name = "vc4_crtc",
671	.of_match_table = vc4_crtc_dt_match,
672	},
673	};