projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 57692c94 EA |
1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* Copyright (C) 2017-2018 Broadcom */ | |
| 3 | ||
| 4 | #ifndef V3D_REGS_H | |
| 5 | #define V3D_REGS_H | |
| 6 | ||
| 7 | #include <linux/bitops.h> | |
| 8 | ||
| 9 | #define V3D_MASK(high, low) ((u32)GENMASK(high, low)) | |
| 10 | /* Using the GNU statement expression extension */ | |
| 11 | #define V3D_SET_FIELD(value, field) \ | |
| 12 | ({ \ | |
| 13 | u32 fieldval = (value) << field##_SHIFT; \ | |
| 14 | WARN_ON((fieldval & ~field##_MASK) != 0); \ | |
| 15 | fieldval & field##_MASK; \ | |
| 16 | }) | |
| 17 | ||
| e987e22e MC |
18 | #define V3D_SET_FIELD_VER(value, field, ver) \ |
| 19 | ({ \ | |
| 20 | typeof(ver) _ver = (ver); \ | |
| 21 | u32 fieldval = (value) << field##_SHIFT(_ver); \ | |
| 22 | WARN_ON((fieldval & ~field##_MASK(_ver)) != 0); \ | |
| 23 | fieldval & field##_MASK(_ver); \ | |
| 24 | }) | |
| 25 | ||
| 57692c94 EA |
26 | #define V3D_GET_FIELD(word, field) (((word) & field##_MASK) >> \ |
| 27 | field##_SHIFT) | |
| 28 | ||
| 29 | /* Hub registers for shared hardware between V3D cores. */ | |
| 30 | ||
| 31 | #define V3D_HUB_AXICFG 0x00000 | |
| 32 | # define V3D_HUB_AXICFG_MAX_LEN_MASK V3D_MASK(3, 0) | |
| 33 | # define V3D_HUB_AXICFG_MAX_LEN_SHIFT 0 | |
| 34 | #define V3D_HUB_UIFCFG 0x00004 | |
| 35 | #define V3D_HUB_IDENT0 0x00008 | |
| 36 | ||
| 37 | #define V3D_HUB_IDENT1 0x0000c | |
| 38 | # define V3D_HUB_IDENT1_WITH_MSO BIT(19) | |
| 39 | # define V3D_HUB_IDENT1_WITH_TSY BIT(18) | |
| 40 | # define V3D_HUB_IDENT1_WITH_TFU BIT(17) | |
| 41 | # define V3D_HUB_IDENT1_WITH_L3C BIT(16) | |
| 42 | # define V3D_HUB_IDENT1_NHOSTS_MASK V3D_MASK(15, 12) | |
| 43 | # define V3D_HUB_IDENT1_NHOSTS_SHIFT 12 | |
| 44 | # define V3D_HUB_IDENT1_NCORES_MASK V3D_MASK(11, 8) | |
| 45 | # define V3D_HUB_IDENT1_NCORES_SHIFT 8 | |
| 46 | # define V3D_HUB_IDENT1_REV_MASK V3D_MASK(7, 4) | |
| 47 | # define V3D_HUB_IDENT1_REV_SHIFT 4 | |
| 48 | # define V3D_HUB_IDENT1_TVER_MASK V3D_MASK(3, 0) | |
| 49 | # define V3D_HUB_IDENT1_TVER_SHIFT 0 | |
| 50 | ||
| 51 | #define V3D_HUB_IDENT2 0x00010 | |
| 52 | # define V3D_HUB_IDENT2_WITH_MMU BIT(8) | |
| 53 | # define V3D_HUB_IDENT2_L3C_NKB_MASK V3D_MASK(7, 0) | |
| 54 | # define V3D_HUB_IDENT2_L3C_NKB_SHIFT 0 | |
| 55 | ||
| 56 | #define V3D_HUB_IDENT3 0x00014 | |
| 57 | # define V3D_HUB_IDENT3_IPREV_MASK V3D_MASK(15, 8) | |
| 58 | # define V3D_HUB_IDENT3_IPREV_SHIFT 8 | |
| 59 | # define V3D_HUB_IDENT3_IPIDX_MASK V3D_MASK(7, 0) | |
| 60 | # define V3D_HUB_IDENT3_IPIDX_SHIFT 0 | |
| 61 | ||
| 62 | #define V3D_HUB_INT_STS 0x00050 | |
| 63 | #define V3D_HUB_INT_SET 0x00054 | |
| 64 | #define V3D_HUB_INT_CLR 0x00058 | |
| 65 | #define V3D_HUB_INT_MSK_STS 0x0005c | |
| 66 | #define V3D_HUB_INT_MSK_SET 0x00060 | |
| 67 | #define V3D_HUB_INT_MSK_CLR 0x00064 | |
| 0ad5bc1c | 68 | # define V3D_V7_HUB_INT_GMPV BIT(6) |
| 57692c94 EA |
69 | # define V3D_HUB_INT_MMU_WRV BIT(5) |
| 70 | # define V3D_HUB_INT_MMU_PTI BIT(4) | |
| 71 | # define V3D_HUB_INT_MMU_CAP BIT(3) | |
| 72 | # define V3D_HUB_INT_MSO BIT(2) | |
| 73 | # define V3D_HUB_INT_TFUC BIT(1) | |
| 74 | # define V3D_HUB_INT_TFUF BIT(0) | |
| 75 | ||
| 0ad5bc1c | 76 | /* GCA registers only exist in V3D < 41 */ |
| 57692c94 EA |
77 | #define V3D_GCA_CACHE_CTRL 0x0000c |
| 78 | # define V3D_GCA_CACHE_CTRL_FLUSH BIT(0) | |
| 79 | ||
| 80 | #define V3D_GCA_SAFE_SHUTDOWN 0x000b0 | |
| 81 | # define V3D_GCA_SAFE_SHUTDOWN_EN BIT(0) | |
| 82 | ||
| 83 | #define V3D_GCA_SAFE_SHUTDOWN_ACK 0x000b4 | |
| 84 | # define V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED 3 | |
| 85 | ||
| 86 | # define V3D_TOP_GR_BRIDGE_REVISION 0x00000 | |
| 87 | # define V3D_TOP_GR_BRIDGE_MAJOR_MASK V3D_MASK(15, 8) | |
| 88 | # define V3D_TOP_GR_BRIDGE_MAJOR_SHIFT 8 | |
| 89 | # define V3D_TOP_GR_BRIDGE_MINOR_MASK V3D_MASK(7, 0) | |
| 90 | # define V3D_TOP_GR_BRIDGE_MINOR_SHIFT 0 | |
| 91 | ||
| 92 | /* 7268 reset reg */ | |
| 93 | # define V3D_TOP_GR_BRIDGE_SW_INIT_0 0x00008 | |
| 94 | # define V3D_TOP_GR_BRIDGE_SW_INIT_0_V3D_CLK_108_SW_INIT BIT(0) | |
| 95 | /* 7278 reset reg */ | |
| 96 | # define V3D_TOP_GR_BRIDGE_SW_INIT_1 0x0000c | |
| 97 | # define V3D_TOP_GR_BRIDGE_SW_INIT_1_V3D_CLK_108_SW_INIT BIT(0) | |
| 98 | ||
| 0ad5bc1c ITQ |
99 | #define V3D_TFU_CS(ver) ((ver >= 71) ? 0x00700 : 0x00400) |
| 100 | ||
| 1584f16c EA |
101 | /* Stops current job, empties input fifo. */ |
| 102 | # define V3D_TFU_CS_TFURST BIT(31) | |
| 103 | # define V3D_TFU_CS_CVTCT_MASK V3D_MASK(23, 16) | |
| 104 | # define V3D_TFU_CS_CVTCT_SHIFT 16 | |
| 105 | # define V3D_TFU_CS_NFREE_MASK V3D_MASK(13, 8) | |
| 106 | # define V3D_TFU_CS_NFREE_SHIFT 8 | |
| 107 | # define V3D_TFU_CS_BUSY BIT(0) | |
| 108 | ||
| 0ad5bc1c | 109 | #define V3D_TFU_SU(ver) ((ver >= 71) ? 0x00704 : 0x00404) |
| 1584f16c EA |
110 | /* Interrupt when FINTTHR input slots are free (0 = disabled) */ |
| 111 | # define V3D_TFU_SU_FINTTHR_MASK V3D_MASK(13, 8) | |
| 112 | # define V3D_TFU_SU_FINTTHR_SHIFT 8 | |
| 113 | /* Skips resetting the CRC at the start of CRC generation. */ | |
| 114 | # define V3D_TFU_SU_CRCCHAIN BIT(4) | |
| 115 | /* skips writes, computes CRC of the image. miplevels must be 0. */ | |
| 116 | # define V3D_TFU_SU_CRC BIT(3) | |
| 117 | # define V3D_TFU_SU_THROTTLE_MASK V3D_MASK(1, 0) | |
| 118 | # define V3D_TFU_SU_THROTTLE_SHIFT 0 | |
| 119 | ||
| 0ad5bc1c | 120 | #define V3D_TFU_ICFG(ver) ((ver >= 71) ? 0x00708 : 0x00408) |
| 1584f16c EA |
121 | /* Interrupt when the conversion is complete. */ |
| 122 | # define V3D_TFU_ICFG_IOC BIT(0) | |
| 123 | ||
| 124 | /* Input Image Address */ | |
| 0ad5bc1c | 125 | #define V3D_TFU_IIA(ver) ((ver >= 71) ? 0x0070c : 0x0040c) |
| 1584f16c | 126 | /* Input Chroma Address */ |
| 0ad5bc1c | 127 | #define V3D_TFU_ICA(ver) ((ver >= 71) ? 0x00710 : 0x00410) |
| 1584f16c | 128 | /* Input Image Stride */ |
| 0ad5bc1c | 129 | #define V3D_TFU_IIS(ver) ((ver >= 71) ? 0x00714 : 0x00414) |
| 1584f16c | 130 | /* Input Image U-Plane Address */ |
| 0ad5bc1c ITQ |
131 | #define V3D_TFU_IUA(ver) ((ver >= 71) ? 0x00718 : 0x00418) |
| 132 | /* Image output config (VD 7.x only) */ | |
| 133 | #define V3D_V7_TFU_IOC 0x0071c | |
| 1584f16c | 134 | /* Output Image Address */ |
| 0ad5bc1c | 135 | #define V3D_TFU_IOA(ver) ((ver >= 71) ? 0x00720 : 0x0041c) |
| 1584f16c | 136 | /* Image Output Size */ |
| 0ad5bc1c | 137 | #define V3D_TFU_IOS(ver) ((ver >= 71) ? 0x00724 : 0x00420) |
| 1584f16c | 138 | /* TFU YUV Coefficient 0 */ |
| 0ad5bc1c ITQ |
139 | #define V3D_TFU_COEF0(ver) ((ver >= 71) ? 0x00728 : 0x00424) |
| 140 | /* Use these regs instead of the defaults (V3D 4.x only) */ | |
| 1584f16c EA |
141 | # define V3D_TFU_COEF0_USECOEF BIT(31) |
| 142 | /* TFU YUV Coefficient 1 */ | |
| 0ad5bc1c | 143 | #define V3D_TFU_COEF1(ver) ((ver >= 71) ? 0x0072c : 0x00428) |
| 1584f16c | 144 | /* TFU YUV Coefficient 2 */ |
| 0ad5bc1c | 145 | #define V3D_TFU_COEF2(ver) ((ver >= 71) ? 0x00730 : 0x0042c) |
| 1584f16c | 146 | /* TFU YUV Coefficient 3 */ |
| 0ad5bc1c | 147 | #define V3D_TFU_COEF3(ver) ((ver >= 71) ? 0x00734 : 0x00430) |
| 1584f16c | 148 | |
| 0ad5bc1c | 149 | /* V3D 4.x only */ |
| 1584f16c EA |
150 | #define V3D_TFU_CRC 0x00434 |
| 151 | ||
| 57692c94 EA |
152 | /* Per-MMU registers. */ |
| 153 | ||
| 154 | #define V3D_MMUC_CONTROL 0x01000 | |
| 0ad5bc1c | 155 | #define V3D_MMUC_CONTROL_CLEAR(ver) ((ver >= 71) ? BIT(11) : BIT(3)) |
| 57692c94 EA |
156 | # define V3D_MMUC_CONTROL_FLUSHING BIT(2) |
| 157 | # define V3D_MMUC_CONTROL_FLUSH BIT(1) | |
| 158 | # define V3D_MMUC_CONTROL_ENABLE BIT(0) | |
| 159 | ||
| 160 | #define V3D_MMU_CTL 0x01200 | |
| 161 | # define V3D_MMU_CTL_CAP_EXCEEDED BIT(27) | |
| 162 | # define V3D_MMU_CTL_CAP_EXCEEDED_ABORT BIT(26) | |
| 163 | # define V3D_MMU_CTL_CAP_EXCEEDED_INT BIT(25) | |
| 164 | # define V3D_MMU_CTL_CAP_EXCEEDED_EXCEPTION BIT(24) | |
| 165 | # define V3D_MMU_CTL_PT_INVALID BIT(20) | |
| 166 | # define V3D_MMU_CTL_PT_INVALID_ABORT BIT(19) | |
| 167 | # define V3D_MMU_CTL_PT_INVALID_INT BIT(18) | |
| 168 | # define V3D_MMU_CTL_PT_INVALID_EXCEPTION BIT(17) | |
| 38c2c791 EA |
169 | # define V3D_MMU_CTL_PT_INVALID_ENABLE BIT(16) |
| 170 | # define V3D_MMU_CTL_WRITE_VIOLATION BIT(12) | |
| 57692c94 EA |
171 | # define V3D_MMU_CTL_WRITE_VIOLATION_ABORT BIT(11) |
| 172 | # define V3D_MMU_CTL_WRITE_VIOLATION_INT BIT(10) | |
| 173 | # define V3D_MMU_CTL_WRITE_VIOLATION_EXCEPTION BIT(9) | |
| 174 | # define V3D_MMU_CTL_TLB_CLEARING BIT(7) | |
| 175 | # define V3D_MMU_CTL_TLB_STATS_CLEAR BIT(3) | |
| 176 | # define V3D_MMU_CTL_TLB_CLEAR BIT(2) | |
| 177 | # define V3D_MMU_CTL_TLB_STATS_ENABLE BIT(1) | |
| 178 | # define V3D_MMU_CTL_ENABLE BIT(0) | |
| 179 | ||
| 180 | #define V3D_MMU_PT_PA_BASE 0x01204 | |
| 181 | #define V3D_MMU_HIT 0x01208 | |
| 182 | #define V3D_MMU_MISSES 0x0120c | |
| 183 | #define V3D_MMU_STALLS 0x01210 | |
| 184 | ||
| 185 | #define V3D_MMU_ADDR_CAP 0x01214 | |
| 186 | # define V3D_MMU_ADDR_CAP_ENABLE BIT(31) | |
| 187 | # define V3D_MMU_ADDR_CAP_MPAGE_MASK V3D_MASK(11, 0) | |
| 188 | # define V3D_MMU_ADDR_CAP_MPAGE_SHIFT 0 | |
| 189 | ||
| 190 | #define V3D_MMU_SHOOT_DOWN 0x01218 | |
| 191 | # define V3D_MMU_SHOOT_DOWN_SHOOTING BIT(29) | |
| 192 | # define V3D_MMU_SHOOT_DOWN_SHOOT BIT(28) | |
| 193 | # define V3D_MMU_SHOOT_DOWN_PAGE_MASK V3D_MASK(27, 0) | |
| 194 | # define V3D_MMU_SHOOT_DOWN_PAGE_SHIFT 0 | |
| 195 | ||
| 196 | #define V3D_MMU_BYPASS_START 0x0121c | |
| 197 | #define V3D_MMU_BYPASS_END 0x01220 | |
| 198 | ||
| 199 | /* AXI ID of the access that faulted */ | |
| 200 | #define V3D_MMU_VIO_ID 0x0122c | |
| 201 | ||
| 202 | /* Address for illegal PTEs to return */ | |
| 203 | #define V3D_MMU_ILLEGAL_ADDR 0x01230 | |
| 204 | # define V3D_MMU_ILLEGAL_ADDR_ENABLE BIT(31) | |
| 205 | ||
| 206 | /* Address that faulted */ | |
| 207 | #define V3D_MMU_VIO_ADDR 0x01234 | |
| 208 | ||
| 091d6283 EA |
209 | #define V3D_MMU_DEBUG_INFO 0x01238 |
| 210 | # define V3D_MMU_PA_WIDTH_MASK V3D_MASK(11, 8) | |
| 211 | # define V3D_MMU_PA_WIDTH_SHIFT 8 | |
| 212 | # define V3D_MMU_VA_WIDTH_MASK V3D_MASK(7, 4) | |
| 213 | # define V3D_MMU_VA_WIDTH_SHIFT 4 | |
| 214 | # define V3D_MMU_VERSION_MASK V3D_MASK(3, 0) | |
| 215 | # define V3D_MMU_VERSION_SHIFT 0 | |
| 216 | ||
| 57692c94 EA |
217 | /* Per-V3D-core registers */ |
| 218 | ||
| 219 | #define V3D_CTL_IDENT0 0x00000 | |
| 220 | # define V3D_IDENT0_VER_MASK V3D_MASK(31, 24) | |
| 221 | # define V3D_IDENT0_VER_SHIFT 24 | |
| 222 | ||
| 223 | #define V3D_CTL_IDENT1 0x00004 | |
| 224 | /* Multiples of 1kb */ | |
| 225 | # define V3D_IDENT1_VPM_SIZE_MASK V3D_MASK(31, 28) | |
| 226 | # define V3D_IDENT1_VPM_SIZE_SHIFT 28 | |
| 227 | # define V3D_IDENT1_NSEM_MASK V3D_MASK(23, 16) | |
| 228 | # define V3D_IDENT1_NSEM_SHIFT 16 | |
| 229 | # define V3D_IDENT1_NTMU_MASK V3D_MASK(15, 12) | |
| 230 | # define V3D_IDENT1_NTMU_SHIFT 12 | |
| 231 | # define V3D_IDENT1_QUPS_MASK V3D_MASK(11, 8) | |
| 232 | # define V3D_IDENT1_QUPS_SHIFT 8 | |
| 233 | # define V3D_IDENT1_NSLC_MASK V3D_MASK(7, 4) | |
| 234 | # define V3D_IDENT1_NSLC_SHIFT 4 | |
| 235 | # define V3D_IDENT1_REV_MASK V3D_MASK(3, 0) | |
| 236 | # define V3D_IDENT1_REV_SHIFT 0 | |
| 237 | ||
| 238 | #define V3D_CTL_IDENT2 0x00008 | |
| 239 | # define V3D_IDENT2_BCG_INT BIT(28) | |
| 240 | ||
| 241 | #define V3D_CTL_MISCCFG 0x00018 | |
| a7dde1b7 EA |
242 | # define V3D_CTL_MISCCFG_QRMAXCNT_MASK V3D_MASK(3, 1) |
| 243 | # define V3D_CTL_MISCCFG_QRMAXCNT_SHIFT 1 | |
| 57692c94 EA |
244 | # define V3D_MISCCFG_OVRTMUOUT BIT(0) |
| 245 | ||
| 246 | #define V3D_CTL_L2CACTL 0x00020 | |
| 247 | # define V3D_L2CACTL_L2CCLR BIT(2) | |
| 248 | # define V3D_L2CACTL_L2CDIS BIT(1) | |
| 249 | # define V3D_L2CACTL_L2CENA BIT(0) | |
| 250 | ||
| 251 | #define V3D_CTL_SLCACTL 0x00024 | |
| 252 | # define V3D_SLCACTL_TVCCS_MASK V3D_MASK(27, 24) | |
| 253 | # define V3D_SLCACTL_TVCCS_SHIFT 24 | |
| 254 | # define V3D_SLCACTL_TDCCS_MASK V3D_MASK(19, 16) | |
| 255 | # define V3D_SLCACTL_TDCCS_SHIFT 16 | |
| 256 | # define V3D_SLCACTL_UCC_MASK V3D_MASK(11, 8) | |
| 257 | # define V3D_SLCACTL_UCC_SHIFT 8 | |
| 258 | # define V3D_SLCACTL_ICC_MASK V3D_MASK(3, 0) | |
| 259 | # define V3D_SLCACTL_ICC_SHIFT 0 | |
| 260 | ||
| 261 | #define V3D_CTL_L2TCACTL 0x00030 | |
| 262 | # define V3D_L2TCACTL_TMUWCF BIT(8) | |
| d223f98f | 263 | /* Invalidates cache lines. */ |
| 57692c94 | 264 | # define V3D_L2TCACTL_FLM_FLUSH 0 |
| d223f98f | 265 | /* Removes cachelines without writing dirty lines back. */ |
| 57692c94 | 266 | # define V3D_L2TCACTL_FLM_CLEAR 1 |
| d223f98f | 267 | /* Writes out dirty cachelines and marks them clean, but doesn't invalidate. */ |
| 57692c94 EA |
268 | # define V3D_L2TCACTL_FLM_CLEAN 2 |
| 269 | # define V3D_L2TCACTL_FLM_MASK V3D_MASK(2, 1) | |
| 270 | # define V3D_L2TCACTL_FLM_SHIFT 1 | |
| 271 | # define V3D_L2TCACTL_L2TFLS BIT(0) | |
| 272 | #define V3D_CTL_L2TFLSTA 0x00034 | |
| 273 | #define V3D_CTL_L2TFLEND 0x00038 | |
| 274 | ||
| 275 | #define V3D_CTL_INT_STS 0x00050 | |
| 276 | #define V3D_CTL_INT_SET 0x00054 | |
| 277 | #define V3D_CTL_INT_CLR 0x00058 | |
| 278 | #define V3D_CTL_INT_MSK_STS 0x0005c | |
| 279 | #define V3D_CTL_INT_MSK_SET 0x00060 | |
| 280 | #define V3D_CTL_INT_MSK_CLR 0x00064 | |
| 281 | # define V3D_INT_QPU_MASK V3D_MASK(27, 16) | |
| 282 | # define V3D_INT_QPU_SHIFT 16 | |
| 0ad5bc1c ITQ |
283 | #define V3D_INT_CSDDONE(ver) ((ver >= 71) ? BIT(6) : BIT(7)) |
| 284 | #define V3D_INT_PCTR(ver) ((ver >= 71) ? BIT(5) : BIT(6)) | |
| 57692c94 EA |
285 | # define V3D_INT_GMPV BIT(5) |
| 286 | # define V3D_INT_TRFB BIT(4) | |
| 287 | # define V3D_INT_SPILLUSE BIT(3) | |
| 288 | # define V3D_INT_OUTOMEM BIT(2) | |
| 289 | # define V3D_INT_FLDONE BIT(1) | |
| 290 | # define V3D_INT_FRDONE BIT(0) | |
| 291 | ||
| 292 | #define V3D_CLE_CT0CS 0x00100 | |
| 293 | #define V3D_CLE_CT1CS 0x00104 | |
| 294 | #define V3D_CLE_CTNCS(n) (V3D_CLE_CT0CS + 4 * n) | |
| 295 | #define V3D_CLE_CT0EA 0x00108 | |
| 296 | #define V3D_CLE_CT1EA 0x0010c | |
| 297 | #define V3D_CLE_CTNEA(n) (V3D_CLE_CT0EA + 4 * n) | |
| 298 | #define V3D_CLE_CT0CA 0x00110 | |
| 299 | #define V3D_CLE_CT1CA 0x00114 | |
| 300 | #define V3D_CLE_CTNCA(n) (V3D_CLE_CT0CA + 4 * n) | |
| 301 | #define V3D_CLE_CT0RA 0x00118 | |
| 302 | #define V3D_CLE_CT1RA 0x0011c | |
| 624bb0c0 | 303 | #define V3D_CLE_CTNRA(n) (V3D_CLE_CT0RA + 4 * n) |
| 57692c94 EA |
304 | #define V3D_CLE_CT0LC 0x00120 |
| 305 | #define V3D_CLE_CT1LC 0x00124 | |
| 306 | #define V3D_CLE_CT0PC 0x00128 | |
| 307 | #define V3D_CLE_CT1PC 0x0012c | |
| 308 | #define V3D_CLE_PCS 0x00130 | |
| 309 | #define V3D_CLE_BFC 0x00134 | |
| 310 | #define V3D_CLE_RFC 0x00138 | |
| 311 | #define V3D_CLE_TFBC 0x0013c | |
| 312 | #define V3D_CLE_TFIT 0x00140 | |
| 313 | #define V3D_CLE_CT1CFG 0x00144 | |
| 314 | #define V3D_CLE_CT1TILECT 0x00148 | |
| 315 | #define V3D_CLE_CT1TSKIP 0x0014c | |
| 316 | #define V3D_CLE_CT1PTCT 0x00150 | |
| 317 | #define V3D_CLE_CT0SYNC 0x00154 | |
| 318 | #define V3D_CLE_CT1SYNC 0x00158 | |
| 319 | #define V3D_CLE_CT0QTS 0x0015c | |
| 320 | # define V3D_CLE_CT0QTS_ENABLE BIT(1) | |
| 321 | #define V3D_CLE_CT0QBA 0x00160 | |
| 322 | #define V3D_CLE_CT1QBA 0x00164 | |
| 323 | #define V3D_CLE_CTNQBA(n) (V3D_CLE_CT0QBA + 4 * n) | |
| 324 | #define V3D_CLE_CT0QEA 0x00168 | |
| 325 | #define V3D_CLE_CT1QEA 0x0016c | |
| 326 | #define V3D_CLE_CTNQEA(n) (V3D_CLE_CT0QEA + 4 * n) | |
| 327 | #define V3D_CLE_CT0QMA 0x00170 | |
| 328 | #define V3D_CLE_CT0QMS 0x00174 | |
| 329 | #define V3D_CLE_CT1QCFG 0x00178 | |
| 330 | /* If set without ETPROC, entirely skip tiles with no primitives. */ | |
| 331 | # define V3D_CLE_QCFG_ETFILT BIT(7) | |
| 332 | /* If set with ETFILT, just write the clear color to tiles with no | |
| 333 | * primitives. | |
| 334 | */ | |
| 335 | # define V3D_CLE_QCFG_ETPROC BIT(6) | |
| 336 | # define V3D_CLE_QCFG_ETSFLUSH BIT(1) | |
| 337 | # define V3D_CLE_QCFG_MCDIS BIT(0) | |
| 338 | ||
| 339 | #define V3D_PTB_BPCA 0x00300 | |
| 340 | #define V3D_PTB_BPCS 0x00304 | |
| 341 | #define V3D_PTB_BPOA 0x00308 | |
| 342 | #define V3D_PTB_BPOS 0x0030c | |
| 343 | ||
| 344 | #define V3D_PTB_BXCF 0x00310 | |
| 345 | # define V3D_PTB_BXCF_RWORDERDISA BIT(1) | |
| 346 | # define V3D_PTB_BXCF_CLIPDISA BIT(0) | |
| 347 | ||
| 6915c9a5 EA |
348 | #define V3D_V3_PCTR_0_EN 0x00674 |
| 349 | #define V3D_V3_PCTR_0_EN_ENABLE BIT(31) | |
| 350 | #define V3D_V4_PCTR_0_EN 0x00650 | |
| 351 | /* When a bit is set, resets the counter to 0. */ | |
| 352 | #define V3D_V3_PCTR_0_CLR 0x00670 | |
| 353 | #define V3D_V4_PCTR_0_CLR 0x00654 | |
| 354 | #define V3D_PCTR_0_OVERFLOW 0x00658 | |
| 355 | ||
| 356 | #define V3D_V3_PCTR_0_PCTRS0 0x00684 | |
| 357 | #define V3D_V3_PCTR_0_PCTRS15 0x00660 | |
| 358 | #define V3D_V3_PCTR_0_PCTRSX(x) (V3D_V3_PCTR_0_PCTRS0 + \ | |
| 359 | 4 * (x)) | |
| 360 | /* Each src reg muxes four counters each. */ | |
| 361 | #define V3D_V4_PCTR_0_SRC_0_3 0x00660 | |
| 362 | #define V3D_V4_PCTR_0_SRC_28_31 0x0067c | |
| 26a4dc29 JSR |
363 | #define V3D_V4_PCTR_0_SRC_X(x) (V3D_V4_PCTR_0_SRC_0_3 + \ |
| 364 | 4 * (x)) | |
| e987e22e MC |
365 | # define V3D_PCTR_S0_MASK(ver) (((ver) >= 71) ? V3D_MASK(7, 0) : V3D_MASK(6, 0)) |
| 366 | # define V3D_PCTR_S0_SHIFT(ver) 0 | |
| 367 | # define V3D_PCTR_S1_MASK(ver) (((ver) >= 71) ? V3D_MASK(15, 8) : V3D_MASK(14, 8)) | |
| 368 | # define V3D_PCTR_S1_SHIFT(ver) 8 | |
| 369 | # define V3D_PCTR_S2_MASK(ver) (((ver) >= 71) ? V3D_MASK(23, 16) : V3D_MASK(22, 16)) | |
| 370 | # define V3D_PCTR_S2_SHIFT(ver) 16 | |
| 371 | # define V3D_PCTR_S3_MASK(ver) (((ver) >= 71) ? V3D_MASK(31, 24) : V3D_MASK(30, 24)) | |
| 372 | # define V3D_PCTR_S3_SHIFT(ver) 24 | |
| 373 | ||
| 0ad5bc1c | 374 | #define V3D_PCTR_CYCLE_COUNT(ver) ((ver >= 71) ? 0 : 32) |
| 6915c9a5 EA |
375 | |
| 376 | /* Output values of the counters. */ | |
| 377 | #define V3D_PCTR_0_PCTR0 0x00680 | |
| 378 | #define V3D_PCTR_0_PCTR31 0x006fc | |
| 379 | #define V3D_PCTR_0_PCTRX(x) (V3D_PCTR_0_PCTR0 + \ | |
| 380 | 4 * (x)) | |
| 0ad5bc1c | 381 | #define V3D_GMP_STATUS(ver) ((ver >= 71) ? 0x00600 : 0x00800) |
| 57692c94 EA |
382 | # define V3D_GMP_STATUS_GMPRST BIT(31) |
| 383 | # define V3D_GMP_STATUS_WR_COUNT_MASK V3D_MASK(30, 24) | |
| 384 | # define V3D_GMP_STATUS_WR_COUNT_SHIFT 24 | |
| 385 | # define V3D_GMP_STATUS_RD_COUNT_MASK V3D_MASK(22, 16) | |
| 386 | # define V3D_GMP_STATUS_RD_COUNT_SHIFT 16 | |
| 387 | # define V3D_GMP_STATUS_WR_ACTIVE BIT(5) | |
| 388 | # define V3D_GMP_STATUS_RD_ACTIVE BIT(4) | |
| 389 | # define V3D_GMP_STATUS_CFG_BUSY BIT(3) | |
| 390 | # define V3D_GMP_STATUS_CNTOVF BIT(2) | |
| 391 | # define V3D_GMP_STATUS_INVPROT BIT(1) | |
| 392 | # define V3D_GMP_STATUS_VIO BIT(0) | |
| 393 | ||
| 0ad5bc1c | 394 | #define V3D_GMP_CFG(ver) ((ver >= 71) ? 0x00604 : 0x00804) |
| 57692c94 EA |
395 | # define V3D_GMP_CFG_LBURSTEN BIT(3) |
| 396 | # define V3D_GMP_CFG_PGCRSEN BIT() | |
| 397 | # define V3D_GMP_CFG_STOP_REQ BIT(1) | |
| 398 | # define V3D_GMP_CFG_PROT_ENABLE BIT(0) | |
| 399 | ||
| 0ad5bc1c | 400 | #define V3D_GMP_VIO_ADDR(ver) ((ver >= 71) ? 0x00608 : 0x00808) |
| 57692c94 EA |
401 | #define V3D_GMP_VIO_TYPE 0x0080c |
| 402 | #define V3D_GMP_TABLE_ADDR 0x00810 | |
| 403 | #define V3D_GMP_CLEAR_LOAD 0x00814 | |
| 404 | #define V3D_GMP_PRESERVE_LOAD 0x00818 | |
| 405 | #define V3D_GMP_VALID_LINES 0x00820 | |
| 406 | ||
| d223f98f EA |
407 | #define V3D_CSD_STATUS 0x00900 |
| 408 | # define V3D_CSD_STATUS_NUM_COMPLETED_MASK V3D_MASK(11, 4) | |
| 409 | # define V3D_CSD_STATUS_NUM_COMPLETED_SHIFT 4 | |
| 410 | # define V3D_CSD_STATUS_NUM_ACTIVE_MASK V3D_MASK(3, 2) | |
| 411 | # define V3D_CSD_STATUS_NUM_ACTIVE_SHIFT 2 | |
| 412 | # define V3D_CSD_STATUS_HAVE_CURRENT_DISPATCH BIT(1) | |
| 413 | # define V3D_CSD_STATUS_HAVE_QUEUED_DISPATCH BIT(0) | |
| 414 | ||
| 0ad5bc1c | 415 | #define V3D_CSD_QUEUED_CFG0(ver) ((ver >= 71) ? 0x00930 : 0x00904) |
| d223f98f EA |
416 | # define V3D_CSD_QUEUED_CFG0_NUM_WGS_X_MASK V3D_MASK(31, 16) |
| 417 | # define V3D_CSD_QUEUED_CFG0_NUM_WGS_X_SHIFT 16 | |
| 418 | # define V3D_CSD_QUEUED_CFG0_WG_X_OFFSET_MASK V3D_MASK(15, 0) | |
| 419 | # define V3D_CSD_QUEUED_CFG0_WG_X_OFFSET_SHIFT 0 | |
| 420 | ||
| 0ad5bc1c | 421 | #define V3D_CSD_QUEUED_CFG1(ver) ((ver >= 71) ? 0x00934 : 0x00908) |
| d223f98f EA |
422 | # define V3D_CSD_QUEUED_CFG1_NUM_WGS_Y_MASK V3D_MASK(31, 16) |
| 423 | # define V3D_CSD_QUEUED_CFG1_NUM_WGS_Y_SHIFT 16 | |
| 424 | # define V3D_CSD_QUEUED_CFG1_WG_Y_OFFSET_MASK V3D_MASK(15, 0) | |
| 425 | # define V3D_CSD_QUEUED_CFG1_WG_Y_OFFSET_SHIFT 0 | |
| 426 | ||
| 0ad5bc1c | 427 | #define V3D_CSD_QUEUED_CFG2(ver) ((ver >= 71) ? 0x00938 : 0x0090c) |
| d223f98f EA |
428 | # define V3D_CSD_QUEUED_CFG2_NUM_WGS_Z_MASK V3D_MASK(31, 16) |
| 429 | # define V3D_CSD_QUEUED_CFG2_NUM_WGS_Z_SHIFT 16 | |
| 430 | # define V3D_CSD_QUEUED_CFG2_WG_Z_OFFSET_MASK V3D_MASK(15, 0) | |
| 431 | # define V3D_CSD_QUEUED_CFG2_WG_Z_OFFSET_SHIFT 0 | |
| 432 | ||
| 0ad5bc1c | 433 | #define V3D_CSD_QUEUED_CFG3(ver) ((ver >= 71) ? 0x0093c : 0x00910) |
| d223f98f EA |
434 | # define V3D_CSD_QUEUED_CFG3_OVERLAP_WITH_PREV BIT(26) |
| 435 | # define V3D_CSD_QUEUED_CFG3_MAX_SG_ID_MASK V3D_MASK(25, 20) | |
| 436 | # define V3D_CSD_QUEUED_CFG3_MAX_SG_ID_SHIFT 20 | |
| 437 | # define V3D_CSD_QUEUED_CFG3_BATCHES_PER_SG_M1_MASK V3D_MASK(19, 12) | |
| 438 | # define V3D_CSD_QUEUED_CFG3_BATCHES_PER_SG_M1_SHIFT 12 | |
| 439 | # define V3D_CSD_QUEUED_CFG3_WGS_PER_SG_MASK V3D_MASK(11, 8) | |
| 440 | # define V3D_CSD_QUEUED_CFG3_WGS_PER_SG_SHIFT 8 | |
| 441 | # define V3D_CSD_QUEUED_CFG3_WG_SIZE_MASK V3D_MASK(7, 0) | |
| 442 | # define V3D_CSD_QUEUED_CFG3_WG_SIZE_SHIFT 0 | |
| 443 | ||
| 444 | /* Number of batches, minus 1 */ | |
| 0ad5bc1c | 445 | #define V3D_CSD_QUEUED_CFG4(ver) ((ver >= 71) ? 0x00940 : 0x00914) |
| d223f98f EA |
446 | |
| 447 | /* Shader address, pnan, singleseg, threading, like a shader record. */ | |
| 0ad5bc1c | 448 | #define V3D_CSD_QUEUED_CFG5(ver) ((ver >= 71) ? 0x00944 : 0x00918) |
| d223f98f EA |
449 | |
| 450 | /* Uniforms address (4 byte aligned) */ | |
| 0ad5bc1c ITQ |
451 | #define V3D_CSD_QUEUED_CFG6(ver) ((ver >= 71) ? 0x00948 : 0x0091c) |
| 452 | ||
| 453 | /* V3D 7.x+ only */ | |
| 454 | #define V3D_V7_CSD_QUEUED_CFG7 0x0094c | |
| 455 | ||
| 456 | #define V3D_CSD_CURRENT_CFG0(ver) ((ver >= 71) ? 0x00958 : 0x00920) | |
| 457 | #define V3D_CSD_CURRENT_CFG1(ver) ((ver >= 71) ? 0x0095c : 0x00924) | |
| 458 | #define V3D_CSD_CURRENT_CFG2(ver) ((ver >= 71) ? 0x00960 : 0x00928) | |
| 459 | #define V3D_CSD_CURRENT_CFG3(ver) ((ver >= 71) ? 0x00964 : 0x0092c) | |
| 460 | #define V3D_CSD_CURRENT_CFG4(ver) ((ver >= 71) ? 0x00968 : 0x00930) | |
| 461 | #define V3D_CSD_CURRENT_CFG5(ver) ((ver >= 71) ? 0x0096c : 0x00934) | |
| 462 | #define V3D_CSD_CURRENT_CFG6(ver) ((ver >= 71) ? 0x00970 : 0x00938) | |
| 463 | /* V3D 7.x+ only */ | |
| 464 | #define V3D_V7_CSD_CURRENT_CFG7 0x00974 | |
| 465 | ||
| 466 | #define V3D_CSD_CURRENT_ID0(ver) ((ver >= 71) ? 0x00978 : 0x0093c) | |
| d223f98f EA |
467 | # define V3D_CSD_CURRENT_ID0_WG_X_MASK V3D_MASK(31, 16) |
| 468 | # define V3D_CSD_CURRENT_ID0_WG_X_SHIFT 16 | |
| 469 | # define V3D_CSD_CURRENT_ID0_WG_IN_SG_MASK V3D_MASK(11, 8) | |
| 470 | # define V3D_CSD_CURRENT_ID0_WG_IN_SG_SHIFT 8 | |
| 471 | # define V3D_CSD_CURRENT_ID0_L_IDX_MASK V3D_MASK(7, 0) | |
| 472 | # define V3D_CSD_CURRENT_ID0_L_IDX_SHIFT 0 | |
| 473 | ||
| 0ad5bc1c | 474 | #define V3D_CSD_CURRENT_ID1(ver) ((ver >= 71) ? 0x0097c : 0x00940) |
| d223f98f EA |
475 | # define V3D_CSD_CURRENT_ID0_WG_Z_MASK V3D_MASK(31, 16) |
| 476 | # define V3D_CSD_CURRENT_ID0_WG_Z_SHIFT 16 | |
| 477 | # define V3D_CSD_CURRENT_ID0_WG_Y_MASK V3D_MASK(15, 0) | |
| 478 | # define V3D_CSD_CURRENT_ID0_WG_Y_SHIFT 0 | |
| 479 | ||
| 1ba9d7cb EA |
480 | #define V3D_ERR_FDBGO 0x00f04 |
| 481 | #define V3D_ERR_FDBGB 0x00f08 | |
| 482 | #define V3D_ERR_FDBGR 0x00f0c | |
| 483 | ||
| 484 | #define V3D_ERR_FDBGS 0x00f10 | |
| 485 | # define V3D_ERR_FDBGS_INTERPZ_IP_STALL BIT(17) | |
| 486 | # define V3D_ERR_FDBGS_DEPTHO_FIFO_IP_STALL BIT(16) | |
| 487 | # define V3D_ERR_FDBGS_XYNRM_IP_STALL BIT(14) | |
| 488 | # define V3D_ERR_FDBGS_EZREQ_FIFO_OP_VALID BIT(13) | |
| 489 | # define V3D_ERR_FDBGS_QXYF_FIFO_OP_VALID BIT(12) | |
| 490 | # define V3D_ERR_FDBGS_QXYF_FIFO_OP_LAST BIT(11) | |
| 491 | # define V3D_ERR_FDBGS_EZTEST_ANYQVALID BIT(7) | |
| 492 | # define V3D_ERR_FDBGS_EZTEST_PASS BIT(6) | |
| 493 | # define V3D_ERR_FDBGS_EZTEST_QREADY BIT(5) | |
| 494 | # define V3D_ERR_FDBGS_EZTEST_VLF_OKNOVALID BIT(4) | |
| 495 | # define V3D_ERR_FDBGS_EZTEST_QSTALL BIT(3) | |
| 496 | # define V3D_ERR_FDBGS_EZTEST_IP_VLFSTALL BIT(2) | |
| 497 | # define V3D_ERR_FDBGS_EZTEST_IP_PRSTALL BIT(1) | |
| 498 | # define V3D_ERR_FDBGS_EZTEST_IP_QSTALL BIT(0) | |
| 499 | ||
| 500 | #define V3D_ERR_STAT 0x00f20 | |
| 501 | # define V3D_ERR_L2CARE BIT(15) | |
| 502 | # define V3D_ERR_VCMBE BIT(14) | |
| 503 | # define V3D_ERR_VCMRE BIT(13) | |
| 504 | # define V3D_ERR_VCDI BIT(12) | |
| 505 | # define V3D_ERR_VCDE BIT(11) | |
| 506 | # define V3D_ERR_VDWE BIT(10) | |
| 507 | # define V3D_ERR_VPMEAS BIT(9) | |
| 508 | # define V3D_ERR_VPMEFNA BIT(8) | |
| 509 | # define V3D_ERR_VPMEWNA BIT(7) | |
| 510 | # define V3D_ERR_VPMERNA BIT(6) | |
| 511 | # define V3D_ERR_VPMERR BIT(5) | |
| 512 | # define V3D_ERR_VPMEWR BIT(4) | |
| 513 | # define V3D_ERR_VPAERRGL BIT(3) | |
| 514 | # define V3D_ERR_VPAEBRGL BIT(2) | |
| 515 | # define V3D_ERR_VPAERGS BIT(1) | |
| 516 | # define V3D_ERR_VPAEABB BIT(0) | |
| 517 | ||
| 1bdf2ccc MC |
518 | #define V3D_SMS_REE_CS 0x00000 |
| 519 | #define V3D_SMS_TEE_CS 0x00400 | |
| 520 | # define V3D_SMS_INTERRUPT BIT(31) | |
| 521 | # define V3D_SMS_POWER_OFF BIT(30) | |
| 522 | # define V3D_SMS_CLEAR_POWER_OFF BIT(29) | |
| 523 | # define V3D_SMS_LOCK BIT(28) | |
| 524 | # define V3D_SMS_CLEAR_LOCK BIT(27) | |
| 525 | # define V3D_SMS_SVP_MODE_EXIT BIT(26) | |
| 526 | # define V3D_SMS_CLEAR_SVP_MODE_EXIT BIT(25) | |
| 527 | # define V3D_SMS_SVP_MODE_ENTER BIT(24) | |
| 528 | # define V3D_SMS_CLEAR_SVP_MODE_ENTER BIT(23) | |
| 529 | # define V3D_SMS_THEIR_MODE_EXIT BIT(22) | |
| 530 | # define V3D_SMS_THEIR_MODE_ENTER BIT(21) | |
| 531 | # define V3D_SMS_OUR_MODE_EXIT BIT(20) | |
| 532 | # define V3D_SMS_CLEAR_OUR_MODE_EXIT BIT(19) | |
| 533 | # define V3D_SMS_SEQ_PC_MASK V3D_MASK(16, 10) | |
| 534 | # define V3D_SMS_SEQ_PC_SHIFT 10 | |
| 535 | # define V3D_SMS_HUBCORE_STATUS_MASK V3D_MASK(9, 8) | |
| 536 | # define V3D_SMS_HUBCORE_STATUS_SHIFT 8 | |
| 537 | # define V3D_SMS_NEW_MODE_MASK V3D_MASK(7, 6) | |
| 538 | # define V3D_SMS_NEW_MODE_SHIFT 6 | |
| 539 | # define V3D_SMS_OLD_MODE_MASK V3D_MASK(5, 4) | |
| 540 | # define V3D_SMS_OLD_MODE_SHIFT 4 | |
| 541 | # define V3D_SMS_STATE_MASK V3D_MASK(3, 0) | |
| 542 | # define V3D_SMS_STATE_SHIFT 0 | |
| 543 | ||
| 57692c94 | 544 | #endif /* V3D_REGS_H */ |