[linux-block.git] / drivers / gpu / drm / tiny / bochs.c

// SPDX-License-Identifier: GPL-2.0-or-later

#include <linux/module.h>
#include <linux/pci.h>

#include <drm/drm_aperture.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_drv.h>
#include <drm/drm_edid.h>
#include <drm/drm_fb_helper.h>
#include <drm/drm_fourcc.h>
#include <drm/drm_framebuffer.h>
#include <drm/drm_gem_framebuffer_helper.h>
#include <drm/drm_gem_vram_helper.h>
#include <drm/drm_managed.h>
#include <drm/drm_module.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_simple_kms_helper.h>

#include <video/vga.h>

/* ---------------------------------------------------------------------- */

#define VBE_DISPI_IOPORT_INDEX           0x01CE
#define VBE_DISPI_IOPORT_DATA            0x01CF

#define VBE_DISPI_INDEX_ID               0x0
#define VBE_DISPI_INDEX_XRES             0x1
#define VBE_DISPI_INDEX_YRES             0x2
#define VBE_DISPI_INDEX_BPP              0x3
#define VBE_DISPI_INDEX_ENABLE           0x4
#define VBE_DISPI_INDEX_BANK             0x5
#define VBE_DISPI_INDEX_VIRT_WIDTH       0x6
#define VBE_DISPI_INDEX_VIRT_HEIGHT      0x7
#define VBE_DISPI_INDEX_X_OFFSET         0x8
#define VBE_DISPI_INDEX_Y_OFFSET         0x9
#define VBE_DISPI_INDEX_VIDEO_MEMORY_64K 0xa

#define VBE_DISPI_ID0                    0xB0C0
#define VBE_DISPI_ID1                    0xB0C1
#define VBE_DISPI_ID2                    0xB0C2
#define VBE_DISPI_ID3                    0xB0C3
#define VBE_DISPI_ID4                    0xB0C4
#define VBE_DISPI_ID5                    0xB0C5

#define VBE_DISPI_DISABLED               0x00
#define VBE_DISPI_ENABLED                0x01
#define VBE_DISPI_GETCAPS                0x02
#define VBE_DISPI_8BIT_DAC               0x20
#define VBE_DISPI_LFB_ENABLED            0x40
#define VBE_DISPI_NOCLEARMEM             0x80

static int bochs_modeset = -1;
static int defx = 1024;
static int defy = 768;

module_param_named(modeset, bochs_modeset, int, 0444);
MODULE_PARM_DESC(modeset, "enable/disable kernel modesetting");

module_param(defx, int, 0444);
module_param(defy, int, 0444);
MODULE_PARM_DESC(defx, "default x resolution");
MODULE_PARM_DESC(defy, "default y resolution");

/* ---------------------------------------------------------------------- */

enum bochs_types {
	BOCHS_QEMU_STDVGA,
	BOCHS_SIMICS,
	BOCHS_UNKNOWN,
};

struct bochs_device {
	/* hw */
	void __iomem   *mmio;
	int            ioports;
	void __iomem   *fb_map;
	unsigned long  fb_base;
	unsigned long  fb_size;
	unsigned long  qext_size;

	/* mode */
	u16 xres;
	u16 yres;
	u16 yres_virtual;
	u32 stride;
	u32 bpp;
	struct edid *edid;

	/* drm */
	struct drm_device *dev;
	struct drm_simple_display_pipe pipe;
	struct drm_connector connector;
};

/* ---------------------------------------------------------------------- */

static void bochs_vga_writeb(struct bochs_device *bochs, u16 ioport, u8 val)
{
	if (WARN_ON(ioport < 0x3c0 || ioport > 0x3df))
		return;

	if (bochs->mmio) {
		int offset = ioport - 0x3c0 + 0x400;

		writeb(val, bochs->mmio + offset);
	} else {
		outb(val, ioport);
	}
}

static u8 bochs_vga_readb(struct bochs_device *bochs, u16 ioport)
{
	if (WARN_ON(ioport < 0x3c0 || ioport > 0x3df))
		return 0xff;

	if (bochs->mmio) {
		int offset = ioport - 0x3c0 + 0x400;

		return readb(bochs->mmio + offset);
	} else {
		return inb(ioport);
	}
}

static u16 bochs_dispi_read(struct bochs_device *bochs, u16 reg)
{
	u16 ret = 0;

	if (bochs->mmio) {
		int offset = 0x500 + (reg << 1);

		ret = readw(bochs->mmio + offset);
	} else {
		outw(reg, VBE_DISPI_IOPORT_INDEX);
		ret = inw(VBE_DISPI_IOPORT_DATA);
	}
	return ret;
}

static void bochs_dispi_write(struct bochs_device *bochs, u16 reg, u16 val)
{
	if (bochs->mmio) {
		int offset = 0x500 + (reg << 1);

		writew(val, bochs->mmio + offset);
	} else {
		outw(reg, VBE_DISPI_IOPORT_INDEX);
		outw(val, VBE_DISPI_IOPORT_DATA);
	}
}

static void bochs_hw_set_big_endian(struct bochs_device *bochs)
{
	if (bochs->qext_size < 8)
		return;

	writel(0xbebebebe, bochs->mmio + 0x604);
}

static void bochs_hw_set_little_endian(struct bochs_device *bochs)
{
	if (bochs->qext_size < 8)
		return;

	writel(0x1e1e1e1e, bochs->mmio + 0x604);
}

#ifdef __BIG_ENDIAN
#define bochs_hw_set_native_endian(_b) bochs_hw_set_big_endian(_b)
#else
#define bochs_hw_set_native_endian(_b) bochs_hw_set_little_endian(_b)
#endif

static int bochs_get_edid_block(void *data, u8 *buf,
				unsigned int block, size_t len)
{
	struct bochs_device *bochs = data;
	size_t i, start = block * EDID_LENGTH;

	if (start + len > 0x400 /* vga register offset */)
		return -1;

	for (i = 0; i < len; i++)
		buf[i] = readb(bochs->mmio + start + i);

	return 0;
}

static int bochs_hw_load_edid(struct bochs_device *bochs)
{
	u8 header[8];

	if (!bochs->mmio)
		return -1;

	/* check header to detect whenever edid support is enabled in qemu */
	bochs_get_edid_block(bochs, header, 0, ARRAY_SIZE(header));
	if (drm_edid_header_is_valid(header) != 8)
		return -1;

	kfree(bochs->edid);
	bochs->edid = drm_do_get_edid(&bochs->connector,
				      bochs_get_edid_block, bochs);
	if (bochs->edid == NULL)
		return -1;

	return 0;
}

static int bochs_hw_init(struct drm_device *dev)
{
	struct bochs_device *bochs = dev->dev_private;
	struct pci_dev *pdev = to_pci_dev(dev->dev);
	unsigned long addr, size, mem, ioaddr, iosize;
	u16 id;

	if (pdev->resource[2].flags & IORESOURCE_MEM) {
		/* mmio bar with vga and bochs registers present */
		if (pci_request_region(pdev, 2, "bochs-drm") != 0) {
			DRM_ERROR("Cannot request mmio region\n");
			return -EBUSY;
		}
		ioaddr = pci_resource_start(pdev, 2);
		iosize = pci_resource_len(pdev, 2);
		bochs->mmio = ioremap(ioaddr, iosize);
		if (bochs->mmio == NULL) {
			DRM_ERROR("Cannot map mmio region\n");
			return -ENOMEM;
		}
	} else {
		ioaddr = VBE_DISPI_IOPORT_INDEX;
		iosize = 2;
		if (!request_region(ioaddr, iosize, "bochs-drm")) {
			DRM_ERROR("Cannot request ioports\n");
			return -EBUSY;
		}
		bochs->ioports = 1;
	}

	id = bochs_dispi_read(bochs, VBE_DISPI_INDEX_ID);
	mem = bochs_dispi_read(bochs, VBE_DISPI_INDEX_VIDEO_MEMORY_64K)
		* 64 * 1024;
	if ((id & 0xfff0) != VBE_DISPI_ID0) {
		DRM_ERROR("ID mismatch\n");
		return -ENODEV;
	}

	if ((pdev->resource[0].flags & IORESOURCE_MEM) == 0)
		return -ENODEV;
	addr = pci_resource_start(pdev, 0);
	size = pci_resource_len(pdev, 0);
	if (addr == 0)
		return -ENODEV;
	if (size != mem) {
		DRM_ERROR("Size mismatch: pci=%ld, bochs=%ld\n",
			size, mem);
		size = min(size, mem);
	}

	if (pci_request_region(pdev, 0, "bochs-drm") != 0)
		DRM_WARN("Cannot request framebuffer, boot fb still active?\n");

	bochs->fb_map = ioremap(addr, size);
	if (bochs->fb_map == NULL) {
		DRM_ERROR("Cannot map framebuffer\n");
		return -ENOMEM;
	}
	bochs->fb_base = addr;
	bochs->fb_size = size;

	DRM_INFO("Found bochs VGA, ID 0x%x.\n", id);
	DRM_INFO("Framebuffer size %ld kB @ 0x%lx, %s @ 0x%lx.\n",
		 size / 1024, addr,
		 bochs->ioports ? "ioports" : "mmio",
		 ioaddr);

	if (bochs->mmio && pdev->revision >= 2) {
		bochs->qext_size = readl(bochs->mmio + 0x600);
		if (bochs->qext_size < 4 || bochs->qext_size > iosize) {
			bochs->qext_size = 0;
			goto noext;
		}
		DRM_DEBUG("Found qemu ext regs, size %ld\n",
			  bochs->qext_size);
		bochs_hw_set_native_endian(bochs);
	}

noext:
	return 0;
}

static void bochs_hw_fini(struct drm_device *dev)
{
	struct bochs_device *bochs = dev->dev_private;

	/* TODO: shot down existing vram mappings */

	if (bochs->mmio)
		iounmap(bochs->mmio);
	if (bochs->ioports)
		release_region(VBE_DISPI_IOPORT_INDEX, 2);
	if (bochs->fb_map)
		iounmap(bochs->fb_map);
	pci_release_regions(to_pci_dev(dev->dev));
	kfree(bochs->edid);
}

static void bochs_hw_blank(struct bochs_device *bochs, bool blank)
{
	DRM_DEBUG_DRIVER("hw_blank %d\n", blank);
	/* enable color bit (so VGA_IS1_RC access works) */
	bochs_vga_writeb(bochs, VGA_MIS_W, VGA_MIS_COLOR);
	/* discard ar_flip_flop */
	(void)bochs_vga_readb(bochs, VGA_IS1_RC);
	/* blank or unblank; we need only update index and set 0x20 */
	bochs_vga_writeb(bochs, VGA_ATT_W, blank ? 0 : 0x20);
}

static void bochs_hw_setmode(struct bochs_device *bochs, struct drm_display_mode *mode)
{
	int idx;

	if (!drm_dev_enter(bochs->dev, &idx))
		return;

	bochs->xres = mode->hdisplay;
	bochs->yres = mode->vdisplay;
	bochs->bpp = 32;
	bochs->stride = mode->hdisplay * (bochs->bpp / 8);
	bochs->yres_virtual = bochs->fb_size / bochs->stride;

	DRM_DEBUG_DRIVER("%dx%d @ %d bpp, vy %d\n",
			 bochs->xres, bochs->yres, bochs->bpp,
			 bochs->yres_virtual);

	bochs_hw_blank(bochs, false);

	bochs_dispi_write(bochs, VBE_DISPI_INDEX_ENABLE,      0);
	bochs_dispi_write(bochs, VBE_DISPI_INDEX_BPP,         bochs->bpp);
	bochs_dispi_write(bochs, VBE_DISPI_INDEX_XRES,        bochs->xres);
	bochs_dispi_write(bochs, VBE_DISPI_INDEX_YRES,        bochs->yres);
	bochs_dispi_write(bochs, VBE_DISPI_INDEX_BANK,        0);
	bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_WIDTH,  bochs->xres);
	bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_HEIGHT,
			  bochs->yres_virtual);
	bochs_dispi_write(bochs, VBE_DISPI_INDEX_X_OFFSET,    0);
	bochs_dispi_write(bochs, VBE_DISPI_INDEX_Y_OFFSET,    0);

	bochs_dispi_write(bochs, VBE_DISPI_INDEX_ENABLE,
			  VBE_DISPI_ENABLED | VBE_DISPI_LFB_ENABLED);

	drm_dev_exit(idx);
}

static void bochs_hw_setformat(struct bochs_device *bochs, const struct drm_format_info *format)
{
	int idx;

	if (!drm_dev_enter(bochs->dev, &idx))
		return;

	DRM_DEBUG_DRIVER("format %c%c%c%c\n",
			 (format->format >>  0) & 0xff,
			 (format->format >>  8) & 0xff,
			 (format->format >> 16) & 0xff,
			 (format->format >> 24) & 0xff);

	switch (format->format) {
	case DRM_FORMAT_XRGB8888:
		bochs_hw_set_little_endian(bochs);
		break;
	case DRM_FORMAT_BGRX8888:
		bochs_hw_set_big_endian(bochs);
		break;
	default:
		/* should not happen */
		DRM_ERROR("%s: Huh? Got framebuffer format 0x%x",
			  __func__, format->format);
		break;
	}

	drm_dev_exit(idx);
}

static void bochs_hw_setbase(struct bochs_device *bochs, int x, int y, int stride, u64 addr)
{
	unsigned long offset;
	unsigned int vx, vy, vwidth, idx;

	if (!drm_dev_enter(bochs->dev, &idx))
		return;

	bochs->stride = stride;
	offset = (unsigned long)addr +
		y * bochs->stride +
		x * (bochs->bpp / 8);
	vy = offset / bochs->stride;
	vx = (offset % bochs->stride) * 8 / bochs->bpp;
	vwidth = stride * 8 / bochs->bpp;

	DRM_DEBUG_DRIVER("x %d, y %d, addr %llx -> offset %lx, vx %d, vy %d\n",
			 x, y, addr, offset, vx, vy);
	bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_WIDTH, vwidth);
	bochs_dispi_write(bochs, VBE_DISPI_INDEX_X_OFFSET, vx);
	bochs_dispi_write(bochs, VBE_DISPI_INDEX_Y_OFFSET, vy);

	drm_dev_exit(idx);
}

/* ---------------------------------------------------------------------- */

static const uint32_t bochs_formats[] = {
	DRM_FORMAT_XRGB8888,
	DRM_FORMAT_BGRX8888,
};

static void bochs_plane_update(struct bochs_device *bochs, struct drm_plane_state *state)
{
	struct drm_gem_vram_object *gbo;
	s64 gpu_addr;

	if (!state->fb || !bochs->stride)
		return;

	gbo = drm_gem_vram_of_gem(state->fb->obj[0]);
	gpu_addr = drm_gem_vram_offset(gbo);
	if (WARN_ON_ONCE(gpu_addr < 0))
		return; /* Bug: we didn't pin the BO to VRAM in prepare_fb. */

	bochs_hw_setbase(bochs,
			 state->crtc_x,
			 state->crtc_y,
			 state->fb->pitches[0],
			 state->fb->offsets[0] + gpu_addr);
	bochs_hw_setformat(bochs, state->fb->format);
}

static void bochs_pipe_enable(struct drm_simple_display_pipe *pipe,
			      struct drm_crtc_state *crtc_state,
			      struct drm_plane_state *plane_state)
{
	struct bochs_device *bochs = pipe->crtc.dev->dev_private;

	bochs_hw_setmode(bochs, &crtc_state->mode);
	bochs_plane_update(bochs, plane_state);
}

static void bochs_pipe_disable(struct drm_simple_display_pipe *pipe)
{
	struct bochs_device *bochs = pipe->crtc.dev->dev_private;

	bochs_hw_blank(bochs, true);
}

static void bochs_pipe_update(struct drm_simple_display_pipe *pipe,
			      struct drm_plane_state *old_state)
{
	struct bochs_device *bochs = pipe->crtc.dev->dev_private;

	bochs_plane_update(bochs, pipe->plane.state);
}

static const struct drm_simple_display_pipe_funcs bochs_pipe_funcs = {
	.enable	    = bochs_pipe_enable,
	.disable    = bochs_pipe_disable,
	.update	    = bochs_pipe_update,
	.prepare_fb = drm_gem_vram_simple_display_pipe_prepare_fb,
	.cleanup_fb = drm_gem_vram_simple_display_pipe_cleanup_fb,
};

static int bochs_connector_get_modes(struct drm_connector *connector)
{
	struct bochs_device *bochs =
		container_of(connector, struct bochs_device, connector);
	int count = 0;

	if (bochs->edid)
		count = drm_add_edid_modes(connector, bochs->edid);

	if (!count) {
		count = drm_add_modes_noedid(connector, 8192, 8192);
		drm_set_preferred_mode(connector, defx, defy);
	}
	return count;
}

static const struct drm_connector_helper_funcs bochs_connector_connector_helper_funcs = {
	.get_modes = bochs_connector_get_modes,
};

static const struct drm_connector_funcs bochs_connector_connector_funcs = {
	.fill_modes = drm_helper_probe_single_connector_modes,
	.destroy = drm_connector_cleanup,
	.reset = drm_atomic_helper_connector_reset,
	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
};

static void bochs_connector_init(struct drm_device *dev)
{
	struct bochs_device *bochs = dev->dev_private;
	struct drm_connector *connector = &bochs->connector;

	drm_connector_init(dev, connector, &bochs_connector_connector_funcs,
			   DRM_MODE_CONNECTOR_VIRTUAL);
	drm_connector_helper_add(connector, &bochs_connector_connector_helper_funcs);

	bochs_hw_load_edid(bochs);
	if (bochs->edid) {
		DRM_INFO("Found EDID data blob.\n");
		drm_connector_attach_edid_property(connector);
		drm_connector_update_edid_property(connector, bochs->edid);
	}
}

static struct drm_framebuffer *
bochs_gem_fb_create(struct drm_device *dev, struct drm_file *file,
		    const struct drm_mode_fb_cmd2 *mode_cmd)
{
	if (mode_cmd->pixel_format != DRM_FORMAT_XRGB8888 &&
	    mode_cmd->pixel_format != DRM_FORMAT_BGRX8888)
		return ERR_PTR(-EINVAL);

	return drm_gem_fb_create(dev, file, mode_cmd);
}

static const struct drm_mode_config_funcs bochs_mode_funcs = {
	.fb_create = bochs_gem_fb_create,
	.mode_valid = drm_vram_helper_mode_valid,
	.atomic_check = drm_atomic_helper_check,
	.atomic_commit = drm_atomic_helper_commit,
};

static int bochs_kms_init(struct bochs_device *bochs)
{
	int ret;

	ret = drmm_mode_config_init(bochs->dev);
	if (ret)
		return ret;

	bochs->dev->mode_config.max_width = 8192;
	bochs->dev->mode_config.max_height = 8192;

	bochs->dev->mode_config.fb_base = bochs->fb_base;
	bochs->dev->mode_config.preferred_depth = 24;
	bochs->dev->mode_config.prefer_shadow = 0;
	bochs->dev->mode_config.prefer_shadow_fbdev = 1;
	bochs->dev->mode_config.quirk_addfb_prefer_host_byte_order = true;

	bochs->dev->mode_config.funcs = &bochs_mode_funcs;

	bochs_connector_init(bochs->dev);
	drm_simple_display_pipe_init(bochs->dev,
				     &bochs->pipe,
				     &bochs_pipe_funcs,
				     bochs_formats,
				     ARRAY_SIZE(bochs_formats),
				     NULL,
				     &bochs->connector);

	drm_mode_config_reset(bochs->dev);

	return 0;
}

/* ---------------------------------------------------------------------- */
/* drm interface                                                          */

static int bochs_load(struct drm_device *dev)
{
	struct bochs_device *bochs;
	int ret;

	bochs = drmm_kzalloc(dev, sizeof(*bochs), GFP_KERNEL);
	if (bochs == NULL)
		return -ENOMEM;
	dev->dev_private = bochs;
	bochs->dev = dev;

	ret = bochs_hw_init(dev);
	if (ret)
		return ret;

	ret = drmm_vram_helper_init(dev, bochs->fb_base, bochs->fb_size);
	if (ret)
		goto err_hw_fini;

	ret = bochs_kms_init(bochs);
	if (ret)
		goto err_hw_fini;

	return 0;

err_hw_fini:
	bochs_hw_fini(dev);
	return ret;
}

DEFINE_DRM_GEM_FOPS(bochs_fops);

static const struct drm_driver bochs_driver = {
	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
	.fops			= &bochs_fops,
	.name			= "bochs-drm",
	.desc			= "bochs dispi vga interface (qemu stdvga)",
	.date			= "20130925",
	.major			= 1,
	.minor			= 0,
	DRM_GEM_VRAM_DRIVER,
};

/* ---------------------------------------------------------------------- */
/* pm interface                                                           */

#ifdef CONFIG_PM_SLEEP
static int bochs_pm_suspend(struct device *dev)
{
	struct drm_device *drm_dev = dev_get_drvdata(dev);

	return drm_mode_config_helper_suspend(drm_dev);
}

static int bochs_pm_resume(struct device *dev)
{
	struct drm_device *drm_dev = dev_get_drvdata(dev);

	return drm_mode_config_helper_resume(drm_dev);
}
#endif

static const struct dev_pm_ops bochs_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(bochs_pm_suspend,
				bochs_pm_resume)
};

/* ---------------------------------------------------------------------- */
/* pci interface                                                          */

static int bochs_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	struct drm_device *dev;
	unsigned long fbsize;
	int ret;

	fbsize = pci_resource_len(pdev, 0);
	if (fbsize < 4 * 1024 * 1024) {
		DRM_ERROR("less than 4 MB video memory, ignoring device\n");
		return -ENOMEM;
	}

	ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &bochs_driver);
	if (ret)
		return ret;

	dev = drm_dev_alloc(&bochs_driver, &pdev->dev);
	if (IS_ERR(dev))
		return PTR_ERR(dev);

	ret = pcim_enable_device(pdev);
	if (ret)
		goto err_free_dev;

	pci_set_drvdata(pdev, dev);

	ret = bochs_load(dev);
	if (ret)
		goto err_free_dev;

	ret = drm_dev_register(dev, 0);
	if (ret)
		goto err_hw_fini;

	drm_fbdev_generic_setup(dev, 32);
	return ret;

err_hw_fini:
	bochs_hw_fini(dev);
err_free_dev:
	drm_dev_put(dev);
	return ret;
}

static void bochs_pci_remove(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);

	drm_dev_unplug(dev);
	drm_atomic_helper_shutdown(dev);
	bochs_hw_fini(dev);
	drm_dev_put(dev);
}

static const struct pci_device_id bochs_pci_tbl[] = {
	{
		.vendor      = 0x1234,
		.device      = 0x1111,
		.subvendor   = PCI_SUBVENDOR_ID_REDHAT_QUMRANET,
		.subdevice   = PCI_SUBDEVICE_ID_QEMU,
		.driver_data = BOCHS_QEMU_STDVGA,
	},
	{
		.vendor      = 0x1234,
		.device      = 0x1111,
		.subvendor   = PCI_ANY_ID,
		.subdevice   = PCI_ANY_ID,
		.driver_data = BOCHS_UNKNOWN,
	},
	{
		.vendor      = 0x4321,
		.device      = 0x1111,
		.subvendor   = PCI_ANY_ID,
		.subdevice   = PCI_ANY_ID,
		.driver_data = BOCHS_SIMICS,
	},
	{ /* end of list */ }
};

static struct pci_driver bochs_pci_driver = {
	.name =		"bochs-drm",
	.id_table =	bochs_pci_tbl,
	.probe =	bochs_pci_probe,
	.remove =	bochs_pci_remove,
	.driver.pm =    &bochs_pm_ops,
};

/* ---------------------------------------------------------------------- */
/* module init/exit                                                       */

drm_module_pci_driver_if_modeset(bochs_pci_driver, bochs_modeset);

MODULE_DEVICE_TABLE(pci, bochs_pci_tbl);
MODULE_AUTHOR("Gerd Hoffmann <kraxel@redhat.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
796c3e35 TZ	1	// SPDX-License-Identifier: GPL-2.0-or-later
796c3e35 TZ	2
430ac054	3	#include <linux/module.h>
796c3e35 TZ	4	#include <linux/pci.h>
	5
	6	#include <drm/drm_aperture.h>
	7	#include <drm/drm_atomic_helper.h>
	8	#include <drm/drm_drv.h>
255490f9	9	#include <drm/drm_edid.h>
796c3e35 TZ	10	#include <drm/drm_fb_helper.h>
796c3e35 TZ	11	#include <drm/drm_fourcc.h>
720cf96d	12	#include <drm/drm_framebuffer.h>
796c3e35 TZ	13	#include <drm/drm_gem_framebuffer_helper.h>
	14	#include <drm/drm_gem_vram_helper.h>
	15	#include <drm/drm_managed.h>
54e67e5a	16	#include <drm/drm_module.h>
796c3e35 TZ	17	#include <drm/drm_probe_helper.h>
	18	#include <drm/drm_simple_kms_helper.h>
	19
	20	#include <video/vga.h>
	21
	22	/* ---------------------------------------------------------------------- */
	23
	24	#define VBE_DISPI_IOPORT_INDEX 0x01CE
	25	#define VBE_DISPI_IOPORT_DATA 0x01CF
	26
	27	#define VBE_DISPI_INDEX_ID 0x0
	28	#define VBE_DISPI_INDEX_XRES 0x1
	29	#define VBE_DISPI_INDEX_YRES 0x2
	30	#define VBE_DISPI_INDEX_BPP 0x3
	31	#define VBE_DISPI_INDEX_ENABLE 0x4
	32	#define VBE_DISPI_INDEX_BANK 0x5
	33	#define VBE_DISPI_INDEX_VIRT_WIDTH 0x6
	34	#define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7
	35	#define VBE_DISPI_INDEX_X_OFFSET 0x8
	36	#define VBE_DISPI_INDEX_Y_OFFSET 0x9
	37	#define VBE_DISPI_INDEX_VIDEO_MEMORY_64K 0xa
	38
	39	#define VBE_DISPI_ID0 0xB0C0
	40	#define VBE_DISPI_ID1 0xB0C1
	41	#define VBE_DISPI_ID2 0xB0C2
	42	#define VBE_DISPI_ID3 0xB0C3
	43	#define VBE_DISPI_ID4 0xB0C4
	44	#define VBE_DISPI_ID5 0xB0C5
	45
	46	#define VBE_DISPI_DISABLED 0x00
	47	#define VBE_DISPI_ENABLED 0x01
	48	#define VBE_DISPI_GETCAPS 0x02
	49	#define VBE_DISPI_8BIT_DAC 0x20
	50	#define VBE_DISPI_LFB_ENABLED 0x40
	51	#define VBE_DISPI_NOCLEARMEM 0x80
	52
	53	static int bochs_modeset = -1;
	54	static int defx = 1024;
	55	static int defy = 768;
	56
	57	module_param_named(modeset, bochs_modeset, int, 0444);
	58	MODULE_PARM_DESC(modeset, "enable/disable kernel modesetting");
	59
	60	module_param(defx, int, 0444);
	61	module_param(defy, int, 0444);
	62	MODULE_PARM_DESC(defx, "default x resolution");
	63	MODULE_PARM_DESC(defy, "default y resolution");
	64
	65	/* ---------------------------------------------------------------------- */
	66
	67	enum bochs_types {
	68	BOCHS_QEMU_STDVGA,
78afff2a	69	BOCHS_SIMICS,
796c3e35 TZ	70	BOCHS_UNKNOWN,
	71	};
	72
	73	struct bochs_device {
	74	/* hw */
	75	void __iomem *mmio;
	76	int ioports;
	77	void __iomem *fb_map;
	78	unsigned long fb_base;
	79	unsigned long fb_size;
	80	unsigned long qext_size;
	81
	82	/* mode */
	83	u16 xres;
	84	u16 yres;
	85	u16 yres_virtual;
	86	u32 stride;
	87	u32 bpp;
	88	struct edid *edid;
	89
	90	/* drm */
	91	struct drm_device *dev;
	92	struct drm_simple_display_pipe pipe;
	93	struct drm_connector connector;
	94	};
	95
	96	/* ---------------------------------------------------------------------- */
	97
	98	static void bochs_vga_writeb(struct bochs_device *bochs, u16 ioport, u8 val)
	99	{
	100	if (WARN_ON(ioport < 0x3c0 \|\| ioport > 0x3df))
	101	return;
	102
	103	if (bochs->mmio) {
	104	int offset = ioport - 0x3c0 + 0x400;
	105
	106	writeb(val, bochs->mmio + offset);
	107	} else {
	108	outb(val, ioport);
	109	}
	110	}
	111
	112	static u8 bochs_vga_readb(struct bochs_device *bochs, u16 ioport)
	113	{
	114	if (WARN_ON(ioport < 0x3c0 \|\| ioport > 0x3df))
	115	return 0xff;
	116
	117	if (bochs->mmio) {
	118	int offset = ioport - 0x3c0 + 0x400;
	119
	120	return readb(bochs->mmio + offset);
	121	} else {
	122	return inb(ioport);
	123	}
	124	}
	125
	126	static u16 bochs_dispi_read(struct bochs_device *bochs, u16 reg)
	127	{
	128	u16 ret = 0;
	129
	130	if (bochs->mmio) {
	131	int offset = 0x500 + (reg << 1);
	132
	133	ret = readw(bochs->mmio + offset);
134	} else {
135	outw(reg, VBE_DISPI_IOPORT_INDEX);
136	ret = inw(VBE_DISPI_IOPORT_DATA);
137	}
138	return ret;
139	}
140
141	static void bochs_dispi_write(struct bochs_device *bochs, u16 reg, u16 val)
142	{
143	if (bochs->mmio) {
144	int offset = 0x500 + (reg << 1);
145
146	writew(val, bochs->mmio + offset);
147	} else {
148	outw(reg, VBE_DISPI_IOPORT_INDEX);
149	outw(val, VBE_DISPI_IOPORT_DATA);
150	}
151	}
152
153	static void bochs_hw_set_big_endian(struct bochs_device *bochs)
154	{
155	if (bochs->qext_size < 8)
156	return;
157
158	writel(0xbebebebe, bochs->mmio + 0x604);
159	}
160
161	static void bochs_hw_set_little_endian(struct bochs_device *bochs)
162	{
163	if (bochs->qext_size < 8)
164	return;
165
166	writel(0x1e1e1e1e, bochs->mmio + 0x604);
167	}
168
169	#ifdef __BIG_ENDIAN
170	#define bochs_hw_set_native_endian(_b) bochs_hw_set_big_endian(_b)
171	#else
172	#define bochs_hw_set_native_endian(_b) bochs_hw_set_little_endian(_b)
173	#endif
174
175	static int bochs_get_edid_block(void data, u8 buf,
176	unsigned int block, size_t len)
177	{
178	struct bochs_device *bochs = data;
179	size_t i, start = block * EDID_LENGTH;
180
181	if (start + len > 0x400 /* vga register offset */)
182	return -1;
183
184	for (i = 0; i < len; i++)
185	buf[i] = readb(bochs->mmio + start + i);
186
187	return 0;
188	}
189
190	static int bochs_hw_load_edid(struct bochs_device *bochs)
191	{
192	u8 header[8];
193
194	if (!bochs->mmio)
195	return -1;
196
197	/* check header to detect whenever edid support is enabled in qemu */
198	bochs_get_edid_block(bochs, header, 0, ARRAY_SIZE(header));
199	if (drm_edid_header_is_valid(header) != 8)
200	return -1;
201
202	kfree(bochs->edid);
203	bochs->edid = drm_do_get_edid(&bochs->connector,
204	bochs_get_edid_block, bochs);
205	if (bochs->edid == NULL)
206	return -1;
207
208	return 0;
209	}
210
211	static int bochs_hw_init(struct drm_device *dev)
212	{
213	struct bochs_device *bochs = dev->dev_private;
214	struct pci_dev *pdev = to_pci_dev(dev->dev);
215	unsigned long addr, size, mem, ioaddr, iosize;
216	u16 id;
217
218	if (pdev->resource[2].flags & IORESOURCE_MEM) {
219	/* mmio bar with vga and bochs registers present */
220	if (pci_request_region(pdev, 2, "bochs-drm") != 0) {
221	DRM_ERROR("Cannot request mmio region\n");
222	return -EBUSY;
223	}
224	ioaddr = pci_resource_start(pdev, 2);
225	iosize = pci_resource_len(pdev, 2);
226	bochs->mmio = ioremap(ioaddr, iosize);
227	if (bochs->mmio == NULL) {
228	DRM_ERROR("Cannot map mmio region\n");
229	return -ENOMEM;
230	}
231	} else {
232	ioaddr = VBE_DISPI_IOPORT_INDEX;
233	iosize = 2;
234	if (!request_region(ioaddr, iosize, "bochs-drm")) {
235	DRM_ERROR("Cannot request ioports\n");
236	return -EBUSY;
237	}
238	bochs->ioports = 1;
239	}
240
241	id = bochs_dispi_read(bochs, VBE_DISPI_INDEX_ID);
242	mem = bochs_dispi_read(bochs, VBE_DISPI_INDEX_VIDEO_MEMORY_64K)
243	* 64 * 1024;
244	if ((id & 0xfff0) != VBE_DISPI_ID0) {
245	DRM_ERROR("ID mismatch\n");
246	return -ENODEV;
247	}
248
249	if ((pdev->resource[0].flags & IORESOURCE_MEM) == 0)
250	return -ENODEV;
251	addr = pci_resource_start(pdev, 0);
252	size = pci_resource_len(pdev, 0);
253	if (addr == 0)
254	return -ENODEV;
255	if (size != mem) {
256	DRM_ERROR("Size mismatch: pci=%ld, bochs=%ld\n",
257	size, mem);
258	size = min(size, mem);
259	}
260
261	if (pci_request_region(pdev, 0, "bochs-drm") != 0)
262	DRM_WARN("Cannot request framebuffer, boot fb still active?\n");
263
264	bochs->fb_map = ioremap(addr, size);
265	if (bochs->fb_map == NULL) {
266	DRM_ERROR("Cannot map framebuffer\n");
267	return -ENOMEM;
268	}
269	bochs->fb_base = addr;
270	bochs->fb_size = size;
271
272	DRM_INFO("Found bochs VGA, ID 0x%x.\n", id);
273	DRM_INFO("Framebuffer size %ld kB @ 0x%lx, %s @ 0x%lx.\n",
274	size / 1024, addr,
275	bochs->ioports ? "ioports" : "mmio",
276	ioaddr);
277
278	if (bochs->mmio && pdev->revision >= 2) {
279	bochs->qext_size = readl(bochs->mmio + 0x600);
280	if (bochs->qext_size < 4 \|\| bochs->qext_size > iosize) {
281	bochs->qext_size = 0;
282	goto noext;
283	}
284	DRM_DEBUG("Found qemu ext regs, size %ld\n",
285	bochs->qext_size);
286	bochs_hw_set_native_endian(bochs);
287	}
288
289	noext:
290	return 0;
291	}
292
293	static void bochs_hw_fini(struct drm_device *dev)
294	{
295	struct bochs_device *bochs = dev->dev_private;
296
297	/* TODO: shot down existing vram mappings */
298
299	if (bochs->mmio)
300	iounmap(bochs->mmio);
301	if (bochs->ioports)
302	release_region(VBE_DISPI_IOPORT_INDEX, 2);
303	if (bochs->fb_map)
304	iounmap(bochs->fb_map);
305	pci_release_regions(to_pci_dev(dev->dev));
306	kfree(bochs->edid);
307	}
308
309	static void bochs_hw_blank(struct bochs_device *bochs, bool blank)
310	{
311	DRM_DEBUG_DRIVER("hw_blank %d\n", blank);
e740ceb5 GH	312	/* enable color bit (so VGA_IS1_RC access works) */
e740ceb5 GH	313	bochs_vga_writeb(bochs, VGA_MIS_W, VGA_MIS_COLOR);
796c3e35 TZ	314	/* discard ar_flip_flop */
	315	(void)bochs_vga_readb(bochs, VGA_IS1_RC);
	316	/* blank or unblank; we need only update index and set 0x20 */
	317	bochs_vga_writeb(bochs, VGA_ATT_W, blank ? 0 : 0x20);
	318	}
	319
	320	static void bochs_hw_setmode(struct bochs_device bochs, struct drm_display_mode mode)
	321	{
	322	int idx;
	323
	324	if (!drm_dev_enter(bochs->dev, &idx))
	325	return;
	326
	327	bochs->xres = mode->hdisplay;
	328	bochs->yres = mode->vdisplay;
	329	bochs->bpp = 32;
	330	bochs->stride = mode->hdisplay * (bochs->bpp / 8);
	331	bochs->yres_virtual = bochs->fb_size / bochs->stride;
	332
	333	DRM_DEBUG_DRIVER("%dx%d @ %d bpp, vy %d\n",
	334	bochs->xres, bochs->yres, bochs->bpp,
	335	bochs->yres_virtual);
	336
	337	bochs_hw_blank(bochs, false);
	338
	339	bochs_dispi_write(bochs, VBE_DISPI_INDEX_ENABLE, 0);
	340	bochs_dispi_write(bochs, VBE_DISPI_INDEX_BPP, bochs->bpp);
	341	bochs_dispi_write(bochs, VBE_DISPI_INDEX_XRES, bochs->xres);
	342	bochs_dispi_write(bochs, VBE_DISPI_INDEX_YRES, bochs->yres);
	343	bochs_dispi_write(bochs, VBE_DISPI_INDEX_BANK, 0);
	344	bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_WIDTH, bochs->xres);
	345	bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_HEIGHT,
	346	bochs->yres_virtual);
	347	bochs_dispi_write(bochs, VBE_DISPI_INDEX_X_OFFSET, 0);
	348	bochs_dispi_write(bochs, VBE_DISPI_INDEX_Y_OFFSET, 0);
	349
	350	bochs_dispi_write(bochs, VBE_DISPI_INDEX_ENABLE,
	351	VBE_DISPI_ENABLED \| VBE_DISPI_LFB_ENABLED);
	352
	353	drm_dev_exit(idx);
	354	}
	355
	356	static void bochs_hw_setformat(struct bochs_device bochs, const struct drm_format_info format)
	357	{
	358	int idx;
	359
	360	if (!drm_dev_enter(bochs->dev, &idx))
	361	return;
	362
	363	DRM_DEBUG_DRIVER("format %c%c%c%c\n",
	364	(format->format >> 0) & 0xff,
	365	(format->format >> 8) & 0xff,
	366	(format->format >> 16) & 0xff,
	367	(format->format >> 24) & 0xff);
	368
	369	switch (format->format) {
	370	case DRM_FORMAT_XRGB8888:
	371	bochs_hw_set_little_endian(bochs);
	372	break;
	373	case DRM_FORMAT_BGRX8888:
	374	bochs_hw_set_big_endian(bochs);
	375	break;
	376	default:
	377	/* should not happen */
378	DRM_ERROR("%s: Huh? Got framebuffer format 0x%x",
379	__func__, format->format);
380	break;
381	}
382
383	drm_dev_exit(idx);
384	}
385
386	static void bochs_hw_setbase(struct bochs_device *bochs, int x, int y, int stride, u64 addr)
387	{
388	unsigned long offset;
389	unsigned int vx, vy, vwidth, idx;
390
391	if (!drm_dev_enter(bochs->dev, &idx))
392	return;
393
394	bochs->stride = stride;
395	offset = (unsigned long)addr +
396	y * bochs->stride +
397	x * (bochs->bpp / 8);
398	vy = offset / bochs->stride;
399	vx = (offset % bochs->stride) * 8 / bochs->bpp;
400	vwidth = stride * 8 / bochs->bpp;
401
402	DRM_DEBUG_DRIVER("x %d, y %d, addr %llx -> offset %lx, vx %d, vy %d\n",
403	x, y, addr, offset, vx, vy);
404	bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_WIDTH, vwidth);
405	bochs_dispi_write(bochs, VBE_DISPI_INDEX_X_OFFSET, vx);
406	bochs_dispi_write(bochs, VBE_DISPI_INDEX_Y_OFFSET, vy);
407
408	drm_dev_exit(idx);
409	}
410
411	/* ---------------------------------------------------------------------- */
412
796c3e35 TZ	413	static const uint32_t bochs_formats[] = {
	414	DRM_FORMAT_XRGB8888,
	415	DRM_FORMAT_BGRX8888,
	416	};
	417
	418	static void bochs_plane_update(struct bochs_device bochs, struct drm_plane_state state)
	419	{
	420	struct drm_gem_vram_object *gbo;
	421	s64 gpu_addr;
	422
	423	if (!state->fb \|\| !bochs->stride)
	424	return;
	425
	426	gbo = drm_gem_vram_of_gem(state->fb->obj[0]);
	427	gpu_addr = drm_gem_vram_offset(gbo);
	428	if (WARN_ON_ONCE(gpu_addr < 0))
	429	return; /* Bug: we didn't pin the BO to VRAM in prepare_fb. */
	430
	431	bochs_hw_setbase(bochs,
	432	state->crtc_x,
	433	state->crtc_y,
	434	state->fb->pitches[0],
	435	state->fb->offsets[0] + gpu_addr);
	436	bochs_hw_setformat(bochs, state->fb->format);
	437	}
	438
	439	static void bochs_pipe_enable(struct drm_simple_display_pipe *pipe,
	440	struct drm_crtc_state *crtc_state,
	441	struct drm_plane_state *plane_state)
	442	{
	443	struct bochs_device *bochs = pipe->crtc.dev->dev_private;
	444
	445	bochs_hw_setmode(bochs, &crtc_state->mode);
	446	bochs_plane_update(bochs, plane_state);
	447	}
	448
	449	static void bochs_pipe_disable(struct drm_simple_display_pipe *pipe)
	450	{
	451	struct bochs_device *bochs = pipe->crtc.dev->dev_private;
	452
	453	bochs_hw_blank(bochs, true);
	454	}
	455
	456	static void bochs_pipe_update(struct drm_simple_display_pipe *pipe,
	457	struct drm_plane_state *old_state)
	458	{
	459	struct bochs_device *bochs = pipe->crtc.dev->dev_private;
	460
	461	bochs_plane_update(bochs, pipe->plane.state);
	462	}
	463
	464	static const struct drm_simple_display_pipe_funcs bochs_pipe_funcs = {
	465	.enable = bochs_pipe_enable,
	466	.disable = bochs_pipe_disable,
	467	.update = bochs_pipe_update,
	468	.prepare_fb = drm_gem_vram_simple_display_pipe_prepare_fb,
	469	.cleanup_fb = drm_gem_vram_simple_display_pipe_cleanup_fb,
	470	};
	471
	472	static int bochs_connector_get_modes(struct drm_connector *connector)
	473	{
	474	struct bochs_device *bochs =
	475	container_of(connector, struct bochs_device, connector);
	476	int count = 0;
477
478	if (bochs->edid)
479	count = drm_add_edid_modes(connector, bochs->edid);
480
481	if (!count) {
482	count = drm_add_modes_noedid(connector, 8192, 8192);
483	drm_set_preferred_mode(connector, defx, defy);
484	}
485	return count;
486	}
487
488	static const struct drm_connector_helper_funcs bochs_connector_connector_helper_funcs = {
489	.get_modes = bochs_connector_get_modes,
490	};
491
492	static const struct drm_connector_funcs bochs_connector_connector_funcs = {
493	.fill_modes = drm_helper_probe_single_connector_modes,
494	.destroy = drm_connector_cleanup,
495	.reset = drm_atomic_helper_connector_reset,
496	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
497	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
498	};
499
500	static void bochs_connector_init(struct drm_device *dev)
501	{
502	struct bochs_device *bochs = dev->dev_private;
503	struct drm_connector *connector = &bochs->connector;
504
505	drm_connector_init(dev, connector, &bochs_connector_connector_funcs,
506	DRM_MODE_CONNECTOR_VIRTUAL);
507	drm_connector_helper_add(connector, &bochs_connector_connector_helper_funcs);
508
509	bochs_hw_load_edid(bochs);
510	if (bochs->edid) {
511	DRM_INFO("Found EDID data blob.\n");
512	drm_connector_attach_edid_property(connector);
513	drm_connector_update_edid_property(connector, bochs->edid);
514	}
515	}
516
517	static struct drm_framebuffer *
518	bochs_gem_fb_create(struct drm_device dev, struct drm_file file,
519	const struct drm_mode_fb_cmd2 *mode_cmd)
520	{
521	if (mode_cmd->pixel_format != DRM_FORMAT_XRGB8888 &&
522	mode_cmd->pixel_format != DRM_FORMAT_BGRX8888)
523	return ERR_PTR(-EINVAL);
524
525	return drm_gem_fb_create(dev, file, mode_cmd);
526	}
527
528	static const struct drm_mode_config_funcs bochs_mode_funcs = {
529	.fb_create = bochs_gem_fb_create,
530	.mode_valid = drm_vram_helper_mode_valid,
531	.atomic_check = drm_atomic_helper_check,
532	.atomic_commit = drm_atomic_helper_commit,
533	};
534
535	static int bochs_kms_init(struct bochs_device *bochs)
536	{
537	int ret;
538
539	ret = drmm_mode_config_init(bochs->dev);
540	if (ret)
541	return ret;
542
543	bochs->dev->mode_config.max_width = 8192;
544	bochs->dev->mode_config.max_height = 8192;
545
546	bochs->dev->mode_config.fb_base = bochs->fb_base;
547	bochs->dev->mode_config.preferred_depth = 24;
548	bochs->dev->mode_config.prefer_shadow = 0;
549	bochs->dev->mode_config.prefer_shadow_fbdev = 1;
550	bochs->dev->mode_config.quirk_addfb_prefer_host_byte_order = true;
551
552	bochs->dev->mode_config.funcs = &bochs_mode_funcs;
553
554	bochs_connector_init(bochs->dev);
555	drm_simple_display_pipe_init(bochs->dev,
556	&bochs->pipe,
557	&bochs_pipe_funcs,
558	bochs_formats,
559	ARRAY_SIZE(bochs_formats),
560	NULL,
561	&bochs->connector);
562
563	drm_mode_config_reset(bochs->dev);
564
565	return 0;
566	}
567
568	/* ---------------------------------------------------------------------- */
569	/* drm interface */
570
796c3e35 TZ	571	static int bochs_load(struct drm_device *dev)
	572	{
	573	struct bochs_device *bochs;
	574	int ret;
	575
	576	bochs = drmm_kzalloc(dev, sizeof(*bochs), GFP_KERNEL);
	577	if (bochs == NULL)
	578	return -ENOMEM;
	579	dev->dev_private = bochs;
	580	bochs->dev = dev;
	581
	582	ret = bochs_hw_init(dev);
	583	if (ret)
11e96701	584	return ret;
796c3e35	585
11e96701	586	ret = drmm_vram_helper_init(dev, bochs->fb_base, bochs->fb_size);
796c3e35	587	if (ret)
8f48dbd6	588	goto err_hw_fini;
796c3e35 TZ	589
	590	ret = bochs_kms_init(bochs);
	591	if (ret)
8f48dbd6	592	goto err_hw_fini;
796c3e35 TZ	593
796c3e35 TZ	594	return 0;
8f48dbd6 CJ	595
	596	err_hw_fini:
	597	bochs_hw_fini(dev);
	598	return ret;
796c3e35 TZ	599	}
	600
	601	DEFINE_DRM_GEM_FOPS(bochs_fops);
	602
	603	static const struct drm_driver bochs_driver = {
	604	.driver_features = DRIVER_GEM \| DRIVER_MODESET \| DRIVER_ATOMIC,
	605	.fops = &bochs_fops,
	606	.name = "bochs-drm",
	607	.desc = "bochs dispi vga interface (qemu stdvga)",
	608	.date = "20130925",
	609	.major = 1,
	610	.minor = 0,
	611	DRM_GEM_VRAM_DRIVER,
796c3e35 TZ	612	};
	613
	614	/* ---------------------------------------------------------------------- */
	615	/* pm interface */
	616
	617	#ifdef CONFIG_PM_SLEEP
	618	static int bochs_pm_suspend(struct device *dev)
	619	{
	620	struct drm_device *drm_dev = dev_get_drvdata(dev);
	621
	622	return drm_mode_config_helper_suspend(drm_dev);
	623	}
	624
	625	static int bochs_pm_resume(struct device *dev)
	626	{
	627	struct drm_device *drm_dev = dev_get_drvdata(dev);
	628
	629	return drm_mode_config_helper_resume(drm_dev);
	630	}
	631	#endif
	632
	633	static const struct dev_pm_ops bochs_pm_ops = {
	634	SET_SYSTEM_SLEEP_PM_OPS(bochs_pm_suspend,
	635	bochs_pm_resume)
	636	};
	637
	638	/* ---------------------------------------------------------------------- */
	639	/* pci interface */
	640
	641	static int bochs_pci_probe(struct pci_dev pdev, const struct pci_device_id ent)
	642	{
	643	struct drm_device *dev;
	644	unsigned long fbsize;
	645	int ret;
	646
	647	fbsize = pci_resource_len(pdev, 0);
	648	if (fbsize < 4 * 1024 * 1024) {
	649	DRM_ERROR("less than 4 MB video memory, ignoring device\n");
	650	return -ENOMEM;
	651	}
	652
	653	ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &bochs_driver);
	654	if (ret)
	655	return ret;
	656
	657	dev = drm_dev_alloc(&bochs_driver, &pdev->dev);
	658	if (IS_ERR(dev))
	659	return PTR_ERR(dev);
	660
b46998d8	661	ret = pcim_enable_device(pdev);
796c3e35 TZ	662	if (ret)
	663	goto err_free_dev;
	664
	665	pci_set_drvdata(pdev, dev);
	666
	667	ret = bochs_load(dev);
	668	if (ret)
	669	goto err_free_dev;
	670
	671	ret = drm_dev_register(dev, 0);
	672	if (ret)
8f48dbd6	673	goto err_hw_fini;
796c3e35 TZ	674
	675	drm_fbdev_generic_setup(dev, 32);
	676	return ret;
	677
8f48dbd6 CJ	678	err_hw_fini:
8f48dbd6 CJ	679	bochs_hw_fini(dev);
796c3e35 TZ	680	err_free_dev:
	681	drm_dev_put(dev);
	682	return ret;
	683	}
	684
	685	static void bochs_pci_remove(struct pci_dev *pdev)
	686	{
	687	struct drm_device *dev = pci_get_drvdata(pdev);
	688
	689	drm_dev_unplug(dev);
	690	drm_atomic_helper_shutdown(dev);
	691	bochs_hw_fini(dev);
	692	drm_dev_put(dev);
	693	}
	694
	695	static const struct pci_device_id bochs_pci_tbl[] = {
	696	{
	697	.vendor = 0x1234,
	698	.device = 0x1111,
	699	.subvendor = PCI_SUBVENDOR_ID_REDHAT_QUMRANET,
	700	.subdevice = PCI_SUBDEVICE_ID_QEMU,
	701	.driver_data = BOCHS_QEMU_STDVGA,
	702	},
	703	{
	704	.vendor = 0x1234,
	705	.device = 0x1111,
	706	.subvendor = PCI_ANY_ID,
	707	.subdevice = PCI_ANY_ID,
	708	.driver_data = BOCHS_UNKNOWN,
	709	},
78afff2a PAI	710	{
	711	.vendor = 0x4321,
	712	.device = 0x1111,
	713	.subvendor = PCI_ANY_ID,
	714	.subdevice = PCI_ANY_ID,
	715	.driver_data = BOCHS_SIMICS,
	716	},
796c3e35 TZ	717	{ /* end of list */ }
	718	};
	719
	720	static struct pci_driver bochs_pci_driver = {
	721	.name = "bochs-drm",
	722	.id_table = bochs_pci_tbl,
	723	.probe = bochs_pci_probe,
	724	.remove = bochs_pci_remove,
	725	.driver.pm = &bochs_pm_ops,
	726	};
	727
	728	/* ---------------------------------------------------------------------- */
	729	/* module init/exit */
	730
54e67e5a	731	drm_module_pci_driver_if_modeset(bochs_pci_driver, bochs_modeset);
796c3e35 TZ	732
	733	MODULE_DEVICE_TABLE(pci, bochs_pci_tbl);
	734	MODULE_AUTHOR("Gerd Hoffmann <kraxel@redhat.com>");
	735	MODULE_LICENSE("GPL");