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drm/tilcdc: fix build error when !CONFIG_CPU_FREQ
[linux-2.6-block.git] / drivers / gpu / drm / tilcdc / tilcdc_drv.c
CommitLineData
16ea975e
RC		 1/*
2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18/* LCDC DRM driver, based on da8xx-fb */
19
103cd8bc 20#include <linux/component.h>
416a07fb
DG		 21#include <linux/pinctrl/consumer.h>
22#include <linux/suspend.h>
103cd8bc 23
16ea975e
RC		 24#include "tilcdc_drv.h"
25#include "tilcdc_regs.h"
26#include "tilcdc_tfp410.h"
0d4bbaf9 27#include "tilcdc_panel.h"
103cd8bc 28#include "tilcdc_external.h"
16ea975e
RC		 29
30#include "drm_fb_helper.h"
31
32static LIST_HEAD(module_list);
33
34void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
35 const struct tilcdc_module_ops *funcs)
36{
37 mod->name = name;
38 mod->funcs = funcs;
39 INIT_LIST_HEAD(&mod->list);
40 list_add(&mod->list, &module_list);
41}
42
43void tilcdc_module_cleanup(struct tilcdc_module *mod)
44{
45 list_del(&mod->list);
46}
47
48static struct of_device_id tilcdc_of_match[];
49
50static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev,
1eb83451 51 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
16ea975e
RC		 52{
53 return drm_fb_cma_create(dev, file_priv, mode_cmd);
54}
55
56static void tilcdc_fb_output_poll_changed(struct drm_device *dev)
57{
58 struct tilcdc_drm_private *priv = dev->dev_private;
c0844817 59 drm_fbdev_cma_hotplug_event(priv->fbdev);
16ea975e
RC		 60}
61
62static const struct drm_mode_config_funcs mode_config_funcs = {
63 .fb_create = tilcdc_fb_create,
64 .output_poll_changed = tilcdc_fb_output_poll_changed,
65};
66
67static int modeset_init(struct drm_device *dev)
68{
69 struct tilcdc_drm_private *priv = dev->dev_private;
70 struct tilcdc_module *mod;
71
72 drm_mode_config_init(dev);
73
74 priv->crtc = tilcdc_crtc_create(dev);
75
76 list_for_each_entry(mod, &module_list, list) {
77 DBG("loading module: %s", mod->name);
78 mod->funcs->modeset_init(mod, dev);
79 }
80
16ea975e
RC		 81 dev->mode_config.min_width = 0;
82 dev->mode_config.min_height = 0;
83 dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc);
84 dev->mode_config.max_height = 2048;
85 dev->mode_config.funcs = &mode_config_funcs;
86
87 return 0;
88}
89
90#ifdef CONFIG_CPU_FREQ
91static int cpufreq_transition(struct notifier_block *nb,
92 unsigned long val, void *data)
93{
94 struct tilcdc_drm_private *priv = container_of(nb,
95 struct tilcdc_drm_private, freq_transition);
96 if (val == CPUFREQ_POSTCHANGE) {
97 if (priv->lcd_fck_rate != clk_get_rate(priv->clk)) {
98 priv->lcd_fck_rate = clk_get_rate(priv->clk);
99 tilcdc_crtc_update_clk(priv->crtc);
100 }
101 }
102
103 return 0;
104}
105#endif
106
107/*
108 * DRM operations:
109 */
110
111static int tilcdc_unload(struct drm_device *dev)
112{
113 struct tilcdc_drm_private *priv = dev->dev_private;
16ea975e 114
103cd8bc
JS		 115 tilcdc_remove_external_encoders(dev);
116
3a490122 117 drm_fbdev_cma_fini(priv->fbdev);
16ea975e
RC		 118 drm_kms_helper_poll_fini(dev);
119 drm_mode_config_cleanup(dev);
120 drm_vblank_cleanup(dev);
121
122 pm_runtime_get_sync(dev->dev);
123 drm_irq_uninstall(dev);
124 pm_runtime_put_sync(dev->dev);
125
126#ifdef CONFIG_CPU_FREQ
127 cpufreq_unregister_notifier(&priv->freq_transition,
128 CPUFREQ_TRANSITION_NOTIFIER);
129#endif
130
131 if (priv->clk)
132 clk_put(priv->clk);
133
134 if (priv->mmio)
135 iounmap(priv->mmio);
136
137 flush_workqueue(priv->wq);
138 destroy_workqueue(priv->wq);
139
140 dev->dev_private = NULL;
141
142 pm_runtime_disable(dev->dev);
143
16ea975e
RC		 144 kfree(priv);
145
146 return 0;
147}
148
149static int tilcdc_load(struct drm_device *dev, unsigned long flags)
150{
151 struct platform_device *pdev = dev->platformdev;
152 struct device_node *node = pdev->dev.of_node;
153 struct tilcdc_drm_private *priv;
dc28aa07 154 struct tilcdc_module *mod;
16ea975e 155 struct resource *res;
dc28aa07 156 u32 bpp = 0;
16ea975e
RC		 157 int ret;
158
159 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
160 if (!priv) {
161 dev_err(dev->dev, "failed to allocate private data\n");
162 return -ENOMEM;
163 }
164
165 dev->dev_private = priv;
166
103cd8bc
JS		 167 priv->is_componentized =
168 tilcdc_get_external_components(dev->dev, NULL) > 0;
169
16ea975e 170 priv->wq = alloc_ordered_workqueue("tilcdc", 0);
b478e336
EG		 171 if (!priv->wq) {
172 ret = -ENOMEM;
173 goto fail_free_priv;
174 }
16ea975e
RC		 175
176 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
177 if (!res) {
178 dev_err(dev->dev, "failed to get memory resource\n");
179 ret = -EINVAL;
b478e336 180 goto fail_free_wq;
16ea975e
RC		 181 }
182
183 priv->mmio = ioremap_nocache(res->start, resource_size(res));
184 if (!priv->mmio) {
185 dev_err(dev->dev, "failed to ioremap\n");
186 ret = -ENOMEM;
b478e336 187 goto fail_free_wq;
16ea975e
RC		 188 }
189
190 priv->clk = clk_get(dev->dev, "fck");
191 if (IS_ERR(priv->clk)) {
192 dev_err(dev->dev, "failed to get functional clock\n");
193 ret = -ENODEV;
b478e336 194 goto fail_iounmap;
16ea975e
RC		 195 }
196
16ea975e
RC		 197#ifdef CONFIG_CPU_FREQ
198 priv->lcd_fck_rate = clk_get_rate(priv->clk);
199 priv->freq_transition.notifier_call = cpufreq_transition;
200 ret = cpufreq_register_notifier(&priv->freq_transition,
201 CPUFREQ_TRANSITION_NOTIFIER);
202 if (ret) {
203 dev_err(dev->dev, "failed to register cpufreq notifier\n");
3d19306a 204 goto fail_put_clk;
16ea975e
RC		 205 }
206#endif
207
208 if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
4e564346
DE		 209 priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH;
210
211 DBG("Maximum Bandwidth Value %d", priv->max_bandwidth);
212
213 if (of_property_read_u32(node, "ti,max-width", &priv->max_width))
214 priv->max_width = TILCDC_DEFAULT_MAX_WIDTH;
215
216 DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width);
217
218 if (of_property_read_u32(node, "ti,max-pixelclock",
219 &priv->max_pixelclock))
220 priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK;
221
222 DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);
16ea975e
RC		 223
224 pm_runtime_enable(dev->dev);
e3487e07 225 pm_runtime_irq_safe(dev->dev);
16ea975e
RC		 226
227 /* Determine LCD IP Version */
228 pm_runtime_get_sync(dev->dev);
229 switch (tilcdc_read(dev, LCDC_PID_REG)) {
230 case 0x4c100102:
231 priv->rev = 1;
232 break;
233 case 0x4f200800:
234 case 0x4f201000:
235 priv->rev = 2;
236 break;
237 default:
238 dev_warn(dev->dev, "Unknown PID Reg value 0x%08x, "
239 "defaulting to LCD revision 1\n",
240 tilcdc_read(dev, LCDC_PID_REG));
241 priv->rev = 1;
242 break;
243 }
244
245 pm_runtime_put_sync(dev->dev);
246
247 ret = modeset_init(dev);
248 if (ret < 0) {
249 dev_err(dev->dev, "failed to initialize mode setting\n");
b478e336 250 goto fail_cpufreq_unregister;
16ea975e
RC		 251 }
252
103cd8bc
JS		 253 platform_set_drvdata(pdev, dev);
254
255 if (priv->is_componentized) {
256 ret = component_bind_all(dev->dev, dev);
257 if (ret < 0)
258 goto fail_mode_config_cleanup;
259
260 ret = tilcdc_add_external_encoders(dev, &bpp);
261 if (ret < 0)
262 goto fail_component_cleanup;
263 }
264
265 if ((priv->num_encoders == 0) || (priv->num_connectors == 0)) {
266 dev_err(dev->dev, "no encoders/connectors found\n");
267 ret = -ENXIO;
268 goto fail_external_cleanup;
269 }
270
16ea975e
RC		 271 ret = drm_vblank_init(dev, 1);
272 if (ret < 0) {
273 dev_err(dev->dev, "failed to initialize vblank\n");
103cd8bc 274 goto fail_external_cleanup;
16ea975e
RC		 275 }
276
277 pm_runtime_get_sync(dev->dev);
bb0f1b5c 278 ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0));
16ea975e
RC		 279 pm_runtime_put_sync(dev->dev);
280 if (ret < 0) {
281 dev_err(dev->dev, "failed to install IRQ handler\n");
b478e336 282 goto fail_vblank_cleanup;
16ea975e
RC		 283 }
284
dc28aa07
BP		 285 list_for_each_entry(mod, &module_list, list) {
286 DBG("%s: preferred_bpp: %d", mod->name, mod->preferred_bpp);
287 bpp = mod->preferred_bpp;
288 if (bpp > 0)
289 break;
290 }
291
4314e19e 292 drm_helper_disable_unused_functions(dev);
dc28aa07 293 priv->fbdev = drm_fbdev_cma_init(dev, bpp,
16ea975e
RC		 294 dev->mode_config.num_crtc,
295 dev->mode_config.num_connector);
b478e336
EG		 296 if (IS_ERR(priv->fbdev)) {
297 ret = PTR_ERR(priv->fbdev);
298 goto fail_irq_uninstall;
299 }
16ea975e
RC		 300
301 drm_kms_helper_poll_init(dev);
302
303 return 0;
304
b478e336
EG		 305fail_irq_uninstall:
306 pm_runtime_get_sync(dev->dev);
307 drm_irq_uninstall(dev);
308 pm_runtime_put_sync(dev->dev);
309
310fail_vblank_cleanup:
311 drm_vblank_cleanup(dev);
312
313fail_mode_config_cleanup:
314 drm_mode_config_cleanup(dev);
315
103cd8bc
JS		 316fail_component_cleanup:
317 if (priv->is_componentized)
318 component_unbind_all(dev->dev, dev);
319
320fail_external_cleanup:
321 tilcdc_remove_external_encoders(dev);
322
b478e336
EG		 323fail_cpufreq_unregister:
324 pm_runtime_disable(dev->dev);
325#ifdef CONFIG_CPU_FREQ
326 cpufreq_unregister_notifier(&priv->freq_transition,
327 CPUFREQ_TRANSITION_NOTIFIER);
b478e336
EG		 328
329fail_put_clk:
7974dff4 330#endif
b478e336
EG		 331 clk_put(priv->clk);
332
333fail_iounmap:
334 iounmap(priv->mmio);
335
336fail_free_wq:
337 flush_workqueue(priv->wq);
338 destroy_workqueue(priv->wq);
339
340fail_free_priv:
341 dev->dev_private = NULL;
342 kfree(priv);
16ea975e
RC		 343 return ret;
344}
345
16ea975e
RC		 346static void tilcdc_lastclose(struct drm_device *dev)
347{
348 struct tilcdc_drm_private *priv = dev->dev_private;
349 drm_fbdev_cma_restore_mode(priv->fbdev);
350}
351
e9f0d76f 352static irqreturn_t tilcdc_irq(int irq, void *arg)
16ea975e
RC		 353{
354 struct drm_device *dev = arg;
355 struct tilcdc_drm_private *priv = dev->dev_private;
356 return tilcdc_crtc_irq(priv->crtc);
357}
358
359static void tilcdc_irq_preinstall(struct drm_device *dev)
360{
361 tilcdc_clear_irqstatus(dev, 0xffffffff);
362}
363
364static int tilcdc_irq_postinstall(struct drm_device *dev)
365{
366 struct tilcdc_drm_private *priv = dev->dev_private;
367
368 /* enable FIFO underflow irq: */
a50b24f4 369 if (priv->rev == 1)
16ea975e 370 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_UNDERFLOW_INT_ENA);
a50b24f4 371 else
b62222fc
DE		 372 tilcdc_set(dev, LCDC_INT_ENABLE_SET_REG,
373 LCDC_V2_UNDERFLOW_INT_ENA |
374 LCDC_FRAME_DONE);
16ea975e
RC		 375
376 return 0;
377}
378
379static void tilcdc_irq_uninstall(struct drm_device *dev)
380{
381 struct tilcdc_drm_private *priv = dev->dev_private;
382
383 /* disable irqs that we might have enabled: */
384 if (priv->rev == 1) {
385 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
386 LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA);
387 tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_V1_END_OF_FRAME_INT_ENA);
388 } else {
389 tilcdc_clear(dev, LCDC_INT_ENABLE_SET_REG,
390 LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA |
391 LCDC_V2_END_OF_FRAME0_INT_ENA | LCDC_V2_END_OF_FRAME1_INT_ENA |
392 LCDC_FRAME_DONE);
393 }
394
395}
396
397static void enable_vblank(struct drm_device *dev, bool enable)
398{
399 struct tilcdc_drm_private *priv = dev->dev_private;
400 u32 reg, mask;
401
402 if (priv->rev == 1) {
403 reg = LCDC_DMA_CTRL_REG;
404 mask = LCDC_V1_END_OF_FRAME_INT_ENA;
405 } else {
406 reg = LCDC_INT_ENABLE_SET_REG;
407 mask = LCDC_V2_END_OF_FRAME0_INT_ENA |
b62222fc 408 LCDC_V2_END_OF_FRAME1_INT_ENA;
16ea975e
RC		 409 }
410
411 if (enable)
412 tilcdc_set(dev, reg, mask);
413 else
414 tilcdc_clear(dev, reg, mask);
415}
416
88e72717 417static int tilcdc_enable_vblank(struct drm_device *dev, unsigned int pipe)
16ea975e
RC		 418{
419 enable_vblank(dev, true);
420 return 0;
421}
422
88e72717 423static void tilcdc_disable_vblank(struct drm_device *dev, unsigned int pipe)
16ea975e
RC		 424{
425 enable_vblank(dev, false);
426}
427
428#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_PM_SLEEP)
429static const struct {
430 const char *name;
431 uint8_t rev;
432 uint8_t save;
433 uint32_t reg;
32501459 434} registers[] = {
16ea975e
RC		 435#define REG(rev, save, reg) { #reg, rev, save, reg }
436 /* exists in revision 1: */
437 REG(1, false, LCDC_PID_REG),
438 REG(1, true, LCDC_CTRL_REG),
439 REG(1, false, LCDC_STAT_REG),
440 REG(1, true, LCDC_RASTER_CTRL_REG),
441 REG(1, true, LCDC_RASTER_TIMING_0_REG),
442 REG(1, true, LCDC_RASTER_TIMING_1_REG),
443 REG(1, true, LCDC_RASTER_TIMING_2_REG),
444 REG(1, true, LCDC_DMA_CTRL_REG),
445 REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG),
446 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG),
447 REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG),
448 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG),
449 /* new in revision 2: */
450 REG(2, false, LCDC_RAW_STAT_REG),
451 REG(2, false, LCDC_MASKED_STAT_REG),
452 REG(2, false, LCDC_INT_ENABLE_SET_REG),
453 REG(2, false, LCDC_INT_ENABLE_CLR_REG),
454 REG(2, false, LCDC_END_OF_INT_IND_REG),
455 REG(2, true, LCDC_CLK_ENABLE_REG),
456 REG(2, true, LCDC_INT_ENABLE_SET_REG),
457#undef REG
458};
459#endif
460
461#ifdef CONFIG_DEBUG_FS
462static int tilcdc_regs_show(struct seq_file *m, void *arg)
463{
464 struct drm_info_node *node = (struct drm_info_node *) m->private;
465 struct drm_device *dev = node->minor->dev;
466 struct tilcdc_drm_private *priv = dev->dev_private;
467 unsigned i;
468
469 pm_runtime_get_sync(dev->dev);
470
471 seq_printf(m, "revision: %d\n", priv->rev);
472
473 for (i = 0; i < ARRAY_SIZE(registers); i++)
474 if (priv->rev >= registers[i].rev)
475 seq_printf(m, "%s:\t %08x\n", registers[i].name,
476 tilcdc_read(dev, registers[i].reg));
477
478 pm_runtime_put_sync(dev->dev);
479
480 return 0;
481}
482
483static int tilcdc_mm_show(struct seq_file *m, void *arg)
484{
485 struct drm_info_node *node = (struct drm_info_node *) m->private;
486 struct drm_device *dev = node->minor->dev;
b04a5906 487 return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm);
16ea975e
RC		 488}
489
490static struct drm_info_list tilcdc_debugfs_list[] = {
491 { "regs", tilcdc_regs_show, 0 },
492 { "mm", tilcdc_mm_show, 0 },
493 { "fb", drm_fb_cma_debugfs_show, 0 },
494};
495
496static int tilcdc_debugfs_init(struct drm_minor *minor)
497{
498 struct drm_device *dev = minor->dev;
499 struct tilcdc_module *mod;
500 int ret;
501
502 ret = drm_debugfs_create_files(tilcdc_debugfs_list,
503 ARRAY_SIZE(tilcdc_debugfs_list),
504 minor->debugfs_root, minor);
505
506 list_for_each_entry(mod, &module_list, list)
507 if (mod->funcs->debugfs_init)
508 mod->funcs->debugfs_init(mod, minor);
509
510 if (ret) {
511 dev_err(dev->dev, "could not install tilcdc_debugfs_list\n");
512 return ret;
513 }
514
515 return ret;
516}
517
518static void tilcdc_debugfs_cleanup(struct drm_minor *minor)
519{
520 struct tilcdc_module *mod;
521 drm_debugfs_remove_files(tilcdc_debugfs_list,
522 ARRAY_SIZE(tilcdc_debugfs_list), minor);
523
524 list_for_each_entry(mod, &module_list, list)
525 if (mod->funcs->debugfs_cleanup)
526 mod->funcs->debugfs_cleanup(mod, minor);
527}
528#endif
529
530static const struct file_operations fops = {
531 .owner = THIS_MODULE,
532 .open = drm_open,
533 .release = drm_release,
534 .unlocked_ioctl = drm_ioctl,
535#ifdef CONFIG_COMPAT
536 .compat_ioctl = drm_compat_ioctl,
537#endif
538 .poll = drm_poll,
539 .read = drm_read,
16ea975e
RC		 540 .llseek = no_llseek,
541 .mmap = drm_gem_cma_mmap,
542};
543
544static struct drm_driver tilcdc_driver = {
9c153905
JS		 545 .driver_features = (DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET |
546 DRIVER_PRIME),
16ea975e
RC		 547 .load = tilcdc_load,
548 .unload = tilcdc_unload,
16ea975e 549 .lastclose = tilcdc_lastclose,
915b4d11 550 .set_busid = drm_platform_set_busid,
16ea975e
RC		 551 .irq_handler = tilcdc_irq,
552 .irq_preinstall = tilcdc_irq_preinstall,
553 .irq_postinstall = tilcdc_irq_postinstall,
554 .irq_uninstall = tilcdc_irq_uninstall,
b44f8408 555 .get_vblank_counter = drm_vblank_no_hw_counter,
16ea975e
RC		 556 .enable_vblank = tilcdc_enable_vblank,
557 .disable_vblank = tilcdc_disable_vblank,
558 .gem_free_object = drm_gem_cma_free_object,
559 .gem_vm_ops = &drm_gem_cma_vm_ops,
560 .dumb_create = drm_gem_cma_dumb_create,
561 .dumb_map_offset = drm_gem_cma_dumb_map_offset,
43387b37 562 .dumb_destroy = drm_gem_dumb_destroy,
9c153905
JS		 563
564 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
565 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
566 .gem_prime_import = drm_gem_prime_import,
567 .gem_prime_export = drm_gem_prime_export,
568 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
569 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
570 .gem_prime_vmap = drm_gem_cma_prime_vmap,
571 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
572 .gem_prime_mmap = drm_gem_cma_prime_mmap,
16ea975e
RC		 573#ifdef CONFIG_DEBUG_FS
574 .debugfs_init = tilcdc_debugfs_init,
575 .debugfs_cleanup = tilcdc_debugfs_cleanup,
576#endif
577 .fops = &fops,
578 .name = "tilcdc",
579 .desc = "TI LCD Controller DRM",
580 .date = "20121205",
581 .major = 1,
582 .minor = 0,
583};
584
585/*
586 * Power management:
587 */
588
589#ifdef CONFIG_PM_SLEEP
590static int tilcdc_pm_suspend(struct device *dev)
591{
592 struct drm_device *ddev = dev_get_drvdata(dev);
593 struct tilcdc_drm_private *priv = ddev->dev_private;
594 unsigned i, n = 0;
595
596 drm_kms_helper_poll_disable(ddev);
597
85fd27f8
DE		 598 /* Select sleep pin state */
599 pinctrl_pm_select_sleep_state(dev);
600
601 if (pm_runtime_suspended(dev)) {
602 priv->ctx_valid = false;
603 return 0;
604 }
605
614b3cfe
DE		 606 /* Disable the LCDC controller, to avoid locking up the PRCM */
607 tilcdc_crtc_dpms(priv->crtc, DRM_MODE_DPMS_OFF);
608
16ea975e
RC		 609 /* Save register state: */
610 for (i = 0; i < ARRAY_SIZE(registers); i++)
611 if (registers[i].save && (priv->rev >= registers[i].rev))
612 priv->saved_register[n++] = tilcdc_read(ddev, registers[i].reg);
613
85fd27f8 614 priv->ctx_valid = true;
416a07fb 615
16ea975e
RC		 616 return 0;
617}
618
619static int tilcdc_pm_resume(struct device *dev)
620{
621 struct drm_device *ddev = dev_get_drvdata(dev);
622 struct tilcdc_drm_private *priv = ddev->dev_private;
623 unsigned i, n = 0;
624
416a07fb
DG		 625 /* Select default pin state */
626 pinctrl_pm_select_default_state(dev);
627
85fd27f8
DE		 628 if (priv->ctx_valid == true) {
629 /* Restore register state: */
630 for (i = 0; i < ARRAY_SIZE(registers); i++)
631 if (registers[i].save &&
632 (priv->rev >= registers[i].rev))
633 tilcdc_write(ddev, registers[i].reg,
634 priv->saved_register[n++]);
635 }
16ea975e
RC		 636
637 drm_kms_helper_poll_enable(ddev);
638
639 return 0;
640}
641#endif
642
643static const struct dev_pm_ops tilcdc_pm_ops = {
644 SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume)
645};
646
647/*
648 * Platform driver:
649 */
650
103cd8bc
JS		 651static int tilcdc_bind(struct device *dev)
652{
653 return drm_platform_init(&tilcdc_driver, to_platform_device(dev));
654}
655
656static void tilcdc_unbind(struct device *dev)
657{
658 drm_put_dev(dev_get_drvdata(dev));
659}
660
661static const struct component_master_ops tilcdc_comp_ops = {
662 .bind = tilcdc_bind,
663 .unbind = tilcdc_unbind,
664};
665
16ea975e
RC		 666static int tilcdc_pdev_probe(struct platform_device *pdev)
667{
103cd8bc
JS		 668 struct component_match *match = NULL;
669 int ret;
670
16ea975e
RC		 671 /* bail out early if no DT data: */
672 if (!pdev->dev.of_node) {
673 dev_err(&pdev->dev, "device-tree data is missing\n");
674 return -ENXIO;
675 }
676
103cd8bc
JS		 677 ret = tilcdc_get_external_components(&pdev->dev, &match);
678 if (ret < 0)
679 return ret;
680 else if (ret == 0)
681 return drm_platform_init(&tilcdc_driver, pdev);
682 else
683 return component_master_add_with_match(&pdev->dev,
684 &tilcdc_comp_ops,
685 match);
16ea975e
RC		 686}
687
688static int tilcdc_pdev_remove(struct platform_device *pdev)
689{
103cd8bc
JS		 690 struct drm_device *ddev = dev_get_drvdata(&pdev->dev);
691 struct tilcdc_drm_private *priv = ddev->dev_private;
692
693 /* Check if a subcomponent has already triggered the unloading. */
694 if (!priv)
695 return 0;
696
697 if (priv->is_componentized)
698 component_master_del(&pdev->dev, &tilcdc_comp_ops);
699 else
700 drm_put_dev(platform_get_drvdata(pdev));
16ea975e
RC		 701
702 return 0;
703}
704
705static struct of_device_id tilcdc_of_match[] = {
706 { .compatible = "ti,am33xx-tilcdc", },
707 { },
708};
709MODULE_DEVICE_TABLE(of, tilcdc_of_match);
710
711static struct platform_driver tilcdc_platform_driver = {
712 .probe = tilcdc_pdev_probe,
713 .remove = tilcdc_pdev_remove,
714 .driver = {
16ea975e
RC		 715 .name = "tilcdc",
716 .pm = &tilcdc_pm_ops,
717 .of_match_table = tilcdc_of_match,
718 },
719};
720
721static int __init tilcdc_drm_init(void)
722{
723 DBG("init");
724 tilcdc_tfp410_init();
0d4bbaf9 725 tilcdc_panel_init();
16ea975e
RC		 726 return platform_driver_register(&tilcdc_platform_driver);
727}
728
729static void __exit tilcdc_drm_fini(void)
730{
731 DBG("fini");
16ea975e 732 platform_driver_unregister(&tilcdc_platform_driver);
eb565a2b 733 tilcdc_panel_fini();
eb565a2b 734 tilcdc_tfp410_fini();
16ea975e
RC		 735}
736
2023d84d 737module_init(tilcdc_drm_init);
16ea975e
RC		 738module_exit(tilcdc_drm_fini);
739
740MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
741MODULE_DESCRIPTION("TI LCD Controller DRM Driver");
742MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)