Commit | Line | Data |
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caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
16ea975e RC |
2 | /* |
3 | * Copyright (C) 2012 Texas Instruments | |
4 | * Author: Rob Clark <robdclark@gmail.com> | |
16ea975e RC |
5 | */ |
6 | ||
7 | /* LCDC DRM driver, based on da8xx-fb */ | |
8 | ||
103cd8bc | 9 | #include <linux/component.h> |
416a07fb DG |
10 | #include <linux/pinctrl/consumer.h> |
11 | #include <linux/suspend.h> | |
edc43303 JS |
12 | #include <drm/drm_atomic.h> |
13 | #include <drm/drm_atomic_helper.h> | |
bb2af9bd | 14 | #include <drm/drm_fb_helper.h> |
6025a157 | 15 | #include <drm/drm_gem_framebuffer_helper.h> |
fcd70cd3 | 16 | #include <drm/drm_probe_helper.h> |
103cd8bc | 17 | |
16ea975e RC |
18 | #include "tilcdc_drv.h" |
19 | #include "tilcdc_regs.h" | |
20 | #include "tilcdc_tfp410.h" | |
0d4bbaf9 | 21 | #include "tilcdc_panel.h" |
103cd8bc | 22 | #include "tilcdc_external.h" |
16ea975e | 23 | |
16ea975e RC |
24 | static LIST_HEAD(module_list); |
25 | ||
bcc5a6f5 JS |
26 | static const u32 tilcdc_rev1_formats[] = { DRM_FORMAT_RGB565 }; |
27 | ||
28 | static const u32 tilcdc_straight_formats[] = { DRM_FORMAT_RGB565, | |
29 | DRM_FORMAT_BGR888, | |
30 | DRM_FORMAT_XBGR8888 }; | |
31 | ||
32 | static const u32 tilcdc_crossed_formats[] = { DRM_FORMAT_BGR565, | |
33 | DRM_FORMAT_RGB888, | |
34 | DRM_FORMAT_XRGB8888 }; | |
35 | ||
36 | static const u32 tilcdc_legacy_formats[] = { DRM_FORMAT_RGB565, | |
37 | DRM_FORMAT_RGB888, | |
38 | DRM_FORMAT_XRGB8888 }; | |
39 | ||
16ea975e RC |
40 | void tilcdc_module_init(struct tilcdc_module *mod, const char *name, |
41 | const struct tilcdc_module_ops *funcs) | |
42 | { | |
43 | mod->name = name; | |
44 | mod->funcs = funcs; | |
45 | INIT_LIST_HEAD(&mod->list); | |
46 | list_add(&mod->list, &module_list); | |
47 | } | |
48 | ||
49 | void tilcdc_module_cleanup(struct tilcdc_module *mod) | |
50 | { | |
51 | list_del(&mod->list); | |
52 | } | |
53 | ||
54 | static struct of_device_id tilcdc_of_match[]; | |
55 | ||
56 | static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev, | |
1eb83451 | 57 | struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd) |
16ea975e | 58 | { |
6025a157 | 59 | return drm_gem_fb_create(dev, file_priv, mode_cmd); |
16ea975e RC |
60 | } |
61 | ||
30457676 WY |
62 | static int tilcdc_atomic_check(struct drm_device *dev, |
63 | struct drm_atomic_state *state) | |
edc43303 JS |
64 | { |
65 | int ret; | |
66 | ||
67 | ret = drm_atomic_helper_check_modeset(dev, state); | |
68 | if (ret) | |
69 | return ret; | |
70 | ||
71 | ret = drm_atomic_helper_check_planes(dev, state); | |
72 | if (ret) | |
73 | return ret; | |
74 | ||
75 | /* | |
76 | * tilcdc ->atomic_check can update ->mode_changed if pixel format | |
77 | * changes, hence will we check modeset changes again. | |
78 | */ | |
79 | ret = drm_atomic_helper_check_modeset(dev, state); | |
80 | if (ret) | |
81 | return ret; | |
82 | ||
83 | return ret; | |
84 | } | |
85 | ||
86 | static int tilcdc_commit(struct drm_device *dev, | |
87 | struct drm_atomic_state *state, | |
88 | bool async) | |
89 | { | |
90 | int ret; | |
91 | ||
92 | ret = drm_atomic_helper_prepare_planes(dev, state); | |
93 | if (ret) | |
94 | return ret; | |
95 | ||
fad9e43a ML |
96 | ret = drm_atomic_helper_swap_state(state, true); |
97 | if (ret) { | |
98 | drm_atomic_helper_cleanup_planes(dev, state); | |
99 | return ret; | |
100 | } | |
edc43303 JS |
101 | |
102 | /* | |
103 | * Everything below can be run asynchronously without the need to grab | |
104 | * any modeset locks at all under one condition: It must be guaranteed | |
105 | * that the asynchronous work has either been cancelled (if the driver | |
106 | * supports it, which at least requires that the framebuffers get | |
107 | * cleaned up with drm_atomic_helper_cleanup_planes()) or completed | |
108 | * before the new state gets committed on the software side with | |
109 | * drm_atomic_helper_swap_state(). | |
110 | * | |
111 | * This scheme allows new atomic state updates to be prepared and | |
112 | * checked in parallel to the asynchronous completion of the previous | |
113 | * update. Which is important since compositors need to figure out the | |
114 | * composition of the next frame right after having submitted the | |
115 | * current layout. | |
116 | */ | |
117 | ||
118 | drm_atomic_helper_commit_modeset_disables(dev, state); | |
119 | ||
2b58e98d | 120 | drm_atomic_helper_commit_planes(dev, state, 0); |
edc43303 JS |
121 | |
122 | drm_atomic_helper_commit_modeset_enables(dev, state); | |
123 | ||
124 | drm_atomic_helper_wait_for_vblanks(dev, state); | |
125 | ||
126 | drm_atomic_helper_cleanup_planes(dev, state); | |
127 | ||
edc43303 JS |
128 | return 0; |
129 | } | |
130 | ||
16ea975e RC |
131 | static const struct drm_mode_config_funcs mode_config_funcs = { |
132 | .fb_create = tilcdc_fb_create, | |
edc43303 JS |
133 | .atomic_check = tilcdc_atomic_check, |
134 | .atomic_commit = tilcdc_commit, | |
16ea975e RC |
135 | }; |
136 | ||
9963d36d | 137 | static void modeset_init(struct drm_device *dev) |
16ea975e RC |
138 | { |
139 | struct tilcdc_drm_private *priv = dev->dev_private; | |
140 | struct tilcdc_module *mod; | |
141 | ||
16ea975e RC |
142 | list_for_each_entry(mod, &module_list, list) { |
143 | DBG("loading module: %s", mod->name); | |
144 | mod->funcs->modeset_init(mod, dev); | |
145 | } | |
146 | ||
16ea975e RC |
147 | dev->mode_config.min_width = 0; |
148 | dev->mode_config.min_height = 0; | |
149 | dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc); | |
150 | dev->mode_config.max_height = 2048; | |
151 | dev->mode_config.funcs = &mode_config_funcs; | |
16ea975e RC |
152 | } |
153 | ||
154 | #ifdef CONFIG_CPU_FREQ | |
155 | static int cpufreq_transition(struct notifier_block *nb, | |
156 | unsigned long val, void *data) | |
157 | { | |
158 | struct tilcdc_drm_private *priv = container_of(nb, | |
159 | struct tilcdc_drm_private, freq_transition); | |
a6b7ebaa | 160 | |
642e5167 JS |
161 | if (val == CPUFREQ_POSTCHANGE) |
162 | tilcdc_crtc_update_clk(priv->crtc); | |
16ea975e RC |
163 | |
164 | return 0; | |
165 | } | |
166 | #endif | |
167 | ||
168 | /* | |
169 | * DRM operations: | |
170 | */ | |
171 | ||
923310ba | 172 | static void tilcdc_fini(struct drm_device *dev) |
16ea975e RC |
173 | { |
174 | struct tilcdc_drm_private *priv = dev->dev_private; | |
16ea975e | 175 | |
432973fd JS |
176 | #ifdef CONFIG_CPU_FREQ |
177 | if (priv->freq_transition.notifier_call) | |
178 | cpufreq_unregister_notifier(&priv->freq_transition, | |
179 | CPUFREQ_TRANSITION_NOTIFIER); | |
180 | #endif | |
181 | ||
9e79e062 | 182 | if (priv->crtc) |
2d53a180 | 183 | tilcdc_crtc_shutdown(priv->crtc); |
923310ba | 184 | |
9e79e062 JS |
185 | if (priv->is_registered) |
186 | drm_dev_unregister(dev); | |
103cd8bc | 187 | |
16ea975e | 188 | drm_kms_helper_poll_fini(dev); |
923310ba | 189 | drm_irq_uninstall(dev); |
16ea975e | 190 | drm_mode_config_cleanup(dev); |
ec9eab09 | 191 | tilcdc_remove_external_device(dev); |
16ea975e | 192 | |
16ea975e RC |
193 | if (priv->clk) |
194 | clk_put(priv->clk); | |
195 | ||
196 | if (priv->mmio) | |
197 | iounmap(priv->mmio); | |
198 | ||
9e79e062 JS |
199 | if (priv->wq) { |
200 | flush_workqueue(priv->wq); | |
201 | destroy_workqueue(priv->wq); | |
202 | } | |
16ea975e RC |
203 | |
204 | dev->dev_private = NULL; | |
205 | ||
206 | pm_runtime_disable(dev->dev); | |
207 | ||
ce7b700d | 208 | drm_dev_put(dev); |
16ea975e RC |
209 | } |
210 | ||
923310ba | 211 | static int tilcdc_init(struct drm_driver *ddrv, struct device *dev) |
16ea975e | 212 | { |
923310ba JS |
213 | struct drm_device *ddev; |
214 | struct platform_device *pdev = to_platform_device(dev); | |
215 | struct device_node *node = dev->of_node; | |
16ea975e RC |
216 | struct tilcdc_drm_private *priv; |
217 | struct resource *res; | |
dc28aa07 | 218 | u32 bpp = 0; |
16ea975e RC |
219 | int ret; |
220 | ||
923310ba | 221 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
3366ba38 | 222 | if (!priv) |
16ea975e | 223 | return -ENOMEM; |
16ea975e | 224 | |
923310ba JS |
225 | ddev = drm_dev_alloc(ddrv, dev); |
226 | if (IS_ERR(ddev)) | |
227 | return PTR_ERR(ddev); | |
228 | ||
923310ba | 229 | ddev->dev_private = priv; |
9e79e062 JS |
230 | platform_set_drvdata(pdev, ddev); |
231 | drm_mode_config_init(ddev); | |
16ea975e | 232 | |
103cd8bc | 233 | priv->is_componentized = |
923310ba | 234 | tilcdc_get_external_components(dev, NULL) > 0; |
103cd8bc | 235 | |
16ea975e | 236 | priv->wq = alloc_ordered_workqueue("tilcdc", 0); |
b478e336 EG |
237 | if (!priv->wq) { |
238 | ret = -ENOMEM; | |
9e79e062 | 239 | goto init_failed; |
b478e336 | 240 | } |
16ea975e RC |
241 | |
242 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
243 | if (!res) { | |
923310ba | 244 | dev_err(dev, "failed to get memory resource\n"); |
16ea975e | 245 | ret = -EINVAL; |
9e79e062 | 246 | goto init_failed; |
16ea975e RC |
247 | } |
248 | ||
249 | priv->mmio = ioremap_nocache(res->start, resource_size(res)); | |
250 | if (!priv->mmio) { | |
923310ba | 251 | dev_err(dev, "failed to ioremap\n"); |
16ea975e | 252 | ret = -ENOMEM; |
9e79e062 | 253 | goto init_failed; |
16ea975e RC |
254 | } |
255 | ||
923310ba | 256 | priv->clk = clk_get(dev, "fck"); |
16ea975e | 257 | if (IS_ERR(priv->clk)) { |
923310ba | 258 | dev_err(dev, "failed to get functional clock\n"); |
16ea975e | 259 | ret = -ENODEV; |
9e79e062 | 260 | goto init_failed; |
16ea975e RC |
261 | } |
262 | ||
16ea975e | 263 | if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth)) |
4e564346 DE |
264 | priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH; |
265 | ||
266 | DBG("Maximum Bandwidth Value %d", priv->max_bandwidth); | |
267 | ||
0186fcce | 268 | if (of_property_read_u32(node, "max-width", &priv->max_width)) |
4e564346 DE |
269 | priv->max_width = TILCDC_DEFAULT_MAX_WIDTH; |
270 | ||
271 | DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width); | |
272 | ||
0186fcce | 273 | if (of_property_read_u32(node, "max-pixelclock", |
4e564346 DE |
274 | &priv->max_pixelclock)) |
275 | priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK; | |
276 | ||
277 | DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock); | |
16ea975e | 278 | |
923310ba | 279 | pm_runtime_enable(dev); |
16ea975e RC |
280 | |
281 | /* Determine LCD IP Version */ | |
923310ba JS |
282 | pm_runtime_get_sync(dev); |
283 | switch (tilcdc_read(ddev, LCDC_PID_REG)) { | |
16ea975e RC |
284 | case 0x4c100102: |
285 | priv->rev = 1; | |
286 | break; | |
287 | case 0x4f200800: | |
288 | case 0x4f201000: | |
289 | priv->rev = 2; | |
290 | break; | |
291 | default: | |
923310ba JS |
292 | dev_warn(dev, "Unknown PID Reg value 0x%08x, " |
293 | "defaulting to LCD revision 1\n", | |
294 | tilcdc_read(ddev, LCDC_PID_REG)); | |
16ea975e RC |
295 | priv->rev = 1; |
296 | break; | |
297 | } | |
298 | ||
923310ba | 299 | pm_runtime_put_sync(dev); |
16ea975e | 300 | |
bcc5a6f5 JS |
301 | if (priv->rev == 1) { |
302 | DBG("Revision 1 LCDC supports only RGB565 format"); | |
303 | priv->pixelformats = tilcdc_rev1_formats; | |
304 | priv->num_pixelformats = ARRAY_SIZE(tilcdc_rev1_formats); | |
c5665385 | 305 | bpp = 16; |
bcc5a6f5 JS |
306 | } else { |
307 | const char *str = "\0"; | |
308 | ||
309 | of_property_read_string(node, "blue-and-red-wiring", &str); | |
310 | if (0 == strcmp(str, "crossed")) { | |
311 | DBG("Configured for crossed blue and red wires"); | |
312 | priv->pixelformats = tilcdc_crossed_formats; | |
313 | priv->num_pixelformats = | |
314 | ARRAY_SIZE(tilcdc_crossed_formats); | |
c5665385 | 315 | bpp = 32; /* Choose bpp with RGB support for fbdef */ |
bcc5a6f5 JS |
316 | } else if (0 == strcmp(str, "straight")) { |
317 | DBG("Configured for straight blue and red wires"); | |
318 | priv->pixelformats = tilcdc_straight_formats; | |
319 | priv->num_pixelformats = | |
320 | ARRAY_SIZE(tilcdc_straight_formats); | |
c5665385 | 321 | bpp = 16; /* Choose bpp with RGB support for fbdef */ |
bcc5a6f5 JS |
322 | } else { |
323 | DBG("Blue and red wiring '%s' unknown, use legacy mode", | |
324 | str); | |
325 | priv->pixelformats = tilcdc_legacy_formats; | |
326 | priv->num_pixelformats = | |
327 | ARRAY_SIZE(tilcdc_legacy_formats); | |
c5665385 | 328 | bpp = 16; /* This is just a guess */ |
bcc5a6f5 JS |
329 | } |
330 | } | |
331 | ||
9963d36d | 332 | ret = tilcdc_crtc_create(ddev); |
16ea975e | 333 | if (ret < 0) { |
9963d36d | 334 | dev_err(dev, "failed to create crtc\n"); |
9e79e062 | 335 | goto init_failed; |
16ea975e | 336 | } |
9963d36d | 337 | modeset_init(ddev); |
16ea975e | 338 | |
432973fd JS |
339 | #ifdef CONFIG_CPU_FREQ |
340 | priv->freq_transition.notifier_call = cpufreq_transition; | |
341 | ret = cpufreq_register_notifier(&priv->freq_transition, | |
342 | CPUFREQ_TRANSITION_NOTIFIER); | |
343 | if (ret) { | |
344 | dev_err(dev, "failed to register cpufreq notifier\n"); | |
345 | priv->freq_transition.notifier_call = NULL; | |
346 | goto init_failed; | |
347 | } | |
348 | #endif | |
349 | ||
103cd8bc | 350 | if (priv->is_componentized) { |
923310ba | 351 | ret = component_bind_all(dev, ddev); |
103cd8bc | 352 | if (ret < 0) |
9e79e062 | 353 | goto init_failed; |
103cd8bc | 354 | |
ec9eab09 | 355 | ret = tilcdc_add_component_encoder(ddev); |
103cd8bc | 356 | if (ret < 0) |
9e79e062 | 357 | goto init_failed; |
ec9eab09 JS |
358 | } else { |
359 | ret = tilcdc_attach_external_device(ddev); | |
360 | if (ret) | |
361 | goto init_failed; | |
103cd8bc JS |
362 | } |
363 | ||
ec9eab09 JS |
364 | if (!priv->external_connector && |
365 | ((priv->num_encoders == 0) || (priv->num_connectors == 0))) { | |
923310ba | 366 | dev_err(dev, "no encoders/connectors found\n"); |
a132b5a5 | 367 | ret = -EPROBE_DEFER; |
9e79e062 | 368 | goto init_failed; |
103cd8bc JS |
369 | } |
370 | ||
923310ba | 371 | ret = drm_vblank_init(ddev, 1); |
16ea975e | 372 | if (ret < 0) { |
923310ba | 373 | dev_err(dev, "failed to initialize vblank\n"); |
9e79e062 | 374 | goto init_failed; |
16ea975e RC |
375 | } |
376 | ||
923310ba | 377 | ret = drm_irq_install(ddev, platform_get_irq(pdev, 0)); |
16ea975e | 378 | if (ret < 0) { |
923310ba | 379 | dev_err(dev, "failed to install IRQ handler\n"); |
9e79e062 | 380 | goto init_failed; |
16ea975e RC |
381 | } |
382 | ||
923310ba | 383 | drm_mode_config_reset(ddev); |
522a76f8 | 384 | |
923310ba JS |
385 | drm_kms_helper_poll_init(ddev); |
386 | ||
387 | ret = drm_dev_register(ddev, 0); | |
388 | if (ret) | |
9e79e062 | 389 | goto init_failed; |
16ea975e | 390 | |
45cf8756 NT |
391 | drm_fbdev_generic_setup(ddev, bpp); |
392 | ||
9e79e062 | 393 | priv->is_registered = true; |
16ea975e RC |
394 | return 0; |
395 | ||
9e79e062 JS |
396 | init_failed: |
397 | tilcdc_fini(ddev); | |
d0ec32ca | 398 | |
16ea975e RC |
399 | return ret; |
400 | } | |
401 | ||
e9f0d76f | 402 | static irqreturn_t tilcdc_irq(int irq, void *arg) |
16ea975e RC |
403 | { |
404 | struct drm_device *dev = arg; | |
405 | struct tilcdc_drm_private *priv = dev->dev_private; | |
406 | return tilcdc_crtc_irq(priv->crtc); | |
407 | } | |
408 | ||
514d1a1f | 409 | #if defined(CONFIG_DEBUG_FS) |
16ea975e RC |
410 | static const struct { |
411 | const char *name; | |
412 | uint8_t rev; | |
413 | uint8_t save; | |
414 | uint32_t reg; | |
32501459 | 415 | } registers[] = { |
16ea975e RC |
416 | #define REG(rev, save, reg) { #reg, rev, save, reg } |
417 | /* exists in revision 1: */ | |
418 | REG(1, false, LCDC_PID_REG), | |
419 | REG(1, true, LCDC_CTRL_REG), | |
420 | REG(1, false, LCDC_STAT_REG), | |
421 | REG(1, true, LCDC_RASTER_CTRL_REG), | |
422 | REG(1, true, LCDC_RASTER_TIMING_0_REG), | |
423 | REG(1, true, LCDC_RASTER_TIMING_1_REG), | |
424 | REG(1, true, LCDC_RASTER_TIMING_2_REG), | |
425 | REG(1, true, LCDC_DMA_CTRL_REG), | |
426 | REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG), | |
427 | REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG), | |
428 | REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG), | |
429 | REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG), | |
430 | /* new in revision 2: */ | |
431 | REG(2, false, LCDC_RAW_STAT_REG), | |
432 | REG(2, false, LCDC_MASKED_STAT_REG), | |
f3a99946 | 433 | REG(2, true, LCDC_INT_ENABLE_SET_REG), |
16ea975e RC |
434 | REG(2, false, LCDC_INT_ENABLE_CLR_REG), |
435 | REG(2, false, LCDC_END_OF_INT_IND_REG), | |
436 | REG(2, true, LCDC_CLK_ENABLE_REG), | |
16ea975e RC |
437 | #undef REG |
438 | }; | |
29ddd6e1 | 439 | |
16ea975e RC |
440 | #endif |
441 | ||
442 | #ifdef CONFIG_DEBUG_FS | |
443 | static int tilcdc_regs_show(struct seq_file *m, void *arg) | |
444 | { | |
445 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
446 | struct drm_device *dev = node->minor->dev; | |
447 | struct tilcdc_drm_private *priv = dev->dev_private; | |
448 | unsigned i; | |
449 | ||
450 | pm_runtime_get_sync(dev->dev); | |
451 | ||
452 | seq_printf(m, "revision: %d\n", priv->rev); | |
453 | ||
454 | for (i = 0; i < ARRAY_SIZE(registers); i++) | |
455 | if (priv->rev >= registers[i].rev) | |
456 | seq_printf(m, "%s:\t %08x\n", registers[i].name, | |
457 | tilcdc_read(dev, registers[i].reg)); | |
458 | ||
459 | pm_runtime_put_sync(dev->dev); | |
460 | ||
461 | return 0; | |
462 | } | |
463 | ||
464 | static int tilcdc_mm_show(struct seq_file *m, void *arg) | |
465 | { | |
466 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
467 | struct drm_device *dev = node->minor->dev; | |
b5c3714f DV |
468 | struct drm_printer p = drm_seq_file_printer(m); |
469 | drm_mm_print(&dev->vma_offset_manager->vm_addr_space_mm, &p); | |
470 | return 0; | |
16ea975e RC |
471 | } |
472 | ||
473 | static struct drm_info_list tilcdc_debugfs_list[] = { | |
474 | { "regs", tilcdc_regs_show, 0 }, | |
475 | { "mm", tilcdc_mm_show, 0 }, | |
16ea975e RC |
476 | }; |
477 | ||
478 | static int tilcdc_debugfs_init(struct drm_minor *minor) | |
479 | { | |
480 | struct drm_device *dev = minor->dev; | |
481 | struct tilcdc_module *mod; | |
482 | int ret; | |
483 | ||
484 | ret = drm_debugfs_create_files(tilcdc_debugfs_list, | |
485 | ARRAY_SIZE(tilcdc_debugfs_list), | |
486 | minor->debugfs_root, minor); | |
487 | ||
488 | list_for_each_entry(mod, &module_list, list) | |
489 | if (mod->funcs->debugfs_init) | |
490 | mod->funcs->debugfs_init(mod, minor); | |
491 | ||
492 | if (ret) { | |
493 | dev_err(dev->dev, "could not install tilcdc_debugfs_list\n"); | |
494 | return ret; | |
495 | } | |
496 | ||
497 | return ret; | |
498 | } | |
16ea975e RC |
499 | #endif |
500 | ||
d55f7e5d | 501 | DEFINE_DRM_GEM_CMA_FOPS(fops); |
16ea975e RC |
502 | |
503 | static struct drm_driver tilcdc_driver = { | |
5b38e747 | 504 | .driver_features = (DRIVER_GEM | DRIVER_MODESET | |
305198de | 505 | DRIVER_PRIME | DRIVER_ATOMIC), |
16ea975e | 506 | .irq_handler = tilcdc_irq, |
aa0438ce | 507 | .gem_free_object_unlocked = drm_gem_cma_free_object, |
fbf65b7e | 508 | .gem_print_info = drm_gem_cma_print_info, |
16ea975e RC |
509 | .gem_vm_ops = &drm_gem_cma_vm_ops, |
510 | .dumb_create = drm_gem_cma_dumb_create, | |
9c153905 JS |
511 | |
512 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
513 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
514 | .gem_prime_import = drm_gem_prime_import, | |
515 | .gem_prime_export = drm_gem_prime_export, | |
516 | .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table, | |
517 | .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table, | |
518 | .gem_prime_vmap = drm_gem_cma_prime_vmap, | |
519 | .gem_prime_vunmap = drm_gem_cma_prime_vunmap, | |
520 | .gem_prime_mmap = drm_gem_cma_prime_mmap, | |
16ea975e RC |
521 | #ifdef CONFIG_DEBUG_FS |
522 | .debugfs_init = tilcdc_debugfs_init, | |
16ea975e RC |
523 | #endif |
524 | .fops = &fops, | |
525 | .name = "tilcdc", | |
526 | .desc = "TI LCD Controller DRM", | |
527 | .date = "20121205", | |
528 | .major = 1, | |
529 | .minor = 0, | |
530 | }; | |
531 | ||
532 | /* | |
533 | * Power management: | |
534 | */ | |
535 | ||
536 | #ifdef CONFIG_PM_SLEEP | |
537 | static int tilcdc_pm_suspend(struct device *dev) | |
538 | { | |
539 | struct drm_device *ddev = dev_get_drvdata(dev); | |
4fdce78a | 540 | int ret = 0; |
16ea975e | 541 | |
4fdce78a | 542 | ret = drm_mode_config_helper_suspend(ddev); |
16ea975e | 543 | |
85fd27f8 DE |
544 | /* Select sleep pin state */ |
545 | pinctrl_pm_select_sleep_state(dev); | |
546 | ||
4fdce78a | 547 | return ret; |
16ea975e RC |
548 | } |
549 | ||
550 | static int tilcdc_pm_resume(struct device *dev) | |
551 | { | |
552 | struct drm_device *ddev = dev_get_drvdata(dev); | |
16ea975e | 553 | |
416a07fb DG |
554 | /* Select default pin state */ |
555 | pinctrl_pm_select_default_state(dev); | |
4fdce78a | 556 | return drm_mode_config_helper_resume(ddev); |
16ea975e RC |
557 | } |
558 | #endif | |
559 | ||
560 | static const struct dev_pm_ops tilcdc_pm_ops = { | |
561 | SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume) | |
562 | }; | |
563 | ||
564 | /* | |
565 | * Platform driver: | |
566 | */ | |
103cd8bc JS |
567 | static int tilcdc_bind(struct device *dev) |
568 | { | |
923310ba | 569 | return tilcdc_init(&tilcdc_driver, dev); |
103cd8bc JS |
570 | } |
571 | ||
572 | static void tilcdc_unbind(struct device *dev) | |
573 | { | |
20a98acb JS |
574 | struct drm_device *ddev = dev_get_drvdata(dev); |
575 | ||
576 | /* Check if a subcomponent has already triggered the unloading. */ | |
577 | if (!ddev->dev_private) | |
578 | return; | |
579 | ||
923310ba | 580 | tilcdc_fini(dev_get_drvdata(dev)); |
103cd8bc JS |
581 | } |
582 | ||
583 | static const struct component_master_ops tilcdc_comp_ops = { | |
584 | .bind = tilcdc_bind, | |
585 | .unbind = tilcdc_unbind, | |
586 | }; | |
587 | ||
16ea975e RC |
588 | static int tilcdc_pdev_probe(struct platform_device *pdev) |
589 | { | |
103cd8bc JS |
590 | struct component_match *match = NULL; |
591 | int ret; | |
592 | ||
16ea975e RC |
593 | /* bail out early if no DT data: */ |
594 | if (!pdev->dev.of_node) { | |
595 | dev_err(&pdev->dev, "device-tree data is missing\n"); | |
596 | return -ENXIO; | |
597 | } | |
598 | ||
103cd8bc JS |
599 | ret = tilcdc_get_external_components(&pdev->dev, &match); |
600 | if (ret < 0) | |
601 | return ret; | |
602 | else if (ret == 0) | |
923310ba | 603 | return tilcdc_init(&tilcdc_driver, &pdev->dev); |
103cd8bc JS |
604 | else |
605 | return component_master_add_with_match(&pdev->dev, | |
606 | &tilcdc_comp_ops, | |
607 | match); | |
16ea975e RC |
608 | } |
609 | ||
610 | static int tilcdc_pdev_remove(struct platform_device *pdev) | |
611 | { | |
20a98acb | 612 | int ret; |
103cd8bc | 613 | |
20a98acb JS |
614 | ret = tilcdc_get_external_components(&pdev->dev, NULL); |
615 | if (ret < 0) | |
616 | return ret; | |
617 | else if (ret == 0) | |
923310ba | 618 | tilcdc_fini(platform_get_drvdata(pdev)); |
20a98acb JS |
619 | else |
620 | component_master_del(&pdev->dev, &tilcdc_comp_ops); | |
16ea975e RC |
621 | |
622 | return 0; | |
623 | } | |
624 | ||
625 | static struct of_device_id tilcdc_of_match[] = { | |
626 | { .compatible = "ti,am33xx-tilcdc", }, | |
507b72b2 | 627 | { .compatible = "ti,da850-tilcdc", }, |
16ea975e RC |
628 | { }, |
629 | }; | |
630 | MODULE_DEVICE_TABLE(of, tilcdc_of_match); | |
631 | ||
632 | static struct platform_driver tilcdc_platform_driver = { | |
633 | .probe = tilcdc_pdev_probe, | |
634 | .remove = tilcdc_pdev_remove, | |
635 | .driver = { | |
16ea975e RC |
636 | .name = "tilcdc", |
637 | .pm = &tilcdc_pm_ops, | |
638 | .of_match_table = tilcdc_of_match, | |
639 | }, | |
640 | }; | |
641 | ||
642 | static int __init tilcdc_drm_init(void) | |
643 | { | |
644 | DBG("init"); | |
645 | tilcdc_tfp410_init(); | |
0d4bbaf9 | 646 | tilcdc_panel_init(); |
16ea975e RC |
647 | return platform_driver_register(&tilcdc_platform_driver); |
648 | } | |
649 | ||
650 | static void __exit tilcdc_drm_fini(void) | |
651 | { | |
652 | DBG("fini"); | |
16ea975e | 653 | platform_driver_unregister(&tilcdc_platform_driver); |
eb565a2b | 654 | tilcdc_panel_fini(); |
eb565a2b | 655 | tilcdc_tfp410_fini(); |
16ea975e RC |
656 | } |
657 | ||
2023d84d | 658 | module_init(tilcdc_drm_init); |
16ea975e RC |
659 | module_exit(tilcdc_drm_fini); |
660 | ||
661 | MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); | |
662 | MODULE_DESCRIPTION("TI LCD Controller DRM Driver"); | |
663 | MODULE_LICENSE("GPL"); |