Commit | Line | Data |
---|---|---|
16ea975e RC |
1 | /* |
2 | * Copyright (C) 2012 Texas Instruments | |
3 | * Author: Rob Clark <robdclark@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
ce2f2c3f | 18 | #include <drm/drm_atomic.h> |
305198de | 19 | #include <drm/drm_atomic_helper.h> |
ce2f2c3f SP |
20 | #include <drm/drm_crtc.h> |
21 | #include <drm/drm_flip_work.h> | |
22 | #include <drm/drm_plane_helper.h> | |
4e910c7a | 23 | #include <linux/workqueue.h> |
16ea975e RC |
24 | |
25 | #include "tilcdc_drv.h" | |
26 | #include "tilcdc_regs.h" | |
27 | ||
2b3a8cd7 TV |
28 | #define TILCDC_VBLANK_SAFETY_THRESHOLD_US 1000 |
29 | ||
16ea975e RC |
30 | struct tilcdc_crtc { |
31 | struct drm_crtc base; | |
32 | ||
47f571c6 | 33 | struct drm_plane primary; |
16ea975e | 34 | const struct tilcdc_panel_info *info; |
16ea975e | 35 | struct drm_pending_vblank_event *event; |
47bfd6c0 | 36 | bool enabled; |
16ea975e RC |
37 | wait_queue_head_t frame_done_wq; |
38 | bool frame_done; | |
2b3a8cd7 TV |
39 | spinlock_t irq_lock; |
40 | ||
642e5167 JS |
41 | unsigned int lcd_fck_rate; |
42 | ||
2b3a8cd7 | 43 | ktime_t last_vblank; |
16ea975e | 44 | |
2b2080d7 | 45 | struct drm_framebuffer *curr_fb; |
2b3a8cd7 | 46 | struct drm_framebuffer *next_fb; |
16ea975e RC |
47 | |
48 | /* for deferred fb unref's: */ | |
a464d618 | 49 | struct drm_flip_work unref_work; |
103cd8bc JS |
50 | |
51 | /* Only set if an external encoder is connected */ | |
52 | bool simulate_vesa_sync; | |
5895d08f JS |
53 | |
54 | int sync_lost_count; | |
55 | bool frame_intact; | |
16ea975e RC |
56 | }; |
57 | #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base) | |
58 | ||
a464d618 | 59 | static void unref_worker(struct drm_flip_work *work, void *val) |
16ea975e | 60 | { |
f7b45756 | 61 | struct tilcdc_crtc *tilcdc_crtc = |
a464d618 | 62 | container_of(work, struct tilcdc_crtc, unref_work); |
16ea975e | 63 | struct drm_device *dev = tilcdc_crtc->base.dev; |
16ea975e RC |
64 | |
65 | mutex_lock(&dev->mode_config.mutex); | |
a464d618 | 66 | drm_framebuffer_unreference(val); |
16ea975e RC |
67 | mutex_unlock(&dev->mode_config.mutex); |
68 | } | |
69 | ||
2b2080d7 | 70 | static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb) |
16ea975e RC |
71 | { |
72 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
73 | struct drm_device *dev = crtc->dev; | |
16ea975e RC |
74 | struct drm_gem_cma_object *gem; |
75 | unsigned int depth, bpp; | |
2b2080d7 | 76 | dma_addr_t start, end; |
7eb9f069 | 77 | u64 dma_base_and_ceiling; |
16ea975e RC |
78 | |
79 | drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp); | |
80 | gem = drm_fb_cma_get_gem_obj(fb, 0); | |
81 | ||
2b2080d7 TV |
82 | start = gem->paddr + fb->offsets[0] + |
83 | crtc->y * fb->pitches[0] + | |
84 | crtc->x * bpp / 8; | |
16ea975e | 85 | |
2b2080d7 | 86 | end = start + (crtc->mode.vdisplay * fb->pitches[0]); |
16ea975e | 87 | |
7eb9f069 JS |
88 | /* Write LCDC_DMA_FB_BASE_ADDR_0_REG and LCDC_DMA_FB_CEILING_ADDR_0_REG |
89 | * with a single insruction, if available. This should make it more | |
90 | * unlikely that LCDC would fetch the DMA addresses in the middle of | |
91 | * an update. | |
92 | */ | |
93 | dma_base_and_ceiling = (u64)(end - 1) << 32 | start; | |
94 | tilcdc_write64(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, dma_base_and_ceiling); | |
2b2080d7 TV |
95 | |
96 | if (tilcdc_crtc->curr_fb) | |
97 | drm_flip_work_queue(&tilcdc_crtc->unref_work, | |
98 | tilcdc_crtc->curr_fb); | |
99 | ||
100 | tilcdc_crtc->curr_fb = fb; | |
16ea975e RC |
101 | } |
102 | ||
afaf833d JS |
103 | static void tilcdc_crtc_enable_irqs(struct drm_device *dev) |
104 | { | |
105 | struct tilcdc_drm_private *priv = dev->dev_private; | |
106 | ||
107 | tilcdc_clear_irqstatus(dev, 0xffffffff); | |
108 | ||
109 | if (priv->rev == 1) { | |
110 | tilcdc_set(dev, LCDC_RASTER_CTRL_REG, | |
111 | LCDC_V1_UNDERFLOW_INT_ENA); | |
8d6c3f7d KB |
112 | tilcdc_set(dev, LCDC_DMA_CTRL_REG, |
113 | LCDC_V1_END_OF_FRAME_INT_ENA); | |
afaf833d JS |
114 | } else { |
115 | tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG, | |
116 | LCDC_V2_UNDERFLOW_INT_ENA | | |
117 | LCDC_V2_END_OF_FRAME0_INT_ENA | | |
118 | LCDC_FRAME_DONE | LCDC_SYNC_LOST); | |
119 | } | |
120 | } | |
121 | ||
122 | static void tilcdc_crtc_disable_irqs(struct drm_device *dev) | |
123 | { | |
124 | struct tilcdc_drm_private *priv = dev->dev_private; | |
125 | ||
126 | /* disable irqs that we might have enabled: */ | |
127 | if (priv->rev == 1) { | |
128 | tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, | |
129 | LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA); | |
130 | tilcdc_clear(dev, LCDC_DMA_CTRL_REG, | |
131 | LCDC_V1_END_OF_FRAME_INT_ENA); | |
132 | } else { | |
133 | tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, | |
134 | LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA | | |
135 | LCDC_V2_END_OF_FRAME0_INT_ENA | | |
136 | LCDC_FRAME_DONE | LCDC_SYNC_LOST); | |
137 | } | |
138 | } | |
139 | ||
2efec4f3 | 140 | static void reset(struct drm_crtc *crtc) |
16ea975e RC |
141 | { |
142 | struct drm_device *dev = crtc->dev; | |
143 | struct tilcdc_drm_private *priv = dev->dev_private; | |
144 | ||
2efec4f3 TV |
145 | if (priv->rev != 2) |
146 | return; | |
147 | ||
148 | tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET); | |
149 | usleep_range(250, 1000); | |
150 | tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET); | |
151 | } | |
152 | ||
47bfd6c0 | 153 | static void tilcdc_crtc_enable(struct drm_crtc *crtc) |
2efec4f3 TV |
154 | { |
155 | struct drm_device *dev = crtc->dev; | |
47bfd6c0 JS |
156 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); |
157 | ||
2e0965b0 JS |
158 | WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); |
159 | ||
47bfd6c0 JS |
160 | if (tilcdc_crtc->enabled) |
161 | return; | |
162 | ||
163 | pm_runtime_get_sync(dev->dev); | |
2efec4f3 TV |
164 | |
165 | reset(crtc); | |
16ea975e | 166 | |
afaf833d JS |
167 | tilcdc_crtc_enable_irqs(dev); |
168 | ||
2b2080d7 | 169 | tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE); |
16ea975e RC |
170 | tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_PALETTE_LOAD_MODE(DATA_ONLY)); |
171 | tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); | |
d85f850e JS |
172 | |
173 | drm_crtc_vblank_on(crtc); | |
47bfd6c0 JS |
174 | |
175 | tilcdc_crtc->enabled = true; | |
16ea975e RC |
176 | } |
177 | ||
47bfd6c0 | 178 | void tilcdc_crtc_disable(struct drm_crtc *crtc) |
16ea975e | 179 | { |
2d5be882 | 180 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); |
16ea975e | 181 | struct drm_device *dev = crtc->dev; |
2d5be882 | 182 | struct tilcdc_drm_private *priv = dev->dev_private; |
16ea975e | 183 | |
2e0965b0 JS |
184 | WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); |
185 | ||
47bfd6c0 JS |
186 | if (!tilcdc_crtc->enabled) |
187 | return; | |
188 | ||
2d5be882 | 189 | tilcdc_crtc->frame_done = false; |
16ea975e | 190 | tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); |
2d5be882 JS |
191 | |
192 | /* | |
193 | * if necessary wait for framedone irq which will still come | |
194 | * before putting things to sleep.. | |
195 | */ | |
196 | if (priv->rev == 2) { | |
197 | int ret = wait_event_timeout(tilcdc_crtc->frame_done_wq, | |
198 | tilcdc_crtc->frame_done, | |
437c7d94 | 199 | msecs_to_jiffies(500)); |
2d5be882 JS |
200 | if (ret == 0) |
201 | dev_err(dev->dev, "%s: timeout waiting for framedone\n", | |
202 | __func__); | |
203 | } | |
d85f850e JS |
204 | |
205 | drm_crtc_vblank_off(crtc); | |
afaf833d JS |
206 | |
207 | tilcdc_crtc_disable_irqs(dev); | |
47bfd6c0 JS |
208 | |
209 | pm_runtime_put_sync(dev->dev); | |
210 | ||
211 | if (tilcdc_crtc->next_fb) { | |
212 | drm_flip_work_queue(&tilcdc_crtc->unref_work, | |
213 | tilcdc_crtc->next_fb); | |
214 | tilcdc_crtc->next_fb = NULL; | |
215 | } | |
216 | ||
217 | if (tilcdc_crtc->curr_fb) { | |
218 | drm_flip_work_queue(&tilcdc_crtc->unref_work, | |
219 | tilcdc_crtc->curr_fb); | |
220 | tilcdc_crtc->curr_fb = NULL; | |
221 | } | |
222 | ||
223 | drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq); | |
224 | tilcdc_crtc->last_vblank = ktime_set(0, 0); | |
225 | ||
226 | tilcdc_crtc->enabled = false; | |
227 | } | |
228 | ||
229 | static bool tilcdc_crtc_is_on(struct drm_crtc *crtc) | |
230 | { | |
231 | return crtc->state && crtc->state->enable && crtc->state->active; | |
16ea975e RC |
232 | } |
233 | ||
234 | static void tilcdc_crtc_destroy(struct drm_crtc *crtc) | |
235 | { | |
236 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
4e910c7a | 237 | struct tilcdc_drm_private *priv = crtc->dev->dev_private; |
16ea975e | 238 | |
6c94c714 | 239 | drm_modeset_lock_crtc(crtc, NULL); |
47bfd6c0 | 240 | tilcdc_crtc_disable(crtc); |
6c94c714 | 241 | drm_modeset_unlock_crtc(crtc); |
16ea975e | 242 | |
4e910c7a | 243 | flush_workqueue(priv->wq); |
16ea975e | 244 | |
d66284fb | 245 | of_node_put(crtc->port); |
16ea975e | 246 | drm_crtc_cleanup(crtc); |
a464d618 | 247 | drm_flip_work_cleanup(&tilcdc_crtc->unref_work); |
16ea975e RC |
248 | } |
249 | ||
e0e344e6 | 250 | int tilcdc_crtc_update_fb(struct drm_crtc *crtc, |
16ea975e | 251 | struct drm_framebuffer *fb, |
e0e344e6 | 252 | struct drm_pending_vblank_event *event) |
16ea975e RC |
253 | { |
254 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
255 | struct drm_device *dev = crtc->dev; | |
2b2080d7 | 256 | unsigned long flags; |
6f206e9d | 257 | |
2e0965b0 JS |
258 | WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); |
259 | ||
16ea975e RC |
260 | if (tilcdc_crtc->event) { |
261 | dev_err(dev->dev, "already pending page flip!\n"); | |
262 | return -EBUSY; | |
263 | } | |
264 | ||
2b2080d7 TV |
265 | drm_framebuffer_reference(fb); |
266 | ||
f4510a27 | 267 | crtc->primary->fb = fb; |
65734a26 | 268 | |
2b3a8cd7 TV |
269 | spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags); |
270 | ||
0a1fe1b7 JS |
271 | if (crtc->hwmode.vrefresh && ktime_to_ns(tilcdc_crtc->last_vblank)) { |
272 | ktime_t next_vblank; | |
273 | s64 tdiff; | |
2b2080d7 | 274 | |
0a1fe1b7 JS |
275 | next_vblank = ktime_add_us(tilcdc_crtc->last_vblank, |
276 | 1000000 / crtc->hwmode.vrefresh); | |
2b3a8cd7 | 277 | |
0a1fe1b7 JS |
278 | tdiff = ktime_to_us(ktime_sub(next_vblank, ktime_get())); |
279 | ||
280 | if (tdiff < TILCDC_VBLANK_SAFETY_THRESHOLD_US) | |
281 | tilcdc_crtc->next_fb = fb; | |
282 | } | |
283 | ||
284 | if (tilcdc_crtc->next_fb != fb) | |
2b3a8cd7 | 285 | set_scanout(crtc, fb); |
2b2080d7 | 286 | |
2b2080d7 | 287 | tilcdc_crtc->event = event; |
2b3a8cd7 TV |
288 | |
289 | spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags); | |
16ea975e RC |
290 | |
291 | return 0; | |
292 | } | |
293 | ||
16ea975e RC |
294 | static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc, |
295 | const struct drm_display_mode *mode, | |
296 | struct drm_display_mode *adjusted_mode) | |
297 | { | |
103cd8bc JS |
298 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); |
299 | ||
300 | if (!tilcdc_crtc->simulate_vesa_sync) | |
301 | return true; | |
302 | ||
303 | /* | |
304 | * tilcdc does not generate VESA-compliant sync but aligns | |
305 | * VS on the second edge of HS instead of first edge. | |
306 | * We use adjusted_mode, to fixup sync by aligning both rising | |
307 | * edges and add HSKEW offset to fix the sync. | |
308 | */ | |
309 | adjusted_mode->hskew = mode->hsync_end - mode->hsync_start; | |
310 | adjusted_mode->flags |= DRM_MODE_FLAG_HSKEW; | |
311 | ||
312 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) { | |
313 | adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC; | |
314 | adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC; | |
315 | } else { | |
316 | adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC; | |
317 | adjusted_mode->flags &= ~DRM_MODE_FLAG_PHSYNC; | |
318 | } | |
319 | ||
16ea975e RC |
320 | return true; |
321 | } | |
322 | ||
642e5167 JS |
323 | static void tilcdc_crtc_set_clk(struct drm_crtc *crtc) |
324 | { | |
325 | struct drm_device *dev = crtc->dev; | |
326 | struct tilcdc_drm_private *priv = dev->dev_private; | |
327 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
328 | const unsigned clkdiv = 2; /* using a fixed divider of 2 */ | |
329 | int ret; | |
330 | ||
331 | /* mode.clock is in KHz, set_rate wants parameter in Hz */ | |
332 | ret = clk_set_rate(priv->clk, crtc->mode.clock * 1000 * clkdiv); | |
333 | if (ret < 0) { | |
334 | dev_err(dev->dev, "failed to set display clock rate to: %d\n", | |
335 | crtc->mode.clock); | |
336 | return; | |
337 | } | |
338 | ||
339 | tilcdc_crtc->lcd_fck_rate = clk_get_rate(priv->clk); | |
340 | ||
341 | DBG("lcd_clk=%u, mode clock=%d, div=%u", | |
342 | tilcdc_crtc->lcd_fck_rate, crtc->mode.clock, clkdiv); | |
343 | ||
344 | /* Configure the LCD clock divisor. */ | |
345 | tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) | | |
346 | LCDC_RASTER_MODE); | |
347 | ||
348 | if (priv->rev == 2) | |
349 | tilcdc_set(dev, LCDC_CLK_ENABLE_REG, | |
350 | LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN | | |
351 | LCDC_V2_CORE_CLK_EN); | |
352 | } | |
353 | ||
f6382f18 JS |
354 | static void tilcdc_crtc_mode_set_nofb(struct drm_crtc *crtc) |
355 | { | |
356 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
357 | struct drm_device *dev = crtc->dev; | |
358 | struct tilcdc_drm_private *priv = dev->dev_private; | |
359 | const struct tilcdc_panel_info *info = tilcdc_crtc->info; | |
360 | uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw; | |
361 | struct drm_display_mode *mode = &crtc->state->adjusted_mode; | |
362 | struct drm_framebuffer *fb = crtc->primary->state->fb; | |
363 | ||
2e0965b0 JS |
364 | WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); |
365 | ||
f6382f18 JS |
366 | if (WARN_ON(!info)) |
367 | return; | |
368 | ||
369 | if (WARN_ON(!fb)) | |
370 | return; | |
371 | ||
f6382f18 JS |
372 | /* Configure the Burst Size and fifo threshold of DMA: */ |
373 | reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770; | |
374 | switch (info->dma_burst_sz) { | |
375 | case 1: | |
376 | reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1); | |
377 | break; | |
378 | case 2: | |
379 | reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2); | |
380 | break; | |
381 | case 4: | |
382 | reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4); | |
383 | break; | |
384 | case 8: | |
385 | reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8); | |
386 | break; | |
387 | case 16: | |
388 | reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16); | |
389 | break; | |
390 | default: | |
391 | dev_err(dev->dev, "invalid burst size\n"); | |
392 | return; | |
393 | } | |
394 | reg |= (info->fifo_th << 8); | |
395 | tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg); | |
396 | ||
397 | /* Configure timings: */ | |
398 | hbp = mode->htotal - mode->hsync_end; | |
399 | hfp = mode->hsync_start - mode->hdisplay; | |
400 | hsw = mode->hsync_end - mode->hsync_start; | |
401 | vbp = mode->vtotal - mode->vsync_end; | |
402 | vfp = mode->vsync_start - mode->vdisplay; | |
403 | vsw = mode->vsync_end - mode->vsync_start; | |
404 | ||
405 | DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u", | |
406 | mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw); | |
407 | ||
408 | /* Set AC Bias Period and Number of Transitions per Interrupt: */ | |
409 | reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00; | |
410 | reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) | | |
411 | LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt); | |
412 | ||
413 | /* | |
414 | * subtract one from hfp, hbp, hsw because the hardware uses | |
415 | * a value of 0 as 1 | |
416 | */ | |
417 | if (priv->rev == 2) { | |
418 | /* clear bits we're going to set */ | |
419 | reg &= ~0x78000033; | |
420 | reg |= ((hfp-1) & 0x300) >> 8; | |
421 | reg |= ((hbp-1) & 0x300) >> 4; | |
422 | reg |= ((hsw-1) & 0x3c0) << 21; | |
423 | } | |
424 | tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg); | |
425 | ||
426 | reg = (((mode->hdisplay >> 4) - 1) << 4) | | |
427 | (((hbp-1) & 0xff) << 24) | | |
428 | (((hfp-1) & 0xff) << 16) | | |
429 | (((hsw-1) & 0x3f) << 10); | |
430 | if (priv->rev == 2) | |
431 | reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3; | |
432 | tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg); | |
433 | ||
434 | reg = ((mode->vdisplay - 1) & 0x3ff) | | |
435 | ((vbp & 0xff) << 24) | | |
436 | ((vfp & 0xff) << 16) | | |
437 | (((vsw-1) & 0x3f) << 10); | |
438 | tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg); | |
439 | ||
440 | /* | |
441 | * be sure to set Bit 10 for the V2 LCDC controller, | |
442 | * otherwise limited to 1024 pixels width, stopping | |
443 | * 1920x1080 being supported. | |
444 | */ | |
445 | if (priv->rev == 2) { | |
446 | if ((mode->vdisplay - 1) & 0x400) { | |
447 | tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, | |
448 | LCDC_LPP_B10); | |
449 | } else { | |
450 | tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, | |
451 | LCDC_LPP_B10); | |
452 | } | |
453 | } | |
454 | ||
455 | /* Configure display type: */ | |
456 | reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) & | |
457 | ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE | | |
458 | LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK | | |
459 | 0x000ff000 /* Palette Loading Delay bits */); | |
460 | reg |= LCDC_TFT_MODE; /* no monochrome/passive support */ | |
461 | if (info->tft_alt_mode) | |
462 | reg |= LCDC_TFT_ALT_ENABLE; | |
463 | if (priv->rev == 2) { | |
464 | unsigned int depth, bpp; | |
465 | ||
466 | drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp); | |
467 | switch (bpp) { | |
468 | case 16: | |
469 | break; | |
470 | case 32: | |
471 | reg |= LCDC_V2_TFT_24BPP_UNPACK; | |
472 | /* fallthrough */ | |
473 | case 24: | |
474 | reg |= LCDC_V2_TFT_24BPP_MODE; | |
475 | break; | |
476 | default: | |
477 | dev_err(dev->dev, "invalid pixel format\n"); | |
478 | return; | |
479 | } | |
480 | } | |
481 | reg |= info->fdd < 12; | |
482 | tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg); | |
483 | ||
484 | if (info->invert_pxl_clk) | |
485 | tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK); | |
486 | else | |
487 | tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK); | |
488 | ||
489 | if (info->sync_ctrl) | |
490 | tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); | |
491 | else | |
492 | tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); | |
493 | ||
494 | if (info->sync_edge) | |
495 | tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE); | |
496 | else | |
497 | tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE); | |
498 | ||
499 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
500 | tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC); | |
501 | else | |
502 | tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC); | |
503 | ||
504 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
505 | tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC); | |
506 | else | |
507 | tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC); | |
508 | ||
509 | if (info->raster_order) | |
510 | tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER); | |
511 | else | |
512 | tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER); | |
513 | ||
514 | drm_framebuffer_reference(fb); | |
515 | ||
516 | set_scanout(crtc, fb); | |
517 | ||
642e5167 | 518 | tilcdc_crtc_set_clk(crtc); |
f6382f18 | 519 | |
f6382f18 JS |
520 | crtc->hwmode = crtc->state->adjusted_mode; |
521 | } | |
522 | ||
db380c58 JS |
523 | static int tilcdc_crtc_atomic_check(struct drm_crtc *crtc, |
524 | struct drm_crtc_state *state) | |
525 | { | |
526 | struct drm_display_mode *mode = &state->mode; | |
527 | int ret; | |
528 | ||
529 | /* If we are not active we don't care */ | |
530 | if (!state->active) | |
531 | return 0; | |
532 | ||
533 | if (state->state->planes[0].ptr != crtc->primary || | |
534 | state->state->planes[0].state == NULL || | |
535 | state->state->planes[0].state->crtc != crtc) { | |
536 | dev_dbg(crtc->dev->dev, "CRTC primary plane must be present"); | |
537 | return -EINVAL; | |
538 | } | |
539 | ||
540 | ret = tilcdc_crtc_mode_valid(crtc, mode); | |
541 | if (ret) { | |
542 | dev_dbg(crtc->dev->dev, "Mode \"%s\" not valid", mode->name); | |
543 | return -EINVAL; | |
544 | } | |
545 | ||
546 | return 0; | |
547 | } | |
548 | ||
16ea975e | 549 | static const struct drm_crtc_funcs tilcdc_crtc_funcs = { |
305198de JS |
550 | .destroy = tilcdc_crtc_destroy, |
551 | .set_config = drm_atomic_helper_set_config, | |
552 | .page_flip = drm_atomic_helper_page_flip, | |
553 | .reset = drm_atomic_helper_crtc_reset, | |
554 | .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, | |
555 | .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, | |
16ea975e RC |
556 | }; |
557 | ||
558 | static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = { | |
16ea975e | 559 | .mode_fixup = tilcdc_crtc_mode_fixup, |
305198de JS |
560 | .enable = tilcdc_crtc_enable, |
561 | .disable = tilcdc_crtc_disable, | |
db380c58 | 562 | .atomic_check = tilcdc_crtc_atomic_check, |
f6382f18 | 563 | .mode_set_nofb = tilcdc_crtc_mode_set_nofb, |
16ea975e RC |
564 | }; |
565 | ||
566 | int tilcdc_crtc_max_width(struct drm_crtc *crtc) | |
567 | { | |
568 | struct drm_device *dev = crtc->dev; | |
569 | struct tilcdc_drm_private *priv = dev->dev_private; | |
570 | int max_width = 0; | |
571 | ||
572 | if (priv->rev == 1) | |
573 | max_width = 1024; | |
574 | else if (priv->rev == 2) | |
575 | max_width = 2048; | |
576 | ||
577 | return max_width; | |
578 | } | |
579 | ||
580 | int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode) | |
581 | { | |
582 | struct tilcdc_drm_private *priv = crtc->dev->dev_private; | |
583 | unsigned int bandwidth; | |
e1c5d0a8 | 584 | uint32_t hbp, hfp, hsw, vbp, vfp, vsw; |
16ea975e | 585 | |
e1c5d0a8 DE |
586 | /* |
587 | * check to see if the width is within the range that | |
588 | * the LCD Controller physically supports | |
589 | */ | |
16ea975e RC |
590 | if (mode->hdisplay > tilcdc_crtc_max_width(crtc)) |
591 | return MODE_VIRTUAL_X; | |
592 | ||
593 | /* width must be multiple of 16 */ | |
594 | if (mode->hdisplay & 0xf) | |
595 | return MODE_VIRTUAL_X; | |
596 | ||
597 | if (mode->vdisplay > 2048) | |
598 | return MODE_VIRTUAL_Y; | |
599 | ||
e1c5d0a8 DE |
600 | DBG("Processing mode %dx%d@%d with pixel clock %d", |
601 | mode->hdisplay, mode->vdisplay, | |
602 | drm_mode_vrefresh(mode), mode->clock); | |
603 | ||
604 | hbp = mode->htotal - mode->hsync_end; | |
605 | hfp = mode->hsync_start - mode->hdisplay; | |
606 | hsw = mode->hsync_end - mode->hsync_start; | |
607 | vbp = mode->vtotal - mode->vsync_end; | |
608 | vfp = mode->vsync_start - mode->vdisplay; | |
609 | vsw = mode->vsync_end - mode->vsync_start; | |
610 | ||
611 | if ((hbp-1) & ~0x3ff) { | |
612 | DBG("Pruning mode: Horizontal Back Porch out of range"); | |
613 | return MODE_HBLANK_WIDE; | |
614 | } | |
615 | ||
616 | if ((hfp-1) & ~0x3ff) { | |
617 | DBG("Pruning mode: Horizontal Front Porch out of range"); | |
618 | return MODE_HBLANK_WIDE; | |
619 | } | |
620 | ||
621 | if ((hsw-1) & ~0x3ff) { | |
622 | DBG("Pruning mode: Horizontal Sync Width out of range"); | |
623 | return MODE_HSYNC_WIDE; | |
624 | } | |
625 | ||
626 | if (vbp & ~0xff) { | |
627 | DBG("Pruning mode: Vertical Back Porch out of range"); | |
628 | return MODE_VBLANK_WIDE; | |
629 | } | |
630 | ||
631 | if (vfp & ~0xff) { | |
632 | DBG("Pruning mode: Vertical Front Porch out of range"); | |
633 | return MODE_VBLANK_WIDE; | |
634 | } | |
635 | ||
636 | if ((vsw-1) & ~0x3f) { | |
637 | DBG("Pruning mode: Vertical Sync Width out of range"); | |
638 | return MODE_VSYNC_WIDE; | |
639 | } | |
640 | ||
4e564346 DE |
641 | /* |
642 | * some devices have a maximum allowed pixel clock | |
643 | * configured from the DT | |
644 | */ | |
645 | if (mode->clock > priv->max_pixelclock) { | |
f7b45756 | 646 | DBG("Pruning mode: pixel clock too high"); |
4e564346 DE |
647 | return MODE_CLOCK_HIGH; |
648 | } | |
649 | ||
650 | /* | |
651 | * some devices further limit the max horizontal resolution | |
652 | * configured from the DT | |
653 | */ | |
654 | if (mode->hdisplay > priv->max_width) | |
655 | return MODE_BAD_WIDTH; | |
656 | ||
16ea975e | 657 | /* filter out modes that would require too much memory bandwidth: */ |
4e564346 DE |
658 | bandwidth = mode->hdisplay * mode->vdisplay * |
659 | drm_mode_vrefresh(mode); | |
660 | if (bandwidth > priv->max_bandwidth) { | |
f7b45756 | 661 | DBG("Pruning mode: exceeds defined bandwidth limit"); |
16ea975e | 662 | return MODE_BAD; |
4e564346 | 663 | } |
16ea975e RC |
664 | |
665 | return MODE_OK; | |
666 | } | |
667 | ||
668 | void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc, | |
669 | const struct tilcdc_panel_info *info) | |
670 | { | |
671 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
672 | tilcdc_crtc->info = info; | |
673 | } | |
674 | ||
103cd8bc JS |
675 | void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc, |
676 | bool simulate_vesa_sync) | |
677 | { | |
678 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
679 | ||
680 | tilcdc_crtc->simulate_vesa_sync = simulate_vesa_sync; | |
681 | } | |
682 | ||
16ea975e RC |
683 | void tilcdc_crtc_update_clk(struct drm_crtc *crtc) |
684 | { | |
16ea975e RC |
685 | struct drm_device *dev = crtc->dev; |
686 | struct tilcdc_drm_private *priv = dev->dev_private; | |
642e5167 | 687 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); |
16ea975e | 688 | |
642e5167 JS |
689 | drm_modeset_lock_crtc(crtc, NULL); |
690 | if (tilcdc_crtc->lcd_fck_rate != clk_get_rate(priv->clk)) { | |
691 | if (tilcdc_crtc_is_on(crtc)) { | |
692 | pm_runtime_get_sync(dev->dev); | |
693 | tilcdc_crtc_disable(crtc); | |
16ea975e | 694 | |
642e5167 | 695 | tilcdc_crtc_set_clk(crtc); |
16ea975e | 696 | |
642e5167 JS |
697 | tilcdc_crtc_enable(crtc); |
698 | pm_runtime_put_sync(dev->dev); | |
699 | } | |
16ea975e | 700 | } |
642e5167 | 701 | drm_modeset_unlock_crtc(crtc); |
16ea975e RC |
702 | } |
703 | ||
5895d08f JS |
704 | #define SYNC_LOST_COUNT_LIMIT 50 |
705 | ||
16ea975e RC |
706 | irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc) |
707 | { | |
708 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
709 | struct drm_device *dev = crtc->dev; | |
710 | struct tilcdc_drm_private *priv = dev->dev_private; | |
317aae73 | 711 | uint32_t stat; |
16ea975e | 712 | |
317aae73 TV |
713 | stat = tilcdc_read_irqstatus(dev); |
714 | tilcdc_clear_irqstatus(dev, stat); | |
715 | ||
2b2080d7 | 716 | if (stat & LCDC_END_OF_FRAME0) { |
16ea975e | 717 | unsigned long flags; |
2b3a8cd7 TV |
718 | bool skip_event = false; |
719 | ktime_t now; | |
720 | ||
721 | now = ktime_get(); | |
16ea975e | 722 | |
2b2080d7 | 723 | drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq); |
16ea975e | 724 | |
2b3a8cd7 TV |
725 | spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags); |
726 | ||
727 | tilcdc_crtc->last_vblank = now; | |
728 | ||
729 | if (tilcdc_crtc->next_fb) { | |
730 | set_scanout(crtc, tilcdc_crtc->next_fb); | |
731 | tilcdc_crtc->next_fb = NULL; | |
732 | skip_event = true; | |
733 | } | |
734 | ||
735 | spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags); | |
736 | ||
099ede83 | 737 | drm_crtc_handle_vblank(crtc); |
16ea975e | 738 | |
2b3a8cd7 TV |
739 | if (!skip_event) { |
740 | struct drm_pending_vblank_event *event; | |
16ea975e | 741 | |
2b3a8cd7 TV |
742 | spin_lock_irqsave(&dev->event_lock, flags); |
743 | ||
744 | event = tilcdc_crtc->event; | |
2b2080d7 | 745 | tilcdc_crtc->event = NULL; |
2b3a8cd7 | 746 | if (event) |
dfebc152 | 747 | drm_crtc_send_vblank_event(crtc, event); |
2b2080d7 | 748 | |
2b3a8cd7 TV |
749 | spin_unlock_irqrestore(&dev->event_lock, flags); |
750 | } | |
5895d08f JS |
751 | |
752 | if (tilcdc_crtc->frame_intact) | |
753 | tilcdc_crtc->sync_lost_count = 0; | |
754 | else | |
755 | tilcdc_crtc->frame_intact = true; | |
16ea975e RC |
756 | } |
757 | ||
14944113 JS |
758 | if (stat & LCDC_FIFO_UNDERFLOW) |
759 | dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underfow", | |
760 | __func__, stat); | |
761 | ||
762 | /* For revision 2 only */ | |
16ea975e RC |
763 | if (priv->rev == 2) { |
764 | if (stat & LCDC_FRAME_DONE) { | |
765 | tilcdc_crtc->frame_done = true; | |
766 | wake_up(&tilcdc_crtc->frame_done_wq); | |
767 | } | |
16ea975e | 768 | |
1abcdac8 JS |
769 | if (stat & LCDC_SYNC_LOST) { |
770 | dev_err_ratelimited(dev->dev, "%s(0x%08x): Sync lost", | |
771 | __func__, stat); | |
772 | tilcdc_crtc->frame_intact = false; | |
773 | if (tilcdc_crtc->sync_lost_count++ > | |
774 | SYNC_LOST_COUNT_LIMIT) { | |
775 | dev_err(dev->dev, "%s(0x%08x): Sync lost flood detected, disabling the interrupt", __func__, stat); | |
776 | tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, | |
777 | LCDC_SYNC_LOST); | |
778 | } | |
5895d08f | 779 | } |
c0c2baaa | 780 | |
14944113 JS |
781 | /* Indicate to LCDC that the interrupt service routine has |
782 | * completed, see 13.3.6.1.6 in AM335x TRM. | |
783 | */ | |
784 | tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0); | |
785 | } | |
c0c2baaa | 786 | |
16ea975e RC |
787 | return IRQ_HANDLED; |
788 | } | |
789 | ||
16ea975e RC |
790 | struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev) |
791 | { | |
d66284fb | 792 | struct tilcdc_drm_private *priv = dev->dev_private; |
16ea975e RC |
793 | struct tilcdc_crtc *tilcdc_crtc; |
794 | struct drm_crtc *crtc; | |
795 | int ret; | |
796 | ||
d0ec32ca | 797 | tilcdc_crtc = devm_kzalloc(dev->dev, sizeof(*tilcdc_crtc), GFP_KERNEL); |
16ea975e RC |
798 | if (!tilcdc_crtc) { |
799 | dev_err(dev->dev, "allocation failed\n"); | |
800 | return NULL; | |
801 | } | |
802 | ||
803 | crtc = &tilcdc_crtc->base; | |
804 | ||
47f571c6 JS |
805 | ret = tilcdc_plane_init(dev, &tilcdc_crtc->primary); |
806 | if (ret < 0) | |
807 | goto fail; | |
808 | ||
16ea975e RC |
809 | init_waitqueue_head(&tilcdc_crtc->frame_done_wq); |
810 | ||
d7f8db53 | 811 | drm_flip_work_init(&tilcdc_crtc->unref_work, |
a464d618 | 812 | "unref", unref_worker); |
16ea975e | 813 | |
2b3a8cd7 TV |
814 | spin_lock_init(&tilcdc_crtc->irq_lock); |
815 | ||
47f571c6 JS |
816 | ret = drm_crtc_init_with_planes(dev, crtc, |
817 | &tilcdc_crtc->primary, | |
818 | NULL, | |
819 | &tilcdc_crtc_funcs, | |
820 | "tilcdc crtc"); | |
16ea975e RC |
821 | if (ret < 0) |
822 | goto fail; | |
823 | ||
824 | drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs); | |
825 | ||
d66284fb JS |
826 | if (priv->is_componentized) { |
827 | struct device_node *ports = | |
828 | of_get_child_by_name(dev->dev->of_node, "ports"); | |
829 | ||
830 | if (ports) { | |
831 | crtc->port = of_get_child_by_name(ports, "port"); | |
832 | of_node_put(ports); | |
833 | } else { | |
834 | crtc->port = | |
835 | of_get_child_by_name(dev->dev->of_node, "port"); | |
836 | } | |
837 | if (!crtc->port) { /* This should never happen */ | |
838 | dev_err(dev->dev, "Port node not found in %s\n", | |
839 | dev->dev->of_node->full_name); | |
840 | goto fail; | |
841 | } | |
842 | } | |
843 | ||
16ea975e RC |
844 | return crtc; |
845 | ||
846 | fail: | |
847 | tilcdc_crtc_destroy(crtc); | |
848 | return NULL; | |
849 | } |