[linux-2.6-block.git] / drivers / gpu / drm / tidss / tidss_kms.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
 */

#include <linux/dma-fence.h>

#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_bridge.h>
#include <drm/drm_gem_framebuffer_helper.h>
#include <drm/drm_of.h>
#include <drm/drm_panel.h>
#include <drm/drm_vblank.h>

#include "tidss_crtc.h"
#include "tidss_dispc.h"
#include "tidss_drv.h"
#include "tidss_encoder.h"
#include "tidss_kms.h"
#include "tidss_plane.h"

static void tidss_atomic_commit_tail(struct drm_atomic_state *old_state)
{
	struct drm_device *ddev = old_state->dev;
	struct tidss_device *tidss = to_tidss(ddev);
	bool fence_cookie = dma_fence_begin_signalling();

	dev_dbg(ddev->dev, "%s\n", __func__);

	tidss_runtime_get(tidss);

	drm_atomic_helper_commit_modeset_disables(ddev, old_state);
	drm_atomic_helper_commit_planes(ddev, old_state, 0);
	drm_atomic_helper_commit_modeset_enables(ddev, old_state);

	drm_atomic_helper_commit_hw_done(old_state);
	dma_fence_end_signalling(fence_cookie);
	drm_atomic_helper_wait_for_flip_done(ddev, old_state);

	drm_atomic_helper_cleanup_planes(ddev, old_state);

	tidss_runtime_put(tidss);
}

static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
	.atomic_commit_tail = tidss_atomic_commit_tail,
};

static int tidss_atomic_check(struct drm_device *ddev,
			      struct drm_atomic_state *state)
{
	struct drm_plane_state *opstate;
	struct drm_plane_state *npstate;
	struct drm_plane *plane;
	struct drm_crtc_state *cstate;
	struct drm_crtc *crtc;
	int ret, i;

	ret = drm_atomic_helper_check(ddev, state);
	if (ret)
		return ret;

	/*
	 * Add all active planes on a CRTC to the atomic state, if
	 * x/y/z position or activity of any plane on that CRTC
	 * changes. This is needed for updating the plane positions in
	 * tidss_crtc_position_planes() which is called from
	 * crtc_atomic_enable() and crtc_atomic_flush(). We have an
	 * extra flag to mark x,y-position changes and together
	 * with zpos_changed the condition recognizes all the above
	 * cases.
	 */
	for_each_oldnew_plane_in_state(state, plane, opstate, npstate, i) {
		if (!npstate->crtc || !npstate->visible)
			continue;

		if (!opstate->crtc || opstate->crtc_x != npstate->crtc_x ||
		    opstate->crtc_y != npstate->crtc_y) {
			cstate = drm_atomic_get_crtc_state(state,
							   npstate->crtc);
			if (IS_ERR(cstate))
				return PTR_ERR(cstate);
			to_tidss_crtc_state(cstate)->plane_pos_changed = true;
		}
	}

	for_each_new_crtc_in_state(state, crtc, cstate, i) {
		if (to_tidss_crtc_state(cstate)->plane_pos_changed ||
		    cstate->zpos_changed) {
			ret = drm_atomic_add_affected_planes(state, crtc);
			if (ret)
				return ret;
		}
	}

	return 0;
}

static const struct drm_mode_config_funcs mode_config_funcs = {
	.fb_create = drm_gem_fb_create,
	.atomic_check = tidss_atomic_check,
	.atomic_commit = drm_atomic_helper_commit,
};

static int tidss_dispc_modeset_init(struct tidss_device *tidss)
{
	struct device *dev = tidss->dev;
	unsigned int fourccs_len;
	const u32 *fourccs = dispc_plane_formats(tidss->dispc, &fourccs_len);
	unsigned int i;

	struct pipe {
		u32 hw_videoport;
		struct drm_bridge *bridge;
		u32 enc_type;
	};

	const struct dispc_features *feat = tidss->feat;
	u32 max_vps = feat->num_vps;
	u32 max_planes = feat->num_planes;

	struct pipe pipes[TIDSS_MAX_PORTS];
	u32 num_pipes = 0;
	u32 crtc_mask;

	/* first find all the connected panels & bridges */

	for (i = 0; i < max_vps; i++) {
		struct drm_panel *panel;
		struct drm_bridge *bridge;
		u32 enc_type = DRM_MODE_ENCODER_NONE;
		int ret;

		ret = drm_of_find_panel_or_bridge(dev->of_node, i, 0,
						  &panel, &bridge);
		if (ret == -ENODEV) {
			dev_dbg(dev, "no panel/bridge for port %d\n", i);
			continue;
		} else if (ret) {
			dev_dbg(dev, "port %d probe returned %d\n", i, ret);
			return ret;
		}

		if (panel) {
			u32 conn_type;

			dev_dbg(dev, "Setting up panel for port %d\n", i);

			switch (feat->vp_bus_type[i]) {
			case DISPC_VP_OLDI:
				enc_type = DRM_MODE_ENCODER_LVDS;
				conn_type = DRM_MODE_CONNECTOR_LVDS;
				break;
			case DISPC_VP_DPI:
				enc_type = DRM_MODE_ENCODER_DPI;
				conn_type = DRM_MODE_CONNECTOR_DPI;
				break;
			default:
				WARN_ON(1);
				return -EINVAL;
			}

			if (panel->connector_type != conn_type) {
				dev_err(dev,
					"%s: Panel %s has incompatible connector type for vp%d (%d != %d)\n",
					 __func__, dev_name(panel->dev), i,
					 panel->connector_type, conn_type);
				return -EINVAL;
			}

			bridge = devm_drm_panel_bridge_add(dev, panel);
			if (IS_ERR(bridge)) {
				dev_err(dev,
					"failed to set up panel bridge for port %d\n",
					i);
				return PTR_ERR(bridge);
			}
		}

		pipes[num_pipes].hw_videoport = i;
		pipes[num_pipes].bridge = bridge;
		pipes[num_pipes].enc_type = enc_type;
		num_pipes++;
	}

	/* all planes can be on any crtc */
	crtc_mask = (1 << num_pipes) - 1;

	/* then create a plane, a crtc and an encoder for each panel/bridge */

	for (i = 0; i < num_pipes; ++i) {
		struct tidss_plane *tplane;
		struct tidss_crtc *tcrtc;
		struct drm_encoder *enc;
		u32 hw_plane_id = feat->vid_order[tidss->num_planes];
		int ret;

		tplane = tidss_plane_create(tidss, hw_plane_id,
					    DRM_PLANE_TYPE_PRIMARY, crtc_mask,
					    fourccs, fourccs_len);
		if (IS_ERR(tplane)) {
			dev_err(tidss->dev, "plane create failed\n");
			return PTR_ERR(tplane);
		}

		tidss->planes[tidss->num_planes++] = &tplane->plane;

		tcrtc = tidss_crtc_create(tidss, pipes[i].hw_videoport,
					  &tplane->plane);
		if (IS_ERR(tcrtc)) {
			dev_err(tidss->dev, "crtc create failed\n");
			return PTR_ERR(tcrtc);
		}

		tidss->crtcs[tidss->num_crtcs++] = &tcrtc->crtc;

		enc = tidss_encoder_create(tidss, pipes[i].enc_type,
					   1 << tcrtc->crtc.index);
		if (IS_ERR(enc)) {
			dev_err(tidss->dev, "encoder create failed\n");
			return PTR_ERR(enc);
		}

		ret = drm_bridge_attach(enc, pipes[i].bridge, NULL, 0);
		if (ret)
			return ret;
	}

	/* create overlay planes of the leftover planes */

	while (tidss->num_planes < max_planes) {
		struct tidss_plane *tplane;
		u32 hw_plane_id = feat->vid_order[tidss->num_planes];

		tplane = tidss_plane_create(tidss, hw_plane_id,
					    DRM_PLANE_TYPE_OVERLAY, crtc_mask,
					    fourccs, fourccs_len);

		if (IS_ERR(tplane)) {
			dev_err(tidss->dev, "plane create failed\n");
			return PTR_ERR(tplane);
		}

		tidss->planes[tidss->num_planes++] = &tplane->plane;
	}

	return 0;
}

int tidss_modeset_init(struct tidss_device *tidss)
{
	struct drm_device *ddev = &tidss->ddev;
	int ret;

	dev_dbg(tidss->dev, "%s\n", __func__);

	ret = drmm_mode_config_init(ddev);
	if (ret)
		return ret;

	ddev->mode_config.min_width = 8;
	ddev->mode_config.min_height = 8;
	ddev->mode_config.max_width = 8096;
	ddev->mode_config.max_height = 8096;
	ddev->mode_config.normalize_zpos = true;
	ddev->mode_config.funcs = &mode_config_funcs;
	ddev->mode_config.helper_private = &mode_config_helper_funcs;

	ret = tidss_dispc_modeset_init(tidss);
	if (ret)
		return ret;

	ret = drm_vblank_init(ddev, tidss->num_crtcs);
	if (ret)
		return ret;

	drm_mode_config_reset(ddev);

	dev_dbg(tidss->dev, "%s done\n", __func__);

	return 0;
}
Commit	Line	Data
32a1795f JS	1	// SPDX-License-Identifier: GPL-2.0
32a1795f JS	2	/*
9410113f	3	* Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
32a1795f JS	4	* Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
	5	*/
	6
4d56a4f0 DV	7	#include <linux/dma-fence.h>
4d56a4f0 DV	8
32a1795f JS	9	#include <drm/drm_atomic.h>
	10	#include <drm/drm_atomic_helper.h>
	11	#include <drm/drm_bridge.h>
32a1795f JS	12	#include <drm/drm_gem_framebuffer_helper.h>
	13	#include <drm/drm_of.h>
	14	#include <drm/drm_panel.h>
	15	#include <drm/drm_vblank.h>
	16
	17	#include "tidss_crtc.h"
	18	#include "tidss_dispc.h"
	19	#include "tidss_drv.h"
	20	#include "tidss_encoder.h"
	21	#include "tidss_kms.h"
	22	#include "tidss_plane.h"
	23
	24	static void tidss_atomic_commit_tail(struct drm_atomic_state *old_state)
	25	{
	26	struct drm_device *ddev = old_state->dev;
02bb1317	27	struct tidss_device *tidss = to_tidss(ddev);
4d56a4f0	28	bool fence_cookie = dma_fence_begin_signalling();
32a1795f JS	29
	30	dev_dbg(ddev->dev, "%s\n", __func__);
	31
	32	tidss_runtime_get(tidss);
	33
	34	drm_atomic_helper_commit_modeset_disables(ddev, old_state);
	35	drm_atomic_helper_commit_planes(ddev, old_state, 0);
	36	drm_atomic_helper_commit_modeset_enables(ddev, old_state);
	37
	38	drm_atomic_helper_commit_hw_done(old_state);
4d56a4f0	39	dma_fence_end_signalling(fence_cookie);
32a1795f JS	40	drm_atomic_helper_wait_for_flip_done(ddev, old_state);
	41
	42	drm_atomic_helper_cleanup_planes(ddev, old_state);
	43
	44	tidss_runtime_put(tidss);
	45	}
	46
	47	static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
	48	.atomic_commit_tail = tidss_atomic_commit_tail,
	49	};
	50
b33b5474 JS	51	static int tidss_atomic_check(struct drm_device *ddev,
	52	struct drm_atomic_state *state)
	53	{
	54	struct drm_plane_state *opstate;
	55	struct drm_plane_state *npstate;
	56	struct drm_plane *plane;
	57	struct drm_crtc_state *cstate;
	58	struct drm_crtc *crtc;
	59	int ret, i;
	60
	61	ret = drm_atomic_helper_check(ddev, state);
	62	if (ret)
	63	return ret;
	64
	65	/*
	66	* Add all active planes on a CRTC to the atomic state, if
	67	* x/y/z position or activity of any plane on that CRTC
	68	* changes. This is needed for updating the plane positions in
	69	* tidss_crtc_position_planes() which is called from
	70	* crtc_atomic_enable() and crtc_atomic_flush(). We have an
51865139	71	* extra flag to mark x,y-position changes and together
b33b5474 JS	72	* with zpos_changed the condition recognizes all the above
	73	* cases.
	74	*/
	75	for_each_oldnew_plane_in_state(state, plane, opstate, npstate, i) {
	76	if (!npstate->crtc \|\| !npstate->visible)
	77	continue;
	78
	79	if (!opstate->crtc \|\| opstate->crtc_x != npstate->crtc_x \|\|
	80	opstate->crtc_y != npstate->crtc_y) {
	81	cstate = drm_atomic_get_crtc_state(state,
	82	npstate->crtc);
	83	if (IS_ERR(cstate))
	84	return PTR_ERR(cstate);
	85	to_tidss_crtc_state(cstate)->plane_pos_changed = true;
	86	}
	87	}
	88
	89	for_each_new_crtc_in_state(state, crtc, cstate, i) {
	90	if (to_tidss_crtc_state(cstate)->plane_pos_changed \|\|
	91	cstate->zpos_changed) {
	92	ret = drm_atomic_add_affected_planes(state, crtc);
	93	if (ret)
	94	return ret;
	95	}
	96	}
	97
	98	return 0;
	99	}
	100
32a1795f JS	101	static const struct drm_mode_config_funcs mode_config_funcs = {
32a1795f JS	102	.fb_create = drm_gem_fb_create,
b33b5474	103	.atomic_check = tidss_atomic_check,
32a1795f JS	104	.atomic_commit = drm_atomic_helper_commit,
	105	};
	106
	107	static int tidss_dispc_modeset_init(struct tidss_device *tidss)
	108	{
	109	struct device *dev = tidss->dev;
	110	unsigned int fourccs_len;
	111	const u32 *fourccs = dispc_plane_formats(tidss->dispc, &fourccs_len);
	112	unsigned int i;
	113
	114	struct pipe {
	115	u32 hw_videoport;
	116	struct drm_bridge *bridge;
	117	u32 enc_type;
	118	};
	119
	120	const struct dispc_features *feat = tidss->feat;
	121	u32 max_vps = feat->num_vps;
	122	u32 max_planes = feat->num_planes;
	123
	124	struct pipe pipes[TIDSS_MAX_PORTS];
	125	u32 num_pipes = 0;
	126	u32 crtc_mask;
	127
	128	/* first find all the connected panels & bridges */
	129
	130	for (i = 0; i < max_vps; i++) {
	131	struct drm_panel *panel;
	132	struct drm_bridge *bridge;
	133	u32 enc_type = DRM_MODE_ENCODER_NONE;
	134	int ret;
	135
	136	ret = drm_of_find_panel_or_bridge(dev->of_node, i, 0,
	137	&panel, &bridge);
	138	if (ret == -ENODEV) {
	139	dev_dbg(dev, "no panel/bridge for port %d\n", i);
	140	continue;
	141	} else if (ret) {
	142	dev_dbg(dev, "port %d probe returned %d\n", i, ret);
	143	return ret;
	144	}
	145
	146	if (panel) {
	147	u32 conn_type;
	148
	149	dev_dbg(dev, "Setting up panel for port %d\n", i);
	150
	151	switch (feat->vp_bus_type[i]) {
	152	case DISPC_VP_OLDI:
	153	enc_type = DRM_MODE_ENCODER_LVDS;
	154	conn_type = DRM_MODE_CONNECTOR_LVDS;
	155	break;
	156	case DISPC_VP_DPI:
	157	enc_type = DRM_MODE_ENCODER_DPI;
a72a6a16	158	conn_type = DRM_MODE_CONNECTOR_DPI;
32a1795f JS	159	break;
	160	default:
	161	WARN_ON(1);
	162	return -EINVAL;
	163	}
	164
	165	if (panel->connector_type != conn_type) {
	166	dev_err(dev,
	167	"%s: Panel %s has incompatible connector type for vp%d (%d != %d)\n",
	168	__func__, dev_name(panel->dev), i,
	169	panel->connector_type, conn_type);
	170	return -EINVAL;
	171	}
	172
	173	bridge = devm_drm_panel_bridge_add(dev, panel);
	174	if (IS_ERR(bridge)) {
	175	dev_err(dev,
	176	"failed to set up panel bridge for port %d\n",
	177	i);
	178	return PTR_ERR(bridge);
	179	}
	180	}
	181
	182	pipes[num_pipes].hw_videoport = i;
	183	pipes[num_pipes].bridge = bridge;
	184	pipes[num_pipes].enc_type = enc_type;
	185	num_pipes++;
	186	}
	187
	188	/* all planes can be on any crtc */
	189	crtc_mask = (1 << num_pipes) - 1;
	190
	191	/* then create a plane, a crtc and an encoder for each panel/bridge */
	192
	193	for (i = 0; i < num_pipes; ++i) {
	194	struct tidss_plane *tplane;
	195	struct tidss_crtc *tcrtc;
	196	struct drm_encoder *enc;
	197	u32 hw_plane_id = feat->vid_order[tidss->num_planes];
	198	int ret;
	199
	200	tplane = tidss_plane_create(tidss, hw_plane_id,
	201	DRM_PLANE_TYPE_PRIMARY, crtc_mask,
	202	fourccs, fourccs_len);
	203	if (IS_ERR(tplane)) {
	204	dev_err(tidss->dev, "plane create failed\n");
	205	return PTR_ERR(tplane);
	206	}
	207
	208	tidss->planes[tidss->num_planes++] = &tplane->plane;
	209
	210	tcrtc = tidss_crtc_create(tidss, pipes[i].hw_videoport,
	211	&tplane->plane);
	212	if (IS_ERR(tcrtc)) {
	213	dev_err(tidss->dev, "crtc create failed\n");
	214	return PTR_ERR(tcrtc);
	215	}
	216
	217	tidss->crtcs[tidss->num_crtcs++] = &tcrtc->crtc;
	218
	219	enc = tidss_encoder_create(tidss, pipes[i].enc_type,
	220	1 << tcrtc->crtc.index);
	221	if (IS_ERR(enc)) {
	222	dev_err(tidss->dev, "encoder create failed\n");
223	return PTR_ERR(enc);
224	}
225
a25b988f	226	ret = drm_bridge_attach(enc, pipes[i].bridge, NULL, 0);
fb8d617f	227	if (ret)
32a1795f	228	return ret;
32a1795f JS	229	}
	230
	231	/* create overlay planes of the leftover planes */
	232
	233	while (tidss->num_planes < max_planes) {
	234	struct tidss_plane *tplane;
	235	u32 hw_plane_id = feat->vid_order[tidss->num_planes];
	236
	237	tplane = tidss_plane_create(tidss, hw_plane_id,
	238	DRM_PLANE_TYPE_OVERLAY, crtc_mask,
	239	fourccs, fourccs_len);
	240
	241	if (IS_ERR(tplane)) {
	242	dev_err(tidss->dev, "plane create failed\n");
	243	return PTR_ERR(tplane);
	244	}
	245
	246	tidss->planes[tidss->num_planes++] = &tplane->plane;
	247	}
	248
	249	return 0;
	250	}
	251
	252	int tidss_modeset_init(struct tidss_device *tidss)
	253	{
	254	struct drm_device *ddev = &tidss->ddev;
32a1795f JS	255	int ret;
	256
	257	dev_dbg(tidss->dev, "%s\n", __func__);
	258
c792098b DV	259	ret = drmm_mode_config_init(ddev);
	260	if (ret)
	261	return ret;
32a1795f JS	262
	263	ddev->mode_config.min_width = 8;
	264	ddev->mode_config.min_height = 8;
	265	ddev->mode_config.max_width = 8096;
	266	ddev->mode_config.max_height = 8096;
	267	ddev->mode_config.normalize_zpos = true;
	268	ddev->mode_config.funcs = &mode_config_funcs;
	269	ddev->mode_config.helper_private = &mode_config_helper_funcs;
	270
	271	ret = tidss_dispc_modeset_init(tidss);
	272	if (ret)
c792098b	273	return ret;
32a1795f JS	274
	275	ret = drm_vblank_init(ddev, tidss->num_crtcs);
	276	if (ret)
c792098b	277	return ret;
32a1795f	278
32a1795f JS	279	drm_mode_config_reset(ddev);
	280
	281	dev_dbg(tidss->dev, "%s done\n", __func__);
	282
	283	return 0;
32a1795f	284	}