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Merge tag 'trace-v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux...
[linux-2.6-block.git] / drivers / gpu / drm / tegra / sor.c
CommitLineData
6b6b6042
TR		 1/*
2 * Copyright (C) 2013 NVIDIA Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/clk.h>
a82752e1 10#include <linux/debugfs.h>
6fad8f66 11#include <linux/gpio.h>
6b6b6042
TR		 12#include <linux/io.h>
13#include <linux/platform_device.h>
14#include <linux/reset.h>
306a7f91 15
7232398a 16#include <soc/tegra/pmc.h>
6b6b6042 17
4aa3df71 18#include <drm/drm_atomic_helper.h>
6b6b6042 19#include <drm/drm_dp_helper.h>
6fad8f66 20#include <drm/drm_panel.h>
6b6b6042
TR		 21
22#include "dc.h"
23#include "drm.h"
24#include "sor.h"
25
26struct tegra_sor {
27 struct host1x_client client;
28 struct tegra_output output;
29 struct device *dev;
30
31 void __iomem *regs;
32
33 struct reset_control *rst;
34 struct clk *clk_parent;
35 struct clk *clk_safe;
36 struct clk *clk_dp;
37 struct clk *clk;
38
39 struct tegra_dpaux *dpaux;
40
86f5c52d 41 struct mutex lock;
6b6b6042 42 bool enabled;
a82752e1 43
dab16336
TR		 44 struct drm_info_list *debugfs_files;
45 struct drm_minor *minor;
a82752e1 46 struct dentry *debugfs;
6b6b6042
TR		 47};
48
34fa183b
TR		 49struct tegra_sor_config {
50 u32 bits_per_pixel;
51
52 u32 active_polarity;
53 u32 active_count;
54 u32 tu_size;
55 u32 active_frac;
56 u32 watermark;
7890b576
TR		 57
58 u32 hblank_symbols;
59 u32 vblank_symbols;
34fa183b
TR		 60};
61
6b6b6042
TR		 62static inline struct tegra_sor *
63host1x_client_to_sor(struct host1x_client *client)
64{
65 return container_of(client, struct tegra_sor, client);
66}
67
68static inline struct tegra_sor *to_sor(struct tegra_output *output)
69{
70 return container_of(output, struct tegra_sor, output);
71}
72
28fe2076 73static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned long offset)
6b6b6042
TR		 74{
75 return readl(sor->regs + (offset << 2));
76}
77
28fe2076 78static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
6b6b6042
TR		 79 unsigned long offset)
80{
81 writel(value, sor->regs + (offset << 2));
82}
83
84static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
85 struct drm_dp_link *link)
86{
6b6b6042
TR		 87 unsigned int i;
88 u8 pattern;
28fe2076 89 u32 value;
6b6b6042
TR		 90 int err;
91
92 /* setup lane parameters */
93 value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) |
94 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) |
95 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) |
96 SOR_LANE_DRIVE_CURRENT_LANE0(0x40);
97 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT_0);
98
99 value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) |
100 SOR_LANE_PREEMPHASIS_LANE2(0x0f) |
101 SOR_LANE_PREEMPHASIS_LANE1(0x0f) |
102 SOR_LANE_PREEMPHASIS_LANE0(0x0f);
103 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS_0);
104
105 value = SOR_LANE_POST_CURSOR_LANE3(0x00) |
106 SOR_LANE_POST_CURSOR_LANE2(0x00) |
107 SOR_LANE_POST_CURSOR_LANE1(0x00) |
108 SOR_LANE_POST_CURSOR_LANE0(0x00);
109 tegra_sor_writel(sor, value, SOR_LANE_POST_CURSOR_0);
110
111 /* disable LVDS mode */
112 tegra_sor_writel(sor, 0, SOR_LVDS);
113
114 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
115 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
116 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
117 value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */
118 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
119
120 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
121 value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
122 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0;
123 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
124
125 usleep_range(10, 100);
126
127 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
128 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
129 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
130 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
131
132 err = tegra_dpaux_prepare(sor->dpaux, DP_SET_ANSI_8B10B);
133 if (err < 0)
134 return err;
135
136 for (i = 0, value = 0; i < link->num_lanes; i++) {
137 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
138 SOR_DP_TPG_SCRAMBLER_NONE |
139 SOR_DP_TPG_PATTERN_TRAIN1;
140 value = (value << 8) | lane;
141 }
142
143 tegra_sor_writel(sor, value, SOR_DP_TPG);
144
145 pattern = DP_TRAINING_PATTERN_1;
146
147 err = tegra_dpaux_train(sor->dpaux, link, pattern);
148 if (err < 0)
149 return err;
150
151 value = tegra_sor_readl(sor, SOR_DP_SPARE_0);
152 value |= SOR_DP_SPARE_SEQ_ENABLE;
153 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
154 value |= SOR_DP_SPARE_MACRO_SOR_CLK;
155 tegra_sor_writel(sor, value, SOR_DP_SPARE_0);
156
157 for (i = 0, value = 0; i < link->num_lanes; i++) {
158 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
159 SOR_DP_TPG_SCRAMBLER_NONE |
160 SOR_DP_TPG_PATTERN_TRAIN2;
161 value = (value << 8) | lane;
162 }
163
164 tegra_sor_writel(sor, value, SOR_DP_TPG);
165
166 pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2;
167
168 err = tegra_dpaux_train(sor->dpaux, link, pattern);
169 if (err < 0)
170 return err;
171
172 for (i = 0, value = 0; i < link->num_lanes; i++) {
173 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
174 SOR_DP_TPG_SCRAMBLER_GALIOS |
175 SOR_DP_TPG_PATTERN_NONE;
176 value = (value << 8) | lane;
177 }
178
179 tegra_sor_writel(sor, value, SOR_DP_TPG);
180
181 pattern = DP_TRAINING_PATTERN_DISABLE;
182
183 err = tegra_dpaux_train(sor->dpaux, link, pattern);
184 if (err < 0)
185 return err;
186
187 return 0;
188}
189
190static void tegra_sor_super_update(struct tegra_sor *sor)
191{
192 tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0);
193 tegra_sor_writel(sor, 1, SOR_SUPER_STATE_0);
194 tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0);
195}
196
197static void tegra_sor_update(struct tegra_sor *sor)
198{
199 tegra_sor_writel(sor, 0, SOR_STATE_0);
200 tegra_sor_writel(sor, 1, SOR_STATE_0);
201 tegra_sor_writel(sor, 0, SOR_STATE_0);
202}
203
204static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
205{
28fe2076 206 u32 value;
6b6b6042
TR		 207
208 value = tegra_sor_readl(sor, SOR_PWM_DIV);
209 value &= ~SOR_PWM_DIV_MASK;
210 value |= 0x400; /* period */
211 tegra_sor_writel(sor, value, SOR_PWM_DIV);
212
213 value = tegra_sor_readl(sor, SOR_PWM_CTL);
214 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
215 value |= 0x400; /* duty cycle */
216 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
217 value |= SOR_PWM_CTL_TRIGGER;
218 tegra_sor_writel(sor, value, SOR_PWM_CTL);
219
220 timeout = jiffies + msecs_to_jiffies(timeout);
221
222 while (time_before(jiffies, timeout)) {
223 value = tegra_sor_readl(sor, SOR_PWM_CTL);
224 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
225 return 0;
226
227 usleep_range(25, 100);
228 }
229
230 return -ETIMEDOUT;
231}
232
233static int tegra_sor_attach(struct tegra_sor *sor)
234{
235 unsigned long value, timeout;
236
237 /* wake up in normal mode */
238 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
239 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
240 value |= SOR_SUPER_STATE_MODE_NORMAL;
241 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
242 tegra_sor_super_update(sor);
243
244 /* attach */
245 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
246 value |= SOR_SUPER_STATE_ATTACHED;
247 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
248 tegra_sor_super_update(sor);
249
250 timeout = jiffies + msecs_to_jiffies(250);
251
252 while (time_before(jiffies, timeout)) {
253 value = tegra_sor_readl(sor, SOR_TEST);
254 if ((value & SOR_TEST_ATTACHED) != 0)
255 return 0;
256
257 usleep_range(25, 100);
258 }
259
260 return -ETIMEDOUT;
261}
262
263static int tegra_sor_wakeup(struct tegra_sor *sor)
264{
6b6b6042
TR		 265 unsigned long value, timeout;
266
6b6b6042
TR		 267 timeout = jiffies + msecs_to_jiffies(250);
268
269 /* wait for head to wake up */
270 while (time_before(jiffies, timeout)) {
271 value = tegra_sor_readl(sor, SOR_TEST);
272 value &= SOR_TEST_HEAD_MODE_MASK;
273
274 if (value == SOR_TEST_HEAD_MODE_AWAKE)
275 return 0;
276
277 usleep_range(25, 100);
278 }
279
280 return -ETIMEDOUT;
281}
282
283static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
284{
28fe2076 285 u32 value;
6b6b6042
TR		 286
287 value = tegra_sor_readl(sor, SOR_PWR);
288 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
289 tegra_sor_writel(sor, value, SOR_PWR);
290
291 timeout = jiffies + msecs_to_jiffies(timeout);
292
293 while (time_before(jiffies, timeout)) {
294 value = tegra_sor_readl(sor, SOR_PWR);
295 if ((value & SOR_PWR_TRIGGER) == 0)
296 return 0;
297
298 usleep_range(25, 100);
299 }
300
301 return -ETIMEDOUT;
302}
303
34fa183b
TR		 304struct tegra_sor_params {
305 /* number of link clocks per line */
306 unsigned int num_clocks;
307 /* ratio between input and output */
308 u64 ratio;
309 /* precision factor */
310 u64 precision;
311
312 unsigned int active_polarity;
313 unsigned int active_count;
314 unsigned int active_frac;
315 unsigned int tu_size;
316 unsigned int error;
317};
318
319static int tegra_sor_compute_params(struct tegra_sor *sor,
320 struct tegra_sor_params *params,
321 unsigned int tu_size)
322{
323 u64 active_sym, active_count, frac, approx;
324 u32 active_polarity, active_frac = 0;
325 const u64 f = params->precision;
326 s64 error;
327
328 active_sym = params->ratio * tu_size;
329 active_count = div_u64(active_sym, f) * f;
330 frac = active_sym - active_count;
331
332 /* fraction < 0.5 */
333 if (frac >= (f / 2)) {
334 active_polarity = 1;
335 frac = f - frac;
336 } else {
337 active_polarity = 0;
338 }
339
340 if (frac != 0) {
341 frac = div_u64(f * f, frac); /* 1/fraction */
342 if (frac <= (15 * f)) {
343 active_frac = div_u64(frac, f);
344
345 /* round up */
346 if (active_polarity)
347 active_frac++;
348 } else {
349 active_frac = active_polarity ? 1 : 15;
350 }
351 }
352
353 if (active_frac == 1)
354 active_polarity = 0;
355
356 if (active_polarity == 1) {
357 if (active_frac) {
358 approx = active_count + (active_frac * (f - 1)) * f;
359 approx = div_u64(approx, active_frac * f);
360 } else {
361 approx = active_count + f;
362 }
363 } else {
364 if (active_frac)
365 approx = active_count + div_u64(f, active_frac);
366 else
367 approx = active_count;
368 }
369
370 error = div_s64(active_sym - approx, tu_size);
371 error *= params->num_clocks;
372
373 if (error <= 0 && abs64(error) < params->error) {
374 params->active_count = div_u64(active_count, f);
375 params->active_polarity = active_polarity;
376 params->active_frac = active_frac;
377 params->error = abs64(error);
378 params->tu_size = tu_size;
379
380 if (error == 0)
381 return true;
382 }
383
384 return false;
385}
386
387static int tegra_sor_calc_config(struct tegra_sor *sor,
388 struct drm_display_mode *mode,
389 struct tegra_sor_config *config,
390 struct drm_dp_link *link)
391{
392 const u64 f = 100000, link_rate = link->rate * 1000;
393 const u64 pclk = mode->clock * 1000;
7890b576 394 u64 input, output, watermark, num;
34fa183b 395 struct tegra_sor_params params;
34fa183b
TR		 396 u32 num_syms_per_line;
397 unsigned int i;
398
399 if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel)
400 return -EINVAL;
401
402 output = link_rate * 8 * link->num_lanes;
403 input = pclk * config->bits_per_pixel;
404
405 if (input >= output)
406 return -ERANGE;
407
408 memset(&params, 0, sizeof(params));
409 params.ratio = div64_u64(input * f, output);
410 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
411 params.precision = f;
412 params.error = 64 * f;
413 params.tu_size = 64;
414
415 for (i = params.tu_size; i >= 32; i--)
416 if (tegra_sor_compute_params(sor, &params, i))
417 break;
418
419 if (params.active_frac == 0) {
420 config->active_polarity = 0;
421 config->active_count = params.active_count;
422
423 if (!params.active_polarity)
424 config->active_count--;
425
426 config->tu_size = params.tu_size;
427 config->active_frac = 1;
428 } else {
429 config->active_polarity = params.active_polarity;
430 config->active_count = params.active_count;
431 config->active_frac = params.active_frac;
432 config->tu_size = params.tu_size;
433 }
434
435 dev_dbg(sor->dev,
436 "polarity: %d active count: %d tu size: %d active frac: %d\n",
437 config->active_polarity, config->active_count,
438 config->tu_size, config->active_frac);
439
440 watermark = params.ratio * config->tu_size * (f - params.ratio);
441 watermark = div_u64(watermark, f);
442
443 watermark = div_u64(watermark + params.error, f);
444 config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
445 num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
446 (link->num_lanes * 8);
447
448 if (config->watermark > 30) {
449 config->watermark = 30;
450 dev_err(sor->dev,
451 "unable to compute TU size, forcing watermark to %u\n",
452 config->watermark);
453 } else if (config->watermark > num_syms_per_line) {
454 config->watermark = num_syms_per_line;
455 dev_err(sor->dev, "watermark too high, forcing to %u\n",
456 config->watermark);
457 }
458
7890b576
TR		 459 /* compute the number of symbols per horizontal blanking interval */
460 num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
461 config->hblank_symbols = div_u64(num, pclk);
462
463 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
464 config->hblank_symbols -= 3;
465
466 config->hblank_symbols -= 12 / link->num_lanes;
467
468 /* compute the number of symbols per vertical blanking interval */
469 num = (mode->hdisplay - 25) * link_rate;
470 config->vblank_symbols = div_u64(num, pclk);
471 config->vblank_symbols -= 36 / link->num_lanes + 4;
472
473 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
474 config->vblank_symbols);
475
34fa183b
TR		 476 return 0;
477}
478
6fad8f66
TR		 479static int tegra_sor_detach(struct tegra_sor *sor)
480{
481 unsigned long value, timeout;
482
483 /* switch to safe mode */
484 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
485 value &= ~SOR_SUPER_STATE_MODE_NORMAL;
486 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
487 tegra_sor_super_update(sor);
488
489 timeout = jiffies + msecs_to_jiffies(250);
490
491 while (time_before(jiffies, timeout)) {
492 value = tegra_sor_readl(sor, SOR_PWR);
493 if (value & SOR_PWR_MODE_SAFE)
494 break;
495 }
496
497 if ((value & SOR_PWR_MODE_SAFE) == 0)
498 return -ETIMEDOUT;
499
500 /* go to sleep */
501 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
502 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
503 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
504 tegra_sor_super_update(sor);
505
506 /* detach */
507 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
508 value &= ~SOR_SUPER_STATE_ATTACHED;
509 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
510 tegra_sor_super_update(sor);
511
512 timeout = jiffies + msecs_to_jiffies(250);
513
514 while (time_before(jiffies, timeout)) {
515 value = tegra_sor_readl(sor, SOR_TEST);
516 if ((value & SOR_TEST_ATTACHED) == 0)
517 break;
518
519 usleep_range(25, 100);
520 }
521
522 if ((value & SOR_TEST_ATTACHED) != 0)
523 return -ETIMEDOUT;
524
525 return 0;
526}
527
528static int tegra_sor_power_down(struct tegra_sor *sor)
529{
530 unsigned long value, timeout;
531 int err;
532
533 value = tegra_sor_readl(sor, SOR_PWR);
534 value &= ~SOR_PWR_NORMAL_STATE_PU;
535 value |= SOR_PWR_TRIGGER;
536 tegra_sor_writel(sor, value, SOR_PWR);
537
538 timeout = jiffies + msecs_to_jiffies(250);
539
540 while (time_before(jiffies, timeout)) {
541 value = tegra_sor_readl(sor, SOR_PWR);
542 if ((value & SOR_PWR_TRIGGER) == 0)
543 return 0;
544
545 usleep_range(25, 100);
546 }
547
548 if ((value & SOR_PWR_TRIGGER) != 0)
549 return -ETIMEDOUT;
550
551 err = clk_set_parent(sor->clk, sor->clk_safe);
552 if (err < 0)
553 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
554
555 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
556 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
557 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
558 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
559
560 /* stop lane sequencer */
561 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
562 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
563 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
564
565 timeout = jiffies + msecs_to_jiffies(250);
566
567 while (time_before(jiffies, timeout)) {
568 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
569 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
570 break;
571
572 usleep_range(25, 100);
573 }
574
575 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
576 return -ETIMEDOUT;
577
578 value = tegra_sor_readl(sor, SOR_PLL_2);
579 value |= SOR_PLL_2_PORT_POWERDOWN;
580 tegra_sor_writel(sor, value, SOR_PLL_2);
581
582 usleep_range(20, 100);
583
584 value = tegra_sor_readl(sor, SOR_PLL_0);
585 value |= SOR_PLL_0_POWER_OFF;
586 value |= SOR_PLL_0_VCOPD;
587 tegra_sor_writel(sor, value, SOR_PLL_0);
588
589 value = tegra_sor_readl(sor, SOR_PLL_2);
590 value |= SOR_PLL_2_SEQ_PLLCAPPD;
591 value |= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE;
592 tegra_sor_writel(sor, value, SOR_PLL_2);
593
594 usleep_range(20, 100);
595
596 return 0;
597}
598
599static int tegra_sor_crc_open(struct inode *inode, struct file *file)
600{
601 file->private_data = inode->i_private;
602
603 return 0;
604}
605
606static int tegra_sor_crc_release(struct inode *inode, struct file *file)
607{
608 return 0;
609}
610
611static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
612{
613 u32 value;
614
615 timeout = jiffies + msecs_to_jiffies(timeout);
616
617 while (time_before(jiffies, timeout)) {
618 value = tegra_sor_readl(sor, SOR_CRC_A);
619 if (value & SOR_CRC_A_VALID)
620 return 0;
621
622 usleep_range(100, 200);
623 }
624
625 return -ETIMEDOUT;
626}
627
628static ssize_t tegra_sor_crc_read(struct file *file, char __user *buffer,
629 size_t size, loff_t *ppos)
630{
631 struct tegra_sor *sor = file->private_data;
632 ssize_t num, err;
633 char buf[10];
634 u32 value;
635
636 mutex_lock(&sor->lock);
637
638 if (!sor->enabled) {
639 err = -EAGAIN;
640 goto unlock;
641 }
642
643 value = tegra_sor_readl(sor, SOR_STATE_1);
644 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
645 tegra_sor_writel(sor, value, SOR_STATE_1);
646
647 value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
648 value |= SOR_CRC_CNTRL_ENABLE;
649 tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
650
651 value = tegra_sor_readl(sor, SOR_TEST);
652 value &= ~SOR_TEST_CRC_POST_SERIALIZE;
653 tegra_sor_writel(sor, value, SOR_TEST);
654
655 err = tegra_sor_crc_wait(sor, 100);
656 if (err < 0)
657 goto unlock;
658
659 tegra_sor_writel(sor, SOR_CRC_A_RESET, SOR_CRC_A);
660 value = tegra_sor_readl(sor, SOR_CRC_B);
661
662 num = scnprintf(buf, sizeof(buf), "%08x\n", value);
663
664 err = simple_read_from_buffer(buffer, size, ppos, buf, num);
665
666unlock:
667 mutex_unlock(&sor->lock);
668 return err;
669}
670
671static const struct file_operations tegra_sor_crc_fops = {
672 .owner = THIS_MODULE,
673 .open = tegra_sor_crc_open,
674 .read = tegra_sor_crc_read,
675 .release = tegra_sor_crc_release,
676};
677
dab16336
TR		 678static int tegra_sor_show_regs(struct seq_file *s, void *data)
679{
680 struct drm_info_node *node = s->private;
681 struct tegra_sor *sor = node->info_ent->data;
682
683#define DUMP_REG(name) \
684 seq_printf(s, "%-38s %#05x %08x\n", #name, name, \
685 tegra_sor_readl(sor, name))
686
687 DUMP_REG(SOR_CTXSW);
688 DUMP_REG(SOR_SUPER_STATE_0);
689 DUMP_REG(SOR_SUPER_STATE_1);
690 DUMP_REG(SOR_STATE_0);
691 DUMP_REG(SOR_STATE_1);
692 DUMP_REG(SOR_HEAD_STATE_0(0));
693 DUMP_REG(SOR_HEAD_STATE_0(1));
694 DUMP_REG(SOR_HEAD_STATE_1(0));
695 DUMP_REG(SOR_HEAD_STATE_1(1));
696 DUMP_REG(SOR_HEAD_STATE_2(0));
697 DUMP_REG(SOR_HEAD_STATE_2(1));
698 DUMP_REG(SOR_HEAD_STATE_3(0));
699 DUMP_REG(SOR_HEAD_STATE_3(1));
700 DUMP_REG(SOR_HEAD_STATE_4(0));
701 DUMP_REG(SOR_HEAD_STATE_4(1));
702 DUMP_REG(SOR_HEAD_STATE_5(0));
703 DUMP_REG(SOR_HEAD_STATE_5(1));
704 DUMP_REG(SOR_CRC_CNTRL);
705 DUMP_REG(SOR_DP_DEBUG_MVID);
706 DUMP_REG(SOR_CLK_CNTRL);
707 DUMP_REG(SOR_CAP);
708 DUMP_REG(SOR_PWR);
709 DUMP_REG(SOR_TEST);
710 DUMP_REG(SOR_PLL_0);
711 DUMP_REG(SOR_PLL_1);
712 DUMP_REG(SOR_PLL_2);
713 DUMP_REG(SOR_PLL_3);
714 DUMP_REG(SOR_CSTM);
715 DUMP_REG(SOR_LVDS);
716 DUMP_REG(SOR_CRC_A);
717 DUMP_REG(SOR_CRC_B);
718 DUMP_REG(SOR_BLANK);
719 DUMP_REG(SOR_SEQ_CTL);
720 DUMP_REG(SOR_LANE_SEQ_CTL);
721 DUMP_REG(SOR_SEQ_INST(0));
722 DUMP_REG(SOR_SEQ_INST(1));
723 DUMP_REG(SOR_SEQ_INST(2));
724 DUMP_REG(SOR_SEQ_INST(3));
725 DUMP_REG(SOR_SEQ_INST(4));
726 DUMP_REG(SOR_SEQ_INST(5));
727 DUMP_REG(SOR_SEQ_INST(6));
728 DUMP_REG(SOR_SEQ_INST(7));
729 DUMP_REG(SOR_SEQ_INST(8));
730 DUMP_REG(SOR_SEQ_INST(9));
731 DUMP_REG(SOR_SEQ_INST(10));
732 DUMP_REG(SOR_SEQ_INST(11));
733 DUMP_REG(SOR_SEQ_INST(12));
734 DUMP_REG(SOR_SEQ_INST(13));
735 DUMP_REG(SOR_SEQ_INST(14));
736 DUMP_REG(SOR_SEQ_INST(15));
737 DUMP_REG(SOR_PWM_DIV);
738 DUMP_REG(SOR_PWM_CTL);
739 DUMP_REG(SOR_VCRC_A_0);
740 DUMP_REG(SOR_VCRC_A_1);
741 DUMP_REG(SOR_VCRC_B_0);
742 DUMP_REG(SOR_VCRC_B_1);
743 DUMP_REG(SOR_CCRC_A_0);
744 DUMP_REG(SOR_CCRC_A_1);
745 DUMP_REG(SOR_CCRC_B_0);
746 DUMP_REG(SOR_CCRC_B_1);
747 DUMP_REG(SOR_EDATA_A_0);
748 DUMP_REG(SOR_EDATA_A_1);
749 DUMP_REG(SOR_EDATA_B_0);
750 DUMP_REG(SOR_EDATA_B_1);
751 DUMP_REG(SOR_COUNT_A_0);
752 DUMP_REG(SOR_COUNT_A_1);
753 DUMP_REG(SOR_COUNT_B_0);
754 DUMP_REG(SOR_COUNT_B_1);
755 DUMP_REG(SOR_DEBUG_A_0);
756 DUMP_REG(SOR_DEBUG_A_1);
757 DUMP_REG(SOR_DEBUG_B_0);
758 DUMP_REG(SOR_DEBUG_B_1);
759 DUMP_REG(SOR_TRIG);
760 DUMP_REG(SOR_MSCHECK);
761 DUMP_REG(SOR_XBAR_CTRL);
762 DUMP_REG(SOR_XBAR_POL);
763 DUMP_REG(SOR_DP_LINKCTL_0);
764 DUMP_REG(SOR_DP_LINKCTL_1);
765 DUMP_REG(SOR_LANE_DRIVE_CURRENT_0);
766 DUMP_REG(SOR_LANE_DRIVE_CURRENT_1);
767 DUMP_REG(SOR_LANE4_DRIVE_CURRENT_0);
768 DUMP_REG(SOR_LANE4_DRIVE_CURRENT_1);
769 DUMP_REG(SOR_LANE_PREEMPHASIS_0);
770 DUMP_REG(SOR_LANE_PREEMPHASIS_1);
771 DUMP_REG(SOR_LANE4_PREEMPHASIS_0);
772 DUMP_REG(SOR_LANE4_PREEMPHASIS_1);
773 DUMP_REG(SOR_LANE_POST_CURSOR_0);
774 DUMP_REG(SOR_LANE_POST_CURSOR_1);
775 DUMP_REG(SOR_DP_CONFIG_0);
776 DUMP_REG(SOR_DP_CONFIG_1);
777 DUMP_REG(SOR_DP_MN_0);
778 DUMP_REG(SOR_DP_MN_1);
779 DUMP_REG(SOR_DP_PADCTL_0);
780 DUMP_REG(SOR_DP_PADCTL_1);
781 DUMP_REG(SOR_DP_DEBUG_0);
782 DUMP_REG(SOR_DP_DEBUG_1);
783 DUMP_REG(SOR_DP_SPARE_0);
784 DUMP_REG(SOR_DP_SPARE_1);
785 DUMP_REG(SOR_DP_AUDIO_CTRL);
786 DUMP_REG(SOR_DP_AUDIO_HBLANK_SYMBOLS);
787 DUMP_REG(SOR_DP_AUDIO_VBLANK_SYMBOLS);
788 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_HEADER);
789 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK_0);
790 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK_1);
791 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK_2);
792 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK_3);
793 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK_4);
794 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK_5);
795 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK_6);
796 DUMP_REG(SOR_DP_TPG);
797 DUMP_REG(SOR_DP_TPG_CONFIG);
798 DUMP_REG(SOR_DP_LQ_CSTM_0);
799 DUMP_REG(SOR_DP_LQ_CSTM_1);
800 DUMP_REG(SOR_DP_LQ_CSTM_2);
801
802#undef DUMP_REG
803
804 return 0;
805}
806
807static const struct drm_info_list debugfs_files[] = {
808 { "regs", tegra_sor_show_regs, 0, NULL },
809};
810
6fad8f66
TR		 811static int tegra_sor_debugfs_init(struct tegra_sor *sor,
812 struct drm_minor *minor)
6b6b6042 813{
6fad8f66 814 struct dentry *entry;
dab16336 815 unsigned int i;
6fad8f66
TR		 816 int err = 0;
817
818 sor->debugfs = debugfs_create_dir("sor", minor->debugfs_root);
819 if (!sor->debugfs)
820 return -ENOMEM;
821
dab16336
TR		 822 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
823 GFP_KERNEL);
824 if (!sor->debugfs_files) {
825 err = -ENOMEM;
826 goto remove;
827 }
828
829 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
830 sor->debugfs_files[i].data = sor;
831
832 err = drm_debugfs_create_files(sor->debugfs_files,
833 ARRAY_SIZE(debugfs_files),
834 sor->debugfs, minor);
835 if (err < 0)
836 goto free;
837
6fad8f66
TR		 838 entry = debugfs_create_file("crc", 0644, sor->debugfs, sor,
839 &tegra_sor_crc_fops);
840 if (!entry) {
6fad8f66 841 err = -ENOMEM;
dab16336 842 goto free;
6fad8f66
TR		 843 }
844
845 return err;
846
dab16336
TR		 847free:
848 kfree(sor->debugfs_files);
849 sor->debugfs_files = NULL;
6fad8f66 850remove:
dab16336 851 debugfs_remove_recursive(sor->debugfs);
6fad8f66
TR		 852 sor->debugfs = NULL;
853 return err;
854}
855
4009c224 856static void tegra_sor_debugfs_exit(struct tegra_sor *sor)
6fad8f66 857{
dab16336
TR		 858 drm_debugfs_remove_files(sor->debugfs_files, ARRAY_SIZE(debugfs_files),
859 sor->minor);
860 sor->minor = NULL;
861
862 kfree(sor->debugfs_files);
6fad8f66 863 sor->debugfs = NULL;
dab16336
TR		 864
865 debugfs_remove_recursive(sor->debugfs);
866 sor->debugfs_files = NULL;
6fad8f66
TR		 867}
868
869static void tegra_sor_connector_dpms(struct drm_connector *connector, int mode)
870{
871}
872
873static enum drm_connector_status
874tegra_sor_connector_detect(struct drm_connector *connector, bool force)
875{
876 struct tegra_output *output = connector_to_output(connector);
877 struct tegra_sor *sor = to_sor(output);
878
879 if (sor->dpaux)
880 return tegra_dpaux_detect(sor->dpaux);
881
882 return connector_status_unknown;
883}
884
885static const struct drm_connector_funcs tegra_sor_connector_funcs = {
886 .dpms = tegra_sor_connector_dpms,
9d44189f 887 .reset = drm_atomic_helper_connector_reset,
6fad8f66
TR		 888 .detect = tegra_sor_connector_detect,
889 .fill_modes = drm_helper_probe_single_connector_modes,
890 .destroy = tegra_output_connector_destroy,
9d44189f 891 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
4aa3df71 892 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6fad8f66
TR		 893};
894
895static int tegra_sor_connector_get_modes(struct drm_connector *connector)
896{
897 struct tegra_output *output = connector_to_output(connector);
898 struct tegra_sor *sor = to_sor(output);
899 int err;
900
901 if (sor->dpaux)
902 tegra_dpaux_enable(sor->dpaux);
903
904 err = tegra_output_connector_get_modes(connector);
905
906 if (sor->dpaux)
907 tegra_dpaux_disable(sor->dpaux);
908
909 return err;
910}
911
912static enum drm_mode_status
913tegra_sor_connector_mode_valid(struct drm_connector *connector,
914 struct drm_display_mode *mode)
915{
916 return MODE_OK;
917}
918
919static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
920 .get_modes = tegra_sor_connector_get_modes,
921 .mode_valid = tegra_sor_connector_mode_valid,
922 .best_encoder = tegra_output_connector_best_encoder,
923};
924
925static const struct drm_encoder_funcs tegra_sor_encoder_funcs = {
926 .destroy = tegra_output_encoder_destroy,
927};
928
929static void tegra_sor_encoder_dpms(struct drm_encoder *encoder, int mode)
930{
931}
932
6fad8f66
TR		 933static void tegra_sor_encoder_prepare(struct drm_encoder *encoder)
934{
935}
936
937static void tegra_sor_encoder_commit(struct drm_encoder *encoder)
938{
939}
940
941static void tegra_sor_encoder_mode_set(struct drm_encoder *encoder,
942 struct drm_display_mode *mode,
943 struct drm_display_mode *adjusted)
944{
945 struct tegra_output *output = encoder_to_output(encoder);
946 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
6b6b6042
TR		 947 unsigned int vbe, vse, hbe, hse, vbs, hbs, i;
948 struct tegra_sor *sor = to_sor(output);
34fa183b
TR		 949 struct tegra_sor_config config;
950 struct drm_dp_link link;
951 struct drm_dp_aux *aux;
86f5c52d 952 int err = 0;
28fe2076 953 u32 value;
86f5c52d
TR		 954
955 mutex_lock(&sor->lock);
6b6b6042
TR		 956
957 if (sor->enabled)
86f5c52d 958 goto unlock;
6b6b6042
TR		 959
960 err = clk_prepare_enable(sor->clk);
961 if (err < 0)
86f5c52d 962 goto unlock;
6b6b6042
TR		 963
964 reset_control_deassert(sor->rst);
965
6fad8f66
TR		 966 if (output->panel)
967 drm_panel_prepare(output->panel);
968
34fa183b
TR		 969 /* FIXME: properly convert to struct drm_dp_aux */
970 aux = (struct drm_dp_aux *)sor->dpaux;
971
6b6b6042
TR		 972 if (sor->dpaux) {
973 err = tegra_dpaux_enable(sor->dpaux);
974 if (err < 0)
975 dev_err(sor->dev, "failed to enable DP: %d\n", err);
34fa183b
TR		 976
977 err = drm_dp_link_probe(aux, &link);
978 if (err < 0) {
979 dev_err(sor->dev, "failed to probe eDP link: %d\n",
980 err);
2263c460 981 goto unlock;
34fa183b 982 }
6b6b6042
TR		 983 }
984
985 err = clk_set_parent(sor->clk, sor->clk_safe);
986 if (err < 0)
987 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
988
34fa183b 989 memset(&config, 0, sizeof(config));
054b1bd1 990 config.bits_per_pixel = output->connector.display_info.bpc * 3;
34fa183b
TR		 991
992 err = tegra_sor_calc_config(sor, mode, &config, &link);
993 if (err < 0)
994 dev_err(sor->dev, "failed to compute link configuration: %d\n",
995 err);
996
6b6b6042
TR		 997 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
998 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
999 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
1000 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1001
1002 value = tegra_sor_readl(sor, SOR_PLL_2);
1003 value &= ~SOR_PLL_2_BANDGAP_POWERDOWN;
1004 tegra_sor_writel(sor, value, SOR_PLL_2);
1005 usleep_range(20, 100);
1006
1007 value = tegra_sor_readl(sor, SOR_PLL_3);
1008 value |= SOR_PLL_3_PLL_VDD_MODE_V3_3;
1009 tegra_sor_writel(sor, value, SOR_PLL_3);
1010
1011 value = SOR_PLL_0_ICHPMP(0xf) | SOR_PLL_0_VCOCAP_RST |
1012 SOR_PLL_0_PLLREG_LEVEL_V45 | SOR_PLL_0_RESISTOR_EXT;
1013 tegra_sor_writel(sor, value, SOR_PLL_0);
1014
1015 value = tegra_sor_readl(sor, SOR_PLL_2);
1016 value |= SOR_PLL_2_SEQ_PLLCAPPD;
1017 value &= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE;
1018 value |= SOR_PLL_2_LVDS_ENABLE;
1019 tegra_sor_writel(sor, value, SOR_PLL_2);
1020
1021 value = SOR_PLL_1_TERM_COMPOUT | SOR_PLL_1_TMDS_TERM;
1022 tegra_sor_writel(sor, value, SOR_PLL_1);
1023
1024 while (true) {
1025 value = tegra_sor_readl(sor, SOR_PLL_2);
1026 if ((value & SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE) == 0)
1027 break;
1028
1029 usleep_range(250, 1000);
1030 }
1031
1032 value = tegra_sor_readl(sor, SOR_PLL_2);
1033 value &= ~SOR_PLL_2_POWERDOWN_OVERRIDE;
1034 value &= ~SOR_PLL_2_PORT_POWERDOWN;
1035 tegra_sor_writel(sor, value, SOR_PLL_2);
1036
1037 /*
1038 * power up
1039 */
1040
1041 /* set safe link bandwidth (1.62 Gbps) */
1042 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1043 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1044 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62;
1045 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1046
1047 /* step 1 */
1048 value = tegra_sor_readl(sor, SOR_PLL_2);
1049 value |= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL_2_PORT_POWERDOWN |
1050 SOR_PLL_2_BANDGAP_POWERDOWN;
1051 tegra_sor_writel(sor, value, SOR_PLL_2);
1052
1053 value = tegra_sor_readl(sor, SOR_PLL_0);
1054 value |= SOR_PLL_0_VCOPD | SOR_PLL_0_POWER_OFF;
1055 tegra_sor_writel(sor, value, SOR_PLL_0);
1056
1057 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
1058 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
1059 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
1060
1061 /* step 2 */
1062 err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS);
1063 if (err < 0) {
1064 dev_err(sor->dev, "failed to power on I/O rail: %d\n", err);
86f5c52d 1065 goto unlock;
6b6b6042
TR		 1066 }
1067
1068 usleep_range(5, 100);
1069
1070 /* step 3 */
1071 value = tegra_sor_readl(sor, SOR_PLL_2);
1072 value &= ~SOR_PLL_2_BANDGAP_POWERDOWN;
1073 tegra_sor_writel(sor, value, SOR_PLL_2);
1074
1075 usleep_range(20, 100);
1076
1077 /* step 4 */
1078 value = tegra_sor_readl(sor, SOR_PLL_0);
1079 value &= ~SOR_PLL_0_POWER_OFF;
1080 value &= ~SOR_PLL_0_VCOPD;
1081 tegra_sor_writel(sor, value, SOR_PLL_0);
1082
1083 value = tegra_sor_readl(sor, SOR_PLL_2);
1084 value &= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE;
1085 tegra_sor_writel(sor, value, SOR_PLL_2);
1086
1087 usleep_range(200, 1000);
1088
1089 /* step 5 */
1090 value = tegra_sor_readl(sor, SOR_PLL_2);
1091 value &= ~SOR_PLL_2_PORT_POWERDOWN;
1092 tegra_sor_writel(sor, value, SOR_PLL_2);
1093
1094 /* switch to DP clock */
1095 err = clk_set_parent(sor->clk, sor->clk_dp);
1096 if (err < 0)
1097 dev_err(sor->dev, "failed to set DP parent clock: %d\n", err);
1098
899451b7 1099 /* power DP lanes */
6b6b6042 1100 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
899451b7
TR		 1101
1102 if (link.num_lanes <= 2)
1103 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2);
1104 else
1105 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2;
1106
1107 if (link.num_lanes <= 1)
1108 value &= ~SOR_DP_PADCTL_PD_TXD_1;
1109 else
1110 value |= SOR_DP_PADCTL_PD_TXD_1;
1111
1112 if (link.num_lanes == 0)
1113 value &= ~SOR_DP_PADCTL_PD_TXD_0;
1114 else
1115 value |= SOR_DP_PADCTL_PD_TXD_0;
1116
6b6b6042
TR		 1117 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
1118
1119 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0);
1120 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
0c90a184 1121 value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes);
6b6b6042
TR		 1122 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0);
1123
1124 /* start lane sequencer */
1125 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
1126 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
1127 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1128
1129 while (true) {
1130 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1131 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1132 break;
1133
1134 usleep_range(250, 1000);
1135 }
1136
a4263fed 1137 /* set link bandwidth */
6b6b6042
TR		 1138 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1139 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
a4263fed 1140 value |= drm_dp_link_rate_to_bw_code(link.rate) << 2;
6b6b6042
TR		 1141 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1142
1143 /* set linkctl */
1144 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0);
1145 value |= SOR_DP_LINKCTL_ENABLE;
1146
1147 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
34fa183b 1148 value |= SOR_DP_LINKCTL_TU_SIZE(config.tu_size);
6b6b6042
TR		 1149
1150 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1151 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0);
1152
1153 for (i = 0, value = 0; i < 4; i++) {
1154 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1155 SOR_DP_TPG_SCRAMBLER_GALIOS |
1156 SOR_DP_TPG_PATTERN_NONE;
1157 value = (value << 8) | lane;
1158 }
1159
1160 tegra_sor_writel(sor, value, SOR_DP_TPG);
1161
1162 value = tegra_sor_readl(sor, SOR_DP_CONFIG_0);
1163 value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
34fa183b 1164 value |= SOR_DP_CONFIG_WATERMARK(config.watermark);
6b6b6042
TR		 1165
1166 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
34fa183b 1167 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config.active_count);
6b6b6042
TR		 1168
1169 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
34fa183b 1170 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config.active_frac);
6b6b6042 1171
34fa183b
TR		 1172 if (config.active_polarity)
1173 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1174 else
1175 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
6b6b6042
TR		 1176
1177 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
1f64ae7c 1178 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
6b6b6042
TR		 1179 tegra_sor_writel(sor, value, SOR_DP_CONFIG_0);
1180
1181 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1182 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
7890b576 1183 value |= config.hblank_symbols & 0xffff;
6b6b6042
TR		 1184 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1185
1186 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1187 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
7890b576 1188 value |= config.vblank_symbols & 0xffff;
6b6b6042
TR		 1189 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1190
1191 /* enable pad calibration logic */
1192 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
1193 value |= SOR_DP_PADCTL_PAD_CAL_PD;
1194 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
1195
1196 if (sor->dpaux) {
6b6b6042
TR		 1197 u8 rate, lanes;
1198
1199 err = drm_dp_link_probe(aux, &link);
1200 if (err < 0) {
1201 dev_err(sor->dev, "failed to probe eDP link: %d\n",
1202 err);
86f5c52d 1203 goto unlock;
6b6b6042
TR		 1204 }
1205
1206 err = drm_dp_link_power_up(aux, &link);
1207 if (err < 0) {
1208 dev_err(sor->dev, "failed to power up eDP link: %d\n",
1209 err);
86f5c52d 1210 goto unlock;
6b6b6042
TR		 1211 }
1212
1213 err = drm_dp_link_configure(aux, &link);
1214 if (err < 0) {
1215 dev_err(sor->dev, "failed to configure eDP link: %d\n",
1216 err);
86f5c52d 1217 goto unlock;
6b6b6042
TR		 1218 }
1219
1220 rate = drm_dp_link_rate_to_bw_code(link.rate);
1221 lanes = link.num_lanes;
1222
1223 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1224 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1225 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
1226 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1227
1228 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0);
1229 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1230 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
1231
1232 if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
1233 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1234
1235 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0);
1236
1237 /* disable training pattern generator */
1238
1239 for (i = 0; i < link.num_lanes; i++) {
1240 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1241 SOR_DP_TPG_SCRAMBLER_GALIOS |
1242 SOR_DP_TPG_PATTERN_NONE;
1243 value = (value << 8) | lane;
1244 }
1245
1246 tegra_sor_writel(sor, value, SOR_DP_TPG);
1247
1248 err = tegra_sor_dp_train_fast(sor, &link);
1249 if (err < 0) {
1250 dev_err(sor->dev, "DP fast link training failed: %d\n",
1251 err);
86f5c52d 1252 goto unlock;
6b6b6042
TR		 1253 }
1254
1255 dev_dbg(sor->dev, "fast link training succeeded\n");
1256 }
1257
1258 err = tegra_sor_power_up(sor, 250);
1259 if (err < 0) {
1260 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
86f5c52d 1261 goto unlock;
6b6b6042
TR		 1262 }
1263
6b6b6042
TR		 1264 /*
1265 * configure panel (24bpp, vsync-, hsync-, DP-A protocol, complete
1266 * raster, associate with display controller)
1267 */
3f4f3b5f 1268 value = SOR_STATE_ASY_PROTOCOL_DP_A |
6b6b6042
TR		 1269 SOR_STATE_ASY_CRC_MODE_COMPLETE |
1270 SOR_STATE_ASY_OWNER(dc->pipe + 1);
34fa183b 1271
3f4f3b5f
TR		 1272 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1273 value &= ~SOR_STATE_ASY_HSYNCPOL;
1274
1275 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1276 value |= SOR_STATE_ASY_HSYNCPOL;
1277
1278 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1279 value &= ~SOR_STATE_ASY_VSYNCPOL;
1280
1281 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1282 value |= SOR_STATE_ASY_VSYNCPOL;
1283
34fa183b
TR		 1284 switch (config.bits_per_pixel) {
1285 case 24:
1286 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1287 break;
1288
1289 case 18:
1290 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
1291 break;
1292
1293 default:
1294 BUG();
1295 break;
1296 }
1297
6b6b6042
TR		 1298 tegra_sor_writel(sor, value, SOR_STATE_1);
1299
1300 /*
1301 * TODO: The video timing programming below doesn't seem to match the
1302 * register definitions.
1303 */
1304
1305 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
1306 tegra_sor_writel(sor, value, SOR_HEAD_STATE_1(0));
1307
1308 vse = mode->vsync_end - mode->vsync_start - 1;
1309 hse = mode->hsync_end - mode->hsync_start - 1;
1310
1311 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
1312 tegra_sor_writel(sor, value, SOR_HEAD_STATE_2(0));
1313
1314 vbe = vse + (mode->vsync_start - mode->vdisplay);
1315 hbe = hse + (mode->hsync_start - mode->hdisplay);
1316
1317 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
1318 tegra_sor_writel(sor, value, SOR_HEAD_STATE_3(0));
1319
1320 vbs = vbe + mode->vdisplay;
1321 hbs = hbe + mode->hdisplay;
1322
1323 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
1324 tegra_sor_writel(sor, value, SOR_HEAD_STATE_4(0));
1325
6fad8f66
TR		 1326 /* CSTM (LVDS, link A/B, upper) */
1327 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
1328 SOR_CSTM_UPPER;
1329 tegra_sor_writel(sor, value, SOR_CSTM);
1330
1331 /* PWM setup */
1332 err = tegra_sor_setup_pwm(sor, 250);
1333 if (err < 0) {
1334 dev_err(sor->dev, "failed to setup PWM: %d\n", err);
1335 goto unlock;
6b6b6042
TR		 1336 }
1337
666cb873
TR		 1338 tegra_sor_update(sor);
1339
6fad8f66
TR		 1340 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1341 value |= SOR_ENABLE;
1342 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
6b6b6042 1343
666cb873 1344 tegra_dc_commit(dc);
6b6b6042 1345
6fad8f66
TR		 1346 err = tegra_sor_attach(sor);
1347 if (err < 0) {
1348 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
1349 goto unlock;
1350 }
6b6b6042 1351
6fad8f66
TR		 1352 err = tegra_sor_wakeup(sor);
1353 if (err < 0) {
1354 dev_err(sor->dev, "failed to enable DC: %d\n", err);
1355 goto unlock;
1356 }
6b6b6042 1357
6fad8f66
TR		 1358 if (output->panel)
1359 drm_panel_enable(output->panel);
6b6b6042 1360
6fad8f66 1361 sor->enabled = true;
6b6b6042 1362
6fad8f66
TR		 1363unlock:
1364 mutex_unlock(&sor->lock);
6b6b6042
TR		 1365}
1366
6fad8f66 1367static void tegra_sor_encoder_disable(struct drm_encoder *encoder)
6b6b6042 1368{
6fad8f66
TR		 1369 struct tegra_output *output = encoder_to_output(encoder);
1370 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
6b6b6042 1371 struct tegra_sor *sor = to_sor(output);
6fad8f66
TR		 1372 u32 value;
1373 int err;
86f5c52d
TR		 1374
1375 mutex_lock(&sor->lock);
6b6b6042
TR		 1376
1377 if (!sor->enabled)
86f5c52d 1378 goto unlock;
6b6b6042 1379
6fad8f66
TR		 1380 if (output->panel)
1381 drm_panel_disable(output->panel);
1382
6b6b6042
TR		 1383 err = tegra_sor_detach(sor);
1384 if (err < 0) {
1385 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
86f5c52d 1386 goto unlock;
6b6b6042
TR		 1387 }
1388
1389 tegra_sor_writel(sor, 0, SOR_STATE_1);
1390 tegra_sor_update(sor);
1391
1392 /*
1393 * The following accesses registers of the display controller, so make
1394 * sure it's only executed when the output is attached to one.
1395 */
1396 if (dc) {
6b6b6042
TR		 1397 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1398 value &= ~SOR_ENABLE;
1399 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1400
62b9e063 1401 tegra_dc_commit(dc);
6b6b6042
TR		 1402 }
1403
1404 err = tegra_sor_power_down(sor);
1405 if (err < 0) {
1406 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
86f5c52d 1407 goto unlock;
6b6b6042
TR		 1408 }
1409
1410 if (sor->dpaux) {
1411 err = tegra_dpaux_disable(sor->dpaux);
1412 if (err < 0) {
1413 dev_err(sor->dev, "failed to disable DP: %d\n", err);
86f5c52d 1414 goto unlock;
6b6b6042
TR		 1415 }
1416 }
1417
1418 err = tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS);
1419 if (err < 0) {
1420 dev_err(sor->dev, "failed to power off I/O rail: %d\n", err);
86f5c52d 1421 goto unlock;
6b6b6042
TR		 1422 }
1423
6fad8f66
TR		 1424 if (output->panel)
1425 drm_panel_unprepare(output->panel);
1426
6b6b6042 1427 clk_disable_unprepare(sor->clk);
6fad8f66 1428 reset_control_assert(sor->rst);
6b6b6042
TR		 1429
1430 sor->enabled = false;
1431
86f5c52d
TR		 1432unlock:
1433 mutex_unlock(&sor->lock);
a82752e1
TR		 1434}
1435
82f1511c
TR		 1436static int
1437tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
1438 struct drm_crtc_state *crtc_state,
1439 struct drm_connector_state *conn_state)
1440{
1441 struct tegra_output *output = encoder_to_output(encoder);
1442 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1443 unsigned long pclk = crtc_state->mode.clock * 1000;
1444 struct tegra_sor *sor = to_sor(output);
1445 int err;
1446
1447 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
1448 pclk, 0);
1449 if (err < 0) {
1450 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1451 return err;
1452 }
1453
1454 return 0;
1455}
1456
6fad8f66
TR		 1457static const struct drm_encoder_helper_funcs tegra_sor_encoder_helper_funcs = {
1458 .dpms = tegra_sor_encoder_dpms,
6fad8f66
TR		 1459 .prepare = tegra_sor_encoder_prepare,
1460 .commit = tegra_sor_encoder_commit,
1461 .mode_set = tegra_sor_encoder_mode_set,
1462 .disable = tegra_sor_encoder_disable,
82f1511c 1463 .atomic_check = tegra_sor_encoder_atomic_check,
a82752e1
TR		 1464};
1465
6b6b6042
TR		 1466static int tegra_sor_init(struct host1x_client *client)
1467{
9910f5c4 1468 struct drm_device *drm = dev_get_drvdata(client->parent);
6b6b6042
TR		 1469 struct tegra_sor *sor = host1x_client_to_sor(client);
1470 int err;
1471
1472 if (!sor->dpaux)
1473 return -ENODEV;
1474
6b6b6042 1475 sor->output.dev = sor->dev;
6b6b6042 1476
6fad8f66
TR		 1477 drm_connector_init(drm, &sor->output.connector,
1478 &tegra_sor_connector_funcs,
1479 DRM_MODE_CONNECTOR_eDP);
1480 drm_connector_helper_add(&sor->output.connector,
1481 &tegra_sor_connector_helper_funcs);
1482 sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
1483
6fad8f66
TR		 1484 drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs,
1485 DRM_MODE_ENCODER_TMDS);
1486 drm_encoder_helper_add(&sor->output.encoder,
1487 &tegra_sor_encoder_helper_funcs);
1488
1489 drm_mode_connector_attach_encoder(&sor->output.connector,
1490 &sor->output.encoder);
1491 drm_connector_register(&sor->output.connector);
1492
ea130b24
TR		 1493 err = tegra_output_init(drm, &sor->output);
1494 if (err < 0) {
1495 dev_err(client->dev, "failed to initialize output: %d\n", err);
1496 return err;
1497 }
6fad8f66 1498
ea130b24 1499 sor->output.encoder.possible_crtcs = 0x3;
6b6b6042 1500
a82752e1 1501 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1b0c7b48 1502 err = tegra_sor_debugfs_init(sor, drm->primary);
a82752e1
TR		 1503 if (err < 0)
1504 dev_err(sor->dev, "debugfs setup failed: %d\n", err);
1505 }
1506
6b6b6042
TR		 1507 if (sor->dpaux) {
1508 err = tegra_dpaux_attach(sor->dpaux, &sor->output);
1509 if (err < 0) {
1510 dev_err(sor->dev, "failed to attach DP: %d\n", err);
1511 return err;
1512 }
1513 }
1514
535a65db
TV		 1515 /*
1516 * XXX: Remove this reset once proper hand-over from firmware to
1517 * kernel is possible.
1518 */
1519 err = reset_control_assert(sor->rst);
1520 if (err < 0) {
1521 dev_err(sor->dev, "failed to assert SOR reset: %d\n", err);
1522 return err;
1523 }
1524
6fad8f66
TR		 1525 err = clk_prepare_enable(sor->clk);
1526 if (err < 0) {
1527 dev_err(sor->dev, "failed to enable clock: %d\n", err);
1528 return err;
1529 }
1530
535a65db
TV		 1531 usleep_range(1000, 3000);
1532
1533 err = reset_control_deassert(sor->rst);
1534 if (err < 0) {
1535 dev_err(sor->dev, "failed to deassert SOR reset: %d\n", err);
1536 return err;
1537 }
1538
6fad8f66
TR		 1539 err = clk_prepare_enable(sor->clk_safe);
1540 if (err < 0)
1541 return err;
1542
1543 err = clk_prepare_enable(sor->clk_dp);
1544 if (err < 0)
1545 return err;
1546
6b6b6042
TR		 1547 return 0;
1548}
1549
1550static int tegra_sor_exit(struct host1x_client *client)
1551{
1552 struct tegra_sor *sor = host1x_client_to_sor(client);
1553 int err;
1554
328ec69e
TR		 1555 tegra_output_exit(&sor->output);
1556
6b6b6042
TR		 1557 if (sor->dpaux) {
1558 err = tegra_dpaux_detach(sor->dpaux);
1559 if (err < 0) {
1560 dev_err(sor->dev, "failed to detach DP: %d\n", err);
1561 return err;
1562 }
1563 }
1564
6fad8f66
TR		 1565 clk_disable_unprepare(sor->clk_safe);
1566 clk_disable_unprepare(sor->clk_dp);
1567 clk_disable_unprepare(sor->clk);
1568
4009c224
TR		 1569 if (IS_ENABLED(CONFIG_DEBUG_FS))
1570 tegra_sor_debugfs_exit(sor);
a82752e1 1571
6b6b6042
TR		 1572 return 0;
1573}
1574
1575static const struct host1x_client_ops sor_client_ops = {
1576 .init = tegra_sor_init,
1577 .exit = tegra_sor_exit,
1578};
1579
1580static int tegra_sor_probe(struct platform_device *pdev)
1581{
1582 struct device_node *np;
1583 struct tegra_sor *sor;
1584 struct resource *regs;
1585 int err;
1586
1587 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
1588 if (!sor)
1589 return -ENOMEM;
1590
1591 sor->output.dev = sor->dev = &pdev->dev;
1592
1593 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
1594 if (np) {
1595 sor->dpaux = tegra_dpaux_find_by_of_node(np);
1596 of_node_put(np);
1597
1598 if (!sor->dpaux)
1599 return -EPROBE_DEFER;
1600 }
1601
1602 err = tegra_output_probe(&sor->output);
1603 if (err < 0)
1604 return err;
1605
1606 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1607 sor->regs = devm_ioremap_resource(&pdev->dev, regs);
1608 if (IS_ERR(sor->regs))
1609 return PTR_ERR(sor->regs);
1610
1611 sor->rst = devm_reset_control_get(&pdev->dev, "sor");
1612 if (IS_ERR(sor->rst))
1613 return PTR_ERR(sor->rst);
1614
1615 sor->clk = devm_clk_get(&pdev->dev, NULL);
1616 if (IS_ERR(sor->clk))
1617 return PTR_ERR(sor->clk);
1618
1619 sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
1620 if (IS_ERR(sor->clk_parent))
1621 return PTR_ERR(sor->clk_parent);
1622
6b6b6042
TR		 1623 sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
1624 if (IS_ERR(sor->clk_safe))
1625 return PTR_ERR(sor->clk_safe);
1626
6b6b6042
TR		 1627 sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
1628 if (IS_ERR(sor->clk_dp))
1629 return PTR_ERR(sor->clk_dp);
1630
6b6b6042
TR		 1631 INIT_LIST_HEAD(&sor->client.list);
1632 sor->client.ops = &sor_client_ops;
1633 sor->client.dev = &pdev->dev;
1634
86f5c52d
TR		 1635 mutex_init(&sor->lock);
1636
6b6b6042
TR		 1637 err = host1x_client_register(&sor->client);
1638 if (err < 0) {
1639 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1640 err);
1641 return err;
1642 }
1643
1644 platform_set_drvdata(pdev, sor);
1645
1646 return 0;
1647}
1648
1649static int tegra_sor_remove(struct platform_device *pdev)
1650{
1651 struct tegra_sor *sor = platform_get_drvdata(pdev);
1652 int err;
1653
1654 err = host1x_client_unregister(&sor->client);
1655 if (err < 0) {
1656 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1657 err);
1658 return err;
1659 }
1660
328ec69e 1661 tegra_output_remove(&sor->output);
6b6b6042
TR		 1662
1663 return 0;
1664}
1665
1666static const struct of_device_id tegra_sor_of_match[] = {
1667 { .compatible = "nvidia,tegra124-sor", },
1668 { },
1669};
ef70728c 1670MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
6b6b6042
TR		 1671
1672struct platform_driver tegra_sor_driver = {
1673 .driver = {
1674 .name = "tegra-sor",
1675 .of_match_table = tegra_sor_of_match,
1676 },
1677 .probe = tegra_sor_probe,
1678 .remove = tegra_sor_remove,
1679};
Linux 6.x block layer and io_uring tree(s)