Commit | Line | Data |
---|---|---|
dec72739 TR |
1 | /* |
2 | * Copyright (C) 2013 NVIDIA Corporation | |
3 | * | |
9a2ac2dc TR |
4 | * This program is free software; you can redistribute it and/or modify |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
dec72739 TR |
7 | */ |
8 | ||
9 | #include <linux/clk.h> | |
10 | #include <linux/debugfs.h> | |
11 | #include <linux/host1x.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/of.h> | |
e94236cd | 14 | #include <linux/of_platform.h> |
dec72739 | 15 | #include <linux/platform_device.h> |
ef8187d7 | 16 | #include <linux/pm_runtime.h> |
dec72739 TR |
17 | #include <linux/reset.h> |
18 | ||
3b077afb TR |
19 | #include <linux/regulator/consumer.h> |
20 | ||
4aa3df71 | 21 | #include <drm/drm_atomic_helper.h> |
dec72739 TR |
22 | #include <drm/drm_mipi_dsi.h> |
23 | #include <drm/drm_panel.h> | |
24 | ||
25 | #include <video/mipi_display.h> | |
26 | ||
27 | #include "dc.h" | |
28 | #include "drm.h" | |
29 | #include "dsi.h" | |
30 | #include "mipi-phy.h" | |
31 | ||
ebd14afe TR |
32 | struct tegra_dsi_state { |
33 | struct drm_connector_state base; | |
34 | ||
35 | struct mipi_dphy_timing timing; | |
36 | unsigned long period; | |
37 | ||
38 | unsigned int vrefresh; | |
39 | unsigned int lanes; | |
40 | unsigned long pclk; | |
41 | unsigned long bclk; | |
42 | ||
43 | enum tegra_dsi_format format; | |
44 | unsigned int mul; | |
45 | unsigned int div; | |
46 | }; | |
47 | ||
48 | static inline struct tegra_dsi_state * | |
49 | to_dsi_state(struct drm_connector_state *state) | |
50 | { | |
51 | return container_of(state, struct tegra_dsi_state, base); | |
52 | } | |
53 | ||
dec72739 TR |
54 | struct tegra_dsi { |
55 | struct host1x_client client; | |
56 | struct tegra_output output; | |
57 | struct device *dev; | |
58 | ||
59 | void __iomem *regs; | |
60 | ||
61 | struct reset_control *rst; | |
62 | struct clk *clk_parent; | |
63 | struct clk *clk_lp; | |
64 | struct clk *clk; | |
65 | ||
66 | struct drm_info_list *debugfs_files; | |
67 | struct drm_minor *minor; | |
68 | struct dentry *debugfs; | |
69 | ||
17297a28 | 70 | unsigned long flags; |
dec72739 TR |
71 | enum mipi_dsi_pixel_format format; |
72 | unsigned int lanes; | |
73 | ||
74 | struct tegra_mipi_device *mipi; | |
75 | struct mipi_dsi_host host; | |
3b077afb TR |
76 | |
77 | struct regulator *vdd; | |
976cebc3 TR |
78 | |
79 | unsigned int video_fifo_depth; | |
80 | unsigned int host_fifo_depth; | |
e94236cd TR |
81 | |
82 | /* for ganged-mode support */ | |
83 | struct tegra_dsi *master; | |
84 | struct tegra_dsi *slave; | |
dec72739 TR |
85 | }; |
86 | ||
87 | static inline struct tegra_dsi * | |
88 | host1x_client_to_dsi(struct host1x_client *client) | |
89 | { | |
90 | return container_of(client, struct tegra_dsi, client); | |
91 | } | |
92 | ||
93 | static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host) | |
94 | { | |
95 | return container_of(host, struct tegra_dsi, host); | |
96 | } | |
97 | ||
98 | static inline struct tegra_dsi *to_dsi(struct tegra_output *output) | |
99 | { | |
100 | return container_of(output, struct tegra_dsi, output); | |
101 | } | |
102 | ||
ebd14afe TR |
103 | static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi) |
104 | { | |
105 | return to_dsi_state(dsi->output.connector.state); | |
106 | } | |
107 | ||
9c0b4ca1 | 108 | static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned long reg) |
dec72739 TR |
109 | { |
110 | return readl(dsi->regs + (reg << 2)); | |
111 | } | |
112 | ||
9c0b4ca1 | 113 | static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value, |
dec72739 TR |
114 | unsigned long reg) |
115 | { | |
116 | writel(value, dsi->regs + (reg << 2)); | |
117 | } | |
118 | ||
119 | static int tegra_dsi_show_regs(struct seq_file *s, void *data) | |
120 | { | |
121 | struct drm_info_node *node = s->private; | |
122 | struct tegra_dsi *dsi = node->info_ent->data; | |
171e2e6d TR |
123 | struct drm_crtc *crtc = dsi->output.encoder.crtc; |
124 | struct drm_device *drm = node->minor->dev; | |
125 | int err = 0; | |
126 | ||
127 | drm_modeset_lock_all(drm); | |
128 | ||
129 | if (!crtc || !crtc->state->active) { | |
130 | err = -EBUSY; | |
131 | goto unlock; | |
132 | } | |
dec72739 TR |
133 | |
134 | #define DUMP_REG(name) \ | |
9c0b4ca1 | 135 | seq_printf(s, "%-32s %#05x %08x\n", #name, name, \ |
dec72739 TR |
136 | tegra_dsi_readl(dsi, name)) |
137 | ||
138 | DUMP_REG(DSI_INCR_SYNCPT); | |
139 | DUMP_REG(DSI_INCR_SYNCPT_CONTROL); | |
140 | DUMP_REG(DSI_INCR_SYNCPT_ERROR); | |
141 | DUMP_REG(DSI_CTXSW); | |
142 | DUMP_REG(DSI_RD_DATA); | |
143 | DUMP_REG(DSI_WR_DATA); | |
144 | DUMP_REG(DSI_POWER_CONTROL); | |
145 | DUMP_REG(DSI_INT_ENABLE); | |
146 | DUMP_REG(DSI_INT_STATUS); | |
147 | DUMP_REG(DSI_INT_MASK); | |
148 | DUMP_REG(DSI_HOST_CONTROL); | |
149 | DUMP_REG(DSI_CONTROL); | |
150 | DUMP_REG(DSI_SOL_DELAY); | |
151 | DUMP_REG(DSI_MAX_THRESHOLD); | |
152 | DUMP_REG(DSI_TRIGGER); | |
153 | DUMP_REG(DSI_TX_CRC); | |
154 | DUMP_REG(DSI_STATUS); | |
155 | ||
156 | DUMP_REG(DSI_INIT_SEQ_CONTROL); | |
157 | DUMP_REG(DSI_INIT_SEQ_DATA_0); | |
158 | DUMP_REG(DSI_INIT_SEQ_DATA_1); | |
159 | DUMP_REG(DSI_INIT_SEQ_DATA_2); | |
160 | DUMP_REG(DSI_INIT_SEQ_DATA_3); | |
161 | DUMP_REG(DSI_INIT_SEQ_DATA_4); | |
162 | DUMP_REG(DSI_INIT_SEQ_DATA_5); | |
163 | DUMP_REG(DSI_INIT_SEQ_DATA_6); | |
164 | DUMP_REG(DSI_INIT_SEQ_DATA_7); | |
165 | ||
166 | DUMP_REG(DSI_PKT_SEQ_0_LO); | |
167 | DUMP_REG(DSI_PKT_SEQ_0_HI); | |
168 | DUMP_REG(DSI_PKT_SEQ_1_LO); | |
169 | DUMP_REG(DSI_PKT_SEQ_1_HI); | |
170 | DUMP_REG(DSI_PKT_SEQ_2_LO); | |
171 | DUMP_REG(DSI_PKT_SEQ_2_HI); | |
172 | DUMP_REG(DSI_PKT_SEQ_3_LO); | |
173 | DUMP_REG(DSI_PKT_SEQ_3_HI); | |
174 | DUMP_REG(DSI_PKT_SEQ_4_LO); | |
175 | DUMP_REG(DSI_PKT_SEQ_4_HI); | |
176 | DUMP_REG(DSI_PKT_SEQ_5_LO); | |
177 | DUMP_REG(DSI_PKT_SEQ_5_HI); | |
178 | ||
179 | DUMP_REG(DSI_DCS_CMDS); | |
180 | ||
181 | DUMP_REG(DSI_PKT_LEN_0_1); | |
182 | DUMP_REG(DSI_PKT_LEN_2_3); | |
183 | DUMP_REG(DSI_PKT_LEN_4_5); | |
184 | DUMP_REG(DSI_PKT_LEN_6_7); | |
185 | ||
186 | DUMP_REG(DSI_PHY_TIMING_0); | |
187 | DUMP_REG(DSI_PHY_TIMING_1); | |
188 | DUMP_REG(DSI_PHY_TIMING_2); | |
189 | DUMP_REG(DSI_BTA_TIMING); | |
190 | ||
191 | DUMP_REG(DSI_TIMEOUT_0); | |
192 | DUMP_REG(DSI_TIMEOUT_1); | |
193 | DUMP_REG(DSI_TO_TALLY); | |
194 | ||
195 | DUMP_REG(DSI_PAD_CONTROL_0); | |
196 | DUMP_REG(DSI_PAD_CONTROL_CD); | |
197 | DUMP_REG(DSI_PAD_CD_STATUS); | |
198 | DUMP_REG(DSI_VIDEO_MODE_CONTROL); | |
199 | DUMP_REG(DSI_PAD_CONTROL_1); | |
200 | DUMP_REG(DSI_PAD_CONTROL_2); | |
201 | DUMP_REG(DSI_PAD_CONTROL_3); | |
202 | DUMP_REG(DSI_PAD_CONTROL_4); | |
203 | ||
204 | DUMP_REG(DSI_GANGED_MODE_CONTROL); | |
205 | DUMP_REG(DSI_GANGED_MODE_START); | |
206 | DUMP_REG(DSI_GANGED_MODE_SIZE); | |
207 | ||
208 | DUMP_REG(DSI_RAW_DATA_BYTE_COUNT); | |
209 | DUMP_REG(DSI_ULTRA_LOW_POWER_CONTROL); | |
210 | ||
211 | DUMP_REG(DSI_INIT_SEQ_DATA_8); | |
212 | DUMP_REG(DSI_INIT_SEQ_DATA_9); | |
213 | DUMP_REG(DSI_INIT_SEQ_DATA_10); | |
214 | DUMP_REG(DSI_INIT_SEQ_DATA_11); | |
215 | DUMP_REG(DSI_INIT_SEQ_DATA_12); | |
216 | DUMP_REG(DSI_INIT_SEQ_DATA_13); | |
217 | DUMP_REG(DSI_INIT_SEQ_DATA_14); | |
218 | DUMP_REG(DSI_INIT_SEQ_DATA_15); | |
219 | ||
220 | #undef DUMP_REG | |
221 | ||
171e2e6d TR |
222 | unlock: |
223 | drm_modeset_unlock_all(drm); | |
224 | return err; | |
dec72739 TR |
225 | } |
226 | ||
227 | static struct drm_info_list debugfs_files[] = { | |
228 | { "regs", tegra_dsi_show_regs, 0, NULL }, | |
229 | }; | |
230 | ||
231 | static int tegra_dsi_debugfs_init(struct tegra_dsi *dsi, | |
232 | struct drm_minor *minor) | |
233 | { | |
234 | const char *name = dev_name(dsi->dev); | |
235 | unsigned int i; | |
236 | int err; | |
237 | ||
238 | dsi->debugfs = debugfs_create_dir(name, minor->debugfs_root); | |
239 | if (!dsi->debugfs) | |
240 | return -ENOMEM; | |
241 | ||
242 | dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), | |
243 | GFP_KERNEL); | |
244 | if (!dsi->debugfs_files) { | |
245 | err = -ENOMEM; | |
246 | goto remove; | |
247 | } | |
248 | ||
249 | for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) | |
250 | dsi->debugfs_files[i].data = dsi; | |
251 | ||
252 | err = drm_debugfs_create_files(dsi->debugfs_files, | |
253 | ARRAY_SIZE(debugfs_files), | |
254 | dsi->debugfs, minor); | |
255 | if (err < 0) | |
256 | goto free; | |
257 | ||
258 | dsi->minor = minor; | |
259 | ||
260 | return 0; | |
261 | ||
262 | free: | |
263 | kfree(dsi->debugfs_files); | |
264 | dsi->debugfs_files = NULL; | |
265 | remove: | |
266 | debugfs_remove(dsi->debugfs); | |
267 | dsi->debugfs = NULL; | |
268 | ||
269 | return err; | |
270 | } | |
271 | ||
4009c224 | 272 | static void tegra_dsi_debugfs_exit(struct tegra_dsi *dsi) |
dec72739 TR |
273 | { |
274 | drm_debugfs_remove_files(dsi->debugfs_files, ARRAY_SIZE(debugfs_files), | |
275 | dsi->minor); | |
276 | dsi->minor = NULL; | |
277 | ||
278 | kfree(dsi->debugfs_files); | |
279 | dsi->debugfs_files = NULL; | |
280 | ||
281 | debugfs_remove(dsi->debugfs); | |
282 | dsi->debugfs = NULL; | |
dec72739 TR |
283 | } |
284 | ||
285 | #define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9)) | |
286 | #define PKT_LEN0(len) (((len) & 0x07) << 0) | |
287 | #define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19)) | |
288 | #define PKT_LEN1(len) (((len) & 0x07) << 10) | |
289 | #define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29)) | |
290 | #define PKT_LEN2(len) (((len) & 0x07) << 20) | |
291 | ||
292 | #define PKT_LP (1 << 30) | |
293 | #define NUM_PKT_SEQ 12 | |
294 | ||
17297a28 TR |
295 | /* |
296 | * non-burst mode with sync pulses | |
297 | */ | |
298 | static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = { | |
dec72739 TR |
299 | [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) | |
300 | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | | |
301 | PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | | |
302 | PKT_LP, | |
303 | [ 1] = 0, | |
304 | [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) | | |
305 | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | | |
306 | PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | | |
307 | PKT_LP, | |
308 | [ 3] = 0, | |
309 | [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | | |
310 | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | | |
311 | PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | | |
312 | PKT_LP, | |
313 | [ 5] = 0, | |
314 | [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | | |
315 | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | | |
316 | PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0), | |
317 | [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) | | |
318 | PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) | | |
319 | PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4), | |
320 | [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | | |
321 | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | | |
322 | PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | | |
323 | PKT_LP, | |
324 | [ 9] = 0, | |
325 | [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | | |
326 | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | | |
327 | PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0), | |
328 | [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) | | |
329 | PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) | | |
330 | PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4), | |
331 | }; | |
332 | ||
17297a28 TR |
333 | /* |
334 | * non-burst mode with sync events | |
335 | */ | |
336 | static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = { | |
337 | [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) | | |
338 | PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | | |
339 | PKT_LP, | |
340 | [ 1] = 0, | |
341 | [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | | |
342 | PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | | |
343 | PKT_LP, | |
344 | [ 3] = 0, | |
345 | [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | | |
346 | PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | | |
347 | PKT_LP, | |
348 | [ 5] = 0, | |
349 | [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | | |
350 | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) | | |
351 | PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3), | |
352 | [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4), | |
353 | [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | | |
354 | PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | | |
355 | PKT_LP, | |
356 | [ 9] = 0, | |
357 | [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | | |
358 | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) | | |
359 | PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3), | |
360 | [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4), | |
361 | }; | |
362 | ||
337b443d TR |
363 | static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = { |
364 | [ 0] = 0, | |
365 | [ 1] = 0, | |
366 | [ 2] = 0, | |
367 | [ 3] = 0, | |
368 | [ 4] = 0, | |
369 | [ 5] = 0, | |
370 | [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP, | |
371 | [ 7] = 0, | |
372 | [ 8] = 0, | |
373 | [ 9] = 0, | |
374 | [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP, | |
375 | [11] = 0, | |
376 | }; | |
377 | ||
ebd14afe TR |
378 | static void tegra_dsi_set_phy_timing(struct tegra_dsi *dsi, |
379 | unsigned long period, | |
380 | const struct mipi_dphy_timing *timing) | |
dec72739 | 381 | { |
9c0b4ca1 | 382 | u32 value; |
dec72739 | 383 | |
ebd14afe TR |
384 | value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 | |
385 | DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 | | |
386 | DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 | | |
387 | DSI_TIMING_FIELD(timing->hsprepare, period, 1); | |
dec72739 TR |
388 | tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0); |
389 | ||
ebd14afe TR |
390 | value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 | |
391 | DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 | | |
392 | DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 | | |
393 | DSI_TIMING_FIELD(timing->lpx, period, 1); | |
dec72739 TR |
394 | tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1); |
395 | ||
ebd14afe TR |
396 | value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 | |
397 | DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 | | |
dec72739 TR |
398 | DSI_TIMING_FIELD(0xff * period, period, 0) << 0; |
399 | tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2); | |
400 | ||
ebd14afe TR |
401 | value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 | |
402 | DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 | | |
403 | DSI_TIMING_FIELD(timing->tago, period, 1); | |
dec72739 TR |
404 | tegra_dsi_writel(dsi, value, DSI_BTA_TIMING); |
405 | ||
7e3bc3a9 | 406 | if (dsi->slave) |
ebd14afe | 407 | tegra_dsi_set_phy_timing(dsi->slave, period, timing); |
dec72739 TR |
408 | } |
409 | ||
410 | static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format, | |
411 | unsigned int *mulp, unsigned int *divp) | |
412 | { | |
413 | switch (format) { | |
414 | case MIPI_DSI_FMT_RGB666_PACKED: | |
415 | case MIPI_DSI_FMT_RGB888: | |
416 | *mulp = 3; | |
417 | *divp = 1; | |
418 | break; | |
419 | ||
420 | case MIPI_DSI_FMT_RGB565: | |
421 | *mulp = 2; | |
422 | *divp = 1; | |
423 | break; | |
424 | ||
425 | case MIPI_DSI_FMT_RGB666: | |
426 | *mulp = 9; | |
427 | *divp = 4; | |
428 | break; | |
429 | ||
430 | default: | |
431 | return -EINVAL; | |
432 | } | |
433 | ||
434 | return 0; | |
435 | } | |
436 | ||
f7d6889b TR |
437 | static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format, |
438 | enum tegra_dsi_format *fmt) | |
439 | { | |
440 | switch (format) { | |
441 | case MIPI_DSI_FMT_RGB888: | |
442 | *fmt = TEGRA_DSI_FORMAT_24P; | |
443 | break; | |
444 | ||
445 | case MIPI_DSI_FMT_RGB666: | |
446 | *fmt = TEGRA_DSI_FORMAT_18NP; | |
447 | break; | |
448 | ||
449 | case MIPI_DSI_FMT_RGB666_PACKED: | |
450 | *fmt = TEGRA_DSI_FORMAT_18P; | |
451 | break; | |
452 | ||
453 | case MIPI_DSI_FMT_RGB565: | |
454 | *fmt = TEGRA_DSI_FORMAT_16P; | |
455 | break; | |
456 | ||
457 | default: | |
458 | return -EINVAL; | |
459 | } | |
460 | ||
461 | return 0; | |
462 | } | |
463 | ||
e94236cd TR |
464 | static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start, |
465 | unsigned int size) | |
466 | { | |
467 | u32 value; | |
468 | ||
469 | tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START); | |
470 | tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE); | |
471 | ||
472 | value = DSI_GANGED_MODE_CONTROL_ENABLE; | |
473 | tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL); | |
474 | } | |
475 | ||
563eff1f TR |
476 | static void tegra_dsi_enable(struct tegra_dsi *dsi) |
477 | { | |
478 | u32 value; | |
479 | ||
480 | value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); | |
481 | value |= DSI_POWER_CONTROL_ENABLE; | |
482 | tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); | |
e94236cd TR |
483 | |
484 | if (dsi->slave) | |
485 | tegra_dsi_enable(dsi->slave); | |
486 | } | |
487 | ||
488 | static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi) | |
489 | { | |
490 | if (dsi->master) | |
491 | return dsi->master->lanes + dsi->lanes; | |
492 | ||
493 | if (dsi->slave) | |
494 | return dsi->lanes + dsi->slave->lanes; | |
495 | ||
496 | return dsi->lanes; | |
563eff1f TR |
497 | } |
498 | ||
ebd14afe TR |
499 | static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe, |
500 | const struct drm_display_mode *mode) | |
dec72739 | 501 | { |
dec72739 | 502 | unsigned int hact, hsw, hbp, hfp, i, mul, div; |
ebd14afe | 503 | struct tegra_dsi_state *state; |
17297a28 | 504 | const u32 *pkt_seq; |
563eff1f | 505 | u32 value; |
ebd14afe TR |
506 | |
507 | /* XXX: pass in state into this function? */ | |
508 | if (dsi->master) | |
509 | state = tegra_dsi_get_state(dsi->master); | |
510 | else | |
511 | state = tegra_dsi_get_state(dsi); | |
512 | ||
513 | mul = state->mul; | |
514 | div = state->div; | |
dec72739 | 515 | |
17297a28 TR |
516 | if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { |
517 | DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n"); | |
518 | pkt_seq = pkt_seq_video_non_burst_sync_pulses; | |
337b443d | 519 | } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) { |
17297a28 TR |
520 | DRM_DEBUG_KMS("Non-burst video mode with sync events\n"); |
521 | pkt_seq = pkt_seq_video_non_burst_sync_events; | |
337b443d TR |
522 | } else { |
523 | DRM_DEBUG_KMS("Command mode\n"); | |
524 | pkt_seq = pkt_seq_command_mode; | |
17297a28 TR |
525 | } |
526 | ||
ebd14afe TR |
527 | value = DSI_CONTROL_CHANNEL(0) | |
528 | DSI_CONTROL_FORMAT(state->format) | | |
dec72739 | 529 | DSI_CONTROL_LANES(dsi->lanes - 1) | |
563eff1f | 530 | DSI_CONTROL_SOURCE(pipe); |
dec72739 TR |
531 | tegra_dsi_writel(dsi, value, DSI_CONTROL); |
532 | ||
976cebc3 | 533 | tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD); |
dec72739 | 534 | |
563eff1f | 535 | value = DSI_HOST_CONTROL_HS; |
dec72739 TR |
536 | tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); |
537 | ||
538 | value = tegra_dsi_readl(dsi, DSI_CONTROL); | |
563eff1f | 539 | |
0c6b1e4b AC |
540 | if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) |
541 | value |= DSI_CONTROL_HS_CLK_CTRL; | |
563eff1f | 542 | |
dec72739 | 543 | value &= ~DSI_CONTROL_TX_TRIG(3); |
337b443d TR |
544 | |
545 | /* enable DCS commands for command mode */ | |
546 | if (dsi->flags & MIPI_DSI_MODE_VIDEO) | |
547 | value &= ~DSI_CONTROL_DCS_ENABLE; | |
548 | else | |
549 | value |= DSI_CONTROL_DCS_ENABLE; | |
550 | ||
dec72739 TR |
551 | value |= DSI_CONTROL_VIDEO_ENABLE; |
552 | value &= ~DSI_CONTROL_HOST_ENABLE; | |
553 | tegra_dsi_writel(dsi, value, DSI_CONTROL); | |
554 | ||
dec72739 TR |
555 | for (i = 0; i < NUM_PKT_SEQ; i++) |
556 | tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i); | |
557 | ||
337b443d TR |
558 | if (dsi->flags & MIPI_DSI_MODE_VIDEO) { |
559 | /* horizontal active pixels */ | |
560 | hact = mode->hdisplay * mul / div; | |
561 | ||
562 | /* horizontal sync width */ | |
563 | hsw = (mode->hsync_end - mode->hsync_start) * mul / div; | |
337b443d TR |
564 | |
565 | /* horizontal back porch */ | |
566 | hbp = (mode->htotal - mode->hsync_end) * mul / div; | |
b8be0bdb TR |
567 | |
568 | if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0) | |
569 | hbp += hsw; | |
337b443d TR |
570 | |
571 | /* horizontal front porch */ | |
572 | hfp = (mode->hsync_start - mode->hdisplay) * mul / div; | |
b8be0bdb TR |
573 | |
574 | /* subtract packet overhead */ | |
575 | hsw -= 10; | |
576 | hbp -= 14; | |
337b443d | 577 | hfp -= 8; |
dec72739 | 578 | |
337b443d TR |
579 | tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1); |
580 | tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3); | |
581 | tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5); | |
582 | tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7); | |
dec72739 | 583 | |
337b443d TR |
584 | /* set SOL delay (for non-burst mode only) */ |
585 | tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY); | |
e94236cd TR |
586 | |
587 | /* TODO: implement ganged mode */ | |
337b443d TR |
588 | } else { |
589 | u16 bytes; | |
590 | ||
e94236cd TR |
591 | if (dsi->master || dsi->slave) { |
592 | /* | |
593 | * For ganged mode, assume symmetric left-right mode. | |
594 | */ | |
595 | bytes = 1 + (mode->hdisplay / 2) * mul / div; | |
596 | } else { | |
597 | /* 1 byte (DCS command) + pixel data */ | |
598 | bytes = 1 + mode->hdisplay * mul / div; | |
599 | } | |
dec72739 | 600 | |
337b443d TR |
601 | tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1); |
602 | tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3); | |
603 | tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5); | |
604 | tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7); | |
dec72739 | 605 | |
337b443d TR |
606 | value = MIPI_DCS_WRITE_MEMORY_START << 8 | |
607 | MIPI_DCS_WRITE_MEMORY_CONTINUE; | |
608 | tegra_dsi_writel(dsi, value, DSI_DCS_CMDS); | |
dec72739 | 609 | |
e94236cd TR |
610 | /* set SOL delay */ |
611 | if (dsi->master || dsi->slave) { | |
e94236cd | 612 | unsigned long delay, bclk, bclk_ganged; |
ebd14afe | 613 | unsigned int lanes = state->lanes; |
e94236cd TR |
614 | |
615 | /* SOL to valid, valid to FIFO and FIFO write delay */ | |
616 | delay = 4 + 4 + 2; | |
617 | delay = DIV_ROUND_UP(delay * mul, div * lanes); | |
618 | /* FIFO read delay */ | |
619 | delay = delay + 6; | |
620 | ||
621 | bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes); | |
622 | bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes); | |
623 | value = bclk - bclk_ganged + delay + 20; | |
624 | } else { | |
625 | /* TODO: revisit for non-ganged mode */ | |
626 | value = 8 * mul / div; | |
627 | } | |
337b443d TR |
628 | |
629 | tegra_dsi_writel(dsi, value, DSI_SOL_DELAY); | |
630 | } | |
dec72739 | 631 | |
e94236cd | 632 | if (dsi->slave) { |
ebd14afe | 633 | tegra_dsi_configure(dsi->slave, pipe, mode); |
e94236cd TR |
634 | |
635 | /* | |
636 | * TODO: Support modes other than symmetrical left-right | |
637 | * split. | |
638 | */ | |
639 | tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2); | |
640 | tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2, | |
641 | mode->hdisplay / 2); | |
642 | } | |
563eff1f TR |
643 | } |
644 | ||
563eff1f TR |
645 | static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout) |
646 | { | |
647 | u32 value; | |
648 | ||
649 | timeout = jiffies + msecs_to_jiffies(timeout); | |
650 | ||
651 | while (time_before(jiffies, timeout)) { | |
652 | value = tegra_dsi_readl(dsi, DSI_STATUS); | |
653 | if (value & DSI_STATUS_IDLE) | |
654 | return 0; | |
655 | ||
656 | usleep_range(1000, 2000); | |
657 | } | |
658 | ||
659 | return -ETIMEDOUT; | |
660 | } | |
661 | ||
662 | static void tegra_dsi_video_disable(struct tegra_dsi *dsi) | |
663 | { | |
664 | u32 value; | |
665 | ||
666 | value = tegra_dsi_readl(dsi, DSI_CONTROL); | |
667 | value &= ~DSI_CONTROL_VIDEO_ENABLE; | |
668 | tegra_dsi_writel(dsi, value, DSI_CONTROL); | |
e94236cd TR |
669 | |
670 | if (dsi->slave) | |
671 | tegra_dsi_video_disable(dsi->slave); | |
672 | } | |
673 | ||
674 | static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi) | |
675 | { | |
676 | tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START); | |
677 | tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE); | |
678 | tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL); | |
563eff1f TR |
679 | } |
680 | ||
ef8187d7 TR |
681 | static int tegra_dsi_pad_enable(struct tegra_dsi *dsi) |
682 | { | |
683 | u32 value; | |
684 | ||
685 | value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0); | |
686 | tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); | |
687 | ||
688 | return 0; | |
689 | } | |
690 | ||
691 | static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi) | |
692 | { | |
693 | u32 value; | |
694 | ||
695 | /* | |
696 | * XXX Is this still needed? The module reset is deasserted right | |
697 | * before this function is called. | |
698 | */ | |
699 | tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0); | |
700 | tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1); | |
701 | tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2); | |
702 | tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3); | |
703 | tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4); | |
704 | ||
705 | /* start calibration */ | |
706 | tegra_dsi_pad_enable(dsi); | |
707 | ||
708 | value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) | | |
709 | DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) | | |
710 | DSI_PAD_OUT_CLK(0x0); | |
711 | tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2); | |
712 | ||
713 | value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | | |
714 | DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3); | |
715 | tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3); | |
716 | ||
717 | return tegra_mipi_calibrate(dsi->mipi); | |
718 | } | |
719 | ||
5b901e78 TR |
720 | static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk, |
721 | unsigned int vrefresh) | |
722 | { | |
723 | unsigned int timeout; | |
724 | u32 value; | |
725 | ||
726 | /* one frame high-speed transmission timeout */ | |
727 | timeout = (bclk / vrefresh) / 512; | |
728 | value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout); | |
729 | tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0); | |
730 | ||
731 | /* 2 ms peripheral timeout for panel */ | |
732 | timeout = 2 * bclk / 512 * 1000; | |
733 | value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000); | |
734 | tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1); | |
735 | ||
736 | value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0); | |
737 | tegra_dsi_writel(dsi, value, DSI_TO_TALLY); | |
738 | ||
739 | if (dsi->slave) | |
740 | tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh); | |
741 | } | |
742 | ||
563eff1f TR |
743 | static void tegra_dsi_disable(struct tegra_dsi *dsi) |
744 | { | |
745 | u32 value; | |
746 | ||
e94236cd TR |
747 | if (dsi->slave) { |
748 | tegra_dsi_ganged_disable(dsi->slave); | |
749 | tegra_dsi_ganged_disable(dsi); | |
750 | } | |
751 | ||
563eff1f TR |
752 | value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); |
753 | value &= ~DSI_POWER_CONTROL_ENABLE; | |
754 | tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); | |
755 | ||
e94236cd TR |
756 | if (dsi->slave) |
757 | tegra_dsi_disable(dsi->slave); | |
758 | ||
563eff1f TR |
759 | usleep_range(5000, 10000); |
760 | } | |
761 | ||
92f0e073 TR |
762 | static void tegra_dsi_soft_reset(struct tegra_dsi *dsi) |
763 | { | |
764 | u32 value; | |
765 | ||
766 | value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); | |
767 | value &= ~DSI_POWER_CONTROL_ENABLE; | |
768 | tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); | |
769 | ||
770 | usleep_range(300, 1000); | |
771 | ||
772 | value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); | |
773 | value |= DSI_POWER_CONTROL_ENABLE; | |
774 | tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); | |
775 | ||
776 | usleep_range(300, 1000); | |
777 | ||
778 | value = tegra_dsi_readl(dsi, DSI_TRIGGER); | |
779 | if (value) | |
780 | tegra_dsi_writel(dsi, 0, DSI_TRIGGER); | |
781 | ||
782 | if (dsi->slave) | |
783 | tegra_dsi_soft_reset(dsi->slave); | |
784 | } | |
785 | ||
ebd14afe TR |
786 | static void tegra_dsi_connector_reset(struct drm_connector *connector) |
787 | { | |
280dc0e1 | 788 | struct tegra_dsi_state *state = kzalloc(sizeof(*state), GFP_KERNEL); |
ebd14afe | 789 | |
280dc0e1 JH |
790 | if (!state) |
791 | return; | |
792 | ||
793 | if (connector->state) { | |
794 | __drm_atomic_helper_connector_destroy_state(connector->state); | |
5459a2ad | 795 | kfree(connector->state); |
5459a2ad | 796 | } |
280dc0e1 JH |
797 | |
798 | __drm_atomic_helper_connector_reset(connector, &state->base); | |
ebd14afe TR |
799 | } |
800 | ||
801 | static struct drm_connector_state * | |
802 | tegra_dsi_connector_duplicate_state(struct drm_connector *connector) | |
803 | { | |
804 | struct tegra_dsi_state *state = to_dsi_state(connector->state); | |
805 | struct tegra_dsi_state *copy; | |
806 | ||
807 | copy = kmemdup(state, sizeof(*state), GFP_KERNEL); | |
808 | if (!copy) | |
809 | return NULL; | |
810 | ||
280dc0e1 JH |
811 | __drm_atomic_helper_connector_duplicate_state(connector, |
812 | ©->base); | |
813 | ||
ebd14afe TR |
814 | return ©->base; |
815 | } | |
816 | ||
5b901e78 | 817 | static const struct drm_connector_funcs tegra_dsi_connector_funcs = { |
171e2e6d | 818 | .dpms = drm_atomic_helper_connector_dpms, |
ebd14afe | 819 | .reset = tegra_dsi_connector_reset, |
5b901e78 TR |
820 | .detect = tegra_output_connector_detect, |
821 | .fill_modes = drm_helper_probe_single_connector_modes, | |
822 | .destroy = tegra_output_connector_destroy, | |
ebd14afe | 823 | .atomic_duplicate_state = tegra_dsi_connector_duplicate_state, |
4aa3df71 | 824 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
5b901e78 | 825 | }; |
3f6b406f | 826 | |
5b901e78 TR |
827 | static enum drm_mode_status |
828 | tegra_dsi_connector_mode_valid(struct drm_connector *connector, | |
829 | struct drm_display_mode *mode) | |
830 | { | |
831 | return MODE_OK; | |
832 | } | |
3f6b406f | 833 | |
5b901e78 TR |
834 | static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs = { |
835 | .get_modes = tegra_output_connector_get_modes, | |
836 | .mode_valid = tegra_dsi_connector_mode_valid, | |
5b901e78 | 837 | }; |
3f6b406f | 838 | |
5b901e78 TR |
839 | static const struct drm_encoder_funcs tegra_dsi_encoder_funcs = { |
840 | .destroy = tegra_output_encoder_destroy, | |
841 | }; | |
e94236cd | 842 | |
87904c3e TR |
843 | static void tegra_dsi_unprepare(struct tegra_dsi *dsi) |
844 | { | |
845 | int err; | |
846 | ||
847 | if (dsi->slave) | |
848 | tegra_dsi_unprepare(dsi->slave); | |
849 | ||
850 | err = tegra_mipi_disable(dsi->mipi); | |
851 | if (err < 0) | |
852 | dev_err(dsi->dev, "failed to disable MIPI calibration: %d\n", | |
853 | err); | |
854 | ||
855 | pm_runtime_put(dsi->dev); | |
856 | } | |
857 | ||
171e2e6d | 858 | static void tegra_dsi_encoder_disable(struct drm_encoder *encoder) |
5b901e78 | 859 | { |
171e2e6d TR |
860 | struct tegra_output *output = encoder_to_output(encoder); |
861 | struct tegra_dc *dc = to_tegra_dc(encoder->crtc); | |
862 | struct tegra_dsi *dsi = to_dsi(output); | |
863 | u32 value; | |
864 | int err; | |
3f6b406f | 865 | |
171e2e6d TR |
866 | if (output->panel) |
867 | drm_panel_disable(output->panel); | |
5b901e78 | 868 | |
171e2e6d TR |
869 | tegra_dsi_video_disable(dsi); |
870 | ||
871 | /* | |
872 | * The following accesses registers of the display controller, so make | |
873 | * sure it's only executed when the output is attached to one. | |
874 | */ | |
875 | if (dc) { | |
876 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); | |
877 | value &= ~DSI_ENABLE; | |
878 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); | |
879 | ||
880 | tegra_dc_commit(dc); | |
881 | } | |
882 | ||
883 | err = tegra_dsi_wait_idle(dsi, 100); | |
884 | if (err < 0) | |
885 | dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err); | |
886 | ||
887 | tegra_dsi_soft_reset(dsi); | |
888 | ||
889 | if (output->panel) | |
890 | drm_panel_unprepare(output->panel); | |
891 | ||
892 | tegra_dsi_disable(dsi); | |
893 | ||
87904c3e TR |
894 | tegra_dsi_unprepare(dsi); |
895 | } | |
896 | ||
897 | static void tegra_dsi_prepare(struct tegra_dsi *dsi) | |
898 | { | |
899 | int err; | |
900 | ||
901 | pm_runtime_get_sync(dsi->dev); | |
902 | ||
903 | err = tegra_mipi_enable(dsi->mipi); | |
904 | if (err < 0) | |
905 | dev_err(dsi->dev, "failed to enable MIPI calibration: %d\n", | |
906 | err); | |
907 | ||
908 | err = tegra_dsi_pad_calibrate(dsi); | |
909 | if (err < 0) | |
910 | dev_err(dsi->dev, "MIPI calibration failed: %d\n", err); | |
911 | ||
912 | if (dsi->slave) | |
913 | tegra_dsi_prepare(dsi->slave); | |
dec72739 TR |
914 | } |
915 | ||
171e2e6d | 916 | static void tegra_dsi_encoder_enable(struct drm_encoder *encoder) |
5b901e78 | 917 | { |
171e2e6d | 918 | struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; |
5b901e78 TR |
919 | struct tegra_output *output = encoder_to_output(encoder); |
920 | struct tegra_dc *dc = to_tegra_dc(encoder->crtc); | |
921 | struct tegra_dsi *dsi = to_dsi(output); | |
ebd14afe | 922 | struct tegra_dsi_state *state; |
5b901e78 | 923 | u32 value; |
ef8187d7 | 924 | |
87904c3e | 925 | tegra_dsi_prepare(dsi); |
5b901e78 | 926 | |
ebd14afe | 927 | state = tegra_dsi_get_state(dsi); |
5b901e78 | 928 | |
ebd14afe TR |
929 | tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh); |
930 | ||
931 | /* | |
932 | * The D-PHY timing fields are expressed in byte-clock cycles, so | |
933 | * multiply the period by 8. | |
934 | */ | |
935 | tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing); | |
5b901e78 TR |
936 | |
937 | if (output->panel) | |
938 | drm_panel_prepare(output->panel); | |
939 | ||
ebd14afe TR |
940 | tegra_dsi_configure(dsi, dc->pipe, mode); |
941 | ||
5b901e78 TR |
942 | /* enable display controller */ |
943 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); | |
944 | value |= DSI_ENABLE; | |
945 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); | |
946 | ||
5b901e78 TR |
947 | tegra_dc_commit(dc); |
948 | ||
949 | /* enable DSI controller */ | |
950 | tegra_dsi_enable(dsi); | |
951 | ||
952 | if (output->panel) | |
953 | drm_panel_enable(output->panel); | |
5b901e78 TR |
954 | } |
955 | ||
ebd14afe TR |
956 | static int |
957 | tegra_dsi_encoder_atomic_check(struct drm_encoder *encoder, | |
958 | struct drm_crtc_state *crtc_state, | |
959 | struct drm_connector_state *conn_state) | |
960 | { | |
961 | struct tegra_output *output = encoder_to_output(encoder); | |
962 | struct tegra_dsi_state *state = to_dsi_state(conn_state); | |
963 | struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); | |
964 | struct tegra_dsi *dsi = to_dsi(output); | |
965 | unsigned int scdiv; | |
966 | unsigned long plld; | |
967 | int err; | |
968 | ||
969 | state->pclk = crtc_state->mode.clock * 1000; | |
970 | ||
971 | err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div); | |
972 | if (err < 0) | |
973 | return err; | |
974 | ||
975 | state->lanes = tegra_dsi_get_lanes(dsi); | |
976 | ||
977 | err = tegra_dsi_get_format(dsi->format, &state->format); | |
978 | if (err < 0) | |
979 | return err; | |
980 | ||
981 | state->vrefresh = drm_mode_vrefresh(&crtc_state->mode); | |
982 | ||
983 | /* compute byte clock */ | |
984 | state->bclk = (state->pclk * state->mul) / (state->div * state->lanes); | |
985 | ||
986 | DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div, | |
987 | state->lanes); | |
988 | DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state->format, | |
989 | state->vrefresh); | |
990 | DRM_DEBUG_KMS("bclk: %lu\n", state->bclk); | |
991 | ||
992 | /* | |
993 | * Compute bit clock and round up to the next MHz. | |
994 | */ | |
995 | plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC; | |
996 | state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld); | |
997 | ||
998 | err = mipi_dphy_timing_get_default(&state->timing, state->period); | |
999 | if (err < 0) | |
1000 | return err; | |
1001 | ||
1002 | err = mipi_dphy_timing_validate(&state->timing, state->period); | |
1003 | if (err < 0) { | |
1004 | dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err); | |
1005 | return err; | |
1006 | } | |
1007 | ||
1008 | /* | |
1009 | * We divide the frequency by two here, but we make up for that by | |
1010 | * setting the shift clock divider (further below) to half of the | |
1011 | * correct value. | |
1012 | */ | |
1013 | plld /= 2; | |
1014 | ||
1015 | /* | |
1016 | * Derive pixel clock from bit clock using the shift clock divider. | |
1017 | * Note that this is only half of what we would expect, but we need | |
1018 | * that to make up for the fact that we divided the bit clock by a | |
1019 | * factor of two above. | |
1020 | * | |
1021 | * It's not clear exactly why this is necessary, but the display is | |
1022 | * not working properly otherwise. Perhaps the PLLs cannot generate | |
1023 | * frequencies sufficiently high. | |
1024 | */ | |
1025 | scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2; | |
1026 | ||
1027 | err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent, | |
1028 | plld, scdiv); | |
1029 | if (err < 0) { | |
1030 | dev_err(output->dev, "failed to setup CRTC state: %d\n", err); | |
1031 | return err; | |
1032 | } | |
1033 | ||
1034 | return err; | |
1035 | } | |
1036 | ||
5b901e78 | 1037 | static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = { |
5b901e78 | 1038 | .disable = tegra_dsi_encoder_disable, |
171e2e6d | 1039 | .enable = tegra_dsi_encoder_enable, |
ebd14afe | 1040 | .atomic_check = tegra_dsi_encoder_atomic_check, |
dec72739 TR |
1041 | }; |
1042 | ||
dec72739 TR |
1043 | static int tegra_dsi_init(struct host1x_client *client) |
1044 | { | |
9910f5c4 | 1045 | struct drm_device *drm = dev_get_drvdata(client->parent); |
dec72739 | 1046 | struct tegra_dsi *dsi = host1x_client_to_dsi(client); |
dec72739 TR |
1047 | int err; |
1048 | ||
e94236cd TR |
1049 | /* Gangsters must not register their own outputs. */ |
1050 | if (!dsi->master) { | |
e94236cd | 1051 | dsi->output.dev = client->dev; |
e94236cd | 1052 | |
5b901e78 TR |
1053 | drm_connector_init(drm, &dsi->output.connector, |
1054 | &tegra_dsi_connector_funcs, | |
1055 | DRM_MODE_CONNECTOR_DSI); | |
1056 | drm_connector_helper_add(&dsi->output.connector, | |
1057 | &tegra_dsi_connector_helper_funcs); | |
1058 | dsi->output.connector.dpms = DRM_MODE_DPMS_OFF; | |
1059 | ||
5b901e78 TR |
1060 | drm_encoder_init(drm, &dsi->output.encoder, |
1061 | &tegra_dsi_encoder_funcs, | |
13a3d91f | 1062 | DRM_MODE_ENCODER_DSI, NULL); |
5b901e78 TR |
1063 | drm_encoder_helper_add(&dsi->output.encoder, |
1064 | &tegra_dsi_encoder_helper_funcs); | |
1065 | ||
1066 | drm_mode_connector_attach_encoder(&dsi->output.connector, | |
1067 | &dsi->output.encoder); | |
1068 | drm_connector_register(&dsi->output.connector); | |
1069 | ||
ea130b24 | 1070 | err = tegra_output_init(drm, &dsi->output); |
ef8187d7 TR |
1071 | if (err < 0) |
1072 | dev_err(dsi->dev, "failed to initialize output: %d\n", | |
ea130b24 | 1073 | err); |
ea130b24 | 1074 | |
5b901e78 | 1075 | dsi->output.encoder.possible_crtcs = 0x3; |
dec72739 TR |
1076 | } |
1077 | ||
1078 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { | |
9910f5c4 | 1079 | err = tegra_dsi_debugfs_init(dsi, drm->primary); |
dec72739 TR |
1080 | if (err < 0) |
1081 | dev_err(dsi->dev, "debugfs setup failed: %d\n", err); | |
1082 | } | |
1083 | ||
dec72739 TR |
1084 | return 0; |
1085 | } | |
1086 | ||
1087 | static int tegra_dsi_exit(struct host1x_client *client) | |
1088 | { | |
1089 | struct tegra_dsi *dsi = host1x_client_to_dsi(client); | |
dec72739 | 1090 | |
5b901e78 TR |
1091 | tegra_output_exit(&dsi->output); |
1092 | ||
4009c224 TR |
1093 | if (IS_ENABLED(CONFIG_DEBUG_FS)) |
1094 | tegra_dsi_debugfs_exit(dsi); | |
dec72739 | 1095 | |
ef8187d7 | 1096 | regulator_disable(dsi->vdd); |
201106d8 | 1097 | |
dec72739 TR |
1098 | return 0; |
1099 | } | |
1100 | ||
1101 | static const struct host1x_client_ops dsi_client_ops = { | |
1102 | .init = tegra_dsi_init, | |
1103 | .exit = tegra_dsi_exit, | |
1104 | }; | |
1105 | ||
1106 | static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi) | |
1107 | { | |
1108 | struct clk *parent; | |
1109 | int err; | |
1110 | ||
1111 | parent = clk_get_parent(dsi->clk); | |
1112 | if (!parent) | |
1113 | return -EINVAL; | |
1114 | ||
1115 | err = clk_set_parent(parent, dsi->clk_parent); | |
1116 | if (err < 0) | |
1117 | return err; | |
1118 | ||
1119 | return 0; | |
1120 | } | |
1121 | ||
0fffdf6c TR |
1122 | static const char * const error_report[16] = { |
1123 | "SoT Error", | |
1124 | "SoT Sync Error", | |
1125 | "EoT Sync Error", | |
1126 | "Escape Mode Entry Command Error", | |
1127 | "Low-Power Transmit Sync Error", | |
1128 | "Peripheral Timeout Error", | |
1129 | "False Control Error", | |
1130 | "Contention Detected", | |
1131 | "ECC Error, single-bit", | |
1132 | "ECC Error, multi-bit", | |
1133 | "Checksum Error", | |
1134 | "DSI Data Type Not Recognized", | |
1135 | "DSI VC ID Invalid", | |
1136 | "Invalid Transmission Length", | |
1137 | "Reserved", | |
1138 | "DSI Protocol Violation", | |
1139 | }; | |
1140 | ||
1141 | static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi, | |
1142 | const struct mipi_dsi_msg *msg, | |
1143 | size_t count) | |
1144 | { | |
1145 | u8 *rx = msg->rx_buf; | |
1146 | unsigned int i, j, k; | |
1147 | size_t size = 0; | |
1148 | u16 errors; | |
1149 | u32 value; | |
1150 | ||
1151 | /* read and parse packet header */ | |
1152 | value = tegra_dsi_readl(dsi, DSI_RD_DATA); | |
1153 | ||
1154 | switch (value & 0x3f) { | |
1155 | case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: | |
1156 | errors = (value >> 8) & 0xffff; | |
1157 | dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n", | |
1158 | errors); | |
1159 | for (i = 0; i < ARRAY_SIZE(error_report); i++) | |
1160 | if (errors & BIT(i)) | |
1161 | dev_dbg(dsi->dev, " %2u: %s\n", i, | |
1162 | error_report[i]); | |
1163 | break; | |
1164 | ||
1165 | case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: | |
1166 | rx[0] = (value >> 8) & 0xff; | |
1167 | size = 1; | |
1168 | break; | |
1169 | ||
1170 | case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: | |
1171 | rx[0] = (value >> 8) & 0xff; | |
1172 | rx[1] = (value >> 16) & 0xff; | |
1173 | size = 2; | |
1174 | break; | |
1175 | ||
1176 | case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: | |
1177 | size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff); | |
1178 | break; | |
1179 | ||
1180 | case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: | |
1181 | size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff); | |
1182 | break; | |
1183 | ||
1184 | default: | |
1185 | dev_err(dsi->dev, "unhandled response type: %02x\n", | |
1186 | value & 0x3f); | |
1187 | return -EPROTO; | |
1188 | } | |
1189 | ||
1190 | size = min(size, msg->rx_len); | |
1191 | ||
1192 | if (msg->rx_buf && size > 0) { | |
1193 | for (i = 0, j = 0; i < count - 1; i++, j += 4) { | |
1194 | u8 *rx = msg->rx_buf + j; | |
1195 | ||
1196 | value = tegra_dsi_readl(dsi, DSI_RD_DATA); | |
1197 | ||
1198 | for (k = 0; k < 4 && (j + k) < msg->rx_len; k++) | |
1199 | rx[j + k] = (value >> (k << 3)) & 0xff; | |
1200 | } | |
1201 | } | |
1202 | ||
1203 | return size; | |
1204 | } | |
1205 | ||
1206 | static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout) | |
1207 | { | |
1208 | tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER); | |
1209 | ||
1210 | timeout = jiffies + msecs_to_jiffies(timeout); | |
1211 | ||
1212 | while (time_before(jiffies, timeout)) { | |
1213 | u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER); | |
1214 | if ((value & DSI_TRIGGER_HOST) == 0) | |
1215 | return 0; | |
1216 | ||
1217 | usleep_range(1000, 2000); | |
1218 | } | |
1219 | ||
1220 | DRM_DEBUG_KMS("timeout waiting for transmission to complete\n"); | |
1221 | return -ETIMEDOUT; | |
1222 | } | |
1223 | ||
1224 | static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi, | |
1225 | unsigned long timeout) | |
1226 | { | |
1227 | timeout = jiffies + msecs_to_jiffies(250); | |
1228 | ||
1229 | while (time_before(jiffies, timeout)) { | |
1230 | u32 value = tegra_dsi_readl(dsi, DSI_STATUS); | |
1231 | u8 count = value & 0x1f; | |
1232 | ||
1233 | if (count > 0) | |
1234 | return count; | |
1235 | ||
1236 | usleep_range(1000, 2000); | |
1237 | } | |
1238 | ||
1239 | DRM_DEBUG_KMS("peripheral returned no data\n"); | |
1240 | return -ETIMEDOUT; | |
1241 | } | |
1242 | ||
1243 | static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset, | |
1244 | const void *buffer, size_t size) | |
1245 | { | |
1246 | const u8 *buf = buffer; | |
1247 | size_t i, j; | |
1248 | u32 value; | |
1249 | ||
1250 | for (j = 0; j < size; j += 4) { | |
1251 | value = 0; | |
1252 | ||
1253 | for (i = 0; i < 4 && j + i < size; i++) | |
1254 | value |= buf[j + i] << (i << 3); | |
1255 | ||
1256 | tegra_dsi_writel(dsi, value, DSI_WR_DATA); | |
1257 | } | |
1258 | } | |
1259 | ||
1260 | static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host, | |
1261 | const struct mipi_dsi_msg *msg) | |
1262 | { | |
1263 | struct tegra_dsi *dsi = host_to_tegra(host); | |
1264 | struct mipi_dsi_packet packet; | |
1265 | const u8 *header; | |
1266 | size_t count; | |
1267 | ssize_t err; | |
1268 | u32 value; | |
1269 | ||
1270 | err = mipi_dsi_create_packet(&packet, msg); | |
1271 | if (err < 0) | |
1272 | return err; | |
1273 | ||
1274 | header = packet.header; | |
1275 | ||
1276 | /* maximum FIFO depth is 1920 words */ | |
1277 | if (packet.size > dsi->video_fifo_depth * 4) | |
1278 | return -ENOSPC; | |
1279 | ||
1280 | /* reset underflow/overflow flags */ | |
1281 | value = tegra_dsi_readl(dsi, DSI_STATUS); | |
1282 | if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) { | |
1283 | value = DSI_HOST_CONTROL_FIFO_RESET; | |
1284 | tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); | |
1285 | usleep_range(10, 20); | |
1286 | } | |
1287 | ||
1288 | value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); | |
1289 | value |= DSI_POWER_CONTROL_ENABLE; | |
1290 | tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); | |
1291 | ||
1292 | usleep_range(5000, 10000); | |
1293 | ||
1294 | value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | | |
1295 | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC; | |
1296 | ||
1297 | if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0) | |
1298 | value |= DSI_HOST_CONTROL_HS; | |
1299 | ||
1300 | /* | |
1301 | * The host FIFO has a maximum of 64 words, so larger transmissions | |
1302 | * need to use the video FIFO. | |
1303 | */ | |
1304 | if (packet.size > dsi->host_fifo_depth * 4) | |
1305 | value |= DSI_HOST_CONTROL_FIFO_SEL; | |
1306 | ||
1307 | tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); | |
1308 | ||
1309 | /* | |
1310 | * For reads and messages with explicitly requested ACK, generate a | |
1311 | * BTA sequence after the transmission of the packet. | |
1312 | */ | |
1313 | if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) || | |
1314 | (msg->rx_buf && msg->rx_len > 0)) { | |
1315 | value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL); | |
1316 | value |= DSI_HOST_CONTROL_PKT_BTA; | |
1317 | tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); | |
1318 | } | |
1319 | ||
1320 | value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE; | |
1321 | tegra_dsi_writel(dsi, value, DSI_CONTROL); | |
1322 | ||
1323 | /* write packet header, ECC is generated by hardware */ | |
1324 | value = header[2] << 16 | header[1] << 8 | header[0]; | |
1325 | tegra_dsi_writel(dsi, value, DSI_WR_DATA); | |
1326 | ||
1327 | /* write payload (if any) */ | |
1328 | if (packet.payload_length > 0) | |
1329 | tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload, | |
1330 | packet.payload_length); | |
1331 | ||
1332 | err = tegra_dsi_transmit(dsi, 250); | |
1333 | if (err < 0) | |
1334 | return err; | |
1335 | ||
1336 | if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) || | |
1337 | (msg->rx_buf && msg->rx_len > 0)) { | |
1338 | err = tegra_dsi_wait_for_response(dsi, 250); | |
1339 | if (err < 0) | |
1340 | return err; | |
1341 | ||
1342 | count = err; | |
1343 | ||
1344 | value = tegra_dsi_readl(dsi, DSI_RD_DATA); | |
1345 | switch (value) { | |
1346 | case 0x84: | |
1347 | /* | |
1348 | dev_dbg(dsi->dev, "ACK\n"); | |
1349 | */ | |
1350 | break; | |
1351 | ||
1352 | case 0x87: | |
1353 | /* | |
1354 | dev_dbg(dsi->dev, "ESCAPE\n"); | |
1355 | */ | |
1356 | break; | |
1357 | ||
1358 | default: | |
1359 | dev_err(dsi->dev, "unknown status: %08x\n", value); | |
1360 | break; | |
1361 | } | |
1362 | ||
1363 | if (count > 1) { | |
1364 | err = tegra_dsi_read_response(dsi, msg, count); | |
1365 | if (err < 0) | |
1366 | dev_err(dsi->dev, | |
1367 | "failed to parse response: %zd\n", | |
1368 | err); | |
1369 | else { | |
1370 | /* | |
1371 | * For read commands, return the number of | |
1372 | * bytes returned by the peripheral. | |
1373 | */ | |
1374 | count = err; | |
1375 | } | |
1376 | } | |
1377 | } else { | |
1378 | /* | |
1379 | * For write commands, we have transmitted the 4-byte header | |
1380 | * plus the variable-length payload. | |
1381 | */ | |
1382 | count = 4 + packet.payload_length; | |
1383 | } | |
1384 | ||
1385 | return count; | |
1386 | } | |
1387 | ||
e94236cd TR |
1388 | static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi) |
1389 | { | |
1390 | struct clk *parent; | |
1391 | int err; | |
1392 | ||
1393 | /* make sure both DSI controllers share the same PLL */ | |
1394 | parent = clk_get_parent(dsi->slave->clk); | |
1395 | if (!parent) | |
1396 | return -EINVAL; | |
1397 | ||
1398 | err = clk_set_parent(parent, dsi->clk_parent); | |
1399 | if (err < 0) | |
1400 | return err; | |
1401 | ||
1402 | return 0; | |
1403 | } | |
1404 | ||
dec72739 TR |
1405 | static int tegra_dsi_host_attach(struct mipi_dsi_host *host, |
1406 | struct mipi_dsi_device *device) | |
1407 | { | |
1408 | struct tegra_dsi *dsi = host_to_tegra(host); | |
dec72739 | 1409 | |
17297a28 | 1410 | dsi->flags = device->mode_flags; |
dec72739 TR |
1411 | dsi->format = device->format; |
1412 | dsi->lanes = device->lanes; | |
1413 | ||
e94236cd TR |
1414 | if (dsi->slave) { |
1415 | int err; | |
1416 | ||
1417 | dev_dbg(dsi->dev, "attaching dual-channel device %s\n", | |
1418 | dev_name(&device->dev)); | |
1419 | ||
1420 | err = tegra_dsi_ganged_setup(dsi); | |
1421 | if (err < 0) { | |
1422 | dev_err(dsi->dev, "failed to set up ganged mode: %d\n", | |
1423 | err); | |
1424 | return err; | |
1425 | } | |
1426 | } | |
1427 | ||
1428 | /* | |
1429 | * Slaves don't have a panel associated with them, so they provide | |
1430 | * merely the second channel. | |
1431 | */ | |
1432 | if (!dsi->master) { | |
1433 | struct tegra_output *output = &dsi->output; | |
1434 | ||
1435 | output->panel = of_drm_find_panel(device->dev.of_node); | |
1436 | if (output->panel && output->connector.dev) { | |
1437 | drm_panel_attach(output->panel, &output->connector); | |
dec72739 | 1438 | drm_helper_hpd_irq_event(output->connector.dev); |
e94236cd | 1439 | } |
dec72739 TR |
1440 | } |
1441 | ||
1442 | return 0; | |
1443 | } | |
1444 | ||
1445 | static int tegra_dsi_host_detach(struct mipi_dsi_host *host, | |
1446 | struct mipi_dsi_device *device) | |
1447 | { | |
1448 | struct tegra_dsi *dsi = host_to_tegra(host); | |
1449 | struct tegra_output *output = &dsi->output; | |
1450 | ||
1451 | if (output->panel && &device->dev == output->panel->dev) { | |
ba3df979 TR |
1452 | output->panel = NULL; |
1453 | ||
dec72739 TR |
1454 | if (output->connector.dev) |
1455 | drm_helper_hpd_irq_event(output->connector.dev); | |
dec72739 TR |
1456 | } |
1457 | ||
1458 | return 0; | |
1459 | } | |
1460 | ||
1461 | static const struct mipi_dsi_host_ops tegra_dsi_host_ops = { | |
1462 | .attach = tegra_dsi_host_attach, | |
1463 | .detach = tegra_dsi_host_detach, | |
0fffdf6c | 1464 | .transfer = tegra_dsi_host_transfer, |
dec72739 TR |
1465 | }; |
1466 | ||
e94236cd TR |
1467 | static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi) |
1468 | { | |
1469 | struct device_node *np; | |
1470 | ||
1471 | np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0); | |
1472 | if (np) { | |
1473 | struct platform_device *gangster = of_find_device_by_node(np); | |
1474 | ||
1475 | dsi->slave = platform_get_drvdata(gangster); | |
1476 | of_node_put(np); | |
1477 | ||
1478 | if (!dsi->slave) | |
1479 | return -EPROBE_DEFER; | |
1480 | ||
1481 | dsi->slave->master = dsi; | |
1482 | } | |
1483 | ||
1484 | return 0; | |
1485 | } | |
1486 | ||
dec72739 TR |
1487 | static int tegra_dsi_probe(struct platform_device *pdev) |
1488 | { | |
1489 | struct tegra_dsi *dsi; | |
1490 | struct resource *regs; | |
1491 | int err; | |
1492 | ||
1493 | dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL); | |
1494 | if (!dsi) | |
1495 | return -ENOMEM; | |
1496 | ||
1497 | dsi->output.dev = dsi->dev = &pdev->dev; | |
976cebc3 TR |
1498 | dsi->video_fifo_depth = 1920; |
1499 | dsi->host_fifo_depth = 64; | |
dec72739 | 1500 | |
e94236cd TR |
1501 | err = tegra_dsi_ganged_probe(dsi); |
1502 | if (err < 0) | |
1503 | return err; | |
1504 | ||
dec72739 TR |
1505 | err = tegra_output_probe(&dsi->output); |
1506 | if (err < 0) | |
1507 | return err; | |
1508 | ||
ba3df979 TR |
1509 | dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD; |
1510 | ||
dec72739 TR |
1511 | /* |
1512 | * Assume these values by default. When a DSI peripheral driver | |
1513 | * attaches to the DSI host, the parameters will be taken from | |
1514 | * the attached device. | |
1515 | */ | |
17297a28 | 1516 | dsi->flags = MIPI_DSI_MODE_VIDEO; |
dec72739 TR |
1517 | dsi->format = MIPI_DSI_FMT_RGB888; |
1518 | dsi->lanes = 4; | |
1519 | ||
64230aa0 JH |
1520 | if (!pdev->dev.pm_domain) { |
1521 | dsi->rst = devm_reset_control_get(&pdev->dev, "dsi"); | |
1522 | if (IS_ERR(dsi->rst)) | |
1523 | return PTR_ERR(dsi->rst); | |
1524 | } | |
dec72739 TR |
1525 | |
1526 | dsi->clk = devm_clk_get(&pdev->dev, NULL); | |
1527 | if (IS_ERR(dsi->clk)) { | |
1528 | dev_err(&pdev->dev, "cannot get DSI clock\n"); | |
ef8187d7 | 1529 | return PTR_ERR(dsi->clk); |
dec72739 TR |
1530 | } |
1531 | ||
1532 | dsi->clk_lp = devm_clk_get(&pdev->dev, "lp"); | |
1533 | if (IS_ERR(dsi->clk_lp)) { | |
1534 | dev_err(&pdev->dev, "cannot get low-power clock\n"); | |
ef8187d7 | 1535 | return PTR_ERR(dsi->clk_lp); |
dec72739 TR |
1536 | } |
1537 | ||
1538 | dsi->clk_parent = devm_clk_get(&pdev->dev, "parent"); | |
1539 | if (IS_ERR(dsi->clk_parent)) { | |
1540 | dev_err(&pdev->dev, "cannot get parent clock\n"); | |
ef8187d7 | 1541 | return PTR_ERR(dsi->clk_parent); |
dec72739 TR |
1542 | } |
1543 | ||
3b077afb TR |
1544 | dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi"); |
1545 | if (IS_ERR(dsi->vdd)) { | |
1546 | dev_err(&pdev->dev, "cannot get VDD supply\n"); | |
ef8187d7 | 1547 | return PTR_ERR(dsi->vdd); |
3b077afb TR |
1548 | } |
1549 | ||
dec72739 TR |
1550 | err = tegra_dsi_setup_clocks(dsi); |
1551 | if (err < 0) { | |
1552 | dev_err(&pdev->dev, "cannot setup clocks\n"); | |
ef8187d7 | 1553 | return err; |
dec72739 TR |
1554 | } |
1555 | ||
1556 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1557 | dsi->regs = devm_ioremap_resource(&pdev->dev, regs); | |
ef8187d7 TR |
1558 | if (IS_ERR(dsi->regs)) |
1559 | return PTR_ERR(dsi->regs); | |
dec72739 | 1560 | |
dec72739 | 1561 | dsi->mipi = tegra_mipi_request(&pdev->dev); |
ef8187d7 TR |
1562 | if (IS_ERR(dsi->mipi)) |
1563 | return PTR_ERR(dsi->mipi); | |
dec72739 TR |
1564 | |
1565 | dsi->host.ops = &tegra_dsi_host_ops; | |
1566 | dsi->host.dev = &pdev->dev; | |
1567 | ||
1568 | err = mipi_dsi_host_register(&dsi->host); | |
1569 | if (err < 0) { | |
1570 | dev_err(&pdev->dev, "failed to register DSI host: %d\n", err); | |
d2d0a9d2 | 1571 | goto mipi_free; |
dec72739 TR |
1572 | } |
1573 | ||
ef8187d7 TR |
1574 | platform_set_drvdata(pdev, dsi); |
1575 | pm_runtime_enable(&pdev->dev); | |
1576 | ||
dec72739 TR |
1577 | INIT_LIST_HEAD(&dsi->client.list); |
1578 | dsi->client.ops = &dsi_client_ops; | |
1579 | dsi->client.dev = &pdev->dev; | |
1580 | ||
1581 | err = host1x_client_register(&dsi->client); | |
1582 | if (err < 0) { | |
1583 | dev_err(&pdev->dev, "failed to register host1x client: %d\n", | |
1584 | err); | |
d2d0a9d2 | 1585 | goto unregister; |
dec72739 TR |
1586 | } |
1587 | ||
dec72739 | 1588 | return 0; |
d2d0a9d2 TR |
1589 | |
1590 | unregister: | |
1591 | mipi_dsi_host_unregister(&dsi->host); | |
1592 | mipi_free: | |
1593 | tegra_mipi_free(dsi->mipi); | |
d2d0a9d2 | 1594 | return err; |
dec72739 TR |
1595 | } |
1596 | ||
1597 | static int tegra_dsi_remove(struct platform_device *pdev) | |
1598 | { | |
1599 | struct tegra_dsi *dsi = platform_get_drvdata(pdev); | |
1600 | int err; | |
1601 | ||
ef8187d7 TR |
1602 | pm_runtime_disable(&pdev->dev); |
1603 | ||
dec72739 TR |
1604 | err = host1x_client_unregister(&dsi->client); |
1605 | if (err < 0) { | |
1606 | dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", | |
1607 | err); | |
1608 | return err; | |
1609 | } | |
1610 | ||
328ec69e | 1611 | tegra_output_remove(&dsi->output); |
5b901e78 | 1612 | |
dec72739 TR |
1613 | mipi_dsi_host_unregister(&dsi->host); |
1614 | tegra_mipi_free(dsi->mipi); | |
1615 | ||
ef8187d7 TR |
1616 | return 0; |
1617 | } | |
1618 | ||
1619 | #ifdef CONFIG_PM | |
1620 | static int tegra_dsi_suspend(struct device *dev) | |
1621 | { | |
1622 | struct tegra_dsi *dsi = dev_get_drvdata(dev); | |
1623 | int err; | |
1624 | ||
64230aa0 JH |
1625 | if (dsi->rst) { |
1626 | err = reset_control_assert(dsi->rst); | |
1627 | if (err < 0) { | |
1628 | dev_err(dev, "failed to assert reset: %d\n", err); | |
1629 | return err; | |
1630 | } | |
ef8187d7 TR |
1631 | } |
1632 | ||
1633 | usleep_range(1000, 2000); | |
1634 | ||
dec72739 TR |
1635 | clk_disable_unprepare(dsi->clk_lp); |
1636 | clk_disable_unprepare(dsi->clk); | |
ef8187d7 TR |
1637 | |
1638 | regulator_disable(dsi->vdd); | |
dec72739 | 1639 | |
dec72739 TR |
1640 | return 0; |
1641 | } | |
1642 | ||
ef8187d7 TR |
1643 | static int tegra_dsi_resume(struct device *dev) |
1644 | { | |
1645 | struct tegra_dsi *dsi = dev_get_drvdata(dev); | |
1646 | int err; | |
1647 | ||
1648 | err = regulator_enable(dsi->vdd); | |
1649 | if (err < 0) { | |
1650 | dev_err(dsi->dev, "failed to enable VDD supply: %d\n", err); | |
1651 | return err; | |
1652 | } | |
1653 | ||
1654 | err = clk_prepare_enable(dsi->clk); | |
1655 | if (err < 0) { | |
1656 | dev_err(dev, "cannot enable DSI clock: %d\n", err); | |
1657 | goto disable_vdd; | |
1658 | } | |
1659 | ||
1660 | err = clk_prepare_enable(dsi->clk_lp); | |
1661 | if (err < 0) { | |
1662 | dev_err(dev, "cannot enable low-power clock: %d\n", err); | |
1663 | goto disable_clk; | |
1664 | } | |
1665 | ||
1666 | usleep_range(1000, 2000); | |
1667 | ||
64230aa0 JH |
1668 | if (dsi->rst) { |
1669 | err = reset_control_deassert(dsi->rst); | |
1670 | if (err < 0) { | |
1671 | dev_err(dev, "cannot assert reset: %d\n", err); | |
1672 | goto disable_clk_lp; | |
1673 | } | |
ef8187d7 TR |
1674 | } |
1675 | ||
1676 | return 0; | |
1677 | ||
1678 | disable_clk_lp: | |
1679 | clk_disable_unprepare(dsi->clk_lp); | |
1680 | disable_clk: | |
1681 | clk_disable_unprepare(dsi->clk); | |
1682 | disable_vdd: | |
1683 | regulator_disable(dsi->vdd); | |
1684 | return err; | |
1685 | } | |
1686 | #endif | |
1687 | ||
1688 | static const struct dev_pm_ops tegra_dsi_pm_ops = { | |
1689 | SET_RUNTIME_PM_OPS(tegra_dsi_suspend, tegra_dsi_resume, NULL) | |
1690 | }; | |
1691 | ||
dec72739 | 1692 | static const struct of_device_id tegra_dsi_of_match[] = { |
ddfb406b | 1693 | { .compatible = "nvidia,tegra210-dsi", }, |
c06c7930 | 1694 | { .compatible = "nvidia,tegra132-dsi", }, |
7d338587 | 1695 | { .compatible = "nvidia,tegra124-dsi", }, |
dec72739 TR |
1696 | { .compatible = "nvidia,tegra114-dsi", }, |
1697 | { }, | |
1698 | }; | |
ef70728c | 1699 | MODULE_DEVICE_TABLE(of, tegra_dsi_of_match); |
dec72739 TR |
1700 | |
1701 | struct platform_driver tegra_dsi_driver = { | |
1702 | .driver = { | |
1703 | .name = "tegra-dsi", | |
1704 | .of_match_table = tegra_dsi_of_match, | |
ef8187d7 | 1705 | .pm = &tegra_dsi_pm_ops, |
dec72739 TR |
1706 | }, |
1707 | .probe = tegra_dsi_probe, | |
1708 | .remove = tegra_dsi_remove, | |
1709 | }; |