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drm/tegra: dsi: Add Tegra124 support
[linux-block.git] / drivers / gpu / drm / tegra / dsi.c
CommitLineData
dec72739
TR		 1/*
2 * Copyright (C) 2013 NVIDIA Corporation
3 *
9a2ac2dc
TR		 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
dec72739
TR		 7 */
8
9#include <linux/clk.h>
10#include <linux/debugfs.h>
11#include <linux/host1x.h>
12#include <linux/module.h>
13#include <linux/of.h>
e94236cd 14#include <linux/of_platform.h>
dec72739
TR		 15#include <linux/platform_device.h>
16#include <linux/reset.h>
17
3b077afb
TR		 18#include <linux/regulator/consumer.h>
19
4aa3df71 20#include <drm/drm_atomic_helper.h>
dec72739
TR		 21#include <drm/drm_mipi_dsi.h>
22#include <drm/drm_panel.h>
23
24#include <video/mipi_display.h>
25
26#include "dc.h"
27#include "drm.h"
28#include "dsi.h"
29#include "mipi-phy.h"
30
ebd14afe
TR		 31struct tegra_dsi_state {
32 struct drm_connector_state base;
33
34 struct mipi_dphy_timing timing;
35 unsigned long period;
36
37 unsigned int vrefresh;
38 unsigned int lanes;
39 unsigned long pclk;
40 unsigned long bclk;
41
42 enum tegra_dsi_format format;
43 unsigned int mul;
44 unsigned int div;
45};
46
47static inline struct tegra_dsi_state *
48to_dsi_state(struct drm_connector_state *state)
49{
50 return container_of(state, struct tegra_dsi_state, base);
51}
52
dec72739
TR		 53struct tegra_dsi {
54 struct host1x_client client;
55 struct tegra_output output;
56 struct device *dev;
57
58 void __iomem *regs;
59
60 struct reset_control *rst;
61 struct clk *clk_parent;
62 struct clk *clk_lp;
63 struct clk *clk;
64
65 struct drm_info_list *debugfs_files;
66 struct drm_minor *minor;
67 struct dentry *debugfs;
68
17297a28 69 unsigned long flags;
dec72739
TR		 70 enum mipi_dsi_pixel_format format;
71 unsigned int lanes;
72
73 struct tegra_mipi_device *mipi;
74 struct mipi_dsi_host host;
3b077afb
TR		 75
76 struct regulator *vdd;
976cebc3
TR		 77
78 unsigned int video_fifo_depth;
79 unsigned int host_fifo_depth;
e94236cd
TR		 80
81 /* for ganged-mode support */
82 struct tegra_dsi *master;
83 struct tegra_dsi *slave;
dec72739
TR		 84};
85
86static inline struct tegra_dsi *
87host1x_client_to_dsi(struct host1x_client *client)
88{
89 return container_of(client, struct tegra_dsi, client);
90}
91
92static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
93{
94 return container_of(host, struct tegra_dsi, host);
95}
96
97static inline struct tegra_dsi *to_dsi(struct tegra_output *output)
98{
99 return container_of(output, struct tegra_dsi, output);
100}
101
ebd14afe
TR		 102static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi)
103{
104 return to_dsi_state(dsi->output.connector.state);
105}
106
9c0b4ca1 107static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned long reg)
dec72739
TR		 108{
109 return readl(dsi->regs + (reg << 2));
110}
111
9c0b4ca1 112static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,
dec72739
TR		 113 unsigned long reg)
114{
115 writel(value, dsi->regs + (reg << 2));
116}
117
118static int tegra_dsi_show_regs(struct seq_file *s, void *data)
119{
120 struct drm_info_node *node = s->private;
121 struct tegra_dsi *dsi = node->info_ent->data;
122
123#define DUMP_REG(name) \
9c0b4ca1 124 seq_printf(s, "%-32s %#05x %08x\n", #name, name, \
dec72739
TR		 125 tegra_dsi_readl(dsi, name))
126
127 DUMP_REG(DSI_INCR_SYNCPT);
128 DUMP_REG(DSI_INCR_SYNCPT_CONTROL);
129 DUMP_REG(DSI_INCR_SYNCPT_ERROR);
130 DUMP_REG(DSI_CTXSW);
131 DUMP_REG(DSI_RD_DATA);
132 DUMP_REG(DSI_WR_DATA);
133 DUMP_REG(DSI_POWER_CONTROL);
134 DUMP_REG(DSI_INT_ENABLE);
135 DUMP_REG(DSI_INT_STATUS);
136 DUMP_REG(DSI_INT_MASK);
137 DUMP_REG(DSI_HOST_CONTROL);
138 DUMP_REG(DSI_CONTROL);
139 DUMP_REG(DSI_SOL_DELAY);
140 DUMP_REG(DSI_MAX_THRESHOLD);
141 DUMP_REG(DSI_TRIGGER);
142 DUMP_REG(DSI_TX_CRC);
143 DUMP_REG(DSI_STATUS);
144
145 DUMP_REG(DSI_INIT_SEQ_CONTROL);
146 DUMP_REG(DSI_INIT_SEQ_DATA_0);
147 DUMP_REG(DSI_INIT_SEQ_DATA_1);
148 DUMP_REG(DSI_INIT_SEQ_DATA_2);
149 DUMP_REG(DSI_INIT_SEQ_DATA_3);
150 DUMP_REG(DSI_INIT_SEQ_DATA_4);
151 DUMP_REG(DSI_INIT_SEQ_DATA_5);
152 DUMP_REG(DSI_INIT_SEQ_DATA_6);
153 DUMP_REG(DSI_INIT_SEQ_DATA_7);
154
155 DUMP_REG(DSI_PKT_SEQ_0_LO);
156 DUMP_REG(DSI_PKT_SEQ_0_HI);
157 DUMP_REG(DSI_PKT_SEQ_1_LO);
158 DUMP_REG(DSI_PKT_SEQ_1_HI);
159 DUMP_REG(DSI_PKT_SEQ_2_LO);
160 DUMP_REG(DSI_PKT_SEQ_2_HI);
161 DUMP_REG(DSI_PKT_SEQ_3_LO);
162 DUMP_REG(DSI_PKT_SEQ_3_HI);
163 DUMP_REG(DSI_PKT_SEQ_4_LO);
164 DUMP_REG(DSI_PKT_SEQ_4_HI);
165 DUMP_REG(DSI_PKT_SEQ_5_LO);
166 DUMP_REG(DSI_PKT_SEQ_5_HI);
167
168 DUMP_REG(DSI_DCS_CMDS);
169
170 DUMP_REG(DSI_PKT_LEN_0_1);
171 DUMP_REG(DSI_PKT_LEN_2_3);
172 DUMP_REG(DSI_PKT_LEN_4_5);
173 DUMP_REG(DSI_PKT_LEN_6_7);
174
175 DUMP_REG(DSI_PHY_TIMING_0);
176 DUMP_REG(DSI_PHY_TIMING_1);
177 DUMP_REG(DSI_PHY_TIMING_2);
178 DUMP_REG(DSI_BTA_TIMING);
179
180 DUMP_REG(DSI_TIMEOUT_0);
181 DUMP_REG(DSI_TIMEOUT_1);
182 DUMP_REG(DSI_TO_TALLY);
183
184 DUMP_REG(DSI_PAD_CONTROL_0);
185 DUMP_REG(DSI_PAD_CONTROL_CD);
186 DUMP_REG(DSI_PAD_CD_STATUS);
187 DUMP_REG(DSI_VIDEO_MODE_CONTROL);
188 DUMP_REG(DSI_PAD_CONTROL_1);
189 DUMP_REG(DSI_PAD_CONTROL_2);
190 DUMP_REG(DSI_PAD_CONTROL_3);
191 DUMP_REG(DSI_PAD_CONTROL_4);
192
193 DUMP_REG(DSI_GANGED_MODE_CONTROL);
194 DUMP_REG(DSI_GANGED_MODE_START);
195 DUMP_REG(DSI_GANGED_MODE_SIZE);
196
197 DUMP_REG(DSI_RAW_DATA_BYTE_COUNT);
198 DUMP_REG(DSI_ULTRA_LOW_POWER_CONTROL);
199
200 DUMP_REG(DSI_INIT_SEQ_DATA_8);
201 DUMP_REG(DSI_INIT_SEQ_DATA_9);
202 DUMP_REG(DSI_INIT_SEQ_DATA_10);
203 DUMP_REG(DSI_INIT_SEQ_DATA_11);
204 DUMP_REG(DSI_INIT_SEQ_DATA_12);
205 DUMP_REG(DSI_INIT_SEQ_DATA_13);
206 DUMP_REG(DSI_INIT_SEQ_DATA_14);
207 DUMP_REG(DSI_INIT_SEQ_DATA_15);
208
209#undef DUMP_REG
210
211 return 0;
212}
213
214static struct drm_info_list debugfs_files[] = {
215 { "regs", tegra_dsi_show_regs, 0, NULL },
216};
217
218static int tegra_dsi_debugfs_init(struct tegra_dsi *dsi,
219 struct drm_minor *minor)
220{
221 const char *name = dev_name(dsi->dev);
222 unsigned int i;
223 int err;
224
225 dsi->debugfs = debugfs_create_dir(name, minor->debugfs_root);
226 if (!dsi->debugfs)
227 return -ENOMEM;
228
229 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
230 GFP_KERNEL);
231 if (!dsi->debugfs_files) {
232 err = -ENOMEM;
233 goto remove;
234 }
235
236 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
237 dsi->debugfs_files[i].data = dsi;
238
239 err = drm_debugfs_create_files(dsi->debugfs_files,
240 ARRAY_SIZE(debugfs_files),
241 dsi->debugfs, minor);
242 if (err < 0)
243 goto free;
244
245 dsi->minor = minor;
246
247 return 0;
248
249free:
250 kfree(dsi->debugfs_files);
251 dsi->debugfs_files = NULL;
252remove:
253 debugfs_remove(dsi->debugfs);
254 dsi->debugfs = NULL;
255
256 return err;
257}
258
4009c224 259static void tegra_dsi_debugfs_exit(struct tegra_dsi *dsi)
dec72739
TR		 260{
261 drm_debugfs_remove_files(dsi->debugfs_files, ARRAY_SIZE(debugfs_files),
262 dsi->minor);
263 dsi->minor = NULL;
264
265 kfree(dsi->debugfs_files);
266 dsi->debugfs_files = NULL;
267
268 debugfs_remove(dsi->debugfs);
269 dsi->debugfs = NULL;
dec72739
TR		 270}
271
272#define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
273#define PKT_LEN0(len) (((len) & 0x07) << 0)
274#define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19))
275#define PKT_LEN1(len) (((len) & 0x07) << 10)
276#define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29))
277#define PKT_LEN2(len) (((len) & 0x07) << 20)
278
279#define PKT_LP (1 << 30)
280#define NUM_PKT_SEQ 12
281
17297a28
TR		 282/*
283 * non-burst mode with sync pulses
284 */
285static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
dec72739
TR		 286 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
287 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
288 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
289 PKT_LP,
290 [ 1] = 0,
291 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
292 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
293 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
294 PKT_LP,
295 [ 3] = 0,
296 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
297 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
298 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
299 PKT_LP,
300 [ 5] = 0,
301 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
302 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
303 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
304 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
305 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
306 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
307 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
308 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
309 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
310 PKT_LP,
311 [ 9] = 0,
312 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
313 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
314 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
315 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
316 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
317 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
318};
319
17297a28
TR		 320/*
321 * non-burst mode with sync events
322 */
323static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
324 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
325 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
326 PKT_LP,
327 [ 1] = 0,
328 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
329 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
330 PKT_LP,
331 [ 3] = 0,
332 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
333 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
334 PKT_LP,
335 [ 5] = 0,
336 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
337 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
338 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
339 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
340 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
341 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
342 PKT_LP,
343 [ 9] = 0,
344 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
345 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
346 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
347 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
348};
349
337b443d
TR		 350static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = {
351 [ 0] = 0,
352 [ 1] = 0,
353 [ 2] = 0,
354 [ 3] = 0,
355 [ 4] = 0,
356 [ 5] = 0,
357 [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP,
358 [ 7] = 0,
359 [ 8] = 0,
360 [ 9] = 0,
361 [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP,
362 [11] = 0,
363};
364
ebd14afe
TR		 365static void tegra_dsi_set_phy_timing(struct tegra_dsi *dsi,
366 unsigned long period,
367 const struct mipi_dphy_timing *timing)
dec72739 368{
9c0b4ca1 369 u32 value;
dec72739 370
ebd14afe
TR		 371 value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 |
372 DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 |
373 DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 |
374 DSI_TIMING_FIELD(timing->hsprepare, period, 1);
dec72739
TR		 375 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
376
ebd14afe
TR		 377 value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 |
378 DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 |
379 DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 |
380 DSI_TIMING_FIELD(timing->lpx, period, 1);
dec72739
TR		 381 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
382
ebd14afe
TR		 383 value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 |
384 DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 |
dec72739
TR		 385 DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
386 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
387
ebd14afe
TR		 388 value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 |
389 DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 |
390 DSI_TIMING_FIELD(timing->tago, period, 1);
dec72739
TR		 391 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
392
7e3bc3a9 393 if (dsi->slave)
ebd14afe 394 tegra_dsi_set_phy_timing(dsi->slave, period, timing);
dec72739
TR		 395}
396
397static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
398 unsigned int *mulp, unsigned int *divp)
399{
400 switch (format) {
401 case MIPI_DSI_FMT_RGB666_PACKED:
402 case MIPI_DSI_FMT_RGB888:
403 *mulp = 3;
404 *divp = 1;
405 break;
406
407 case MIPI_DSI_FMT_RGB565:
408 *mulp = 2;
409 *divp = 1;
410 break;
411
412 case MIPI_DSI_FMT_RGB666:
413 *mulp = 9;
414 *divp = 4;
415 break;
416
417 default:
418 return -EINVAL;
419 }
420
421 return 0;
422}
423
f7d6889b
TR		 424static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
425 enum tegra_dsi_format *fmt)
426{
427 switch (format) {
428 case MIPI_DSI_FMT_RGB888:
429 *fmt = TEGRA_DSI_FORMAT_24P;
430 break;
431
432 case MIPI_DSI_FMT_RGB666:
433 *fmt = TEGRA_DSI_FORMAT_18NP;
434 break;
435
436 case MIPI_DSI_FMT_RGB666_PACKED:
437 *fmt = TEGRA_DSI_FORMAT_18P;
438 break;
439
440 case MIPI_DSI_FMT_RGB565:
441 *fmt = TEGRA_DSI_FORMAT_16P;
442 break;
443
444 default:
445 return -EINVAL;
446 }
447
448 return 0;
449}
450
e94236cd
TR		 451static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start,
452 unsigned int size)
453{
454 u32 value;
455
456 tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START);
457 tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE);
458
459 value = DSI_GANGED_MODE_CONTROL_ENABLE;
460 tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);
461}
462
563eff1f
TR		 463static void tegra_dsi_enable(struct tegra_dsi *dsi)
464{
465 u32 value;
466
467 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
468 value |= DSI_POWER_CONTROL_ENABLE;
469 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
e94236cd
TR		 470
471 if (dsi->slave)
472 tegra_dsi_enable(dsi->slave);
473}
474
475static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi)
476{
477 if (dsi->master)
478 return dsi->master->lanes + dsi->lanes;
479
480 if (dsi->slave)
481 return dsi->lanes + dsi->slave->lanes;
482
483 return dsi->lanes;
563eff1f
TR		 484}
485
ebd14afe
TR		 486static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
487 const struct drm_display_mode *mode)
dec72739 488{
dec72739 489 unsigned int hact, hsw, hbp, hfp, i, mul, div;
ebd14afe 490 struct tegra_dsi_state *state;
17297a28 491 const u32 *pkt_seq;
563eff1f 492 u32 value;
ebd14afe
TR		 493
494 /* XXX: pass in state into this function? */
495 if (dsi->master)
496 state = tegra_dsi_get_state(dsi->master);
497 else
498 state = tegra_dsi_get_state(dsi);
499
500 mul = state->mul;
501 div = state->div;
dec72739 502
17297a28
TR		 503 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
504 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n");
505 pkt_seq = pkt_seq_video_non_burst_sync_pulses;
337b443d 506 } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
17297a28
TR		 507 DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
508 pkt_seq = pkt_seq_video_non_burst_sync_events;
337b443d
TR		 509 } else {
510 DRM_DEBUG_KMS("Command mode\n");
511 pkt_seq = pkt_seq_command_mode;
17297a28
TR		 512 }
513
ebd14afe
TR		 514 value = DSI_CONTROL_CHANNEL(0) |
515 DSI_CONTROL_FORMAT(state->format) |
dec72739 516 DSI_CONTROL_LANES(dsi->lanes - 1) |
563eff1f 517 DSI_CONTROL_SOURCE(pipe);
dec72739
TR		 518 tegra_dsi_writel(dsi, value, DSI_CONTROL);
519
976cebc3 520 tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD);
dec72739 521
563eff1f 522 value = DSI_HOST_CONTROL_HS;
dec72739
TR		 523 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
524
525 value = tegra_dsi_readl(dsi, DSI_CONTROL);
563eff1f 526
0c6b1e4b
AC		 527 if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
528 value |= DSI_CONTROL_HS_CLK_CTRL;
563eff1f 529
dec72739 530 value &= ~DSI_CONTROL_TX_TRIG(3);
337b443d
TR		 531
532 /* enable DCS commands for command mode */
533 if (dsi->flags & MIPI_DSI_MODE_VIDEO)
534 value &= ~DSI_CONTROL_DCS_ENABLE;
535 else
536 value |= DSI_CONTROL_DCS_ENABLE;
537
dec72739
TR		 538 value |= DSI_CONTROL_VIDEO_ENABLE;
539 value &= ~DSI_CONTROL_HOST_ENABLE;
540 tegra_dsi_writel(dsi, value, DSI_CONTROL);
541
dec72739
TR		 542 for (i = 0; i < NUM_PKT_SEQ; i++)
543 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
544
337b443d
TR		 545 if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
546 /* horizontal active pixels */
547 hact = mode->hdisplay * mul / div;
548
549 /* horizontal sync width */
550 hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
337b443d
TR		 551
552 /* horizontal back porch */
553 hbp = (mode->htotal - mode->hsync_end) * mul / div;
b8be0bdb
TR		 554
555 if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0)
556 hbp += hsw;
337b443d
TR		 557
558 /* horizontal front porch */
559 hfp = (mode->hsync_start - mode->hdisplay) * mul / div;
b8be0bdb
TR		 560
561 /* subtract packet overhead */
562 hsw -= 10;
563 hbp -= 14;
337b443d 564 hfp -= 8;
dec72739 565
337b443d
TR		 566 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
567 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
568 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
569 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
dec72739 570
337b443d
TR		 571 /* set SOL delay (for non-burst mode only) */
572 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
e94236cd
TR		 573
574 /* TODO: implement ganged mode */
337b443d
TR		 575 } else {
576 u16 bytes;
577
e94236cd
TR		 578 if (dsi->master || dsi->slave) {
579 /*
580 * For ganged mode, assume symmetric left-right mode.
581 */
582 bytes = 1 + (mode->hdisplay / 2) * mul / div;
583 } else {
584 /* 1 byte (DCS command) + pixel data */
585 bytes = 1 + mode->hdisplay * mul / div;
586 }
dec72739 587
337b443d
TR		 588 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1);
589 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3);
590 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5);
591 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7);
dec72739 592
337b443d
TR		 593 value = MIPI_DCS_WRITE_MEMORY_START << 8 |
594 MIPI_DCS_WRITE_MEMORY_CONTINUE;
595 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);
dec72739 596
e94236cd
TR		 597 /* set SOL delay */
598 if (dsi->master || dsi->slave) {
e94236cd 599 unsigned long delay, bclk, bclk_ganged;
ebd14afe 600 unsigned int lanes = state->lanes;
e94236cd
TR		 601
602 /* SOL to valid, valid to FIFO and FIFO write delay */
603 delay = 4 + 4 + 2;
604 delay = DIV_ROUND_UP(delay * mul, div * lanes);
605 /* FIFO read delay */
606 delay = delay + 6;
607
608 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes);
609 bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
610 value = bclk - bclk_ganged + delay + 20;
611 } else {
612 /* TODO: revisit for non-ganged mode */
613 value = 8 * mul / div;
614 }
337b443d
TR		 615
616 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
617 }
dec72739 618
e94236cd 619 if (dsi->slave) {
ebd14afe 620 tegra_dsi_configure(dsi->slave, pipe, mode);
e94236cd
TR		 621
622 /*
623 * TODO: Support modes other than symmetrical left-right
624 * split.
625 */
626 tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2);
627 tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2,
628 mode->hdisplay / 2);
629 }
563eff1f
TR		 630}
631
563eff1f
TR		 632static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout)
633{
634 u32 value;
635
636 timeout = jiffies + msecs_to_jiffies(timeout);
637
638 while (time_before(jiffies, timeout)) {
639 value = tegra_dsi_readl(dsi, DSI_STATUS);
640 if (value & DSI_STATUS_IDLE)
641 return 0;
642
643 usleep_range(1000, 2000);
644 }
645
646 return -ETIMEDOUT;
647}
648
649static void tegra_dsi_video_disable(struct tegra_dsi *dsi)
650{
651 u32 value;
652
653 value = tegra_dsi_readl(dsi, DSI_CONTROL);
654 value &= ~DSI_CONTROL_VIDEO_ENABLE;
655 tegra_dsi_writel(dsi, value, DSI_CONTROL);
e94236cd
TR		 656
657 if (dsi->slave)
658 tegra_dsi_video_disable(dsi->slave);
659}
660
661static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi)
662{
663 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);
664 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);
665 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);
563eff1f
TR		 666}
667
5b901e78
TR		 668static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk,
669 unsigned int vrefresh)
670{
671 unsigned int timeout;
672 u32 value;
673
674 /* one frame high-speed transmission timeout */
675 timeout = (bclk / vrefresh) / 512;
676 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
677 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
678
679 /* 2 ms peripheral timeout for panel */
680 timeout = 2 * bclk / 512 * 1000;
681 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
682 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
683
684 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
685 tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
686
687 if (dsi->slave)
688 tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh);
689}
690
563eff1f
TR		 691static void tegra_dsi_disable(struct tegra_dsi *dsi)
692{
693 u32 value;
694
e94236cd
TR		 695 if (dsi->slave) {
696 tegra_dsi_ganged_disable(dsi->slave);
697 tegra_dsi_ganged_disable(dsi);
698 }
699
563eff1f
TR		 700 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
701 value &= ~DSI_POWER_CONTROL_ENABLE;
702 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
703
e94236cd
TR		 704 if (dsi->slave)
705 tegra_dsi_disable(dsi->slave);
706
563eff1f
TR		 707 usleep_range(5000, 10000);
708}
709
92f0e073
TR		 710static void tegra_dsi_soft_reset(struct tegra_dsi *dsi)
711{
712 u32 value;
713
714 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
715 value &= ~DSI_POWER_CONTROL_ENABLE;
716 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
717
718 usleep_range(300, 1000);
719
720 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
721 value |= DSI_POWER_CONTROL_ENABLE;
722 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
723
724 usleep_range(300, 1000);
725
726 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
727 if (value)
728 tegra_dsi_writel(dsi, 0, DSI_TRIGGER);
729
730 if (dsi->slave)
731 tegra_dsi_soft_reset(dsi->slave);
732}
733
5b901e78 734static void tegra_dsi_connector_dpms(struct drm_connector *connector, int mode)
dec72739 735{
dec72739
TR		 736}
737
ebd14afe
TR		 738static void tegra_dsi_connector_reset(struct drm_connector *connector)
739{
740 struct tegra_dsi_state *state;
741
742 kfree(connector->state);
743 connector->state = NULL;
744
745 state = kzalloc(sizeof(*state), GFP_KERNEL);
746 if (state)
747 connector->state = &state->base;
748}
749
750static struct drm_connector_state *
751tegra_dsi_connector_duplicate_state(struct drm_connector *connector)
752{
753 struct tegra_dsi_state *state = to_dsi_state(connector->state);
754 struct tegra_dsi_state *copy;
755
756 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
757 if (!copy)
758 return NULL;
759
760 return &copy->base;
761}
762
5b901e78
TR		 763static const struct drm_connector_funcs tegra_dsi_connector_funcs = {
764 .dpms = tegra_dsi_connector_dpms,
ebd14afe 765 .reset = tegra_dsi_connector_reset,
5b901e78
TR		 766 .detect = tegra_output_connector_detect,
767 .fill_modes = drm_helper_probe_single_connector_modes,
768 .destroy = tegra_output_connector_destroy,
ebd14afe 769 .atomic_duplicate_state = tegra_dsi_connector_duplicate_state,
4aa3df71 770 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5b901e78 771};
3f6b406f 772
5b901e78
TR		 773static enum drm_mode_status
774tegra_dsi_connector_mode_valid(struct drm_connector *connector,
775 struct drm_display_mode *mode)
776{
777 return MODE_OK;
778}
3f6b406f 779
5b901e78
TR		 780static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs = {
781 .get_modes = tegra_output_connector_get_modes,
782 .mode_valid = tegra_dsi_connector_mode_valid,
783 .best_encoder = tegra_output_connector_best_encoder,
784};
3f6b406f 785
5b901e78
TR		 786static const struct drm_encoder_funcs tegra_dsi_encoder_funcs = {
787 .destroy = tegra_output_encoder_destroy,
788};
e94236cd 789
5b901e78
TR		 790static void tegra_dsi_encoder_dpms(struct drm_encoder *encoder, int mode)
791{
3f6b406f
TR		 792}
793
5b901e78
TR		 794static void tegra_dsi_encoder_prepare(struct drm_encoder *encoder)
795{
796}
797
798static void tegra_dsi_encoder_commit(struct drm_encoder *encoder)
799{
dec72739
TR		 800}
801
5b901e78 802static void tegra_dsi_encoder_mode_set(struct drm_encoder *encoder,
dec72739 803 struct drm_display_mode *mode,
5b901e78
TR		 804 struct drm_display_mode *adjusted)
805{
806 struct tegra_output *output = encoder_to_output(encoder);
807 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
808 struct tegra_dsi *dsi = to_dsi(output);
ebd14afe 809 struct tegra_dsi_state *state;
5b901e78 810 u32 value;
5b901e78 811
ebd14afe 812 state = tegra_dsi_get_state(dsi);
5b901e78 813
ebd14afe
TR		 814 tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh);
815
816 /*
817 * The D-PHY timing fields are expressed in byte-clock cycles, so
818 * multiply the period by 8.
819 */
820 tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing);
5b901e78
TR		 821
822 if (output->panel)
823 drm_panel_prepare(output->panel);
824
ebd14afe
TR		 825 tegra_dsi_configure(dsi, dc->pipe, mode);
826
5b901e78
TR		 827 /* enable display controller */
828 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
829 value |= DSI_ENABLE;
830 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
831
5b901e78
TR		 832 tegra_dc_commit(dc);
833
834 /* enable DSI controller */
835 tegra_dsi_enable(dsi);
836
837 if (output->panel)
838 drm_panel_enable(output->panel);
839
840 return;
841}
842
843static void tegra_dsi_encoder_disable(struct drm_encoder *encoder)
dec72739 844{
5b901e78
TR		 845 struct tegra_output *output = encoder_to_output(encoder);
846 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
847 struct tegra_dsi *dsi = to_dsi(output);
848 u32 value;
849 int err;
850
851 if (output->panel)
852 drm_panel_disable(output->panel);
853
854 tegra_dsi_video_disable(dsi);
855
dec72739 856 /*
5b901e78
TR		 857 * The following accesses registers of the display controller, so make
858 * sure it's only executed when the output is attached to one.
dec72739 859 */
5b901e78
TR		 860 if (dc) {
861 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
862 value &= ~DSI_ENABLE;
863 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
dec72739 864
5b901e78
TR		 865 tegra_dc_commit(dc);
866 }
dec72739 867
5b901e78
TR		 868 err = tegra_dsi_wait_idle(dsi, 100);
869 if (err < 0)
870 dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err);
871
872 tegra_dsi_soft_reset(dsi);
873
874 if (output->panel)
875 drm_panel_unprepare(output->panel);
876
877 tegra_dsi_disable(dsi);
878
879 return;
dec72739
TR		 880}
881
ebd14afe
TR		 882static int
883tegra_dsi_encoder_atomic_check(struct drm_encoder *encoder,
884 struct drm_crtc_state *crtc_state,
885 struct drm_connector_state *conn_state)
886{
887 struct tegra_output *output = encoder_to_output(encoder);
888 struct tegra_dsi_state *state = to_dsi_state(conn_state);
889 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
890 struct tegra_dsi *dsi = to_dsi(output);
891 unsigned int scdiv;
892 unsigned long plld;
893 int err;
894
895 state->pclk = crtc_state->mode.clock * 1000;
896
897 err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div);
898 if (err < 0)
899 return err;
900
901 state->lanes = tegra_dsi_get_lanes(dsi);
902
903 err = tegra_dsi_get_format(dsi->format, &state->format);
904 if (err < 0)
905 return err;
906
907 state->vrefresh = drm_mode_vrefresh(&crtc_state->mode);
908
909 /* compute byte clock */
910 state->bclk = (state->pclk * state->mul) / (state->div * state->lanes);
911
912 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div,
913 state->lanes);
914 DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state->format,
915 state->vrefresh);
916 DRM_DEBUG_KMS("bclk: %lu\n", state->bclk);
917
918 /*
919 * Compute bit clock and round up to the next MHz.
920 */
921 plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC;
922 state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld);
923
924 err = mipi_dphy_timing_get_default(&state->timing, state->period);
925 if (err < 0)
926 return err;
927
928 err = mipi_dphy_timing_validate(&state->timing, state->period);
929 if (err < 0) {
930 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
931 return err;
932 }
933
934 /*
935 * We divide the frequency by two here, but we make up for that by
936 * setting the shift clock divider (further below) to half of the
937 * correct value.
938 */
939 plld /= 2;
940
941 /*
942 * Derive pixel clock from bit clock using the shift clock divider.
943 * Note that this is only half of what we would expect, but we need
944 * that to make up for the fact that we divided the bit clock by a
945 * factor of two above.
946 *
947 * It's not clear exactly why this is necessary, but the display is
948 * not working properly otherwise. Perhaps the PLLs cannot generate
949 * frequencies sufficiently high.
950 */
951 scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2;
952
953 err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent,
954 plld, scdiv);
955 if (err < 0) {
956 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
957 return err;
958 }
959
960 return err;
961}
962
5b901e78
TR		 963static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = {
964 .dpms = tegra_dsi_encoder_dpms,
5b901e78
TR		 965 .prepare = tegra_dsi_encoder_prepare,
966 .commit = tegra_dsi_encoder_commit,
967 .mode_set = tegra_dsi_encoder_mode_set,
968 .disable = tegra_dsi_encoder_disable,
ebd14afe 969 .atomic_check = tegra_dsi_encoder_atomic_check,
dec72739
TR		 970};
971
972static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
973{
9c0b4ca1 974 u32 value;
dec72739
TR		 975
976 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
977 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
978
979 return 0;
980}
981
982static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
983{
183ef288 984 u32 value;
dec72739
TR		 985
986 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
987 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
988 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
989 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
990 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
991
992 /* start calibration */
993 tegra_dsi_pad_enable(dsi);
994
995 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
996 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
997 DSI_PAD_OUT_CLK(0x0);
998 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
999
1000 return tegra_mipi_calibrate(dsi->mipi);
1001}
1002
1003static int tegra_dsi_init(struct host1x_client *client)
1004{
9910f5c4 1005 struct drm_device *drm = dev_get_drvdata(client->parent);
dec72739 1006 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
dec72739
TR		 1007 int err;
1008
201106d8
TR		 1009 reset_control_deassert(dsi->rst);
1010
1011 err = tegra_dsi_pad_calibrate(dsi);
1012 if (err < 0) {
1013 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
1014 goto reset;
1015 }
1016
e94236cd
TR		 1017 /* Gangsters must not register their own outputs. */
1018 if (!dsi->master) {
e94236cd 1019 dsi->output.dev = client->dev;
e94236cd 1020
5b901e78
TR		 1021 drm_connector_init(drm, &dsi->output.connector,
1022 &tegra_dsi_connector_funcs,
1023 DRM_MODE_CONNECTOR_DSI);
1024 drm_connector_helper_add(&dsi->output.connector,
1025 &tegra_dsi_connector_helper_funcs);
1026 dsi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1027
5b901e78
TR		 1028 drm_encoder_init(drm, &dsi->output.encoder,
1029 &tegra_dsi_encoder_funcs,
1030 DRM_MODE_ENCODER_DSI);
1031 drm_encoder_helper_add(&dsi->output.encoder,
1032 &tegra_dsi_encoder_helper_funcs);
1033
1034 drm_mode_connector_attach_encoder(&dsi->output.connector,
1035 &dsi->output.encoder);
1036 drm_connector_register(&dsi->output.connector);
1037
ea130b24
TR		 1038 err = tegra_output_init(drm, &dsi->output);
1039 if (err < 0) {
1040 dev_err(client->dev,
1041 "failed to initialize output: %d\n",
1042 err);
1043 goto reset;
1044 }
1045
5b901e78 1046 dsi->output.encoder.possible_crtcs = 0x3;
dec72739
TR		 1047 }
1048
1049 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
9910f5c4 1050 err = tegra_dsi_debugfs_init(dsi, drm->primary);
dec72739
TR		 1051 if (err < 0)
1052 dev_err(dsi->dev, "debugfs setup failed: %d\n", err);
1053 }
1054
dec72739 1055 return 0;
201106d8
TR		 1056
1057reset:
1058 reset_control_assert(dsi->rst);
1059 return err;
dec72739
TR		 1060}
1061
1062static int tegra_dsi_exit(struct host1x_client *client)
1063{
1064 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
dec72739 1065
5b901e78
TR		 1066 tegra_output_exit(&dsi->output);
1067
4009c224
TR		 1068 if (IS_ENABLED(CONFIG_DEBUG_FS))
1069 tegra_dsi_debugfs_exit(dsi);
dec72739 1070
201106d8
TR		 1071 reset_control_assert(dsi->rst);
1072
dec72739
TR		 1073 return 0;
1074}
1075
1076static const struct host1x_client_ops dsi_client_ops = {
1077 .init = tegra_dsi_init,
1078 .exit = tegra_dsi_exit,
1079};
1080
1081static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
1082{
1083 struct clk *parent;
1084 int err;
1085
1086 parent = clk_get_parent(dsi->clk);
1087 if (!parent)
1088 return -EINVAL;
1089
1090 err = clk_set_parent(parent, dsi->clk_parent);
1091 if (err < 0)
1092 return err;
1093
1094 return 0;
1095}
1096
0fffdf6c
TR		 1097static const char * const error_report[16] = {
1098 "SoT Error",
1099 "SoT Sync Error",
1100 "EoT Sync Error",
1101 "Escape Mode Entry Command Error",
1102 "Low-Power Transmit Sync Error",
1103 "Peripheral Timeout Error",
1104 "False Control Error",
1105 "Contention Detected",
1106 "ECC Error, single-bit",
1107 "ECC Error, multi-bit",
1108 "Checksum Error",
1109 "DSI Data Type Not Recognized",
1110 "DSI VC ID Invalid",
1111 "Invalid Transmission Length",
1112 "Reserved",
1113 "DSI Protocol Violation",
1114};
1115
1116static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi,
1117 const struct mipi_dsi_msg *msg,
1118 size_t count)
1119{
1120 u8 *rx = msg->rx_buf;
1121 unsigned int i, j, k;
1122 size_t size = 0;
1123 u16 errors;
1124 u32 value;
1125
1126 /* read and parse packet header */
1127 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1128
1129 switch (value & 0x3f) {
1130 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1131 errors = (value >> 8) & 0xffff;
1132 dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n",
1133 errors);
1134 for (i = 0; i < ARRAY_SIZE(error_report); i++)
1135 if (errors & BIT(i))
1136 dev_dbg(dsi->dev, " %2u: %s\n", i,
1137 error_report[i]);
1138 break;
1139
1140 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1141 rx[0] = (value >> 8) & 0xff;
1142 size = 1;
1143 break;
1144
1145 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1146 rx[0] = (value >> 8) & 0xff;
1147 rx[1] = (value >> 16) & 0xff;
1148 size = 2;
1149 break;
1150
1151 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1152 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1153 break;
1154
1155 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1156 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1157 break;
1158
1159 default:
1160 dev_err(dsi->dev, "unhandled response type: %02x\n",
1161 value & 0x3f);
1162 return -EPROTO;
1163 }
1164
1165 size = min(size, msg->rx_len);
1166
1167 if (msg->rx_buf && size > 0) {
1168 for (i = 0, j = 0; i < count - 1; i++, j += 4) {
1169 u8 *rx = msg->rx_buf + j;
1170
1171 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1172
1173 for (k = 0; k < 4 && (j + k) < msg->rx_len; k++)
1174 rx[j + k] = (value >> (k << 3)) & 0xff;
1175 }
1176 }
1177
1178 return size;
1179}
1180
1181static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout)
1182{
1183 tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER);
1184
1185 timeout = jiffies + msecs_to_jiffies(timeout);
1186
1187 while (time_before(jiffies, timeout)) {
1188 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
1189 if ((value & DSI_TRIGGER_HOST) == 0)
1190 return 0;
1191
1192 usleep_range(1000, 2000);
1193 }
1194
1195 DRM_DEBUG_KMS("timeout waiting for transmission to complete\n");
1196 return -ETIMEDOUT;
1197}
1198
1199static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi,
1200 unsigned long timeout)
1201{
1202 timeout = jiffies + msecs_to_jiffies(250);
1203
1204 while (time_before(jiffies, timeout)) {
1205 u32 value = tegra_dsi_readl(dsi, DSI_STATUS);
1206 u8 count = value & 0x1f;
1207
1208 if (count > 0)
1209 return count;
1210
1211 usleep_range(1000, 2000);
1212 }
1213
1214 DRM_DEBUG_KMS("peripheral returned no data\n");
1215 return -ETIMEDOUT;
1216}
1217
1218static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset,
1219 const void *buffer, size_t size)
1220{
1221 const u8 *buf = buffer;
1222 size_t i, j;
1223 u32 value;
1224
1225 for (j = 0; j < size; j += 4) {
1226 value = 0;
1227
1228 for (i = 0; i < 4 && j + i < size; i++)
1229 value |= buf[j + i] << (i << 3);
1230
1231 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1232 }
1233}
1234
1235static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
1236 const struct mipi_dsi_msg *msg)
1237{
1238 struct tegra_dsi *dsi = host_to_tegra(host);
1239 struct mipi_dsi_packet packet;
1240 const u8 *header;
1241 size_t count;
1242 ssize_t err;
1243 u32 value;
1244
1245 err = mipi_dsi_create_packet(&packet, msg);
1246 if (err < 0)
1247 return err;
1248
1249 header = packet.header;
1250
1251 /* maximum FIFO depth is 1920 words */
1252 if (packet.size > dsi->video_fifo_depth * 4)
1253 return -ENOSPC;
1254
1255 /* reset underflow/overflow flags */
1256 value = tegra_dsi_readl(dsi, DSI_STATUS);
1257 if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
1258 value = DSI_HOST_CONTROL_FIFO_RESET;
1259 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1260 usleep_range(10, 20);
1261 }
1262
1263 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
1264 value |= DSI_POWER_CONTROL_ENABLE;
1265 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
1266
1267 usleep_range(5000, 10000);
1268
1269 value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
1270 DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
1271
1272 if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0)
1273 value |= DSI_HOST_CONTROL_HS;
1274
1275 /*
1276 * The host FIFO has a maximum of 64 words, so larger transmissions
1277 * need to use the video FIFO.
1278 */
1279 if (packet.size > dsi->host_fifo_depth * 4)
1280 value |= DSI_HOST_CONTROL_FIFO_SEL;
1281
1282 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1283
1284 /*
1285 * For reads and messages with explicitly requested ACK, generate a
1286 * BTA sequence after the transmission of the packet.
1287 */
1288 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1289 (msg->rx_buf && msg->rx_len > 0)) {
1290 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
1291 value |= DSI_HOST_CONTROL_PKT_BTA;
1292 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1293 }
1294
1295 value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;
1296 tegra_dsi_writel(dsi, value, DSI_CONTROL);
1297
1298 /* write packet header, ECC is generated by hardware */
1299 value = header[2] << 16 | header[1] << 8 | header[0];
1300 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1301
1302 /* write payload (if any) */
1303 if (packet.payload_length > 0)
1304 tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload,
1305 packet.payload_length);
1306
1307 err = tegra_dsi_transmit(dsi, 250);
1308 if (err < 0)
1309 return err;
1310
1311 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1312 (msg->rx_buf && msg->rx_len > 0)) {
1313 err = tegra_dsi_wait_for_response(dsi, 250);
1314 if (err < 0)
1315 return err;
1316
1317 count = err;
1318
1319 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1320 switch (value) {
1321 case 0x84:
1322 /*
1323 dev_dbg(dsi->dev, "ACK\n");
1324 */
1325 break;
1326
1327 case 0x87:
1328 /*
1329 dev_dbg(dsi->dev, "ESCAPE\n");
1330 */
1331 break;
1332
1333 default:
1334 dev_err(dsi->dev, "unknown status: %08x\n", value);
1335 break;
1336 }
1337
1338 if (count > 1) {
1339 err = tegra_dsi_read_response(dsi, msg, count);
1340 if (err < 0)
1341 dev_err(dsi->dev,
1342 "failed to parse response: %zd\n",
1343 err);
1344 else {
1345 /*
1346 * For read commands, return the number of
1347 * bytes returned by the peripheral.
1348 */
1349 count = err;
1350 }
1351 }
1352 } else {
1353 /*
1354 * For write commands, we have transmitted the 4-byte header
1355 * plus the variable-length payload.
1356 */
1357 count = 4 + packet.payload_length;
1358 }
1359
1360 return count;
1361}
1362
e94236cd
TR		 1363static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi)
1364{
1365 struct clk *parent;
1366 int err;
1367
1368 /* make sure both DSI controllers share the same PLL */
1369 parent = clk_get_parent(dsi->slave->clk);
1370 if (!parent)
1371 return -EINVAL;
1372
1373 err = clk_set_parent(parent, dsi->clk_parent);
1374 if (err < 0)
1375 return err;
1376
1377 return 0;
1378}
1379
dec72739
TR		 1380static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
1381 struct mipi_dsi_device *device)
1382{
1383 struct tegra_dsi *dsi = host_to_tegra(host);
dec72739 1384
17297a28 1385 dsi->flags = device->mode_flags;
dec72739
TR		 1386 dsi->format = device->format;
1387 dsi->lanes = device->lanes;
1388
e94236cd
TR		 1389 if (dsi->slave) {
1390 int err;
1391
1392 dev_dbg(dsi->dev, "attaching dual-channel device %s\n",
1393 dev_name(&device->dev));
1394
1395 err = tegra_dsi_ganged_setup(dsi);
1396 if (err < 0) {
1397 dev_err(dsi->dev, "failed to set up ganged mode: %d\n",
1398 err);
1399 return err;
1400 }
1401 }
1402
1403 /*
1404 * Slaves don't have a panel associated with them, so they provide
1405 * merely the second channel.
1406 */
1407 if (!dsi->master) {
1408 struct tegra_output *output = &dsi->output;
1409
1410 output->panel = of_drm_find_panel(device->dev.of_node);
1411 if (output->panel && output->connector.dev) {
1412 drm_panel_attach(output->panel, &output->connector);
dec72739 1413 drm_helper_hpd_irq_event(output->connector.dev);
e94236cd 1414 }
dec72739
TR		 1415 }
1416
1417 return 0;
1418}
1419
1420static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
1421 struct mipi_dsi_device *device)
1422{
1423 struct tegra_dsi *dsi = host_to_tegra(host);
1424 struct tegra_output *output = &dsi->output;
1425
1426 if (output->panel && &device->dev == output->panel->dev) {
ba3df979
TR		 1427 output->panel = NULL;
1428
dec72739
TR		 1429 if (output->connector.dev)
1430 drm_helper_hpd_irq_event(output->connector.dev);
dec72739
TR		 1431 }
1432
1433 return 0;
1434}
1435
1436static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
1437 .attach = tegra_dsi_host_attach,
1438 .detach = tegra_dsi_host_detach,
0fffdf6c 1439 .transfer = tegra_dsi_host_transfer,
dec72739
TR		 1440};
1441
e94236cd
TR		 1442static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi)
1443{
1444 struct device_node *np;
1445
1446 np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0);
1447 if (np) {
1448 struct platform_device *gangster = of_find_device_by_node(np);
1449
1450 dsi->slave = platform_get_drvdata(gangster);
1451 of_node_put(np);
1452
1453 if (!dsi->slave)
1454 return -EPROBE_DEFER;
1455
1456 dsi->slave->master = dsi;
1457 }
1458
1459 return 0;
1460}
1461
dec72739
TR		 1462static int tegra_dsi_probe(struct platform_device *pdev)
1463{
1464 struct tegra_dsi *dsi;
1465 struct resource *regs;
1466 int err;
1467
1468 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1469 if (!dsi)
1470 return -ENOMEM;
1471
1472 dsi->output.dev = dsi->dev = &pdev->dev;
976cebc3
TR		 1473 dsi->video_fifo_depth = 1920;
1474 dsi->host_fifo_depth = 64;
dec72739 1475
e94236cd
TR		 1476 err = tegra_dsi_ganged_probe(dsi);
1477 if (err < 0)
1478 return err;
1479
dec72739
TR		 1480 err = tegra_output_probe(&dsi->output);
1481 if (err < 0)
1482 return err;
1483
ba3df979
TR		 1484 dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD;
1485
dec72739
TR		 1486 /*
1487 * Assume these values by default. When a DSI peripheral driver
1488 * attaches to the DSI host, the parameters will be taken from
1489 * the attached device.
1490 */
17297a28 1491 dsi->flags = MIPI_DSI_MODE_VIDEO;
dec72739
TR		 1492 dsi->format = MIPI_DSI_FMT_RGB888;
1493 dsi->lanes = 4;
1494
1495 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi");
1496 if (IS_ERR(dsi->rst))
1497 return PTR_ERR(dsi->rst);
1498
1499 dsi->clk = devm_clk_get(&pdev->dev, NULL);
1500 if (IS_ERR(dsi->clk)) {
1501 dev_err(&pdev->dev, "cannot get DSI clock\n");
d2d0a9d2
TR		 1502 err = PTR_ERR(dsi->clk);
1503 goto reset;
dec72739
TR		 1504 }
1505
1506 err = clk_prepare_enable(dsi->clk);
1507 if (err < 0) {
1508 dev_err(&pdev->dev, "cannot enable DSI clock\n");
d2d0a9d2 1509 goto reset;
dec72739
TR		 1510 }
1511
1512 dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
1513 if (IS_ERR(dsi->clk_lp)) {
1514 dev_err(&pdev->dev, "cannot get low-power clock\n");
d2d0a9d2
TR		 1515 err = PTR_ERR(dsi->clk_lp);
1516 goto disable_clk;
dec72739
TR		 1517 }
1518
1519 err = clk_prepare_enable(dsi->clk_lp);
1520 if (err < 0) {
1521 dev_err(&pdev->dev, "cannot enable low-power clock\n");
d2d0a9d2 1522 goto disable_clk;
dec72739
TR		 1523 }
1524
1525 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1526 if (IS_ERR(dsi->clk_parent)) {
1527 dev_err(&pdev->dev, "cannot get parent clock\n");
d2d0a9d2
TR		 1528 err = PTR_ERR(dsi->clk_parent);
1529 goto disable_clk_lp;
dec72739
TR		 1530 }
1531
3b077afb
TR		 1532 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi");
1533 if (IS_ERR(dsi->vdd)) {
1534 dev_err(&pdev->dev, "cannot get VDD supply\n");
d2d0a9d2
TR		 1535 err = PTR_ERR(dsi->vdd);
1536 goto disable_clk_lp;
3b077afb
TR		 1537 }
1538
1539 err = regulator_enable(dsi->vdd);
1540 if (err < 0) {
1541 dev_err(&pdev->dev, "cannot enable VDD supply\n");
d2d0a9d2 1542 goto disable_clk_lp;
3b077afb
TR		 1543 }
1544
dec72739
TR		 1545 err = tegra_dsi_setup_clocks(dsi);
1546 if (err < 0) {
1547 dev_err(&pdev->dev, "cannot setup clocks\n");
d2d0a9d2 1548 goto disable_vdd;
dec72739
TR		 1549 }
1550
1551 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1552 dsi->regs = devm_ioremap_resource(&pdev->dev, regs);
d2d0a9d2
TR		 1553 if (IS_ERR(dsi->regs)) {
1554 err = PTR_ERR(dsi->regs);
1555 goto disable_vdd;
1556 }
dec72739 1557
dec72739 1558 dsi->mipi = tegra_mipi_request(&pdev->dev);
d2d0a9d2
TR		 1559 if (IS_ERR(dsi->mipi)) {
1560 err = PTR_ERR(dsi->mipi);
1561 goto disable_vdd;
1562 }
dec72739
TR		 1563
1564 dsi->host.ops = &tegra_dsi_host_ops;
1565 dsi->host.dev = &pdev->dev;
1566
1567 err = mipi_dsi_host_register(&dsi->host);
1568 if (err < 0) {
1569 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err);
d2d0a9d2 1570 goto mipi_free;
dec72739
TR		 1571 }
1572
1573 INIT_LIST_HEAD(&dsi->client.list);
1574 dsi->client.ops = &dsi_client_ops;
1575 dsi->client.dev = &pdev->dev;
1576
1577 err = host1x_client_register(&dsi->client);
1578 if (err < 0) {
1579 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1580 err);
d2d0a9d2 1581 goto unregister;
dec72739
TR		 1582 }
1583
1584 platform_set_drvdata(pdev, dsi);
1585
1586 return 0;
d2d0a9d2
TR		 1587
1588unregister:
1589 mipi_dsi_host_unregister(&dsi->host);
1590mipi_free:
1591 tegra_mipi_free(dsi->mipi);
1592disable_vdd:
1593 regulator_disable(dsi->vdd);
1594disable_clk_lp:
1595 clk_disable_unprepare(dsi->clk_lp);
1596disable_clk:
1597 clk_disable_unprepare(dsi->clk);
1598reset:
1599 reset_control_assert(dsi->rst);
1600 return err;
dec72739
TR		 1601}
1602
1603static int tegra_dsi_remove(struct platform_device *pdev)
1604{
1605 struct tegra_dsi *dsi = platform_get_drvdata(pdev);
1606 int err;
1607
1608 err = host1x_client_unregister(&dsi->client);
1609 if (err < 0) {
1610 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1611 err);
1612 return err;
1613 }
1614
328ec69e 1615 tegra_output_remove(&dsi->output);
5b901e78 1616
dec72739
TR		 1617 mipi_dsi_host_unregister(&dsi->host);
1618 tegra_mipi_free(dsi->mipi);
1619
3b077afb 1620 regulator_disable(dsi->vdd);
dec72739
TR		 1621 clk_disable_unprepare(dsi->clk_lp);
1622 clk_disable_unprepare(dsi->clk);
cb825d89 1623 reset_control_assert(dsi->rst);
dec72739 1624
dec72739
TR		 1625 return 0;
1626}
1627
1628static const struct of_device_id tegra_dsi_of_match[] = {
7d338587 1629 { .compatible = "nvidia,tegra124-dsi", },
dec72739
TR		 1630 { .compatible = "nvidia,tegra114-dsi", },
1631 { },
1632};
ef70728c 1633MODULE_DEVICE_TABLE(of, tegra_dsi_of_match);
dec72739
TR		 1634
1635struct platform_driver tegra_dsi_driver = {
1636 .driver = {
1637 .name = "tegra-dsi",
1638 .of_match_table = tegra_dsi_of_match,
1639 },
1640 .probe = tegra_dsi_probe,
1641 .remove = tegra_dsi_remove,
1642};
Linux 6.x block layer and io_uring tree(s)