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drm/tegra: dsi - Implement VDD supply support
[linux-block.git] / drivers / gpu / drm / tegra / dsi.c
CommitLineData
dec72739
TR		 1/*
2 * Copyright (C) 2013 NVIDIA Corporation
3 *
9a2ac2dc
TR		 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
dec72739
TR		 7 */
8
9#include <linux/clk.h>
10#include <linux/debugfs.h>
11#include <linux/host1x.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15#include <linux/reset.h>
16
3b077afb
TR		 17#include <linux/regulator/consumer.h>
18
dec72739
TR		 19#include <drm/drm_mipi_dsi.h>
20#include <drm/drm_panel.h>
21
22#include <video/mipi_display.h>
23
24#include "dc.h"
25#include "drm.h"
26#include "dsi.h"
27#include "mipi-phy.h"
28
29#define DSI_VIDEO_FIFO_DEPTH (1920 / 4)
30#define DSI_HOST_FIFO_DEPTH 64
31
32struct tegra_dsi {
33 struct host1x_client client;
34 struct tegra_output output;
35 struct device *dev;
36
37 void __iomem *regs;
38
39 struct reset_control *rst;
40 struct clk *clk_parent;
41 struct clk *clk_lp;
42 struct clk *clk;
43
44 struct drm_info_list *debugfs_files;
45 struct drm_minor *minor;
46 struct dentry *debugfs;
47
48 enum mipi_dsi_pixel_format format;
49 unsigned int lanes;
50
51 struct tegra_mipi_device *mipi;
52 struct mipi_dsi_host host;
3b077afb
TR		 53
54 struct regulator *vdd;
dec72739
TR		 55};
56
57static inline struct tegra_dsi *
58host1x_client_to_dsi(struct host1x_client *client)
59{
60 return container_of(client, struct tegra_dsi, client);
61}
62
63static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
64{
65 return container_of(host, struct tegra_dsi, host);
66}
67
68static inline struct tegra_dsi *to_dsi(struct tegra_output *output)
69{
70 return container_of(output, struct tegra_dsi, output);
71}
72
73static inline unsigned long tegra_dsi_readl(struct tegra_dsi *dsi,
74 unsigned long reg)
75{
76 return readl(dsi->regs + (reg << 2));
77}
78
79static inline void tegra_dsi_writel(struct tegra_dsi *dsi, unsigned long value,
80 unsigned long reg)
81{
82 writel(value, dsi->regs + (reg << 2));
83}
84
85static int tegra_dsi_show_regs(struct seq_file *s, void *data)
86{
87 struct drm_info_node *node = s->private;
88 struct tegra_dsi *dsi = node->info_ent->data;
89
90#define DUMP_REG(name) \
91 seq_printf(s, "%-32s %#05x %08lx\n", #name, name, \
92 tegra_dsi_readl(dsi, name))
93
94 DUMP_REG(DSI_INCR_SYNCPT);
95 DUMP_REG(DSI_INCR_SYNCPT_CONTROL);
96 DUMP_REG(DSI_INCR_SYNCPT_ERROR);
97 DUMP_REG(DSI_CTXSW);
98 DUMP_REG(DSI_RD_DATA);
99 DUMP_REG(DSI_WR_DATA);
100 DUMP_REG(DSI_POWER_CONTROL);
101 DUMP_REG(DSI_INT_ENABLE);
102 DUMP_REG(DSI_INT_STATUS);
103 DUMP_REG(DSI_INT_MASK);
104 DUMP_REG(DSI_HOST_CONTROL);
105 DUMP_REG(DSI_CONTROL);
106 DUMP_REG(DSI_SOL_DELAY);
107 DUMP_REG(DSI_MAX_THRESHOLD);
108 DUMP_REG(DSI_TRIGGER);
109 DUMP_REG(DSI_TX_CRC);
110 DUMP_REG(DSI_STATUS);
111
112 DUMP_REG(DSI_INIT_SEQ_CONTROL);
113 DUMP_REG(DSI_INIT_SEQ_DATA_0);
114 DUMP_REG(DSI_INIT_SEQ_DATA_1);
115 DUMP_REG(DSI_INIT_SEQ_DATA_2);
116 DUMP_REG(DSI_INIT_SEQ_DATA_3);
117 DUMP_REG(DSI_INIT_SEQ_DATA_4);
118 DUMP_REG(DSI_INIT_SEQ_DATA_5);
119 DUMP_REG(DSI_INIT_SEQ_DATA_6);
120 DUMP_REG(DSI_INIT_SEQ_DATA_7);
121
122 DUMP_REG(DSI_PKT_SEQ_0_LO);
123 DUMP_REG(DSI_PKT_SEQ_0_HI);
124 DUMP_REG(DSI_PKT_SEQ_1_LO);
125 DUMP_REG(DSI_PKT_SEQ_1_HI);
126 DUMP_REG(DSI_PKT_SEQ_2_LO);
127 DUMP_REG(DSI_PKT_SEQ_2_HI);
128 DUMP_REG(DSI_PKT_SEQ_3_LO);
129 DUMP_REG(DSI_PKT_SEQ_3_HI);
130 DUMP_REG(DSI_PKT_SEQ_4_LO);
131 DUMP_REG(DSI_PKT_SEQ_4_HI);
132 DUMP_REG(DSI_PKT_SEQ_5_LO);
133 DUMP_REG(DSI_PKT_SEQ_5_HI);
134
135 DUMP_REG(DSI_DCS_CMDS);
136
137 DUMP_REG(DSI_PKT_LEN_0_1);
138 DUMP_REG(DSI_PKT_LEN_2_3);
139 DUMP_REG(DSI_PKT_LEN_4_5);
140 DUMP_REG(DSI_PKT_LEN_6_7);
141
142 DUMP_REG(DSI_PHY_TIMING_0);
143 DUMP_REG(DSI_PHY_TIMING_1);
144 DUMP_REG(DSI_PHY_TIMING_2);
145 DUMP_REG(DSI_BTA_TIMING);
146
147 DUMP_REG(DSI_TIMEOUT_0);
148 DUMP_REG(DSI_TIMEOUT_1);
149 DUMP_REG(DSI_TO_TALLY);
150
151 DUMP_REG(DSI_PAD_CONTROL_0);
152 DUMP_REG(DSI_PAD_CONTROL_CD);
153 DUMP_REG(DSI_PAD_CD_STATUS);
154 DUMP_REG(DSI_VIDEO_MODE_CONTROL);
155 DUMP_REG(DSI_PAD_CONTROL_1);
156 DUMP_REG(DSI_PAD_CONTROL_2);
157 DUMP_REG(DSI_PAD_CONTROL_3);
158 DUMP_REG(DSI_PAD_CONTROL_4);
159
160 DUMP_REG(DSI_GANGED_MODE_CONTROL);
161 DUMP_REG(DSI_GANGED_MODE_START);
162 DUMP_REG(DSI_GANGED_MODE_SIZE);
163
164 DUMP_REG(DSI_RAW_DATA_BYTE_COUNT);
165 DUMP_REG(DSI_ULTRA_LOW_POWER_CONTROL);
166
167 DUMP_REG(DSI_INIT_SEQ_DATA_8);
168 DUMP_REG(DSI_INIT_SEQ_DATA_9);
169 DUMP_REG(DSI_INIT_SEQ_DATA_10);
170 DUMP_REG(DSI_INIT_SEQ_DATA_11);
171 DUMP_REG(DSI_INIT_SEQ_DATA_12);
172 DUMP_REG(DSI_INIT_SEQ_DATA_13);
173 DUMP_REG(DSI_INIT_SEQ_DATA_14);
174 DUMP_REG(DSI_INIT_SEQ_DATA_15);
175
176#undef DUMP_REG
177
178 return 0;
179}
180
181static struct drm_info_list debugfs_files[] = {
182 { "regs", tegra_dsi_show_regs, 0, NULL },
183};
184
185static int tegra_dsi_debugfs_init(struct tegra_dsi *dsi,
186 struct drm_minor *minor)
187{
188 const char *name = dev_name(dsi->dev);
189 unsigned int i;
190 int err;
191
192 dsi->debugfs = debugfs_create_dir(name, minor->debugfs_root);
193 if (!dsi->debugfs)
194 return -ENOMEM;
195
196 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
197 GFP_KERNEL);
198 if (!dsi->debugfs_files) {
199 err = -ENOMEM;
200 goto remove;
201 }
202
203 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
204 dsi->debugfs_files[i].data = dsi;
205
206 err = drm_debugfs_create_files(dsi->debugfs_files,
207 ARRAY_SIZE(debugfs_files),
208 dsi->debugfs, minor);
209 if (err < 0)
210 goto free;
211
212 dsi->minor = minor;
213
214 return 0;
215
216free:
217 kfree(dsi->debugfs_files);
218 dsi->debugfs_files = NULL;
219remove:
220 debugfs_remove(dsi->debugfs);
221 dsi->debugfs = NULL;
222
223 return err;
224}
225
226static int tegra_dsi_debugfs_exit(struct tegra_dsi *dsi)
227{
228 drm_debugfs_remove_files(dsi->debugfs_files, ARRAY_SIZE(debugfs_files),
229 dsi->minor);
230 dsi->minor = NULL;
231
232 kfree(dsi->debugfs_files);
233 dsi->debugfs_files = NULL;
234
235 debugfs_remove(dsi->debugfs);
236 dsi->debugfs = NULL;
237
238 return 0;
239}
240
241#define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
242#define PKT_LEN0(len) (((len) & 0x07) << 0)
243#define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19))
244#define PKT_LEN1(len) (((len) & 0x07) << 10)
245#define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29))
246#define PKT_LEN2(len) (((len) & 0x07) << 20)
247
248#define PKT_LP (1 << 30)
249#define NUM_PKT_SEQ 12
250
251/* non-burst mode with sync-end */
252static const u32 pkt_seq_vnb_syne[NUM_PKT_SEQ] = {
253 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
254 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
255 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
256 PKT_LP,
257 [ 1] = 0,
258 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
259 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
260 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
261 PKT_LP,
262 [ 3] = 0,
263 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
264 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
265 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
266 PKT_LP,
267 [ 5] = 0,
268 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
269 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
270 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
271 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
272 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
273 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
274 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
275 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
276 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
277 PKT_LP,
278 [ 9] = 0,
279 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
280 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
281 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
282 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
283 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
284 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
285};
286
287static int tegra_dsi_set_phy_timing(struct tegra_dsi *dsi)
288{
289 struct mipi_dphy_timing timing;
290 unsigned long value, period;
291 long rate;
292 int err;
293
294 rate = clk_get_rate(dsi->clk);
295 if (rate < 0)
296 return rate;
297
298 period = DIV_ROUND_CLOSEST(1000000000UL, rate * 2);
299
300 err = mipi_dphy_timing_get_default(&timing, period);
301 if (err < 0)
302 return err;
303
304 err = mipi_dphy_timing_validate(&timing, period);
305 if (err < 0) {
306 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
307 return err;
308 }
309
310 /*
311 * The D-PHY timing fields below are expressed in byte-clock cycles,
312 * so multiply the period by 8.
313 */
314 period *= 8;
315
316 value = DSI_TIMING_FIELD(timing.hsexit, period, 1) << 24 |
317 DSI_TIMING_FIELD(timing.hstrail, period, 0) << 16 |
318 DSI_TIMING_FIELD(timing.hszero, period, 3) << 8 |
319 DSI_TIMING_FIELD(timing.hsprepare, period, 1);
320 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
321
322 value = DSI_TIMING_FIELD(timing.clktrail, period, 1) << 24 |
323 DSI_TIMING_FIELD(timing.clkpost, period, 1) << 16 |
324 DSI_TIMING_FIELD(timing.clkzero, period, 1) << 8 |
325 DSI_TIMING_FIELD(timing.lpx, period, 1);
326 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
327
328 value = DSI_TIMING_FIELD(timing.clkprepare, period, 1) << 16 |
329 DSI_TIMING_FIELD(timing.clkpre, period, 1) << 8 |
330 DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
331 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
332
333 value = DSI_TIMING_FIELD(timing.taget, period, 1) << 16 |
334 DSI_TIMING_FIELD(timing.tasure, period, 1) << 8 |
335 DSI_TIMING_FIELD(timing.tago, period, 1);
336 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
337
338 return 0;
339}
340
341static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
342 unsigned int *mulp, unsigned int *divp)
343{
344 switch (format) {
345 case MIPI_DSI_FMT_RGB666_PACKED:
346 case MIPI_DSI_FMT_RGB888:
347 *mulp = 3;
348 *divp = 1;
349 break;
350
351 case MIPI_DSI_FMT_RGB565:
352 *mulp = 2;
353 *divp = 1;
354 break;
355
356 case MIPI_DSI_FMT_RGB666:
357 *mulp = 9;
358 *divp = 4;
359 break;
360
361 default:
362 return -EINVAL;
363 }
364
365 return 0;
366}
367
f7d6889b
TR		 368static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
369 enum tegra_dsi_format *fmt)
370{
371 switch (format) {
372 case MIPI_DSI_FMT_RGB888:
373 *fmt = TEGRA_DSI_FORMAT_24P;
374 break;
375
376 case MIPI_DSI_FMT_RGB666:
377 *fmt = TEGRA_DSI_FORMAT_18NP;
378 break;
379
380 case MIPI_DSI_FMT_RGB666_PACKED:
381 *fmt = TEGRA_DSI_FORMAT_18P;
382 break;
383
384 case MIPI_DSI_FMT_RGB565:
385 *fmt = TEGRA_DSI_FORMAT_16P;
386 break;
387
388 default:
389 return -EINVAL;
390 }
391
392 return 0;
393}
394
dec72739
TR		 395static int tegra_output_dsi_enable(struct tegra_output *output)
396{
397 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
398 struct drm_display_mode *mode = &dc->base.mode;
399 unsigned int hact, hsw, hbp, hfp, i, mul, div;
400 struct tegra_dsi *dsi = to_dsi(output);
401 /* FIXME: don't hardcode this */
402 const u32 *pkt_seq = pkt_seq_vnb_syne;
f7d6889b 403 enum tegra_dsi_format format;
dec72739
TR		 404 unsigned long value;
405 int err;
406
407 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
408 if (err < 0)
409 return err;
410
f7d6889b
TR		 411 err = tegra_dsi_get_format(dsi->format, &format);
412 if (err < 0)
413 return err;
414
dec72739
TR		 415 err = clk_enable(dsi->clk);
416 if (err < 0)
417 return err;
418
419 reset_control_deassert(dsi->rst);
420
f7d6889b 421 value = DSI_CONTROL_CHANNEL(0) | DSI_CONTROL_FORMAT(format) |
dec72739
TR		 422 DSI_CONTROL_LANES(dsi->lanes - 1) |
423 DSI_CONTROL_SOURCE(dc->pipe);
424 tegra_dsi_writel(dsi, value, DSI_CONTROL);
425
426 tegra_dsi_writel(dsi, DSI_VIDEO_FIFO_DEPTH, DSI_MAX_THRESHOLD);
427
428 value = DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_CS |
429 DSI_HOST_CONTROL_ECC;
430 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
431
432 value = tegra_dsi_readl(dsi, DSI_CONTROL);
433 value |= DSI_CONTROL_HS_CLK_CTRL;
434 value &= ~DSI_CONTROL_TX_TRIG(3);
435 value &= ~DSI_CONTROL_DCS_ENABLE;
436 value |= DSI_CONTROL_VIDEO_ENABLE;
437 value &= ~DSI_CONTROL_HOST_ENABLE;
438 tegra_dsi_writel(dsi, value, DSI_CONTROL);
439
440 err = tegra_dsi_set_phy_timing(dsi);
441 if (err < 0)
442 return err;
443
444 for (i = 0; i < NUM_PKT_SEQ; i++)
445 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
446
447 /* horizontal active pixels */
448 hact = mode->hdisplay * mul / div;
449
450 /* horizontal sync width */
451 hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
452 hsw -= 10;
453
454 /* horizontal back porch */
455 hbp = (mode->htotal - mode->hsync_end) * mul / div;
456 hbp -= 14;
457
458 /* horizontal front porch */
459 hfp = (mode->hsync_start - mode->hdisplay) * mul / div;
460 hfp -= 8;
461
462 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
463 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
464 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
465 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
466
467 /* set SOL delay */
468 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
469
470 /* enable display controller */
471 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
472 value |= DSI_ENABLE;
473 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
474
dec72739
TR		 475 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
476 value &= ~DISP_CTRL_MODE_MASK;
477 value |= DISP_CTRL_MODE_C_DISPLAY;
478 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
479
72d30286
TR		 480 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
481 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
482 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
483 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
484
dec72739
TR		 485 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
486 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
487
488 /* enable DSI controller */
489 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
490 value |= DSI_POWER_CONTROL_ENABLE;
491 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
492
493 return 0;
494}
495
496static int tegra_output_dsi_disable(struct tegra_output *output)
497{
498 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
499 struct tegra_dsi *dsi = to_dsi(output);
500 unsigned long value;
501
502 /* disable DSI controller */
503 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
504 value &= DSI_POWER_CONTROL_ENABLE;
505 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
506
507 /*
72d30286
TR		 508 * The following accesses registers of the display controller, so make
509 * sure it's only executed when the output is attached to one.
dec72739
TR		 510 */
511 if (dc) {
72d30286
TR		 512 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
513 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
514 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
515 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
516
dec72739
TR		 517 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
518 value &= ~DISP_CTRL_MODE_MASK;
519 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
520
521 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
522 value &= ~DSI_ENABLE;
523 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
72d30286
TR		 524
525 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
526 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
dec72739
TR		 527 }
528
529 clk_disable(dsi->clk);
530
531 return 0;
532}
533
534static int tegra_output_dsi_setup_clock(struct tegra_output *output,
535 struct clk *clk, unsigned long pclk)
536{
537 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
538 struct drm_display_mode *mode = &dc->base.mode;
539 unsigned int timeout, mul, div, vrefresh;
540 struct tegra_dsi *dsi = to_dsi(output);
541 unsigned long bclk, plld, value;
542 struct clk *base;
543 int err;
544
545 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
546 if (err < 0)
547 return err;
548
549 vrefresh = drm_mode_vrefresh(mode);
550
551 pclk = mode->htotal * mode->vtotal * vrefresh;
552 bclk = (pclk * mul) / (div * dsi->lanes);
553 plld = DIV_ROUND_UP(bclk * 8, 1000000);
554 pclk = (plld * 1000000) / 2;
555
556 err = clk_set_parent(clk, dsi->clk_parent);
557 if (err < 0) {
558 dev_err(dsi->dev, "failed to set parent clock: %d\n", err);
559 return err;
560 }
561
562 base = clk_get_parent(dsi->clk_parent);
563
564 /*
565 * This assumes that the parent clock is pll_d_out0 or pll_d2_out
566 * respectively, each of which divides the base pll_d by 2.
567 */
568 err = clk_set_rate(base, pclk * 2);
569 if (err < 0) {
570 dev_err(dsi->dev, "failed to set base clock rate to %lu Hz\n",
571 pclk * 2);
572 return err;
573 }
574
575 /*
576 * XXX: Move the below somewhere else so that we don't need to have
577 * access to the vrefresh in this function?
578 */
579
580 /* one frame high-speed transmission timeout */
581 timeout = (bclk / vrefresh) / 512;
582 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
583 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
584
585 /* 2 ms peripheral timeout for panel */
586 timeout = 2 * bclk / 512 * 1000;
587 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
588 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
589
590 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
591 tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
592
593 return 0;
594}
595
596static int tegra_output_dsi_check_mode(struct tegra_output *output,
597 struct drm_display_mode *mode,
598 enum drm_mode_status *status)
599{
600 /*
601 * FIXME: For now, always assume that the mode is okay.
602 */
603
604 *status = MODE_OK;
605
606 return 0;
607}
608
609static const struct tegra_output_ops dsi_ops = {
610 .enable = tegra_output_dsi_enable,
611 .disable = tegra_output_dsi_disable,
612 .setup_clock = tegra_output_dsi_setup_clock,
613 .check_mode = tegra_output_dsi_check_mode,
614};
615
616static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
617{
618 unsigned long value;
619
620 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
621 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
622
623 return 0;
624}
625
626static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
627{
628 unsigned long value;
629
630 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
631 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
632 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
633 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
634 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
635
636 /* start calibration */
637 tegra_dsi_pad_enable(dsi);
638
639 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
640 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
641 DSI_PAD_OUT_CLK(0x0);
642 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
643
644 return tegra_mipi_calibrate(dsi->mipi);
645}
646
647static int tegra_dsi_init(struct host1x_client *client)
648{
649 struct tegra_drm *tegra = dev_get_drvdata(client->parent);
650 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
dec72739
TR		 651 int err;
652
653 dsi->output.type = TEGRA_OUTPUT_DSI;
654 dsi->output.dev = client->dev;
655 dsi->output.ops = &dsi_ops;
656
657 err = tegra_output_init(tegra->drm, &dsi->output);
658 if (err < 0) {
659 dev_err(client->dev, "output setup failed: %d\n", err);
660 return err;
661 }
662
663 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
664 err = tegra_dsi_debugfs_init(dsi, tegra->drm->primary);
665 if (err < 0)
666 dev_err(dsi->dev, "debugfs setup failed: %d\n", err);
667 }
668
dec72739
TR		 669 err = tegra_dsi_pad_calibrate(dsi);
670 if (err < 0) {
671 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
672 return err;
673 }
674
dec72739
TR		 675 return 0;
676}
677
678static int tegra_dsi_exit(struct host1x_client *client)
679{
680 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
681 int err;
682
683 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
684 err = tegra_dsi_debugfs_exit(dsi);
685 if (err < 0)
686 dev_err(dsi->dev, "debugfs cleanup failed: %d\n", err);
687 }
688
689 err = tegra_output_disable(&dsi->output);
690 if (err < 0) {
691 dev_err(client->dev, "output failed to disable: %d\n", err);
692 return err;
693 }
694
695 err = tegra_output_exit(&dsi->output);
696 if (err < 0) {
697 dev_err(client->dev, "output cleanup failed: %d\n", err);
698 return err;
699 }
700
701 return 0;
702}
703
704static const struct host1x_client_ops dsi_client_ops = {
705 .init = tegra_dsi_init,
706 .exit = tegra_dsi_exit,
707};
708
709static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
710{
711 struct clk *parent;
712 int err;
713
714 parent = clk_get_parent(dsi->clk);
715 if (!parent)
716 return -EINVAL;
717
718 err = clk_set_parent(parent, dsi->clk_parent);
719 if (err < 0)
720 return err;
721
722 return 0;
723}
724
dec72739
TR		 725static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
726 struct mipi_dsi_device *device)
727{
728 struct tegra_dsi *dsi = host_to_tegra(host);
729 struct tegra_output *output = &dsi->output;
730
731 dsi->format = device->format;
732 dsi->lanes = device->lanes;
733
734 output->panel = of_drm_find_panel(device->dev.of_node);
735 if (output->panel) {
736 if (output->connector.dev)
737 drm_helper_hpd_irq_event(output->connector.dev);
738 }
739
740 return 0;
741}
742
743static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
744 struct mipi_dsi_device *device)
745{
746 struct tegra_dsi *dsi = host_to_tegra(host);
747 struct tegra_output *output = &dsi->output;
748
749 if (output->panel && &device->dev == output->panel->dev) {
750 if (output->connector.dev)
751 drm_helper_hpd_irq_event(output->connector.dev);
752
753 output->panel = NULL;
754 }
755
756 return 0;
757}
758
759static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
760 .attach = tegra_dsi_host_attach,
761 .detach = tegra_dsi_host_detach,
762};
763
764static int tegra_dsi_probe(struct platform_device *pdev)
765{
766 struct tegra_dsi *dsi;
767 struct resource *regs;
768 int err;
769
770 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
771 if (!dsi)
772 return -ENOMEM;
773
774 dsi->output.dev = dsi->dev = &pdev->dev;
775
776 err = tegra_output_probe(&dsi->output);
777 if (err < 0)
778 return err;
779
780 /*
781 * Assume these values by default. When a DSI peripheral driver
782 * attaches to the DSI host, the parameters will be taken from
783 * the attached device.
784 */
785 dsi->format = MIPI_DSI_FMT_RGB888;
786 dsi->lanes = 4;
787
788 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi");
789 if (IS_ERR(dsi->rst))
790 return PTR_ERR(dsi->rst);
791
792 dsi->clk = devm_clk_get(&pdev->dev, NULL);
793 if (IS_ERR(dsi->clk)) {
794 dev_err(&pdev->dev, "cannot get DSI clock\n");
795 return PTR_ERR(dsi->clk);
796 }
797
798 err = clk_prepare_enable(dsi->clk);
799 if (err < 0) {
800 dev_err(&pdev->dev, "cannot enable DSI clock\n");
801 return err;
802 }
803
804 dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
805 if (IS_ERR(dsi->clk_lp)) {
806 dev_err(&pdev->dev, "cannot get low-power clock\n");
807 return PTR_ERR(dsi->clk_lp);
808 }
809
810 err = clk_prepare_enable(dsi->clk_lp);
811 if (err < 0) {
812 dev_err(&pdev->dev, "cannot enable low-power clock\n");
813 return err;
814 }
815
816 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent");
817 if (IS_ERR(dsi->clk_parent)) {
818 dev_err(&pdev->dev, "cannot get parent clock\n");
819 return PTR_ERR(dsi->clk_parent);
820 }
821
822 err = clk_prepare_enable(dsi->clk_parent);
823 if (err < 0) {
824 dev_err(&pdev->dev, "cannot enable parent clock\n");
825 return err;
826 }
827
3b077afb
TR		 828 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi");
829 if (IS_ERR(dsi->vdd)) {
830 dev_err(&pdev->dev, "cannot get VDD supply\n");
831 return PTR_ERR(dsi->vdd);
832 }
833
834 err = regulator_enable(dsi->vdd);
835 if (err < 0) {
836 dev_err(&pdev->dev, "cannot enable VDD supply\n");
837 return err;
838 }
839
dec72739
TR		 840 err = tegra_dsi_setup_clocks(dsi);
841 if (err < 0) {
842 dev_err(&pdev->dev, "cannot setup clocks\n");
843 return err;
844 }
845
846 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
847 dsi->regs = devm_ioremap_resource(&pdev->dev, regs);
85316eae
WY		 848 if (IS_ERR(dsi->regs))
849 return PTR_ERR(dsi->regs);
dec72739 850
dec72739
TR		 851 dsi->mipi = tegra_mipi_request(&pdev->dev);
852 if (IS_ERR(dsi->mipi))
853 return PTR_ERR(dsi->mipi);
854
855 dsi->host.ops = &tegra_dsi_host_ops;
856 dsi->host.dev = &pdev->dev;
857
858 err = mipi_dsi_host_register(&dsi->host);
859 if (err < 0) {
860 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err);
861 return err;
862 }
863
864 INIT_LIST_HEAD(&dsi->client.list);
865 dsi->client.ops = &dsi_client_ops;
866 dsi->client.dev = &pdev->dev;
867
868 err = host1x_client_register(&dsi->client);
869 if (err < 0) {
870 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
871 err);
872 return err;
873 }
874
875 platform_set_drvdata(pdev, dsi);
876
877 return 0;
878}
879
880static int tegra_dsi_remove(struct platform_device *pdev)
881{
882 struct tegra_dsi *dsi = platform_get_drvdata(pdev);
883 int err;
884
885 err = host1x_client_unregister(&dsi->client);
886 if (err < 0) {
887 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
888 err);
889 return err;
890 }
891
892 mipi_dsi_host_unregister(&dsi->host);
893 tegra_mipi_free(dsi->mipi);
894
3b077afb 895 regulator_disable(dsi->vdd);
dec72739
TR		 896 clk_disable_unprepare(dsi->clk_parent);
897 clk_disable_unprepare(dsi->clk_lp);
898 clk_disable_unprepare(dsi->clk);
899
900 err = tegra_output_remove(&dsi->output);
901 if (err < 0) {
902 dev_err(&pdev->dev, "failed to remove output: %d\n", err);
903 return err;
904 }
905
906 return 0;
907}
908
909static const struct of_device_id tegra_dsi_of_match[] = {
910 { .compatible = "nvidia,tegra114-dsi", },
911 { },
912};
913
914struct platform_driver tegra_dsi_driver = {
915 .driver = {
916 .name = "tegra-dsi",
917 .of_match_table = tegra_dsi_of_match,
918 },
919 .probe = tegra_dsi_probe,
920 .remove = tegra_dsi_remove,
921};
Linux 6.x block layer and io_uring tree(s)