Commit | Line | Data |
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d8f4a9ed TR |
1 | /* |
2 | * Copyright (C) 2012 Avionic Design GmbH | |
d43f81cb | 3 | * Copyright (C) 2012-2013 NVIDIA CORPORATION. All rights reserved. |
d8f4a9ed TR |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
4231c6b0 TB |
10 | #ifndef HOST1X_DRM_H |
11 | #define HOST1X_DRM_H 1 | |
d8f4a9ed | 12 | |
e1e90644 TR |
13 | #include <uapi/drm/tegra_drm.h> |
14 | #include <linux/host1x.h> | |
ad926015 | 15 | #include <linux/iova.h> |
fb36d0ee | 16 | #include <linux/of_gpio.h> |
e1e90644 | 17 | |
d8f4a9ed TR |
18 | #include <drm/drmP.h> |
19 | #include <drm/drm_crtc_helper.h> | |
20 | #include <drm/drm_edid.h> | |
9338203c | 21 | #include <drm/drm_encoder.h> |
d8f4a9ed | 22 | #include <drm/drm_fb_helper.h> |
d8f4a9ed TR |
23 | #include <drm/drm_fixed.h> |
24 | ||
c134f019 | 25 | #include "gem.h" |
67e04d1a | 26 | #include "trace.h" |
c134f019 | 27 | |
ca48080a SW |
28 | struct reset_control; |
29 | ||
de2ba664 AM |
30 | struct tegra_fb { |
31 | struct drm_framebuffer base; | |
32 | struct tegra_bo **planes; | |
33 | unsigned int num_planes; | |
34 | }; | |
35 | ||
b110ef37 | 36 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
de2ba664 AM |
37 | struct tegra_fbdev { |
38 | struct drm_fb_helper base; | |
39 | struct tegra_fb *fb; | |
40 | }; | |
60c2f709 | 41 | #endif |
de2ba664 | 42 | |
386a2a71 | 43 | struct tegra_drm { |
d8f4a9ed | 44 | struct drm_device *drm; |
d8f4a9ed | 45 | |
df06b759 | 46 | struct iommu_domain *domain; |
347ad49d | 47 | struct mutex mm_lock; |
df06b759 TR |
48 | struct drm_mm mm; |
49 | ||
ad926015 MP |
50 | struct { |
51 | struct iova_domain domain; | |
52 | unsigned long shift; | |
53 | unsigned long limit; | |
54 | } carveout; | |
55 | ||
d8f4a9ed TR |
56 | struct mutex clients_lock; |
57 | struct list_head clients; | |
58 | ||
b110ef37 | 59 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
de2ba664 | 60 | struct tegra_fbdev *fbdev; |
60c2f709 | 61 | #endif |
d1f3e1e0 TR |
62 | |
63 | unsigned int pitch_align; | |
1503ca47 TR |
64 | |
65 | struct { | |
66 | struct drm_atomic_state *state; | |
67 | struct work_struct work; | |
68 | struct mutex lock; | |
69 | } commit; | |
986c58d1 TR |
70 | |
71 | struct drm_atomic_state *state; | |
d8f4a9ed TR |
72 | }; |
73 | ||
53fa7f72 | 74 | struct tegra_drm_client; |
d8f4a9ed | 75 | |
c88c3630 | 76 | struct tegra_drm_context { |
53fa7f72 | 77 | struct tegra_drm_client *client; |
d43f81cb | 78 | struct host1x_channel *channel; |
bdd2f9cd | 79 | unsigned int id; |
d43f81cb TB |
80 | }; |
81 | ||
53fa7f72 TR |
82 | struct tegra_drm_client_ops { |
83 | int (*open_channel)(struct tegra_drm_client *client, | |
c88c3630 TR |
84 | struct tegra_drm_context *context); |
85 | void (*close_channel)(struct tegra_drm_context *context); | |
c40f0f1a | 86 | int (*is_addr_reg)(struct device *dev, u32 class, u32 offset); |
0f563a4b | 87 | int (*is_valid_class)(u32 class); |
c88c3630 | 88 | int (*submit)(struct tegra_drm_context *context, |
d43f81cb TB |
89 | struct drm_tegra_submit *args, struct drm_device *drm, |
90 | struct drm_file *file); | |
91 | }; | |
92 | ||
c40f0f1a TR |
93 | int tegra_drm_submit(struct tegra_drm_context *context, |
94 | struct drm_tegra_submit *args, struct drm_device *drm, | |
95 | struct drm_file *file); | |
96 | ||
53fa7f72 TR |
97 | struct tegra_drm_client { |
98 | struct host1x_client base; | |
776dc384 | 99 | struct list_head list; |
d43f81cb | 100 | |
53fa7f72 | 101 | const struct tegra_drm_client_ops *ops; |
d8f4a9ed TR |
102 | }; |
103 | ||
53fa7f72 | 104 | static inline struct tegra_drm_client * |
776dc384 | 105 | host1x_to_drm_client(struct host1x_client *client) |
53fa7f72 TR |
106 | { |
107 | return container_of(client, struct tegra_drm_client, base); | |
108 | } | |
109 | ||
688c59af TR |
110 | int tegra_drm_register_client(struct tegra_drm *tegra, |
111 | struct tegra_drm_client *client); | |
112 | int tegra_drm_unregister_client(struct tegra_drm *tegra, | |
113 | struct tegra_drm_client *client); | |
776dc384 | 114 | |
688c59af TR |
115 | int tegra_drm_init(struct tegra_drm *tegra, struct drm_device *drm); |
116 | int tegra_drm_exit(struct tegra_drm *tegra); | |
d8f4a9ed | 117 | |
ad926015 MP |
118 | void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *iova); |
119 | void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt, | |
120 | dma_addr_t iova); | |
121 | ||
8620fc62 | 122 | struct tegra_dc_soc_info; |
d8f4a9ed TR |
123 | struct tegra_output; |
124 | ||
791ddb1e TR |
125 | struct tegra_dc_stats { |
126 | unsigned long frames; | |
127 | unsigned long vblank; | |
128 | unsigned long underflow; | |
129 | unsigned long overflow; | |
130 | }; | |
131 | ||
d8f4a9ed | 132 | struct tegra_dc { |
776dc384 | 133 | struct host1x_client client; |
42e9ce05 | 134 | struct host1x_syncpt *syncpt; |
d8f4a9ed | 135 | struct device *dev; |
d18d3033 | 136 | spinlock_t lock; |
d8f4a9ed TR |
137 | |
138 | struct drm_crtc base; | |
70293ed0 | 139 | unsigned int powergate; |
d8f4a9ed TR |
140 | int pipe; |
141 | ||
142 | struct clk *clk; | |
ca48080a | 143 | struct reset_control *rst; |
d8f4a9ed TR |
144 | void __iomem *regs; |
145 | int irq; | |
146 | ||
147 | struct tegra_output *rgb; | |
148 | ||
791ddb1e | 149 | struct tegra_dc_stats stats; |
d8f4a9ed TR |
150 | struct list_head list; |
151 | ||
152 | struct drm_info_list *debugfs_files; | |
153 | struct drm_minor *minor; | |
154 | struct dentry *debugfs; | |
3c03c46a TR |
155 | |
156 | /* page-flip handling */ | |
157 | struct drm_pending_vblank_event *event; | |
8620fc62 TR |
158 | |
159 | const struct tegra_dc_soc_info *soc; | |
df06b759 TR |
160 | |
161 | struct iommu_domain *domain; | |
d8f4a9ed TR |
162 | }; |
163 | ||
53fa7f72 | 164 | static inline struct tegra_dc * |
776dc384 | 165 | host1x_client_to_dc(struct host1x_client *client) |
d8f4a9ed TR |
166 | { |
167 | return container_of(client, struct tegra_dc, client); | |
168 | } | |
169 | ||
170 | static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc) | |
171 | { | |
37826519 | 172 | return crtc ? container_of(crtc, struct tegra_dc, base) : NULL; |
d8f4a9ed TR |
173 | } |
174 | ||
03a60569 | 175 | static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value, |
3be713be | 176 | unsigned int offset) |
d8f4a9ed | 177 | { |
67e04d1a | 178 | trace_dc_writel(dc->dev, offset, value); |
03a60569 | 179 | writel(value, dc->regs + (offset << 2)); |
d8f4a9ed TR |
180 | } |
181 | ||
3be713be | 182 | static inline u32 tegra_dc_readl(struct tegra_dc *dc, unsigned int offset) |
d8f4a9ed | 183 | { |
67e04d1a TR |
184 | u32 value = readl(dc->regs + (offset << 2)); |
185 | ||
186 | trace_dc_readl(dc->dev, offset, value); | |
187 | ||
188 | return value; | |
d8f4a9ed TR |
189 | } |
190 | ||
f34bc787 TR |
191 | struct tegra_dc_window { |
192 | struct { | |
193 | unsigned int x; | |
194 | unsigned int y; | |
195 | unsigned int w; | |
196 | unsigned int h; | |
197 | } src; | |
198 | struct { | |
199 | unsigned int x; | |
200 | unsigned int y; | |
201 | unsigned int w; | |
202 | unsigned int h; | |
203 | } dst; | |
204 | unsigned int bits_per_pixel; | |
f34bc787 TR |
205 | unsigned int stride[2]; |
206 | unsigned long base[3]; | |
db7fbdfd | 207 | bool bottom_up; |
c134f019 TR |
208 | |
209 | struct tegra_bo_tiling tiling; | |
8f604f8c TR |
210 | u32 format; |
211 | u32 swap; | |
f34bc787 TR |
212 | }; |
213 | ||
214 | /* from dc.c */ | |
62b9e063 | 215 | void tegra_dc_commit(struct tegra_dc *dc); |
ca915b10 TR |
216 | int tegra_dc_state_setup_clock(struct tegra_dc *dc, |
217 | struct drm_crtc_state *crtc_state, | |
218 | struct clk *clk, unsigned long pclk, | |
219 | unsigned int div); | |
f34bc787 | 220 | |
d8f4a9ed TR |
221 | struct tegra_output { |
222 | struct device_node *of_node; | |
223 | struct device *dev; | |
224 | ||
9be7d864 | 225 | struct drm_panel *panel; |
d8f4a9ed TR |
226 | struct i2c_adapter *ddc; |
227 | const struct edid *edid; | |
228 | unsigned int hpd_irq; | |
229 | int hpd_gpio; | |
fb36d0ee | 230 | enum of_gpio_flags hpd_gpio_flags; |
d8f4a9ed TR |
231 | |
232 | struct drm_encoder encoder; | |
233 | struct drm_connector connector; | |
234 | }; | |
235 | ||
236 | static inline struct tegra_output *encoder_to_output(struct drm_encoder *e) | |
237 | { | |
238 | return container_of(e, struct tegra_output, encoder); | |
239 | } | |
240 | ||
241 | static inline struct tegra_output *connector_to_output(struct drm_connector *c) | |
242 | { | |
243 | return container_of(c, struct tegra_output, connector); | |
244 | } | |
245 | ||
d8f4a9ed | 246 | /* from rgb.c */ |
688c59af TR |
247 | int tegra_dc_rgb_probe(struct tegra_dc *dc); |
248 | int tegra_dc_rgb_remove(struct tegra_dc *dc); | |
249 | int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc); | |
250 | int tegra_dc_rgb_exit(struct tegra_dc *dc); | |
d8f4a9ed TR |
251 | |
252 | /* from output.c */ | |
688c59af | 253 | int tegra_output_probe(struct tegra_output *output); |
328ec69e | 254 | void tegra_output_remove(struct tegra_output *output); |
688c59af | 255 | int tegra_output_init(struct drm_device *drm, struct tegra_output *output); |
328ec69e | 256 | void tegra_output_exit(struct tegra_output *output); |
d8f4a9ed | 257 | |
132085d8 | 258 | int tegra_output_connector_get_modes(struct drm_connector *connector); |
132085d8 TR |
259 | enum drm_connector_status |
260 | tegra_output_connector_detect(struct drm_connector *connector, bool force); | |
261 | void tegra_output_connector_destroy(struct drm_connector *connector); | |
262 | ||
263 | void tegra_output_encoder_destroy(struct drm_encoder *encoder); | |
264 | ||
6b6b6042 | 265 | /* from dpaux.c */ |
6b6b6042 | 266 | struct drm_dp_link; |
6b6b6042 | 267 | |
9542c237 TR |
268 | struct drm_dp_aux *drm_dp_aux_find_by_of_node(struct device_node *np); |
269 | enum drm_connector_status drm_dp_aux_detect(struct drm_dp_aux *aux); | |
270 | int drm_dp_aux_attach(struct drm_dp_aux *aux, struct tegra_output *output); | |
271 | int drm_dp_aux_detach(struct drm_dp_aux *aux); | |
272 | int drm_dp_aux_enable(struct drm_dp_aux *aux); | |
273 | int drm_dp_aux_disable(struct drm_dp_aux *aux); | |
274 | int drm_dp_aux_prepare(struct drm_dp_aux *aux, u8 encoding); | |
275 | int drm_dp_aux_train(struct drm_dp_aux *aux, struct drm_dp_link *link, | |
276 | u8 pattern); | |
6b6b6042 | 277 | |
d8f4a9ed | 278 | /* from fb.c */ |
de2ba664 AM |
279 | struct tegra_bo *tegra_fb_get_plane(struct drm_framebuffer *framebuffer, |
280 | unsigned int index); | |
db7fbdfd | 281 | bool tegra_fb_is_bottom_up(struct drm_framebuffer *framebuffer); |
c134f019 TR |
282 | int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer, |
283 | struct tegra_bo_tiling *tiling); | |
f9914214 TR |
284 | struct drm_framebuffer *tegra_fb_create(struct drm_device *drm, |
285 | struct drm_file *file, | |
1eb83451 | 286 | const struct drm_mode_fb_cmd2 *cmd); |
e2215321 | 287 | int tegra_drm_fb_prepare(struct drm_device *drm); |
1d1e6fe9 | 288 | void tegra_drm_fb_free(struct drm_device *drm); |
688c59af TR |
289 | int tegra_drm_fb_init(struct drm_device *drm); |
290 | void tegra_drm_fb_exit(struct drm_device *drm); | |
986c58d1 TR |
291 | void tegra_drm_fb_suspend(struct drm_device *drm); |
292 | void tegra_drm_fb_resume(struct drm_device *drm); | |
b110ef37 | 293 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
688c59af | 294 | void tegra_fbdev_restore_mode(struct tegra_fbdev *fbdev); |
f9914214 | 295 | void tegra_fb_output_poll_changed(struct drm_device *drm); |
60c2f709 | 296 | #endif |
d8f4a9ed | 297 | |
776dc384 TR |
298 | extern struct platform_driver tegra_dc_driver; |
299 | extern struct platform_driver tegra_hdmi_driver; | |
473112e4 | 300 | extern struct platform_driver tegra_dsi_driver; |
6b6b6042 | 301 | extern struct platform_driver tegra_dpaux_driver; |
473112e4 | 302 | extern struct platform_driver tegra_sor_driver; |
776dc384 | 303 | extern struct platform_driver tegra_gr2d_driver; |
5f60ed0d | 304 | extern struct platform_driver tegra_gr3d_driver; |
0ae797a8 | 305 | extern struct platform_driver tegra_vic_driver; |
d8f4a9ed | 306 | |
4231c6b0 | 307 | #endif /* HOST1X_DRM_H */ |