Commit | Line | Data |
---|---|---|
d8f4a9ed TR |
1 | /* |
2 | * Copyright (C) 2012 Avionic Design GmbH | |
d43f81cb | 3 | * Copyright (C) 2012-2013 NVIDIA CORPORATION. All rights reserved. |
d8f4a9ed TR |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
776dc384 | 10 | #include <linux/host1x.h> |
df06b759 | 11 | #include <linux/iommu.h> |
776dc384 | 12 | |
1503ca47 | 13 | #include <drm/drm_atomic.h> |
07866963 TR |
14 | #include <drm/drm_atomic_helper.h> |
15 | ||
d8f4a9ed | 16 | #include "drm.h" |
de2ba664 | 17 | #include "gem.h" |
d8f4a9ed TR |
18 | |
19 | #define DRIVER_NAME "tegra" | |
20 | #define DRIVER_DESC "NVIDIA Tegra graphics" | |
21 | #define DRIVER_DATE "20120330" | |
22 | #define DRIVER_MAJOR 0 | |
23 | #define DRIVER_MINOR 0 | |
24 | #define DRIVER_PATCHLEVEL 0 | |
25 | ||
08943e6c TR |
26 | struct tegra_drm_file { |
27 | struct list_head contexts; | |
28 | }; | |
29 | ||
1503ca47 TR |
30 | static void tegra_atomic_schedule(struct tegra_drm *tegra, |
31 | struct drm_atomic_state *state) | |
32 | { | |
33 | tegra->commit.state = state; | |
34 | schedule_work(&tegra->commit.work); | |
35 | } | |
36 | ||
37 | static void tegra_atomic_complete(struct tegra_drm *tegra, | |
38 | struct drm_atomic_state *state) | |
39 | { | |
40 | struct drm_device *drm = tegra->drm; | |
41 | ||
42 | /* | |
43 | * Everything below can be run asynchronously without the need to grab | |
44 | * any modeset locks at all under one condition: It must be guaranteed | |
45 | * that the asynchronous work has either been cancelled (if the driver | |
46 | * supports it, which at least requires that the framebuffers get | |
47 | * cleaned up with drm_atomic_helper_cleanup_planes()) or completed | |
48 | * before the new state gets committed on the software side with | |
49 | * drm_atomic_helper_swap_state(). | |
50 | * | |
51 | * This scheme allows new atomic state updates to be prepared and | |
52 | * checked in parallel to the asynchronous completion of the previous | |
53 | * update. Which is important since compositors need to figure out the | |
54 | * composition of the next frame right after having submitted the | |
55 | * current layout. | |
56 | */ | |
57 | ||
1af434a9 | 58 | drm_atomic_helper_commit_modeset_disables(drm, state); |
1503ca47 | 59 | drm_atomic_helper_commit_planes(drm, state); |
1af434a9 | 60 | drm_atomic_helper_commit_modeset_enables(drm, state); |
1503ca47 TR |
61 | |
62 | drm_atomic_helper_wait_for_vblanks(drm, state); | |
63 | ||
64 | drm_atomic_helper_cleanup_planes(drm, state); | |
65 | drm_atomic_state_free(state); | |
66 | } | |
67 | ||
68 | static void tegra_atomic_work(struct work_struct *work) | |
69 | { | |
70 | struct tegra_drm *tegra = container_of(work, struct tegra_drm, | |
71 | commit.work); | |
72 | ||
73 | tegra_atomic_complete(tegra, tegra->commit.state); | |
74 | } | |
75 | ||
76 | static int tegra_atomic_commit(struct drm_device *drm, | |
77 | struct drm_atomic_state *state, bool async) | |
78 | { | |
79 | struct tegra_drm *tegra = drm->dev_private; | |
80 | int err; | |
81 | ||
82 | err = drm_atomic_helper_prepare_planes(drm, state); | |
83 | if (err) | |
84 | return err; | |
85 | ||
86 | /* serialize outstanding asynchronous commits */ | |
87 | mutex_lock(&tegra->commit.lock); | |
88 | flush_work(&tegra->commit.work); | |
89 | ||
90 | /* | |
91 | * This is the point of no return - everything below never fails except | |
92 | * when the hw goes bonghits. Which means we can commit the new state on | |
93 | * the software side now. | |
94 | */ | |
95 | ||
96 | drm_atomic_helper_swap_state(drm, state); | |
97 | ||
98 | if (async) | |
99 | tegra_atomic_schedule(tegra, state); | |
100 | else | |
101 | tegra_atomic_complete(tegra, state); | |
102 | ||
103 | mutex_unlock(&tegra->commit.lock); | |
104 | return 0; | |
105 | } | |
106 | ||
f9914214 TR |
107 | static const struct drm_mode_config_funcs tegra_drm_mode_funcs = { |
108 | .fb_create = tegra_fb_create, | |
109 | #ifdef CONFIG_DRM_TEGRA_FBDEV | |
110 | .output_poll_changed = tegra_fb_output_poll_changed, | |
111 | #endif | |
07866963 | 112 | .atomic_check = drm_atomic_helper_check, |
1503ca47 | 113 | .atomic_commit = tegra_atomic_commit, |
f9914214 TR |
114 | }; |
115 | ||
776dc384 | 116 | static int tegra_drm_load(struct drm_device *drm, unsigned long flags) |
692e6d7b | 117 | { |
776dc384 | 118 | struct host1x_device *device = to_host1x_device(drm->dev); |
386a2a71 | 119 | struct tegra_drm *tegra; |
692e6d7b TB |
120 | int err; |
121 | ||
776dc384 | 122 | tegra = kzalloc(sizeof(*tegra), GFP_KERNEL); |
386a2a71 | 123 | if (!tegra) |
692e6d7b TB |
124 | return -ENOMEM; |
125 | ||
df06b759 | 126 | if (iommu_present(&platform_bus_type)) { |
4553f733 TR |
127 | struct iommu_domain_geometry *geometry; |
128 | u64 start, end; | |
129 | ||
df06b759 | 130 | tegra->domain = iommu_domain_alloc(&platform_bus_type); |
bf19b885 DC |
131 | if (!tegra->domain) { |
132 | err = -ENOMEM; | |
df06b759 TR |
133 | goto free; |
134 | } | |
135 | ||
4553f733 TR |
136 | geometry = &tegra->domain->geometry; |
137 | start = geometry->aperture_start; | |
138 | end = geometry->aperture_end; | |
139 | ||
140 | DRM_DEBUG("IOMMU context initialized (aperture: %#llx-%#llx)\n", | |
141 | start, end); | |
142 | drm_mm_init(&tegra->mm, start, end - start + 1); | |
df06b759 TR |
143 | } |
144 | ||
386a2a71 TR |
145 | mutex_init(&tegra->clients_lock); |
146 | INIT_LIST_HEAD(&tegra->clients); | |
1503ca47 TR |
147 | |
148 | mutex_init(&tegra->commit.lock); | |
149 | INIT_WORK(&tegra->commit.work, tegra_atomic_work); | |
150 | ||
386a2a71 TR |
151 | drm->dev_private = tegra; |
152 | tegra->drm = drm; | |
d8f4a9ed TR |
153 | |
154 | drm_mode_config_init(drm); | |
155 | ||
f9914214 TR |
156 | drm->mode_config.min_width = 0; |
157 | drm->mode_config.min_height = 0; | |
158 | ||
159 | drm->mode_config.max_width = 4096; | |
160 | drm->mode_config.max_height = 4096; | |
161 | ||
162 | drm->mode_config.funcs = &tegra_drm_mode_funcs; | |
163 | ||
e2215321 TR |
164 | err = tegra_drm_fb_prepare(drm); |
165 | if (err < 0) | |
1d1e6fe9 | 166 | goto config; |
e2215321 TR |
167 | |
168 | drm_kms_helper_poll_init(drm); | |
169 | ||
776dc384 | 170 | err = host1x_device_init(device); |
d8f4a9ed | 171 | if (err < 0) |
1d1e6fe9 | 172 | goto fbdev; |
d8f4a9ed | 173 | |
603f0cc9 TR |
174 | /* |
175 | * We don't use the drm_irq_install() helpers provided by the DRM | |
176 | * core, so we need to set this manually in order to allow the | |
177 | * DRM_IOCTL_WAIT_VBLANK to operate correctly. | |
178 | */ | |
4423843c | 179 | drm->irq_enabled = true; |
603f0cc9 | 180 | |
42e9ce05 | 181 | /* syncpoints are used for full 32-bit hardware VBLANK counters */ |
42e9ce05 | 182 | drm->max_vblank_count = 0xffffffff; |
cdc630b6 | 183 | drm->vblank_disable_allowed = true; |
42e9ce05 | 184 | |
6e5ff998 TR |
185 | err = drm_vblank_init(drm, drm->mode_config.num_crtc); |
186 | if (err < 0) | |
1d1e6fe9 | 187 | goto device; |
6e5ff998 | 188 | |
31930d4d TR |
189 | drm_mode_config_reset(drm); |
190 | ||
d8f4a9ed TR |
191 | err = tegra_drm_fb_init(drm); |
192 | if (err < 0) | |
1d1e6fe9 | 193 | goto vblank; |
d8f4a9ed | 194 | |
d8f4a9ed | 195 | return 0; |
1d1e6fe9 TR |
196 | |
197 | vblank: | |
198 | drm_vblank_cleanup(drm); | |
199 | device: | |
200 | host1x_device_exit(device); | |
201 | fbdev: | |
202 | drm_kms_helper_poll_fini(drm); | |
203 | tegra_drm_fb_free(drm); | |
204 | config: | |
205 | drm_mode_config_cleanup(drm); | |
df06b759 TR |
206 | |
207 | if (tegra->domain) { | |
208 | iommu_domain_free(tegra->domain); | |
209 | drm_mm_takedown(&tegra->mm); | |
210 | } | |
211 | free: | |
1d1e6fe9 TR |
212 | kfree(tegra); |
213 | return err; | |
d8f4a9ed TR |
214 | } |
215 | ||
216 | static int tegra_drm_unload(struct drm_device *drm) | |
217 | { | |
776dc384 | 218 | struct host1x_device *device = to_host1x_device(drm->dev); |
df06b759 | 219 | struct tegra_drm *tegra = drm->dev_private; |
776dc384 TR |
220 | int err; |
221 | ||
d8f4a9ed TR |
222 | drm_kms_helper_poll_fini(drm); |
223 | tegra_drm_fb_exit(drm); | |
f002abc1 | 224 | drm_mode_config_cleanup(drm); |
4aa3df71 | 225 | drm_vblank_cleanup(drm); |
d8f4a9ed | 226 | |
776dc384 TR |
227 | err = host1x_device_exit(device); |
228 | if (err < 0) | |
229 | return err; | |
230 | ||
df06b759 TR |
231 | if (tegra->domain) { |
232 | iommu_domain_free(tegra->domain); | |
233 | drm_mm_takedown(&tegra->mm); | |
234 | } | |
235 | ||
1053f4dd TR |
236 | kfree(tegra); |
237 | ||
d8f4a9ed TR |
238 | return 0; |
239 | } | |
240 | ||
241 | static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp) | |
242 | { | |
08943e6c | 243 | struct tegra_drm_file *fpriv; |
d43f81cb TB |
244 | |
245 | fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); | |
246 | if (!fpriv) | |
247 | return -ENOMEM; | |
248 | ||
249 | INIT_LIST_HEAD(&fpriv->contexts); | |
250 | filp->driver_priv = fpriv; | |
251 | ||
d8f4a9ed TR |
252 | return 0; |
253 | } | |
254 | ||
c88c3630 | 255 | static void tegra_drm_context_free(struct tegra_drm_context *context) |
d43f81cb TB |
256 | { |
257 | context->client->ops->close_channel(context); | |
258 | kfree(context); | |
259 | } | |
260 | ||
d8f4a9ed TR |
261 | static void tegra_drm_lastclose(struct drm_device *drm) |
262 | { | |
6e60163b | 263 | #ifdef CONFIG_DRM_TEGRA_FBDEV |
386a2a71 | 264 | struct tegra_drm *tegra = drm->dev_private; |
d8f4a9ed | 265 | |
386a2a71 | 266 | tegra_fbdev_restore_mode(tegra->fbdev); |
60c2f709 | 267 | #endif |
d8f4a9ed TR |
268 | } |
269 | ||
c40f0f1a TR |
270 | static struct host1x_bo * |
271 | host1x_bo_lookup(struct drm_device *drm, struct drm_file *file, u32 handle) | |
272 | { | |
273 | struct drm_gem_object *gem; | |
274 | struct tegra_bo *bo; | |
275 | ||
276 | gem = drm_gem_object_lookup(drm, file, handle); | |
277 | if (!gem) | |
278 | return NULL; | |
279 | ||
280 | mutex_lock(&drm->struct_mutex); | |
281 | drm_gem_object_unreference(gem); | |
282 | mutex_unlock(&drm->struct_mutex); | |
283 | ||
284 | bo = to_tegra_bo(gem); | |
285 | return &bo->base; | |
286 | } | |
287 | ||
961e3bea TR |
288 | static int host1x_reloc_copy_from_user(struct host1x_reloc *dest, |
289 | struct drm_tegra_reloc __user *src, | |
290 | struct drm_device *drm, | |
291 | struct drm_file *file) | |
292 | { | |
293 | u32 cmdbuf, target; | |
294 | int err; | |
295 | ||
296 | err = get_user(cmdbuf, &src->cmdbuf.handle); | |
297 | if (err < 0) | |
298 | return err; | |
299 | ||
300 | err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset); | |
301 | if (err < 0) | |
302 | return err; | |
303 | ||
304 | err = get_user(target, &src->target.handle); | |
305 | if (err < 0) | |
306 | return err; | |
307 | ||
31f40f86 | 308 | err = get_user(dest->target.offset, &src->target.offset); |
961e3bea TR |
309 | if (err < 0) |
310 | return err; | |
311 | ||
312 | err = get_user(dest->shift, &src->shift); | |
313 | if (err < 0) | |
314 | return err; | |
315 | ||
316 | dest->cmdbuf.bo = host1x_bo_lookup(drm, file, cmdbuf); | |
317 | if (!dest->cmdbuf.bo) | |
318 | return -ENOENT; | |
319 | ||
320 | dest->target.bo = host1x_bo_lookup(drm, file, target); | |
321 | if (!dest->target.bo) | |
322 | return -ENOENT; | |
323 | ||
324 | return 0; | |
325 | } | |
326 | ||
c40f0f1a TR |
327 | int tegra_drm_submit(struct tegra_drm_context *context, |
328 | struct drm_tegra_submit *args, struct drm_device *drm, | |
329 | struct drm_file *file) | |
330 | { | |
331 | unsigned int num_cmdbufs = args->num_cmdbufs; | |
332 | unsigned int num_relocs = args->num_relocs; | |
333 | unsigned int num_waitchks = args->num_waitchks; | |
334 | struct drm_tegra_cmdbuf __user *cmdbufs = | |
a7ed68fc | 335 | (void __user *)(uintptr_t)args->cmdbufs; |
c40f0f1a | 336 | struct drm_tegra_reloc __user *relocs = |
a7ed68fc | 337 | (void __user *)(uintptr_t)args->relocs; |
c40f0f1a | 338 | struct drm_tegra_waitchk __user *waitchks = |
a7ed68fc | 339 | (void __user *)(uintptr_t)args->waitchks; |
c40f0f1a TR |
340 | struct drm_tegra_syncpt syncpt; |
341 | struct host1x_job *job; | |
342 | int err; | |
343 | ||
344 | /* We don't yet support other than one syncpt_incr struct per submit */ | |
345 | if (args->num_syncpts != 1) | |
346 | return -EINVAL; | |
347 | ||
348 | job = host1x_job_alloc(context->channel, args->num_cmdbufs, | |
349 | args->num_relocs, args->num_waitchks); | |
350 | if (!job) | |
351 | return -ENOMEM; | |
352 | ||
353 | job->num_relocs = args->num_relocs; | |
354 | job->num_waitchk = args->num_waitchks; | |
355 | job->client = (u32)args->context; | |
356 | job->class = context->client->base.class; | |
357 | job->serialize = true; | |
358 | ||
359 | while (num_cmdbufs) { | |
360 | struct drm_tegra_cmdbuf cmdbuf; | |
361 | struct host1x_bo *bo; | |
362 | ||
9a991600 DC |
363 | if (copy_from_user(&cmdbuf, cmdbufs, sizeof(cmdbuf))) { |
364 | err = -EFAULT; | |
c40f0f1a | 365 | goto fail; |
9a991600 | 366 | } |
c40f0f1a TR |
367 | |
368 | bo = host1x_bo_lookup(drm, file, cmdbuf.handle); | |
369 | if (!bo) { | |
370 | err = -ENOENT; | |
371 | goto fail; | |
372 | } | |
373 | ||
374 | host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset); | |
375 | num_cmdbufs--; | |
376 | cmdbufs++; | |
377 | } | |
378 | ||
961e3bea | 379 | /* copy and resolve relocations from submit */ |
c40f0f1a | 380 | while (num_relocs--) { |
961e3bea TR |
381 | err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs], |
382 | &relocs[num_relocs], drm, | |
383 | file); | |
384 | if (err < 0) | |
c40f0f1a | 385 | goto fail; |
c40f0f1a TR |
386 | } |
387 | ||
9a991600 DC |
388 | if (copy_from_user(job->waitchk, waitchks, |
389 | sizeof(*waitchks) * num_waitchks)) { | |
390 | err = -EFAULT; | |
c40f0f1a | 391 | goto fail; |
9a991600 | 392 | } |
c40f0f1a | 393 | |
9a991600 DC |
394 | if (copy_from_user(&syncpt, (void __user *)(uintptr_t)args->syncpts, |
395 | sizeof(syncpt))) { | |
396 | err = -EFAULT; | |
c40f0f1a | 397 | goto fail; |
9a991600 | 398 | } |
c40f0f1a TR |
399 | |
400 | job->is_addr_reg = context->client->ops->is_addr_reg; | |
401 | job->syncpt_incrs = syncpt.incrs; | |
402 | job->syncpt_id = syncpt.id; | |
403 | job->timeout = 10000; | |
404 | ||
405 | if (args->timeout && args->timeout < 10000) | |
406 | job->timeout = args->timeout; | |
407 | ||
408 | err = host1x_job_pin(job, context->client->base.dev); | |
409 | if (err) | |
410 | goto fail; | |
411 | ||
412 | err = host1x_job_submit(job); | |
413 | if (err) | |
414 | goto fail_submit; | |
415 | ||
416 | args->fence = job->syncpt_end; | |
417 | ||
418 | host1x_job_put(job); | |
419 | return 0; | |
420 | ||
421 | fail_submit: | |
422 | host1x_job_unpin(job); | |
423 | fail: | |
424 | host1x_job_put(job); | |
425 | return err; | |
426 | } | |
427 | ||
428 | ||
d43f81cb | 429 | #ifdef CONFIG_DRM_TEGRA_STAGING |
c88c3630 TR |
430 | static struct tegra_drm_context *tegra_drm_get_context(__u64 context) |
431 | { | |
432 | return (struct tegra_drm_context *)(uintptr_t)context; | |
433 | } | |
434 | ||
08943e6c | 435 | static bool tegra_drm_file_owns_context(struct tegra_drm_file *file, |
c88c3630 | 436 | struct tegra_drm_context *context) |
d43f81cb | 437 | { |
c88c3630 | 438 | struct tegra_drm_context *ctx; |
d43f81cb TB |
439 | |
440 | list_for_each_entry(ctx, &file->contexts, list) | |
441 | if (ctx == context) | |
442 | return true; | |
443 | ||
444 | return false; | |
445 | } | |
446 | ||
447 | static int tegra_gem_create(struct drm_device *drm, void *data, | |
448 | struct drm_file *file) | |
449 | { | |
450 | struct drm_tegra_gem_create *args = data; | |
451 | struct tegra_bo *bo; | |
452 | ||
773af77f | 453 | bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags, |
d43f81cb TB |
454 | &args->handle); |
455 | if (IS_ERR(bo)) | |
456 | return PTR_ERR(bo); | |
457 | ||
458 | return 0; | |
459 | } | |
460 | ||
461 | static int tegra_gem_mmap(struct drm_device *drm, void *data, | |
462 | struct drm_file *file) | |
463 | { | |
464 | struct drm_tegra_gem_mmap *args = data; | |
465 | struct drm_gem_object *gem; | |
466 | struct tegra_bo *bo; | |
467 | ||
468 | gem = drm_gem_object_lookup(drm, file, args->handle); | |
469 | if (!gem) | |
470 | return -EINVAL; | |
471 | ||
472 | bo = to_tegra_bo(gem); | |
473 | ||
2bc7b0ca | 474 | args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node); |
d43f81cb TB |
475 | |
476 | drm_gem_object_unreference(gem); | |
477 | ||
478 | return 0; | |
479 | } | |
480 | ||
481 | static int tegra_syncpt_read(struct drm_device *drm, void *data, | |
482 | struct drm_file *file) | |
483 | { | |
776dc384 | 484 | struct host1x *host = dev_get_drvdata(drm->dev->parent); |
d43f81cb | 485 | struct drm_tegra_syncpt_read *args = data; |
776dc384 | 486 | struct host1x_syncpt *sp; |
d43f81cb | 487 | |
776dc384 | 488 | sp = host1x_syncpt_get(host, args->id); |
d43f81cb TB |
489 | if (!sp) |
490 | return -EINVAL; | |
491 | ||
492 | args->value = host1x_syncpt_read_min(sp); | |
493 | return 0; | |
494 | } | |
495 | ||
496 | static int tegra_syncpt_incr(struct drm_device *drm, void *data, | |
497 | struct drm_file *file) | |
498 | { | |
776dc384 | 499 | struct host1x *host1x = dev_get_drvdata(drm->dev->parent); |
d43f81cb | 500 | struct drm_tegra_syncpt_incr *args = data; |
776dc384 | 501 | struct host1x_syncpt *sp; |
d43f81cb | 502 | |
776dc384 | 503 | sp = host1x_syncpt_get(host1x, args->id); |
d43f81cb TB |
504 | if (!sp) |
505 | return -EINVAL; | |
506 | ||
ebae30b1 | 507 | return host1x_syncpt_incr(sp); |
d43f81cb TB |
508 | } |
509 | ||
510 | static int tegra_syncpt_wait(struct drm_device *drm, void *data, | |
511 | struct drm_file *file) | |
512 | { | |
776dc384 | 513 | struct host1x *host1x = dev_get_drvdata(drm->dev->parent); |
d43f81cb | 514 | struct drm_tegra_syncpt_wait *args = data; |
776dc384 | 515 | struct host1x_syncpt *sp; |
d43f81cb | 516 | |
776dc384 | 517 | sp = host1x_syncpt_get(host1x, args->id); |
d43f81cb TB |
518 | if (!sp) |
519 | return -EINVAL; | |
520 | ||
521 | return host1x_syncpt_wait(sp, args->thresh, args->timeout, | |
522 | &args->value); | |
523 | } | |
524 | ||
525 | static int tegra_open_channel(struct drm_device *drm, void *data, | |
526 | struct drm_file *file) | |
527 | { | |
08943e6c | 528 | struct tegra_drm_file *fpriv = file->driver_priv; |
386a2a71 | 529 | struct tegra_drm *tegra = drm->dev_private; |
d43f81cb | 530 | struct drm_tegra_open_channel *args = data; |
c88c3630 | 531 | struct tegra_drm_context *context; |
53fa7f72 | 532 | struct tegra_drm_client *client; |
d43f81cb TB |
533 | int err = -ENODEV; |
534 | ||
535 | context = kzalloc(sizeof(*context), GFP_KERNEL); | |
536 | if (!context) | |
537 | return -ENOMEM; | |
538 | ||
776dc384 | 539 | list_for_each_entry(client, &tegra->clients, list) |
53fa7f72 | 540 | if (client->base.class == args->client) { |
d43f81cb TB |
541 | err = client->ops->open_channel(client, context); |
542 | if (err) | |
543 | break; | |
544 | ||
d43f81cb TB |
545 | list_add(&context->list, &fpriv->contexts); |
546 | args->context = (uintptr_t)context; | |
53fa7f72 | 547 | context->client = client; |
d43f81cb TB |
548 | return 0; |
549 | } | |
550 | ||
551 | kfree(context); | |
552 | return err; | |
553 | } | |
554 | ||
555 | static int tegra_close_channel(struct drm_device *drm, void *data, | |
556 | struct drm_file *file) | |
557 | { | |
08943e6c | 558 | struct tegra_drm_file *fpriv = file->driver_priv; |
776dc384 | 559 | struct drm_tegra_close_channel *args = data; |
c88c3630 TR |
560 | struct tegra_drm_context *context; |
561 | ||
562 | context = tegra_drm_get_context(args->context); | |
d43f81cb | 563 | |
08943e6c | 564 | if (!tegra_drm_file_owns_context(fpriv, context)) |
d43f81cb TB |
565 | return -EINVAL; |
566 | ||
567 | list_del(&context->list); | |
c88c3630 | 568 | tegra_drm_context_free(context); |
d43f81cb TB |
569 | |
570 | return 0; | |
571 | } | |
572 | ||
573 | static int tegra_get_syncpt(struct drm_device *drm, void *data, | |
574 | struct drm_file *file) | |
575 | { | |
08943e6c | 576 | struct tegra_drm_file *fpriv = file->driver_priv; |
d43f81cb | 577 | struct drm_tegra_get_syncpt *args = data; |
c88c3630 | 578 | struct tegra_drm_context *context; |
d43f81cb TB |
579 | struct host1x_syncpt *syncpt; |
580 | ||
c88c3630 TR |
581 | context = tegra_drm_get_context(args->context); |
582 | ||
08943e6c | 583 | if (!tegra_drm_file_owns_context(fpriv, context)) |
d43f81cb TB |
584 | return -ENODEV; |
585 | ||
53fa7f72 | 586 | if (args->index >= context->client->base.num_syncpts) |
d43f81cb TB |
587 | return -EINVAL; |
588 | ||
53fa7f72 | 589 | syncpt = context->client->base.syncpts[args->index]; |
d43f81cb TB |
590 | args->id = host1x_syncpt_id(syncpt); |
591 | ||
592 | return 0; | |
593 | } | |
594 | ||
595 | static int tegra_submit(struct drm_device *drm, void *data, | |
596 | struct drm_file *file) | |
597 | { | |
08943e6c | 598 | struct tegra_drm_file *fpriv = file->driver_priv; |
d43f81cb | 599 | struct drm_tegra_submit *args = data; |
c88c3630 TR |
600 | struct tegra_drm_context *context; |
601 | ||
602 | context = tegra_drm_get_context(args->context); | |
d43f81cb | 603 | |
08943e6c | 604 | if (!tegra_drm_file_owns_context(fpriv, context)) |
d43f81cb TB |
605 | return -ENODEV; |
606 | ||
607 | return context->client->ops->submit(context, args, drm, file); | |
608 | } | |
c54a169b AM |
609 | |
610 | static int tegra_get_syncpt_base(struct drm_device *drm, void *data, | |
611 | struct drm_file *file) | |
612 | { | |
613 | struct tegra_drm_file *fpriv = file->driver_priv; | |
614 | struct drm_tegra_get_syncpt_base *args = data; | |
615 | struct tegra_drm_context *context; | |
616 | struct host1x_syncpt_base *base; | |
617 | struct host1x_syncpt *syncpt; | |
618 | ||
619 | context = tegra_drm_get_context(args->context); | |
620 | ||
621 | if (!tegra_drm_file_owns_context(fpriv, context)) | |
622 | return -ENODEV; | |
623 | ||
624 | if (args->syncpt >= context->client->base.num_syncpts) | |
625 | return -EINVAL; | |
626 | ||
627 | syncpt = context->client->base.syncpts[args->syncpt]; | |
628 | ||
629 | base = host1x_syncpt_get_base(syncpt); | |
630 | if (!base) | |
631 | return -ENXIO; | |
632 | ||
633 | args->id = host1x_syncpt_base_id(base); | |
634 | ||
635 | return 0; | |
636 | } | |
7678d71f TR |
637 | |
638 | static int tegra_gem_set_tiling(struct drm_device *drm, void *data, | |
639 | struct drm_file *file) | |
640 | { | |
641 | struct drm_tegra_gem_set_tiling *args = data; | |
642 | enum tegra_bo_tiling_mode mode; | |
643 | struct drm_gem_object *gem; | |
644 | unsigned long value = 0; | |
645 | struct tegra_bo *bo; | |
646 | ||
647 | switch (args->mode) { | |
648 | case DRM_TEGRA_GEM_TILING_MODE_PITCH: | |
649 | mode = TEGRA_BO_TILING_MODE_PITCH; | |
650 | ||
651 | if (args->value != 0) | |
652 | return -EINVAL; | |
653 | ||
654 | break; | |
655 | ||
656 | case DRM_TEGRA_GEM_TILING_MODE_TILED: | |
657 | mode = TEGRA_BO_TILING_MODE_TILED; | |
658 | ||
659 | if (args->value != 0) | |
660 | return -EINVAL; | |
661 | ||
662 | break; | |
663 | ||
664 | case DRM_TEGRA_GEM_TILING_MODE_BLOCK: | |
665 | mode = TEGRA_BO_TILING_MODE_BLOCK; | |
666 | ||
667 | if (args->value > 5) | |
668 | return -EINVAL; | |
669 | ||
670 | value = args->value; | |
671 | break; | |
672 | ||
673 | default: | |
674 | return -EINVAL; | |
675 | } | |
676 | ||
677 | gem = drm_gem_object_lookup(drm, file, args->handle); | |
678 | if (!gem) | |
679 | return -ENOENT; | |
680 | ||
681 | bo = to_tegra_bo(gem); | |
682 | ||
683 | bo->tiling.mode = mode; | |
684 | bo->tiling.value = value; | |
685 | ||
686 | drm_gem_object_unreference(gem); | |
687 | ||
688 | return 0; | |
689 | } | |
690 | ||
691 | static int tegra_gem_get_tiling(struct drm_device *drm, void *data, | |
692 | struct drm_file *file) | |
693 | { | |
694 | struct drm_tegra_gem_get_tiling *args = data; | |
695 | struct drm_gem_object *gem; | |
696 | struct tegra_bo *bo; | |
697 | int err = 0; | |
698 | ||
699 | gem = drm_gem_object_lookup(drm, file, args->handle); | |
700 | if (!gem) | |
701 | return -ENOENT; | |
702 | ||
703 | bo = to_tegra_bo(gem); | |
704 | ||
705 | switch (bo->tiling.mode) { | |
706 | case TEGRA_BO_TILING_MODE_PITCH: | |
707 | args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH; | |
708 | args->value = 0; | |
709 | break; | |
710 | ||
711 | case TEGRA_BO_TILING_MODE_TILED: | |
712 | args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED; | |
713 | args->value = 0; | |
714 | break; | |
715 | ||
716 | case TEGRA_BO_TILING_MODE_BLOCK: | |
717 | args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK; | |
718 | args->value = bo->tiling.value; | |
719 | break; | |
720 | ||
721 | default: | |
722 | err = -EINVAL; | |
723 | break; | |
724 | } | |
725 | ||
726 | drm_gem_object_unreference(gem); | |
727 | ||
728 | return err; | |
729 | } | |
7b129087 TR |
730 | |
731 | static int tegra_gem_set_flags(struct drm_device *drm, void *data, | |
732 | struct drm_file *file) | |
733 | { | |
734 | struct drm_tegra_gem_set_flags *args = data; | |
735 | struct drm_gem_object *gem; | |
736 | struct tegra_bo *bo; | |
737 | ||
738 | if (args->flags & ~DRM_TEGRA_GEM_FLAGS) | |
739 | return -EINVAL; | |
740 | ||
741 | gem = drm_gem_object_lookup(drm, file, args->handle); | |
742 | if (!gem) | |
743 | return -ENOENT; | |
744 | ||
745 | bo = to_tegra_bo(gem); | |
746 | bo->flags = 0; | |
747 | ||
748 | if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP) | |
749 | bo->flags |= TEGRA_BO_BOTTOM_UP; | |
750 | ||
751 | drm_gem_object_unreference(gem); | |
752 | ||
753 | return 0; | |
754 | } | |
755 | ||
756 | static int tegra_gem_get_flags(struct drm_device *drm, void *data, | |
757 | struct drm_file *file) | |
758 | { | |
759 | struct drm_tegra_gem_get_flags *args = data; | |
760 | struct drm_gem_object *gem; | |
761 | struct tegra_bo *bo; | |
762 | ||
763 | gem = drm_gem_object_lookup(drm, file, args->handle); | |
764 | if (!gem) | |
765 | return -ENOENT; | |
766 | ||
767 | bo = to_tegra_bo(gem); | |
768 | args->flags = 0; | |
769 | ||
770 | if (bo->flags & TEGRA_BO_BOTTOM_UP) | |
771 | args->flags |= DRM_TEGRA_GEM_BOTTOM_UP; | |
772 | ||
773 | drm_gem_object_unreference(gem); | |
774 | ||
775 | return 0; | |
776 | } | |
d43f81cb TB |
777 | #endif |
778 | ||
baa70943 | 779 | static const struct drm_ioctl_desc tegra_drm_ioctls[] = { |
d43f81cb | 780 | #ifdef CONFIG_DRM_TEGRA_STAGING |
bd4f2360 | 781 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, DRM_UNLOCKED), |
d43f81cb TB |
782 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, DRM_UNLOCKED), |
783 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, DRM_UNLOCKED), | |
784 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, DRM_UNLOCKED), | |
785 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, DRM_UNLOCKED), | |
786 | DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, DRM_UNLOCKED), | |
787 | DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, DRM_UNLOCKED), | |
788 | DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, DRM_UNLOCKED), | |
789 | DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, DRM_UNLOCKED), | |
c54a169b | 790 | DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, DRM_UNLOCKED), |
7678d71f TR |
791 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, DRM_UNLOCKED), |
792 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, DRM_UNLOCKED), | |
7b129087 TR |
793 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, DRM_UNLOCKED), |
794 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, DRM_UNLOCKED), | |
d43f81cb | 795 | #endif |
d8f4a9ed TR |
796 | }; |
797 | ||
798 | static const struct file_operations tegra_drm_fops = { | |
799 | .owner = THIS_MODULE, | |
800 | .open = drm_open, | |
801 | .release = drm_release, | |
802 | .unlocked_ioctl = drm_ioctl, | |
de2ba664 | 803 | .mmap = tegra_drm_mmap, |
d8f4a9ed | 804 | .poll = drm_poll, |
d8f4a9ed TR |
805 | .read = drm_read, |
806 | #ifdef CONFIG_COMPAT | |
807 | .compat_ioctl = drm_compat_ioctl, | |
808 | #endif | |
809 | .llseek = noop_llseek, | |
810 | }; | |
811 | ||
ed7dae58 TR |
812 | static struct drm_crtc *tegra_crtc_from_pipe(struct drm_device *drm, |
813 | unsigned int pipe) | |
6e5ff998 TR |
814 | { |
815 | struct drm_crtc *crtc; | |
816 | ||
817 | list_for_each_entry(crtc, &drm->mode_config.crtc_list, head) { | |
ed7dae58 | 818 | if (pipe == drm_crtc_index(crtc)) |
6e5ff998 TR |
819 | return crtc; |
820 | } | |
821 | ||
822 | return NULL; | |
823 | } | |
824 | ||
ed7dae58 | 825 | static u32 tegra_drm_get_vblank_counter(struct drm_device *drm, int pipe) |
6e5ff998 | 826 | { |
ed7dae58 | 827 | struct drm_crtc *crtc = tegra_crtc_from_pipe(drm, pipe); |
42e9ce05 | 828 | struct tegra_dc *dc = to_tegra_dc(crtc); |
ed7dae58 TR |
829 | |
830 | if (!crtc) | |
831 | return 0; | |
832 | ||
42e9ce05 | 833 | return tegra_dc_get_vblank_counter(dc); |
6e5ff998 TR |
834 | } |
835 | ||
836 | static int tegra_drm_enable_vblank(struct drm_device *drm, int pipe) | |
837 | { | |
838 | struct drm_crtc *crtc = tegra_crtc_from_pipe(drm, pipe); | |
839 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
840 | ||
841 | if (!crtc) | |
842 | return -ENODEV; | |
843 | ||
844 | tegra_dc_enable_vblank(dc); | |
845 | ||
846 | return 0; | |
847 | } | |
848 | ||
849 | static void tegra_drm_disable_vblank(struct drm_device *drm, int pipe) | |
850 | { | |
851 | struct drm_crtc *crtc = tegra_crtc_from_pipe(drm, pipe); | |
852 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
853 | ||
854 | if (crtc) | |
855 | tegra_dc_disable_vblank(dc); | |
856 | } | |
857 | ||
3c03c46a TR |
858 | static void tegra_drm_preclose(struct drm_device *drm, struct drm_file *file) |
859 | { | |
08943e6c | 860 | struct tegra_drm_file *fpriv = file->driver_priv; |
c88c3630 | 861 | struct tegra_drm_context *context, *tmp; |
3c03c46a TR |
862 | struct drm_crtc *crtc; |
863 | ||
864 | list_for_each_entry(crtc, &drm->mode_config.crtc_list, head) | |
865 | tegra_dc_cancel_page_flip(crtc, file); | |
d43f81cb TB |
866 | |
867 | list_for_each_entry_safe(context, tmp, &fpriv->contexts, list) | |
c88c3630 | 868 | tegra_drm_context_free(context); |
d43f81cb TB |
869 | |
870 | kfree(fpriv); | |
3c03c46a TR |
871 | } |
872 | ||
e450fcc6 TR |
873 | #ifdef CONFIG_DEBUG_FS |
874 | static int tegra_debugfs_framebuffers(struct seq_file *s, void *data) | |
875 | { | |
876 | struct drm_info_node *node = (struct drm_info_node *)s->private; | |
877 | struct drm_device *drm = node->minor->dev; | |
878 | struct drm_framebuffer *fb; | |
879 | ||
880 | mutex_lock(&drm->mode_config.fb_lock); | |
881 | ||
882 | list_for_each_entry(fb, &drm->mode_config.fb_list, head) { | |
883 | seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n", | |
884 | fb->base.id, fb->width, fb->height, fb->depth, | |
885 | fb->bits_per_pixel, | |
886 | atomic_read(&fb->refcount.refcount)); | |
887 | } | |
888 | ||
889 | mutex_unlock(&drm->mode_config.fb_lock); | |
890 | ||
891 | return 0; | |
892 | } | |
893 | ||
28c23373 TR |
894 | static int tegra_debugfs_iova(struct seq_file *s, void *data) |
895 | { | |
896 | struct drm_info_node *node = (struct drm_info_node *)s->private; | |
897 | struct drm_device *drm = node->minor->dev; | |
898 | struct tegra_drm *tegra = drm->dev_private; | |
899 | ||
900 | return drm_mm_dump_table(s, &tegra->mm); | |
901 | } | |
902 | ||
e450fcc6 TR |
903 | static struct drm_info_list tegra_debugfs_list[] = { |
904 | { "framebuffers", tegra_debugfs_framebuffers, 0 }, | |
28c23373 | 905 | { "iova", tegra_debugfs_iova, 0 }, |
e450fcc6 TR |
906 | }; |
907 | ||
908 | static int tegra_debugfs_init(struct drm_minor *minor) | |
909 | { | |
910 | return drm_debugfs_create_files(tegra_debugfs_list, | |
911 | ARRAY_SIZE(tegra_debugfs_list), | |
912 | minor->debugfs_root, minor); | |
913 | } | |
914 | ||
915 | static void tegra_debugfs_cleanup(struct drm_minor *minor) | |
916 | { | |
917 | drm_debugfs_remove_files(tegra_debugfs_list, | |
918 | ARRAY_SIZE(tegra_debugfs_list), minor); | |
919 | } | |
920 | #endif | |
921 | ||
9b57f5f2 | 922 | static struct drm_driver tegra_drm_driver = { |
3800391d | 923 | .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME, |
d8f4a9ed TR |
924 | .load = tegra_drm_load, |
925 | .unload = tegra_drm_unload, | |
926 | .open = tegra_drm_open, | |
3c03c46a | 927 | .preclose = tegra_drm_preclose, |
d8f4a9ed TR |
928 | .lastclose = tegra_drm_lastclose, |
929 | ||
6e5ff998 TR |
930 | .get_vblank_counter = tegra_drm_get_vblank_counter, |
931 | .enable_vblank = tegra_drm_enable_vblank, | |
932 | .disable_vblank = tegra_drm_disable_vblank, | |
933 | ||
e450fcc6 TR |
934 | #if defined(CONFIG_DEBUG_FS) |
935 | .debugfs_init = tegra_debugfs_init, | |
936 | .debugfs_cleanup = tegra_debugfs_cleanup, | |
937 | #endif | |
938 | ||
de2ba664 AM |
939 | .gem_free_object = tegra_bo_free_object, |
940 | .gem_vm_ops = &tegra_bo_vm_ops, | |
3800391d TR |
941 | |
942 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
943 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
944 | .gem_prime_export = tegra_gem_prime_export, | |
945 | .gem_prime_import = tegra_gem_prime_import, | |
946 | ||
de2ba664 AM |
947 | .dumb_create = tegra_bo_dumb_create, |
948 | .dumb_map_offset = tegra_bo_dumb_map_offset, | |
43387b37 | 949 | .dumb_destroy = drm_gem_dumb_destroy, |
d8f4a9ed TR |
950 | |
951 | .ioctls = tegra_drm_ioctls, | |
952 | .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls), | |
953 | .fops = &tegra_drm_fops, | |
954 | ||
955 | .name = DRIVER_NAME, | |
956 | .desc = DRIVER_DESC, | |
957 | .date = DRIVER_DATE, | |
958 | .major = DRIVER_MAJOR, | |
959 | .minor = DRIVER_MINOR, | |
960 | .patchlevel = DRIVER_PATCHLEVEL, | |
961 | }; | |
776dc384 TR |
962 | |
963 | int tegra_drm_register_client(struct tegra_drm *tegra, | |
964 | struct tegra_drm_client *client) | |
965 | { | |
966 | mutex_lock(&tegra->clients_lock); | |
967 | list_add_tail(&client->list, &tegra->clients); | |
968 | mutex_unlock(&tegra->clients_lock); | |
969 | ||
970 | return 0; | |
971 | } | |
972 | ||
973 | int tegra_drm_unregister_client(struct tegra_drm *tegra, | |
974 | struct tegra_drm_client *client) | |
975 | { | |
976 | mutex_lock(&tegra->clients_lock); | |
977 | list_del_init(&client->list); | |
978 | mutex_unlock(&tegra->clients_lock); | |
979 | ||
980 | return 0; | |
981 | } | |
982 | ||
9910f5c4 | 983 | static int host1x_drm_probe(struct host1x_device *dev) |
776dc384 | 984 | { |
9910f5c4 TR |
985 | struct drm_driver *driver = &tegra_drm_driver; |
986 | struct drm_device *drm; | |
987 | int err; | |
988 | ||
989 | drm = drm_dev_alloc(driver, &dev->dev); | |
990 | if (!drm) | |
991 | return -ENOMEM; | |
992 | ||
993 | drm_dev_set_unique(drm, dev_name(&dev->dev)); | |
994 | dev_set_drvdata(&dev->dev, drm); | |
995 | ||
996 | err = drm_dev_register(drm, 0); | |
997 | if (err < 0) | |
998 | goto unref; | |
999 | ||
1000 | DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n", driver->name, | |
1001 | driver->major, driver->minor, driver->patchlevel, | |
1002 | driver->date, drm->primary->index); | |
1003 | ||
1004 | return 0; | |
1005 | ||
1006 | unref: | |
1007 | drm_dev_unref(drm); | |
1008 | return err; | |
776dc384 TR |
1009 | } |
1010 | ||
9910f5c4 | 1011 | static int host1x_drm_remove(struct host1x_device *dev) |
776dc384 | 1012 | { |
9910f5c4 TR |
1013 | struct drm_device *drm = dev_get_drvdata(&dev->dev); |
1014 | ||
1015 | drm_dev_unregister(drm); | |
1016 | drm_dev_unref(drm); | |
776dc384 TR |
1017 | |
1018 | return 0; | |
1019 | } | |
1020 | ||
359ae687 TR |
1021 | #ifdef CONFIG_PM_SLEEP |
1022 | static int host1x_drm_suspend(struct device *dev) | |
1023 | { | |
1024 | struct drm_device *drm = dev_get_drvdata(dev); | |
1025 | ||
1026 | drm_kms_helper_poll_disable(drm); | |
1027 | ||
1028 | return 0; | |
1029 | } | |
1030 | ||
1031 | static int host1x_drm_resume(struct device *dev) | |
1032 | { | |
1033 | struct drm_device *drm = dev_get_drvdata(dev); | |
1034 | ||
1035 | drm_kms_helper_poll_enable(drm); | |
1036 | ||
1037 | return 0; | |
1038 | } | |
1039 | #endif | |
1040 | ||
a13f1dc4 TR |
1041 | static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend, |
1042 | host1x_drm_resume); | |
359ae687 | 1043 | |
776dc384 TR |
1044 | static const struct of_device_id host1x_drm_subdevs[] = { |
1045 | { .compatible = "nvidia,tegra20-dc", }, | |
1046 | { .compatible = "nvidia,tegra20-hdmi", }, | |
1047 | { .compatible = "nvidia,tegra20-gr2d", }, | |
5f60ed0d | 1048 | { .compatible = "nvidia,tegra20-gr3d", }, |
776dc384 TR |
1049 | { .compatible = "nvidia,tegra30-dc", }, |
1050 | { .compatible = "nvidia,tegra30-hdmi", }, | |
1051 | { .compatible = "nvidia,tegra30-gr2d", }, | |
5f60ed0d | 1052 | { .compatible = "nvidia,tegra30-gr3d", }, |
dec72739 | 1053 | { .compatible = "nvidia,tegra114-dsi", }, |
7d1d28ac | 1054 | { .compatible = "nvidia,tegra114-hdmi", }, |
5f60ed0d | 1055 | { .compatible = "nvidia,tegra114-gr3d", }, |
8620fc62 | 1056 | { .compatible = "nvidia,tegra124-dc", }, |
6b6b6042 | 1057 | { .compatible = "nvidia,tegra124-sor", }, |
fb7be70e | 1058 | { .compatible = "nvidia,tegra124-hdmi", }, |
7d338587 | 1059 | { .compatible = "nvidia,tegra124-dsi", }, |
5b4f516f | 1060 | { .compatible = "nvidia,tegra210-dc", }, |
776dc384 TR |
1061 | { /* sentinel */ } |
1062 | }; | |
1063 | ||
1064 | static struct host1x_driver host1x_drm_driver = { | |
f4c5cf88 TR |
1065 | .driver = { |
1066 | .name = "drm", | |
359ae687 | 1067 | .pm = &host1x_drm_pm_ops, |
f4c5cf88 | 1068 | }, |
776dc384 TR |
1069 | .probe = host1x_drm_probe, |
1070 | .remove = host1x_drm_remove, | |
1071 | .subdevs = host1x_drm_subdevs, | |
1072 | }; | |
1073 | ||
1074 | static int __init host1x_drm_init(void) | |
1075 | { | |
1076 | int err; | |
1077 | ||
1078 | err = host1x_driver_register(&host1x_drm_driver); | |
1079 | if (err < 0) | |
1080 | return err; | |
1081 | ||
1082 | err = platform_driver_register(&tegra_dc_driver); | |
1083 | if (err < 0) | |
1084 | goto unregister_host1x; | |
1085 | ||
dec72739 | 1086 | err = platform_driver_register(&tegra_dsi_driver); |
776dc384 TR |
1087 | if (err < 0) |
1088 | goto unregister_dc; | |
1089 | ||
6b6b6042 | 1090 | err = platform_driver_register(&tegra_sor_driver); |
dec72739 TR |
1091 | if (err < 0) |
1092 | goto unregister_dsi; | |
1093 | ||
6b6b6042 TR |
1094 | err = platform_driver_register(&tegra_hdmi_driver); |
1095 | if (err < 0) | |
1096 | goto unregister_sor; | |
1097 | ||
1098 | err = platform_driver_register(&tegra_dpaux_driver); | |
776dc384 TR |
1099 | if (err < 0) |
1100 | goto unregister_hdmi; | |
1101 | ||
6b6b6042 TR |
1102 | err = platform_driver_register(&tegra_gr2d_driver); |
1103 | if (err < 0) | |
1104 | goto unregister_dpaux; | |
1105 | ||
5f60ed0d TR |
1106 | err = platform_driver_register(&tegra_gr3d_driver); |
1107 | if (err < 0) | |
1108 | goto unregister_gr2d; | |
1109 | ||
776dc384 TR |
1110 | return 0; |
1111 | ||
5f60ed0d TR |
1112 | unregister_gr2d: |
1113 | platform_driver_unregister(&tegra_gr2d_driver); | |
6b6b6042 TR |
1114 | unregister_dpaux: |
1115 | platform_driver_unregister(&tegra_dpaux_driver); | |
776dc384 TR |
1116 | unregister_hdmi: |
1117 | platform_driver_unregister(&tegra_hdmi_driver); | |
6b6b6042 TR |
1118 | unregister_sor: |
1119 | platform_driver_unregister(&tegra_sor_driver); | |
dec72739 TR |
1120 | unregister_dsi: |
1121 | platform_driver_unregister(&tegra_dsi_driver); | |
776dc384 TR |
1122 | unregister_dc: |
1123 | platform_driver_unregister(&tegra_dc_driver); | |
1124 | unregister_host1x: | |
1125 | host1x_driver_unregister(&host1x_drm_driver); | |
1126 | return err; | |
1127 | } | |
1128 | module_init(host1x_drm_init); | |
1129 | ||
1130 | static void __exit host1x_drm_exit(void) | |
1131 | { | |
5f60ed0d | 1132 | platform_driver_unregister(&tegra_gr3d_driver); |
776dc384 | 1133 | platform_driver_unregister(&tegra_gr2d_driver); |
6b6b6042 | 1134 | platform_driver_unregister(&tegra_dpaux_driver); |
776dc384 | 1135 | platform_driver_unregister(&tegra_hdmi_driver); |
6b6b6042 | 1136 | platform_driver_unregister(&tegra_sor_driver); |
dec72739 | 1137 | platform_driver_unregister(&tegra_dsi_driver); |
776dc384 TR |
1138 | platform_driver_unregister(&tegra_dc_driver); |
1139 | host1x_driver_unregister(&host1x_drm_driver); | |
1140 | } | |
1141 | module_exit(host1x_drm_exit); | |
1142 | ||
1143 | MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); | |
1144 | MODULE_DESCRIPTION("NVIDIA Tegra DRM driver"); | |
1145 | MODULE_LICENSE("GPL v2"); |