Commit | Line | Data |
---|---|---|
d8f4a9ed TR |
1 | /* |
2 | * Copyright (C) 2012 Avionic Design GmbH | |
d43f81cb | 3 | * Copyright (C) 2012-2013 NVIDIA CORPORATION. All rights reserved. |
d8f4a9ed TR |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
776dc384 | 10 | #include <linux/host1x.h> |
df06b759 | 11 | #include <linux/iommu.h> |
776dc384 | 12 | |
1503ca47 | 13 | #include <drm/drm_atomic.h> |
07866963 TR |
14 | #include <drm/drm_atomic_helper.h> |
15 | ||
d8f4a9ed | 16 | #include "drm.h" |
de2ba664 | 17 | #include "gem.h" |
d8f4a9ed TR |
18 | |
19 | #define DRIVER_NAME "tegra" | |
20 | #define DRIVER_DESC "NVIDIA Tegra graphics" | |
21 | #define DRIVER_DATE "20120330" | |
22 | #define DRIVER_MAJOR 0 | |
23 | #define DRIVER_MINOR 0 | |
24 | #define DRIVER_PATCHLEVEL 0 | |
25 | ||
08943e6c TR |
26 | struct tegra_drm_file { |
27 | struct list_head contexts; | |
28 | }; | |
29 | ||
1503ca47 TR |
30 | static void tegra_atomic_schedule(struct tegra_drm *tegra, |
31 | struct drm_atomic_state *state) | |
32 | { | |
33 | tegra->commit.state = state; | |
34 | schedule_work(&tegra->commit.work); | |
35 | } | |
36 | ||
37 | static void tegra_atomic_complete(struct tegra_drm *tegra, | |
38 | struct drm_atomic_state *state) | |
39 | { | |
40 | struct drm_device *drm = tegra->drm; | |
41 | ||
42 | /* | |
43 | * Everything below can be run asynchronously without the need to grab | |
44 | * any modeset locks at all under one condition: It must be guaranteed | |
45 | * that the asynchronous work has either been cancelled (if the driver | |
46 | * supports it, which at least requires that the framebuffers get | |
47 | * cleaned up with drm_atomic_helper_cleanup_planes()) or completed | |
48 | * before the new state gets committed on the software side with | |
49 | * drm_atomic_helper_swap_state(). | |
50 | * | |
51 | * This scheme allows new atomic state updates to be prepared and | |
52 | * checked in parallel to the asynchronous completion of the previous | |
53 | * update. Which is important since compositors need to figure out the | |
54 | * composition of the next frame right after having submitted the | |
55 | * current layout. | |
56 | */ | |
57 | ||
1af434a9 | 58 | drm_atomic_helper_commit_modeset_disables(drm, state); |
1503ca47 | 59 | drm_atomic_helper_commit_planes(drm, state); |
1af434a9 | 60 | drm_atomic_helper_commit_modeset_enables(drm, state); |
1503ca47 TR |
61 | |
62 | drm_atomic_helper_wait_for_vblanks(drm, state); | |
63 | ||
64 | drm_atomic_helper_cleanup_planes(drm, state); | |
65 | drm_atomic_state_free(state); | |
66 | } | |
67 | ||
68 | static void tegra_atomic_work(struct work_struct *work) | |
69 | { | |
70 | struct tegra_drm *tegra = container_of(work, struct tegra_drm, | |
71 | commit.work); | |
72 | ||
73 | tegra_atomic_complete(tegra, tegra->commit.state); | |
74 | } | |
75 | ||
76 | static int tegra_atomic_commit(struct drm_device *drm, | |
77 | struct drm_atomic_state *state, bool async) | |
78 | { | |
79 | struct tegra_drm *tegra = drm->dev_private; | |
80 | int err; | |
81 | ||
82 | err = drm_atomic_helper_prepare_planes(drm, state); | |
83 | if (err) | |
84 | return err; | |
85 | ||
86 | /* serialize outstanding asynchronous commits */ | |
87 | mutex_lock(&tegra->commit.lock); | |
88 | flush_work(&tegra->commit.work); | |
89 | ||
90 | /* | |
91 | * This is the point of no return - everything below never fails except | |
92 | * when the hw goes bonghits. Which means we can commit the new state on | |
93 | * the software side now. | |
94 | */ | |
95 | ||
96 | drm_atomic_helper_swap_state(drm, state); | |
97 | ||
98 | if (async) | |
99 | tegra_atomic_schedule(tegra, state); | |
100 | else | |
101 | tegra_atomic_complete(tegra, state); | |
102 | ||
103 | mutex_unlock(&tegra->commit.lock); | |
104 | return 0; | |
105 | } | |
106 | ||
f9914214 TR |
107 | static const struct drm_mode_config_funcs tegra_drm_mode_funcs = { |
108 | .fb_create = tegra_fb_create, | |
109 | #ifdef CONFIG_DRM_TEGRA_FBDEV | |
110 | .output_poll_changed = tegra_fb_output_poll_changed, | |
111 | #endif | |
07866963 | 112 | .atomic_check = drm_atomic_helper_check, |
1503ca47 | 113 | .atomic_commit = tegra_atomic_commit, |
f9914214 TR |
114 | }; |
115 | ||
776dc384 | 116 | static int tegra_drm_load(struct drm_device *drm, unsigned long flags) |
692e6d7b | 117 | { |
776dc384 | 118 | struct host1x_device *device = to_host1x_device(drm->dev); |
386a2a71 | 119 | struct tegra_drm *tegra; |
692e6d7b TB |
120 | int err; |
121 | ||
776dc384 | 122 | tegra = kzalloc(sizeof(*tegra), GFP_KERNEL); |
386a2a71 | 123 | if (!tegra) |
692e6d7b TB |
124 | return -ENOMEM; |
125 | ||
df06b759 | 126 | if (iommu_present(&platform_bus_type)) { |
4553f733 TR |
127 | struct iommu_domain_geometry *geometry; |
128 | u64 start, end; | |
129 | ||
df06b759 | 130 | tegra->domain = iommu_domain_alloc(&platform_bus_type); |
bf19b885 DC |
131 | if (!tegra->domain) { |
132 | err = -ENOMEM; | |
df06b759 TR |
133 | goto free; |
134 | } | |
135 | ||
4553f733 TR |
136 | geometry = &tegra->domain->geometry; |
137 | start = geometry->aperture_start; | |
138 | end = geometry->aperture_end; | |
139 | ||
140 | DRM_DEBUG("IOMMU context initialized (aperture: %#llx-%#llx)\n", | |
141 | start, end); | |
142 | drm_mm_init(&tegra->mm, start, end - start + 1); | |
df06b759 TR |
143 | } |
144 | ||
386a2a71 TR |
145 | mutex_init(&tegra->clients_lock); |
146 | INIT_LIST_HEAD(&tegra->clients); | |
1503ca47 TR |
147 | |
148 | mutex_init(&tegra->commit.lock); | |
149 | INIT_WORK(&tegra->commit.work, tegra_atomic_work); | |
150 | ||
386a2a71 TR |
151 | drm->dev_private = tegra; |
152 | tegra->drm = drm; | |
d8f4a9ed TR |
153 | |
154 | drm_mode_config_init(drm); | |
155 | ||
f9914214 TR |
156 | drm->mode_config.min_width = 0; |
157 | drm->mode_config.min_height = 0; | |
158 | ||
159 | drm->mode_config.max_width = 4096; | |
160 | drm->mode_config.max_height = 4096; | |
161 | ||
162 | drm->mode_config.funcs = &tegra_drm_mode_funcs; | |
163 | ||
e2215321 TR |
164 | err = tegra_drm_fb_prepare(drm); |
165 | if (err < 0) | |
1d1e6fe9 | 166 | goto config; |
e2215321 TR |
167 | |
168 | drm_kms_helper_poll_init(drm); | |
169 | ||
776dc384 | 170 | err = host1x_device_init(device); |
d8f4a9ed | 171 | if (err < 0) |
1d1e6fe9 | 172 | goto fbdev; |
d8f4a9ed | 173 | |
9d44189f TR |
174 | drm_mode_config_reset(drm); |
175 | ||
603f0cc9 TR |
176 | /* |
177 | * We don't use the drm_irq_install() helpers provided by the DRM | |
178 | * core, so we need to set this manually in order to allow the | |
179 | * DRM_IOCTL_WAIT_VBLANK to operate correctly. | |
180 | */ | |
4423843c | 181 | drm->irq_enabled = true; |
603f0cc9 | 182 | |
42e9ce05 | 183 | /* syncpoints are used for full 32-bit hardware VBLANK counters */ |
42e9ce05 TR |
184 | drm->max_vblank_count = 0xffffffff; |
185 | ||
6e5ff998 TR |
186 | err = drm_vblank_init(drm, drm->mode_config.num_crtc); |
187 | if (err < 0) | |
1d1e6fe9 | 188 | goto device; |
6e5ff998 | 189 | |
d8f4a9ed TR |
190 | err = tegra_drm_fb_init(drm); |
191 | if (err < 0) | |
1d1e6fe9 | 192 | goto vblank; |
d8f4a9ed | 193 | |
d8f4a9ed | 194 | return 0; |
1d1e6fe9 TR |
195 | |
196 | vblank: | |
197 | drm_vblank_cleanup(drm); | |
198 | device: | |
199 | host1x_device_exit(device); | |
200 | fbdev: | |
201 | drm_kms_helper_poll_fini(drm); | |
202 | tegra_drm_fb_free(drm); | |
203 | config: | |
204 | drm_mode_config_cleanup(drm); | |
df06b759 TR |
205 | |
206 | if (tegra->domain) { | |
207 | iommu_domain_free(tegra->domain); | |
208 | drm_mm_takedown(&tegra->mm); | |
209 | } | |
210 | free: | |
1d1e6fe9 TR |
211 | kfree(tegra); |
212 | return err; | |
d8f4a9ed TR |
213 | } |
214 | ||
215 | static int tegra_drm_unload(struct drm_device *drm) | |
216 | { | |
776dc384 | 217 | struct host1x_device *device = to_host1x_device(drm->dev); |
df06b759 | 218 | struct tegra_drm *tegra = drm->dev_private; |
776dc384 TR |
219 | int err; |
220 | ||
d8f4a9ed TR |
221 | drm_kms_helper_poll_fini(drm); |
222 | tegra_drm_fb_exit(drm); | |
f002abc1 | 223 | drm_mode_config_cleanup(drm); |
4aa3df71 | 224 | drm_vblank_cleanup(drm); |
d8f4a9ed | 225 | |
776dc384 TR |
226 | err = host1x_device_exit(device); |
227 | if (err < 0) | |
228 | return err; | |
229 | ||
df06b759 TR |
230 | if (tegra->domain) { |
231 | iommu_domain_free(tegra->domain); | |
232 | drm_mm_takedown(&tegra->mm); | |
233 | } | |
234 | ||
1053f4dd TR |
235 | kfree(tegra); |
236 | ||
d8f4a9ed TR |
237 | return 0; |
238 | } | |
239 | ||
240 | static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp) | |
241 | { | |
08943e6c | 242 | struct tegra_drm_file *fpriv; |
d43f81cb TB |
243 | |
244 | fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); | |
245 | if (!fpriv) | |
246 | return -ENOMEM; | |
247 | ||
248 | INIT_LIST_HEAD(&fpriv->contexts); | |
249 | filp->driver_priv = fpriv; | |
250 | ||
d8f4a9ed TR |
251 | return 0; |
252 | } | |
253 | ||
c88c3630 | 254 | static void tegra_drm_context_free(struct tegra_drm_context *context) |
d43f81cb TB |
255 | { |
256 | context->client->ops->close_channel(context); | |
257 | kfree(context); | |
258 | } | |
259 | ||
d8f4a9ed TR |
260 | static void tegra_drm_lastclose(struct drm_device *drm) |
261 | { | |
6e60163b | 262 | #ifdef CONFIG_DRM_TEGRA_FBDEV |
386a2a71 | 263 | struct tegra_drm *tegra = drm->dev_private; |
d8f4a9ed | 264 | |
386a2a71 | 265 | tegra_fbdev_restore_mode(tegra->fbdev); |
60c2f709 | 266 | #endif |
d8f4a9ed TR |
267 | } |
268 | ||
c40f0f1a TR |
269 | static struct host1x_bo * |
270 | host1x_bo_lookup(struct drm_device *drm, struct drm_file *file, u32 handle) | |
271 | { | |
272 | struct drm_gem_object *gem; | |
273 | struct tegra_bo *bo; | |
274 | ||
275 | gem = drm_gem_object_lookup(drm, file, handle); | |
276 | if (!gem) | |
277 | return NULL; | |
278 | ||
279 | mutex_lock(&drm->struct_mutex); | |
280 | drm_gem_object_unreference(gem); | |
281 | mutex_unlock(&drm->struct_mutex); | |
282 | ||
283 | bo = to_tegra_bo(gem); | |
284 | return &bo->base; | |
285 | } | |
286 | ||
961e3bea TR |
287 | static int host1x_reloc_copy_from_user(struct host1x_reloc *dest, |
288 | struct drm_tegra_reloc __user *src, | |
289 | struct drm_device *drm, | |
290 | struct drm_file *file) | |
291 | { | |
292 | u32 cmdbuf, target; | |
293 | int err; | |
294 | ||
295 | err = get_user(cmdbuf, &src->cmdbuf.handle); | |
296 | if (err < 0) | |
297 | return err; | |
298 | ||
299 | err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset); | |
300 | if (err < 0) | |
301 | return err; | |
302 | ||
303 | err = get_user(target, &src->target.handle); | |
304 | if (err < 0) | |
305 | return err; | |
306 | ||
31f40f86 | 307 | err = get_user(dest->target.offset, &src->target.offset); |
961e3bea TR |
308 | if (err < 0) |
309 | return err; | |
310 | ||
311 | err = get_user(dest->shift, &src->shift); | |
312 | if (err < 0) | |
313 | return err; | |
314 | ||
315 | dest->cmdbuf.bo = host1x_bo_lookup(drm, file, cmdbuf); | |
316 | if (!dest->cmdbuf.bo) | |
317 | return -ENOENT; | |
318 | ||
319 | dest->target.bo = host1x_bo_lookup(drm, file, target); | |
320 | if (!dest->target.bo) | |
321 | return -ENOENT; | |
322 | ||
323 | return 0; | |
324 | } | |
325 | ||
c40f0f1a TR |
326 | int tegra_drm_submit(struct tegra_drm_context *context, |
327 | struct drm_tegra_submit *args, struct drm_device *drm, | |
328 | struct drm_file *file) | |
329 | { | |
330 | unsigned int num_cmdbufs = args->num_cmdbufs; | |
331 | unsigned int num_relocs = args->num_relocs; | |
332 | unsigned int num_waitchks = args->num_waitchks; | |
333 | struct drm_tegra_cmdbuf __user *cmdbufs = | |
a7ed68fc | 334 | (void __user *)(uintptr_t)args->cmdbufs; |
c40f0f1a | 335 | struct drm_tegra_reloc __user *relocs = |
a7ed68fc | 336 | (void __user *)(uintptr_t)args->relocs; |
c40f0f1a | 337 | struct drm_tegra_waitchk __user *waitchks = |
a7ed68fc | 338 | (void __user *)(uintptr_t)args->waitchks; |
c40f0f1a TR |
339 | struct drm_tegra_syncpt syncpt; |
340 | struct host1x_job *job; | |
341 | int err; | |
342 | ||
343 | /* We don't yet support other than one syncpt_incr struct per submit */ | |
344 | if (args->num_syncpts != 1) | |
345 | return -EINVAL; | |
346 | ||
347 | job = host1x_job_alloc(context->channel, args->num_cmdbufs, | |
348 | args->num_relocs, args->num_waitchks); | |
349 | if (!job) | |
350 | return -ENOMEM; | |
351 | ||
352 | job->num_relocs = args->num_relocs; | |
353 | job->num_waitchk = args->num_waitchks; | |
354 | job->client = (u32)args->context; | |
355 | job->class = context->client->base.class; | |
356 | job->serialize = true; | |
357 | ||
358 | while (num_cmdbufs) { | |
359 | struct drm_tegra_cmdbuf cmdbuf; | |
360 | struct host1x_bo *bo; | |
361 | ||
9a991600 DC |
362 | if (copy_from_user(&cmdbuf, cmdbufs, sizeof(cmdbuf))) { |
363 | err = -EFAULT; | |
c40f0f1a | 364 | goto fail; |
9a991600 | 365 | } |
c40f0f1a TR |
366 | |
367 | bo = host1x_bo_lookup(drm, file, cmdbuf.handle); | |
368 | if (!bo) { | |
369 | err = -ENOENT; | |
370 | goto fail; | |
371 | } | |
372 | ||
373 | host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset); | |
374 | num_cmdbufs--; | |
375 | cmdbufs++; | |
376 | } | |
377 | ||
961e3bea | 378 | /* copy and resolve relocations from submit */ |
c40f0f1a | 379 | while (num_relocs--) { |
961e3bea TR |
380 | err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs], |
381 | &relocs[num_relocs], drm, | |
382 | file); | |
383 | if (err < 0) | |
c40f0f1a | 384 | goto fail; |
c40f0f1a TR |
385 | } |
386 | ||
9a991600 DC |
387 | if (copy_from_user(job->waitchk, waitchks, |
388 | sizeof(*waitchks) * num_waitchks)) { | |
389 | err = -EFAULT; | |
c40f0f1a | 390 | goto fail; |
9a991600 | 391 | } |
c40f0f1a | 392 | |
9a991600 DC |
393 | if (copy_from_user(&syncpt, (void __user *)(uintptr_t)args->syncpts, |
394 | sizeof(syncpt))) { | |
395 | err = -EFAULT; | |
c40f0f1a | 396 | goto fail; |
9a991600 | 397 | } |
c40f0f1a TR |
398 | |
399 | job->is_addr_reg = context->client->ops->is_addr_reg; | |
400 | job->syncpt_incrs = syncpt.incrs; | |
401 | job->syncpt_id = syncpt.id; | |
402 | job->timeout = 10000; | |
403 | ||
404 | if (args->timeout && args->timeout < 10000) | |
405 | job->timeout = args->timeout; | |
406 | ||
407 | err = host1x_job_pin(job, context->client->base.dev); | |
408 | if (err) | |
409 | goto fail; | |
410 | ||
411 | err = host1x_job_submit(job); | |
412 | if (err) | |
413 | goto fail_submit; | |
414 | ||
415 | args->fence = job->syncpt_end; | |
416 | ||
417 | host1x_job_put(job); | |
418 | return 0; | |
419 | ||
420 | fail_submit: | |
421 | host1x_job_unpin(job); | |
422 | fail: | |
423 | host1x_job_put(job); | |
424 | return err; | |
425 | } | |
426 | ||
427 | ||
d43f81cb | 428 | #ifdef CONFIG_DRM_TEGRA_STAGING |
c88c3630 TR |
429 | static struct tegra_drm_context *tegra_drm_get_context(__u64 context) |
430 | { | |
431 | return (struct tegra_drm_context *)(uintptr_t)context; | |
432 | } | |
433 | ||
08943e6c | 434 | static bool tegra_drm_file_owns_context(struct tegra_drm_file *file, |
c88c3630 | 435 | struct tegra_drm_context *context) |
d43f81cb | 436 | { |
c88c3630 | 437 | struct tegra_drm_context *ctx; |
d43f81cb TB |
438 | |
439 | list_for_each_entry(ctx, &file->contexts, list) | |
440 | if (ctx == context) | |
441 | return true; | |
442 | ||
443 | return false; | |
444 | } | |
445 | ||
446 | static int tegra_gem_create(struct drm_device *drm, void *data, | |
447 | struct drm_file *file) | |
448 | { | |
449 | struct drm_tegra_gem_create *args = data; | |
450 | struct tegra_bo *bo; | |
451 | ||
773af77f | 452 | bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags, |
d43f81cb TB |
453 | &args->handle); |
454 | if (IS_ERR(bo)) | |
455 | return PTR_ERR(bo); | |
456 | ||
457 | return 0; | |
458 | } | |
459 | ||
460 | static int tegra_gem_mmap(struct drm_device *drm, void *data, | |
461 | struct drm_file *file) | |
462 | { | |
463 | struct drm_tegra_gem_mmap *args = data; | |
464 | struct drm_gem_object *gem; | |
465 | struct tegra_bo *bo; | |
466 | ||
467 | gem = drm_gem_object_lookup(drm, file, args->handle); | |
468 | if (!gem) | |
469 | return -EINVAL; | |
470 | ||
471 | bo = to_tegra_bo(gem); | |
472 | ||
2bc7b0ca | 473 | args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node); |
d43f81cb TB |
474 | |
475 | drm_gem_object_unreference(gem); | |
476 | ||
477 | return 0; | |
478 | } | |
479 | ||
480 | static int tegra_syncpt_read(struct drm_device *drm, void *data, | |
481 | struct drm_file *file) | |
482 | { | |
776dc384 | 483 | struct host1x *host = dev_get_drvdata(drm->dev->parent); |
d43f81cb | 484 | struct drm_tegra_syncpt_read *args = data; |
776dc384 | 485 | struct host1x_syncpt *sp; |
d43f81cb | 486 | |
776dc384 | 487 | sp = host1x_syncpt_get(host, args->id); |
d43f81cb TB |
488 | if (!sp) |
489 | return -EINVAL; | |
490 | ||
491 | args->value = host1x_syncpt_read_min(sp); | |
492 | return 0; | |
493 | } | |
494 | ||
495 | static int tegra_syncpt_incr(struct drm_device *drm, void *data, | |
496 | struct drm_file *file) | |
497 | { | |
776dc384 | 498 | struct host1x *host1x = dev_get_drvdata(drm->dev->parent); |
d43f81cb | 499 | struct drm_tegra_syncpt_incr *args = data; |
776dc384 | 500 | struct host1x_syncpt *sp; |
d43f81cb | 501 | |
776dc384 | 502 | sp = host1x_syncpt_get(host1x, args->id); |
d43f81cb TB |
503 | if (!sp) |
504 | return -EINVAL; | |
505 | ||
ebae30b1 | 506 | return host1x_syncpt_incr(sp); |
d43f81cb TB |
507 | } |
508 | ||
509 | static int tegra_syncpt_wait(struct drm_device *drm, void *data, | |
510 | struct drm_file *file) | |
511 | { | |
776dc384 | 512 | struct host1x *host1x = dev_get_drvdata(drm->dev->parent); |
d43f81cb | 513 | struct drm_tegra_syncpt_wait *args = data; |
776dc384 | 514 | struct host1x_syncpt *sp; |
d43f81cb | 515 | |
776dc384 | 516 | sp = host1x_syncpt_get(host1x, args->id); |
d43f81cb TB |
517 | if (!sp) |
518 | return -EINVAL; | |
519 | ||
520 | return host1x_syncpt_wait(sp, args->thresh, args->timeout, | |
521 | &args->value); | |
522 | } | |
523 | ||
524 | static int tegra_open_channel(struct drm_device *drm, void *data, | |
525 | struct drm_file *file) | |
526 | { | |
08943e6c | 527 | struct tegra_drm_file *fpriv = file->driver_priv; |
386a2a71 | 528 | struct tegra_drm *tegra = drm->dev_private; |
d43f81cb | 529 | struct drm_tegra_open_channel *args = data; |
c88c3630 | 530 | struct tegra_drm_context *context; |
53fa7f72 | 531 | struct tegra_drm_client *client; |
d43f81cb TB |
532 | int err = -ENODEV; |
533 | ||
534 | context = kzalloc(sizeof(*context), GFP_KERNEL); | |
535 | if (!context) | |
536 | return -ENOMEM; | |
537 | ||
776dc384 | 538 | list_for_each_entry(client, &tegra->clients, list) |
53fa7f72 | 539 | if (client->base.class == args->client) { |
d43f81cb TB |
540 | err = client->ops->open_channel(client, context); |
541 | if (err) | |
542 | break; | |
543 | ||
d43f81cb TB |
544 | list_add(&context->list, &fpriv->contexts); |
545 | args->context = (uintptr_t)context; | |
53fa7f72 | 546 | context->client = client; |
d43f81cb TB |
547 | return 0; |
548 | } | |
549 | ||
550 | kfree(context); | |
551 | return err; | |
552 | } | |
553 | ||
554 | static int tegra_close_channel(struct drm_device *drm, void *data, | |
555 | struct drm_file *file) | |
556 | { | |
08943e6c | 557 | struct tegra_drm_file *fpriv = file->driver_priv; |
776dc384 | 558 | struct drm_tegra_close_channel *args = data; |
c88c3630 TR |
559 | struct tegra_drm_context *context; |
560 | ||
561 | context = tegra_drm_get_context(args->context); | |
d43f81cb | 562 | |
08943e6c | 563 | if (!tegra_drm_file_owns_context(fpriv, context)) |
d43f81cb TB |
564 | return -EINVAL; |
565 | ||
566 | list_del(&context->list); | |
c88c3630 | 567 | tegra_drm_context_free(context); |
d43f81cb TB |
568 | |
569 | return 0; | |
570 | } | |
571 | ||
572 | static int tegra_get_syncpt(struct drm_device *drm, void *data, | |
573 | struct drm_file *file) | |
574 | { | |
08943e6c | 575 | struct tegra_drm_file *fpriv = file->driver_priv; |
d43f81cb | 576 | struct drm_tegra_get_syncpt *args = data; |
c88c3630 | 577 | struct tegra_drm_context *context; |
d43f81cb TB |
578 | struct host1x_syncpt *syncpt; |
579 | ||
c88c3630 TR |
580 | context = tegra_drm_get_context(args->context); |
581 | ||
08943e6c | 582 | if (!tegra_drm_file_owns_context(fpriv, context)) |
d43f81cb TB |
583 | return -ENODEV; |
584 | ||
53fa7f72 | 585 | if (args->index >= context->client->base.num_syncpts) |
d43f81cb TB |
586 | return -EINVAL; |
587 | ||
53fa7f72 | 588 | syncpt = context->client->base.syncpts[args->index]; |
d43f81cb TB |
589 | args->id = host1x_syncpt_id(syncpt); |
590 | ||
591 | return 0; | |
592 | } | |
593 | ||
594 | static int tegra_submit(struct drm_device *drm, void *data, | |
595 | struct drm_file *file) | |
596 | { | |
08943e6c | 597 | struct tegra_drm_file *fpriv = file->driver_priv; |
d43f81cb | 598 | struct drm_tegra_submit *args = data; |
c88c3630 TR |
599 | struct tegra_drm_context *context; |
600 | ||
601 | context = tegra_drm_get_context(args->context); | |
d43f81cb | 602 | |
08943e6c | 603 | if (!tegra_drm_file_owns_context(fpriv, context)) |
d43f81cb TB |
604 | return -ENODEV; |
605 | ||
606 | return context->client->ops->submit(context, args, drm, file); | |
607 | } | |
c54a169b AM |
608 | |
609 | static int tegra_get_syncpt_base(struct drm_device *drm, void *data, | |
610 | struct drm_file *file) | |
611 | { | |
612 | struct tegra_drm_file *fpriv = file->driver_priv; | |
613 | struct drm_tegra_get_syncpt_base *args = data; | |
614 | struct tegra_drm_context *context; | |
615 | struct host1x_syncpt_base *base; | |
616 | struct host1x_syncpt *syncpt; | |
617 | ||
618 | context = tegra_drm_get_context(args->context); | |
619 | ||
620 | if (!tegra_drm_file_owns_context(fpriv, context)) | |
621 | return -ENODEV; | |
622 | ||
623 | if (args->syncpt >= context->client->base.num_syncpts) | |
624 | return -EINVAL; | |
625 | ||
626 | syncpt = context->client->base.syncpts[args->syncpt]; | |
627 | ||
628 | base = host1x_syncpt_get_base(syncpt); | |
629 | if (!base) | |
630 | return -ENXIO; | |
631 | ||
632 | args->id = host1x_syncpt_base_id(base); | |
633 | ||
634 | return 0; | |
635 | } | |
7678d71f TR |
636 | |
637 | static int tegra_gem_set_tiling(struct drm_device *drm, void *data, | |
638 | struct drm_file *file) | |
639 | { | |
640 | struct drm_tegra_gem_set_tiling *args = data; | |
641 | enum tegra_bo_tiling_mode mode; | |
642 | struct drm_gem_object *gem; | |
643 | unsigned long value = 0; | |
644 | struct tegra_bo *bo; | |
645 | ||
646 | switch (args->mode) { | |
647 | case DRM_TEGRA_GEM_TILING_MODE_PITCH: | |
648 | mode = TEGRA_BO_TILING_MODE_PITCH; | |
649 | ||
650 | if (args->value != 0) | |
651 | return -EINVAL; | |
652 | ||
653 | break; | |
654 | ||
655 | case DRM_TEGRA_GEM_TILING_MODE_TILED: | |
656 | mode = TEGRA_BO_TILING_MODE_TILED; | |
657 | ||
658 | if (args->value != 0) | |
659 | return -EINVAL; | |
660 | ||
661 | break; | |
662 | ||
663 | case DRM_TEGRA_GEM_TILING_MODE_BLOCK: | |
664 | mode = TEGRA_BO_TILING_MODE_BLOCK; | |
665 | ||
666 | if (args->value > 5) | |
667 | return -EINVAL; | |
668 | ||
669 | value = args->value; | |
670 | break; | |
671 | ||
672 | default: | |
673 | return -EINVAL; | |
674 | } | |
675 | ||
676 | gem = drm_gem_object_lookup(drm, file, args->handle); | |
677 | if (!gem) | |
678 | return -ENOENT; | |
679 | ||
680 | bo = to_tegra_bo(gem); | |
681 | ||
682 | bo->tiling.mode = mode; | |
683 | bo->tiling.value = value; | |
684 | ||
685 | drm_gem_object_unreference(gem); | |
686 | ||
687 | return 0; | |
688 | } | |
689 | ||
690 | static int tegra_gem_get_tiling(struct drm_device *drm, void *data, | |
691 | struct drm_file *file) | |
692 | { | |
693 | struct drm_tegra_gem_get_tiling *args = data; | |
694 | struct drm_gem_object *gem; | |
695 | struct tegra_bo *bo; | |
696 | int err = 0; | |
697 | ||
698 | gem = drm_gem_object_lookup(drm, file, args->handle); | |
699 | if (!gem) | |
700 | return -ENOENT; | |
701 | ||
702 | bo = to_tegra_bo(gem); | |
703 | ||
704 | switch (bo->tiling.mode) { | |
705 | case TEGRA_BO_TILING_MODE_PITCH: | |
706 | args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH; | |
707 | args->value = 0; | |
708 | break; | |
709 | ||
710 | case TEGRA_BO_TILING_MODE_TILED: | |
711 | args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED; | |
712 | args->value = 0; | |
713 | break; | |
714 | ||
715 | case TEGRA_BO_TILING_MODE_BLOCK: | |
716 | args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK; | |
717 | args->value = bo->tiling.value; | |
718 | break; | |
719 | ||
720 | default: | |
721 | err = -EINVAL; | |
722 | break; | |
723 | } | |
724 | ||
725 | drm_gem_object_unreference(gem); | |
726 | ||
727 | return err; | |
728 | } | |
7b129087 TR |
729 | |
730 | static int tegra_gem_set_flags(struct drm_device *drm, void *data, | |
731 | struct drm_file *file) | |
732 | { | |
733 | struct drm_tegra_gem_set_flags *args = data; | |
734 | struct drm_gem_object *gem; | |
735 | struct tegra_bo *bo; | |
736 | ||
737 | if (args->flags & ~DRM_TEGRA_GEM_FLAGS) | |
738 | return -EINVAL; | |
739 | ||
740 | gem = drm_gem_object_lookup(drm, file, args->handle); | |
741 | if (!gem) | |
742 | return -ENOENT; | |
743 | ||
744 | bo = to_tegra_bo(gem); | |
745 | bo->flags = 0; | |
746 | ||
747 | if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP) | |
748 | bo->flags |= TEGRA_BO_BOTTOM_UP; | |
749 | ||
750 | drm_gem_object_unreference(gem); | |
751 | ||
752 | return 0; | |
753 | } | |
754 | ||
755 | static int tegra_gem_get_flags(struct drm_device *drm, void *data, | |
756 | struct drm_file *file) | |
757 | { | |
758 | struct drm_tegra_gem_get_flags *args = data; | |
759 | struct drm_gem_object *gem; | |
760 | struct tegra_bo *bo; | |
761 | ||
762 | gem = drm_gem_object_lookup(drm, file, args->handle); | |
763 | if (!gem) | |
764 | return -ENOENT; | |
765 | ||
766 | bo = to_tegra_bo(gem); | |
767 | args->flags = 0; | |
768 | ||
769 | if (bo->flags & TEGRA_BO_BOTTOM_UP) | |
770 | args->flags |= DRM_TEGRA_GEM_BOTTOM_UP; | |
771 | ||
772 | drm_gem_object_unreference(gem); | |
773 | ||
774 | return 0; | |
775 | } | |
d43f81cb TB |
776 | #endif |
777 | ||
baa70943 | 778 | static const struct drm_ioctl_desc tegra_drm_ioctls[] = { |
d43f81cb | 779 | #ifdef CONFIG_DRM_TEGRA_STAGING |
bd4f2360 | 780 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, DRM_UNLOCKED), |
d43f81cb TB |
781 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, DRM_UNLOCKED), |
782 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, DRM_UNLOCKED), | |
783 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, DRM_UNLOCKED), | |
784 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, DRM_UNLOCKED), | |
785 | DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, DRM_UNLOCKED), | |
786 | DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, DRM_UNLOCKED), | |
787 | DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, DRM_UNLOCKED), | |
788 | DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, DRM_UNLOCKED), | |
c54a169b | 789 | DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, DRM_UNLOCKED), |
7678d71f TR |
790 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, DRM_UNLOCKED), |
791 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, DRM_UNLOCKED), | |
7b129087 TR |
792 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, DRM_UNLOCKED), |
793 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, DRM_UNLOCKED), | |
d43f81cb | 794 | #endif |
d8f4a9ed TR |
795 | }; |
796 | ||
797 | static const struct file_operations tegra_drm_fops = { | |
798 | .owner = THIS_MODULE, | |
799 | .open = drm_open, | |
800 | .release = drm_release, | |
801 | .unlocked_ioctl = drm_ioctl, | |
de2ba664 | 802 | .mmap = tegra_drm_mmap, |
d8f4a9ed | 803 | .poll = drm_poll, |
d8f4a9ed TR |
804 | .read = drm_read, |
805 | #ifdef CONFIG_COMPAT | |
806 | .compat_ioctl = drm_compat_ioctl, | |
807 | #endif | |
808 | .llseek = noop_llseek, | |
809 | }; | |
810 | ||
ed7dae58 TR |
811 | static struct drm_crtc *tegra_crtc_from_pipe(struct drm_device *drm, |
812 | unsigned int pipe) | |
6e5ff998 TR |
813 | { |
814 | struct drm_crtc *crtc; | |
815 | ||
816 | list_for_each_entry(crtc, &drm->mode_config.crtc_list, head) { | |
ed7dae58 | 817 | if (pipe == drm_crtc_index(crtc)) |
6e5ff998 TR |
818 | return crtc; |
819 | } | |
820 | ||
821 | return NULL; | |
822 | } | |
823 | ||
ed7dae58 | 824 | static u32 tegra_drm_get_vblank_counter(struct drm_device *drm, int pipe) |
6e5ff998 | 825 | { |
ed7dae58 | 826 | struct drm_crtc *crtc = tegra_crtc_from_pipe(drm, pipe); |
42e9ce05 | 827 | struct tegra_dc *dc = to_tegra_dc(crtc); |
ed7dae58 TR |
828 | |
829 | if (!crtc) | |
830 | return 0; | |
831 | ||
42e9ce05 | 832 | return tegra_dc_get_vblank_counter(dc); |
6e5ff998 TR |
833 | } |
834 | ||
835 | static int tegra_drm_enable_vblank(struct drm_device *drm, int pipe) | |
836 | { | |
837 | struct drm_crtc *crtc = tegra_crtc_from_pipe(drm, pipe); | |
838 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
839 | ||
840 | if (!crtc) | |
841 | return -ENODEV; | |
842 | ||
843 | tegra_dc_enable_vblank(dc); | |
844 | ||
845 | return 0; | |
846 | } | |
847 | ||
848 | static void tegra_drm_disable_vblank(struct drm_device *drm, int pipe) | |
849 | { | |
850 | struct drm_crtc *crtc = tegra_crtc_from_pipe(drm, pipe); | |
851 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
852 | ||
853 | if (crtc) | |
854 | tegra_dc_disable_vblank(dc); | |
855 | } | |
856 | ||
3c03c46a TR |
857 | static void tegra_drm_preclose(struct drm_device *drm, struct drm_file *file) |
858 | { | |
08943e6c | 859 | struct tegra_drm_file *fpriv = file->driver_priv; |
c88c3630 | 860 | struct tegra_drm_context *context, *tmp; |
3c03c46a TR |
861 | struct drm_crtc *crtc; |
862 | ||
863 | list_for_each_entry(crtc, &drm->mode_config.crtc_list, head) | |
864 | tegra_dc_cancel_page_flip(crtc, file); | |
d43f81cb TB |
865 | |
866 | list_for_each_entry_safe(context, tmp, &fpriv->contexts, list) | |
c88c3630 | 867 | tegra_drm_context_free(context); |
d43f81cb TB |
868 | |
869 | kfree(fpriv); | |
3c03c46a TR |
870 | } |
871 | ||
e450fcc6 TR |
872 | #ifdef CONFIG_DEBUG_FS |
873 | static int tegra_debugfs_framebuffers(struct seq_file *s, void *data) | |
874 | { | |
875 | struct drm_info_node *node = (struct drm_info_node *)s->private; | |
876 | struct drm_device *drm = node->minor->dev; | |
877 | struct drm_framebuffer *fb; | |
878 | ||
879 | mutex_lock(&drm->mode_config.fb_lock); | |
880 | ||
881 | list_for_each_entry(fb, &drm->mode_config.fb_list, head) { | |
882 | seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n", | |
883 | fb->base.id, fb->width, fb->height, fb->depth, | |
884 | fb->bits_per_pixel, | |
885 | atomic_read(&fb->refcount.refcount)); | |
886 | } | |
887 | ||
888 | mutex_unlock(&drm->mode_config.fb_lock); | |
889 | ||
890 | return 0; | |
891 | } | |
892 | ||
28c23373 TR |
893 | static int tegra_debugfs_iova(struct seq_file *s, void *data) |
894 | { | |
895 | struct drm_info_node *node = (struct drm_info_node *)s->private; | |
896 | struct drm_device *drm = node->minor->dev; | |
897 | struct tegra_drm *tegra = drm->dev_private; | |
898 | ||
899 | return drm_mm_dump_table(s, &tegra->mm); | |
900 | } | |
901 | ||
e450fcc6 TR |
902 | static struct drm_info_list tegra_debugfs_list[] = { |
903 | { "framebuffers", tegra_debugfs_framebuffers, 0 }, | |
28c23373 | 904 | { "iova", tegra_debugfs_iova, 0 }, |
e450fcc6 TR |
905 | }; |
906 | ||
907 | static int tegra_debugfs_init(struct drm_minor *minor) | |
908 | { | |
909 | return drm_debugfs_create_files(tegra_debugfs_list, | |
910 | ARRAY_SIZE(tegra_debugfs_list), | |
911 | minor->debugfs_root, minor); | |
912 | } | |
913 | ||
914 | static void tegra_debugfs_cleanup(struct drm_minor *minor) | |
915 | { | |
916 | drm_debugfs_remove_files(tegra_debugfs_list, | |
917 | ARRAY_SIZE(tegra_debugfs_list), minor); | |
918 | } | |
919 | #endif | |
920 | ||
9b57f5f2 | 921 | static struct drm_driver tegra_drm_driver = { |
3800391d | 922 | .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME, |
d8f4a9ed TR |
923 | .load = tegra_drm_load, |
924 | .unload = tegra_drm_unload, | |
925 | .open = tegra_drm_open, | |
3c03c46a | 926 | .preclose = tegra_drm_preclose, |
d8f4a9ed TR |
927 | .lastclose = tegra_drm_lastclose, |
928 | ||
6e5ff998 TR |
929 | .get_vblank_counter = tegra_drm_get_vblank_counter, |
930 | .enable_vblank = tegra_drm_enable_vblank, | |
931 | .disable_vblank = tegra_drm_disable_vblank, | |
932 | ||
e450fcc6 TR |
933 | #if defined(CONFIG_DEBUG_FS) |
934 | .debugfs_init = tegra_debugfs_init, | |
935 | .debugfs_cleanup = tegra_debugfs_cleanup, | |
936 | #endif | |
937 | ||
de2ba664 AM |
938 | .gem_free_object = tegra_bo_free_object, |
939 | .gem_vm_ops = &tegra_bo_vm_ops, | |
3800391d TR |
940 | |
941 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
942 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
943 | .gem_prime_export = tegra_gem_prime_export, | |
944 | .gem_prime_import = tegra_gem_prime_import, | |
945 | ||
de2ba664 AM |
946 | .dumb_create = tegra_bo_dumb_create, |
947 | .dumb_map_offset = tegra_bo_dumb_map_offset, | |
43387b37 | 948 | .dumb_destroy = drm_gem_dumb_destroy, |
d8f4a9ed TR |
949 | |
950 | .ioctls = tegra_drm_ioctls, | |
951 | .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls), | |
952 | .fops = &tegra_drm_fops, | |
953 | ||
954 | .name = DRIVER_NAME, | |
955 | .desc = DRIVER_DESC, | |
956 | .date = DRIVER_DATE, | |
957 | .major = DRIVER_MAJOR, | |
958 | .minor = DRIVER_MINOR, | |
959 | .patchlevel = DRIVER_PATCHLEVEL, | |
960 | }; | |
776dc384 TR |
961 | |
962 | int tegra_drm_register_client(struct tegra_drm *tegra, | |
963 | struct tegra_drm_client *client) | |
964 | { | |
965 | mutex_lock(&tegra->clients_lock); | |
966 | list_add_tail(&client->list, &tegra->clients); | |
967 | mutex_unlock(&tegra->clients_lock); | |
968 | ||
969 | return 0; | |
970 | } | |
971 | ||
972 | int tegra_drm_unregister_client(struct tegra_drm *tegra, | |
973 | struct tegra_drm_client *client) | |
974 | { | |
975 | mutex_lock(&tegra->clients_lock); | |
976 | list_del_init(&client->list); | |
977 | mutex_unlock(&tegra->clients_lock); | |
978 | ||
979 | return 0; | |
980 | } | |
981 | ||
9910f5c4 | 982 | static int host1x_drm_probe(struct host1x_device *dev) |
776dc384 | 983 | { |
9910f5c4 TR |
984 | struct drm_driver *driver = &tegra_drm_driver; |
985 | struct drm_device *drm; | |
986 | int err; | |
987 | ||
988 | drm = drm_dev_alloc(driver, &dev->dev); | |
989 | if (!drm) | |
990 | return -ENOMEM; | |
991 | ||
992 | drm_dev_set_unique(drm, dev_name(&dev->dev)); | |
993 | dev_set_drvdata(&dev->dev, drm); | |
994 | ||
995 | err = drm_dev_register(drm, 0); | |
996 | if (err < 0) | |
997 | goto unref; | |
998 | ||
999 | DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n", driver->name, | |
1000 | driver->major, driver->minor, driver->patchlevel, | |
1001 | driver->date, drm->primary->index); | |
1002 | ||
1003 | return 0; | |
1004 | ||
1005 | unref: | |
1006 | drm_dev_unref(drm); | |
1007 | return err; | |
776dc384 TR |
1008 | } |
1009 | ||
9910f5c4 | 1010 | static int host1x_drm_remove(struct host1x_device *dev) |
776dc384 | 1011 | { |
9910f5c4 TR |
1012 | struct drm_device *drm = dev_get_drvdata(&dev->dev); |
1013 | ||
1014 | drm_dev_unregister(drm); | |
1015 | drm_dev_unref(drm); | |
776dc384 TR |
1016 | |
1017 | return 0; | |
1018 | } | |
1019 | ||
359ae687 TR |
1020 | #ifdef CONFIG_PM_SLEEP |
1021 | static int host1x_drm_suspend(struct device *dev) | |
1022 | { | |
1023 | struct drm_device *drm = dev_get_drvdata(dev); | |
1024 | ||
1025 | drm_kms_helper_poll_disable(drm); | |
1026 | ||
1027 | return 0; | |
1028 | } | |
1029 | ||
1030 | static int host1x_drm_resume(struct device *dev) | |
1031 | { | |
1032 | struct drm_device *drm = dev_get_drvdata(dev); | |
1033 | ||
1034 | drm_kms_helper_poll_enable(drm); | |
1035 | ||
1036 | return 0; | |
1037 | } | |
1038 | #endif | |
1039 | ||
1040 | static const struct dev_pm_ops host1x_drm_pm_ops = { | |
1041 | SET_SYSTEM_SLEEP_PM_OPS(host1x_drm_suspend, host1x_drm_resume) | |
1042 | }; | |
1043 | ||
776dc384 TR |
1044 | static const struct of_device_id host1x_drm_subdevs[] = { |
1045 | { .compatible = "nvidia,tegra20-dc", }, | |
1046 | { .compatible = "nvidia,tegra20-hdmi", }, | |
1047 | { .compatible = "nvidia,tegra20-gr2d", }, | |
5f60ed0d | 1048 | { .compatible = "nvidia,tegra20-gr3d", }, |
776dc384 TR |
1049 | { .compatible = "nvidia,tegra30-dc", }, |
1050 | { .compatible = "nvidia,tegra30-hdmi", }, | |
1051 | { .compatible = "nvidia,tegra30-gr2d", }, | |
5f60ed0d | 1052 | { .compatible = "nvidia,tegra30-gr3d", }, |
dec72739 | 1053 | { .compatible = "nvidia,tegra114-dsi", }, |
7d1d28ac | 1054 | { .compatible = "nvidia,tegra114-hdmi", }, |
5f60ed0d | 1055 | { .compatible = "nvidia,tegra114-gr3d", }, |
8620fc62 | 1056 | { .compatible = "nvidia,tegra124-dc", }, |
6b6b6042 | 1057 | { .compatible = "nvidia,tegra124-sor", }, |
fb7be70e | 1058 | { .compatible = "nvidia,tegra124-hdmi", }, |
776dc384 TR |
1059 | { /* sentinel */ } |
1060 | }; | |
1061 | ||
1062 | static struct host1x_driver host1x_drm_driver = { | |
f4c5cf88 TR |
1063 | .driver = { |
1064 | .name = "drm", | |
359ae687 | 1065 | .pm = &host1x_drm_pm_ops, |
f4c5cf88 | 1066 | }, |
776dc384 TR |
1067 | .probe = host1x_drm_probe, |
1068 | .remove = host1x_drm_remove, | |
1069 | .subdevs = host1x_drm_subdevs, | |
1070 | }; | |
1071 | ||
1072 | static int __init host1x_drm_init(void) | |
1073 | { | |
1074 | int err; | |
1075 | ||
1076 | err = host1x_driver_register(&host1x_drm_driver); | |
1077 | if (err < 0) | |
1078 | return err; | |
1079 | ||
1080 | err = platform_driver_register(&tegra_dc_driver); | |
1081 | if (err < 0) | |
1082 | goto unregister_host1x; | |
1083 | ||
dec72739 | 1084 | err = platform_driver_register(&tegra_dsi_driver); |
776dc384 TR |
1085 | if (err < 0) |
1086 | goto unregister_dc; | |
1087 | ||
6b6b6042 | 1088 | err = platform_driver_register(&tegra_sor_driver); |
dec72739 TR |
1089 | if (err < 0) |
1090 | goto unregister_dsi; | |
1091 | ||
6b6b6042 TR |
1092 | err = platform_driver_register(&tegra_hdmi_driver); |
1093 | if (err < 0) | |
1094 | goto unregister_sor; | |
1095 | ||
1096 | err = platform_driver_register(&tegra_dpaux_driver); | |
776dc384 TR |
1097 | if (err < 0) |
1098 | goto unregister_hdmi; | |
1099 | ||
6b6b6042 TR |
1100 | err = platform_driver_register(&tegra_gr2d_driver); |
1101 | if (err < 0) | |
1102 | goto unregister_dpaux; | |
1103 | ||
5f60ed0d TR |
1104 | err = platform_driver_register(&tegra_gr3d_driver); |
1105 | if (err < 0) | |
1106 | goto unregister_gr2d; | |
1107 | ||
776dc384 TR |
1108 | return 0; |
1109 | ||
5f60ed0d TR |
1110 | unregister_gr2d: |
1111 | platform_driver_unregister(&tegra_gr2d_driver); | |
6b6b6042 TR |
1112 | unregister_dpaux: |
1113 | platform_driver_unregister(&tegra_dpaux_driver); | |
776dc384 TR |
1114 | unregister_hdmi: |
1115 | platform_driver_unregister(&tegra_hdmi_driver); | |
6b6b6042 TR |
1116 | unregister_sor: |
1117 | platform_driver_unregister(&tegra_sor_driver); | |
dec72739 TR |
1118 | unregister_dsi: |
1119 | platform_driver_unregister(&tegra_dsi_driver); | |
776dc384 TR |
1120 | unregister_dc: |
1121 | platform_driver_unregister(&tegra_dc_driver); | |
1122 | unregister_host1x: | |
1123 | host1x_driver_unregister(&host1x_drm_driver); | |
1124 | return err; | |
1125 | } | |
1126 | module_init(host1x_drm_init); | |
1127 | ||
1128 | static void __exit host1x_drm_exit(void) | |
1129 | { | |
5f60ed0d | 1130 | platform_driver_unregister(&tegra_gr3d_driver); |
776dc384 | 1131 | platform_driver_unregister(&tegra_gr2d_driver); |
6b6b6042 | 1132 | platform_driver_unregister(&tegra_dpaux_driver); |
776dc384 | 1133 | platform_driver_unregister(&tegra_hdmi_driver); |
6b6b6042 | 1134 | platform_driver_unregister(&tegra_sor_driver); |
dec72739 | 1135 | platform_driver_unregister(&tegra_dsi_driver); |
776dc384 TR |
1136 | platform_driver_unregister(&tegra_dc_driver); |
1137 | host1x_driver_unregister(&host1x_drm_driver); | |
1138 | } | |
1139 | module_exit(host1x_drm_exit); | |
1140 | ||
1141 | MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); | |
1142 | MODULE_DESCRIPTION("NVIDIA Tegra DRM driver"); | |
1143 | MODULE_LICENSE("GPL v2"); |