projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/tegra: dc: Move register definitions into a table
[linux-2.6-block.git] / drivers / gpu / drm / tegra / dc.c
CommitLineData
d8f4a9ed
TR		 1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
9eb9b220 11#include <linux/debugfs.h>
df06b759 12#include <linux/iommu.h>
b9ff7aea 13#include <linux/of_device.h>
33a8eb8d 14#include <linux/pm_runtime.h>
ca48080a 15#include <linux/reset.h>
d8f4a9ed 16
9c012700
TR		 17#include <soc/tegra/pmc.h>
18
de2ba664
AM		 19#include "dc.h"
20#include "drm.h"
21#include "gem.h"
d8f4a9ed 22
9d44189f 23#include <drm/drm_atomic.h>
4aa3df71 24#include <drm/drm_atomic_helper.h>
3cb9ae4f
DV		 25#include <drm/drm_plane_helper.h>
26
f34bc787
TR		 27struct tegra_plane {
28 struct drm_plane base;
29 unsigned int index;
d8f4a9ed
TR		 30};
31
f34bc787
TR		 32static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
33{
34 return container_of(plane, struct tegra_plane, base);
35}
36
ca915b10
TR		 37struct tegra_dc_state {
38 struct drm_crtc_state base;
39
40 struct clk *clk;
41 unsigned long pclk;
42 unsigned int div;
47802b09
TR		 43
44 u32 planes;
ca915b10
TR		 45};
46
47static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state)
48{
49 if (state)
50 return container_of(state, struct tegra_dc_state, base);
51
52 return NULL;
53}
54
8f604f8c
TR		 55struct tegra_plane_state {
56 struct drm_plane_state base;
57
58 struct tegra_bo_tiling tiling;
59 u32 format;
60 u32 swap;
61};
62
63static inline struct tegra_plane_state *
64to_tegra_plane_state(struct drm_plane_state *state)
65{
66 if (state)
67 return container_of(state, struct tegra_plane_state, base);
68
69 return NULL;
70}
71
791ddb1e
TR		 72static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
73{
74 stats->frames = 0;
75 stats->vblank = 0;
76 stats->underflow = 0;
77 stats->overflow = 0;
78}
79
86df256f
TR		 80/*
81 * Reads the active copy of a register. This takes the dc->lock spinlock to
82 * prevent races with the VBLANK processing which also needs access to the
83 * active copy of some registers.
84 */
85static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
86{
87 unsigned long flags;
88 u32 value;
89
90 spin_lock_irqsave(&dc->lock, flags);
91
92 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
93 value = tegra_dc_readl(dc, offset);
94 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
95
96 spin_unlock_irqrestore(&dc->lock, flags);
97 return value;
98}
99
d700ba7a
TR		 100/*
101 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
102 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
103 * Latching happens mmediately if the display controller is in STOP mode or
104 * on the next frame boundary otherwise.
105 *
106 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
107 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
108 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
109 * into the ACTIVE copy, either immediately if the display controller is in
110 * STOP mode, or at the next frame boundary otherwise.
111 */
62b9e063 112void tegra_dc_commit(struct tegra_dc *dc)
205d48ed
TR		 113{
114 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
115 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
116}
117
8f604f8c 118static int tegra_dc_format(u32 fourcc, u32 *format, u32 *swap)
10288eea
TR		 119{
120 /* assume no swapping of fetched data */
121 if (swap)
122 *swap = BYTE_SWAP_NOSWAP;
123
8f604f8c 124 switch (fourcc) {
10288eea 125 case DRM_FORMAT_XBGR8888:
8f604f8c
TR		 126 *format = WIN_COLOR_DEPTH_R8G8B8A8;
127 break;
10288eea
TR		 128
129 case DRM_FORMAT_XRGB8888:
8f604f8c
TR		 130 *format = WIN_COLOR_DEPTH_B8G8R8A8;
131 break;
10288eea
TR		 132
133 case DRM_FORMAT_RGB565:
8f604f8c
TR		 134 *format = WIN_COLOR_DEPTH_B5G6R5;
135 break;
10288eea
TR		 136
137 case DRM_FORMAT_UYVY:
8f604f8c
TR		 138 *format = WIN_COLOR_DEPTH_YCbCr422;
139 break;
10288eea
TR		 140
141 case DRM_FORMAT_YUYV:
142 if (swap)
143 *swap = BYTE_SWAP_SWAP2;
144
8f604f8c
TR		 145 *format = WIN_COLOR_DEPTH_YCbCr422;
146 break;
10288eea
TR		 147
148 case DRM_FORMAT_YUV420:
8f604f8c
TR		 149 *format = WIN_COLOR_DEPTH_YCbCr420P;
150 break;
10288eea
TR		 151
152 case DRM_FORMAT_YUV422:
8f604f8c
TR		 153 *format = WIN_COLOR_DEPTH_YCbCr422P;
154 break;
10288eea
TR		 155
156 default:
8f604f8c 157 return -EINVAL;
10288eea
TR		 158 }
159
8f604f8c 160 return 0;
10288eea
TR		 161}
162
163static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
164{
165 switch (format) {
166 case WIN_COLOR_DEPTH_YCbCr422:
167 case WIN_COLOR_DEPTH_YUV422:
168 if (planar)
169 *planar = false;
170
171 return true;
172
173 case WIN_COLOR_DEPTH_YCbCr420P:
174 case WIN_COLOR_DEPTH_YUV420P:
175 case WIN_COLOR_DEPTH_YCbCr422P:
176 case WIN_COLOR_DEPTH_YUV422P:
177 case WIN_COLOR_DEPTH_YCbCr422R:
178 case WIN_COLOR_DEPTH_YUV422R:
179 case WIN_COLOR_DEPTH_YCbCr422RA:
180 case WIN_COLOR_DEPTH_YUV422RA:
181 if (planar)
182 *planar = true;
183
184 return true;
185 }
186
fb35c6b6
TR		 187 if (planar)
188 *planar = false;
189
10288eea
TR		 190 return false;
191}
192
193static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
194 unsigned int bpp)
195{
196 fixed20_12 outf = dfixed_init(out);
197 fixed20_12 inf = dfixed_init(in);
198 u32 dda_inc;
199 int max;
200
201 if (v)
202 max = 15;
203 else {
204 switch (bpp) {
205 case 2:
206 max = 8;
207 break;
208
209 default:
210 WARN_ON_ONCE(1);
211 /* fallthrough */
212 case 4:
213 max = 4;
214 break;
215 }
216 }
217
218 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
219 inf.full -= dfixed_const(1);
220
221 dda_inc = dfixed_div(inf, outf);
222 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
223
224 return dda_inc;
225}
226
227static inline u32 compute_initial_dda(unsigned int in)
228{
229 fixed20_12 inf = dfixed_init(in);
230 return dfixed_frac(inf);
231}
232
4aa3df71
TR		 233static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
234 const struct tegra_dc_window *window)
10288eea
TR		 235{
236 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
93396d0f 237 unsigned long value, flags;
10288eea
TR		 238 bool yuv, planar;
239
240 /*
241 * For YUV planar modes, the number of bytes per pixel takes into
242 * account only the luma component and therefore is 1.
243 */
244 yuv = tegra_dc_format_is_yuv(window->format, &planar);
245 if (!yuv)
246 bpp = window->bits_per_pixel / 8;
247 else
248 bpp = planar ? 1 : 2;
249
93396d0f
SP		 250 spin_lock_irqsave(&dc->lock, flags);
251
10288eea
TR		 252 value = WINDOW_A_SELECT << index;
253 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
254
255 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
256 tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
257
258 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
259 tegra_dc_writel(dc, value, DC_WIN_POSITION);
260
261 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
262 tegra_dc_writel(dc, value, DC_WIN_SIZE);
263
264 h_offset = window->src.x * bpp;
265 v_offset = window->src.y;
266 h_size = window->src.w * bpp;
267 v_size = window->src.h;
268
269 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
270 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
271
272 /*
273 * For DDA computations the number of bytes per pixel for YUV planar
274 * modes needs to take into account all Y, U and V components.
275 */
276 if (yuv && planar)
277 bpp = 2;
278
279 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
280 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
281
282 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
283 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
284
285 h_dda = compute_initial_dda(window->src.x);
286 v_dda = compute_initial_dda(window->src.y);
287
288 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
289 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
290
291 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
292 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
293
294 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
295
296 if (yuv && planar) {
297 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
298 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
299 value = window->stride[1] << 16 | window->stride[0];
300 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
301 } else {
302 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
303 }
304
305 if (window->bottom_up)
306 v_offset += window->src.h - 1;
307
308 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
309 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
310
c134f019
TR		 311 if (dc->soc->supports_block_linear) {
312 unsigned long height = window->tiling.value;
313
314 switch (window->tiling.mode) {
315 case TEGRA_BO_TILING_MODE_PITCH:
316 value = DC_WINBUF_SURFACE_KIND_PITCH;
317 break;
318
319 case TEGRA_BO_TILING_MODE_TILED:
320 value = DC_WINBUF_SURFACE_KIND_TILED;
321 break;
322
323 case TEGRA_BO_TILING_MODE_BLOCK:
324 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
325 DC_WINBUF_SURFACE_KIND_BLOCK;
326 break;
327 }
328
329 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
10288eea 330 } else {
c134f019
TR		 331 switch (window->tiling.mode) {
332 case TEGRA_BO_TILING_MODE_PITCH:
333 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
334 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
335 break;
10288eea 336
c134f019
TR		 337 case TEGRA_BO_TILING_MODE_TILED:
338 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
339 DC_WIN_BUFFER_ADDR_MODE_TILE;
340 break;
341
342 case TEGRA_BO_TILING_MODE_BLOCK:
4aa3df71
TR		 343 /*
344 * No need to handle this here because ->atomic_check
345 * will already have filtered it out.
346 */
347 break;
c134f019
TR		 348 }
349
350 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
351 }
10288eea
TR		 352
353 value = WIN_ENABLE;
354
355 if (yuv) {
356 /* setup default colorspace conversion coefficients */
357 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
358 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
359 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
360 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
361 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
362 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
363 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
364 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
365
366 value |= CSC_ENABLE;
367 } else if (window->bits_per_pixel < 24) {
368 value |= COLOR_EXPAND;
369 }
370
371 if (window->bottom_up)
372 value |= V_DIRECTION;
373
374 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
375
376 /*
377 * Disable blending and assume Window A is the bottom-most window,
378 * Window C is the top-most window and Window B is in the middle.
379 */
380 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
381 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
382
383 switch (index) {
384 case 0:
385 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
386 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
387 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
388 break;
389
390 case 1:
391 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
392 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
393 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
394 break;
395
396 case 2:
397 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
398 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
399 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
400 break;
401 }
402
93396d0f 403 spin_unlock_irqrestore(&dc->lock, flags);
c7679306
TR		 404}
405
406static void tegra_plane_destroy(struct drm_plane *plane)
407{
408 struct tegra_plane *p = to_tegra_plane(plane);
409
410 drm_plane_cleanup(plane);
411 kfree(p);
412}
413
414static const u32 tegra_primary_plane_formats[] = {
415 DRM_FORMAT_XBGR8888,
416 DRM_FORMAT_XRGB8888,
417 DRM_FORMAT_RGB565,
418};
419
4aa3df71 420static void tegra_primary_plane_destroy(struct drm_plane *plane)
c7679306 421{
4aa3df71
TR		 422 tegra_plane_destroy(plane);
423}
424
8f604f8c
TR		 425static void tegra_plane_reset(struct drm_plane *plane)
426{
427 struct tegra_plane_state *state;
428
3b59b7ac 429 if (plane->state)
2f701695 430 __drm_atomic_helper_plane_destroy_state(plane->state);
8f604f8c
TR		 431
432 kfree(plane->state);
433 plane->state = NULL;
434
435 state = kzalloc(sizeof(*state), GFP_KERNEL);
436 if (state) {
437 plane->state = &state->base;
438 plane->state->plane = plane;
439 }
440}
441
442static struct drm_plane_state *tegra_plane_atomic_duplicate_state(struct drm_plane *plane)
443{
444 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
445 struct tegra_plane_state *copy;
446
3b59b7ac 447 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
8f604f8c
TR		 448 if (!copy)
449 return NULL;
450
3b59b7ac
TR		 451 __drm_atomic_helper_plane_duplicate_state(plane, &copy->base);
452 copy->tiling = state->tiling;
453 copy->format = state->format;
454 copy->swap = state->swap;
8f604f8c
TR		 455
456 return &copy->base;
457}
458
459static void tegra_plane_atomic_destroy_state(struct drm_plane *plane,
460 struct drm_plane_state *state)
461{
2f701695 462 __drm_atomic_helper_plane_destroy_state(state);
8f604f8c
TR		 463 kfree(state);
464}
465
4aa3df71 466static const struct drm_plane_funcs tegra_primary_plane_funcs = {
07866963
TR		 467 .update_plane = drm_atomic_helper_update_plane,
468 .disable_plane = drm_atomic_helper_disable_plane,
4aa3df71 469 .destroy = tegra_primary_plane_destroy,
8f604f8c
TR		 470 .reset = tegra_plane_reset,
471 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
472 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
4aa3df71
TR		 473};
474
47802b09
TR		 475static int tegra_plane_state_add(struct tegra_plane *plane,
476 struct drm_plane_state *state)
477{
478 struct drm_crtc_state *crtc_state;
479 struct tegra_dc_state *tegra;
7d205857
DO		 480 struct drm_rect clip;
481 int err;
47802b09
TR		 482
483 /* Propagate errors from allocation or locking failures. */
484 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
485 if (IS_ERR(crtc_state))
486 return PTR_ERR(crtc_state);
487
7d205857
DO		 488 clip.x1 = 0;
489 clip.y1 = 0;
490 clip.x2 = crtc_state->mode.hdisplay;
491 clip.y2 = crtc_state->mode.vdisplay;
492
493 /* Check plane state for visibility and calculate clipping bounds */
a01cb8ba
VS		 494 err = drm_atomic_helper_check_plane_state(state, crtc_state, &clip,
495 0, INT_MAX, true, true);
7d205857
DO		 496 if (err < 0)
497 return err;
498
47802b09
TR		 499 tegra = to_dc_state(crtc_state);
500
501 tegra->planes |= WIN_A_ACT_REQ << plane->index;
502
503 return 0;
504}
505
4aa3df71
TR		 506static int tegra_plane_atomic_check(struct drm_plane *plane,
507 struct drm_plane_state *state)
508{
8f604f8c
TR		 509 struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
510 struct tegra_bo_tiling *tiling = &plane_state->tiling;
47802b09 511 struct tegra_plane *tegra = to_tegra_plane(plane);
4aa3df71 512 struct tegra_dc *dc = to_tegra_dc(state->crtc);
4aa3df71
TR		 513 int err;
514
515 /* no need for further checks if the plane is being disabled */
516 if (!state->crtc)
517 return 0;
518
438b74a5 519 err = tegra_dc_format(state->fb->format->format, &plane_state->format,
8f604f8c 520 &plane_state->swap);
4aa3df71
TR		 521 if (err < 0)
522 return err;
523
8f604f8c
TR		 524 err = tegra_fb_get_tiling(state->fb, tiling);
525 if (err < 0)
526 return err;
527
528 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
4aa3df71
TR		 529 !dc->soc->supports_block_linear) {
530 DRM_ERROR("hardware doesn't support block linear mode\n");
531 return -EINVAL;
532 }
533
534 /*
535 * Tegra doesn't support different strides for U and V planes so we
536 * error out if the user tries to display a framebuffer with such a
537 * configuration.
538 */
bcb0b461 539 if (state->fb->format->num_planes > 2) {
4aa3df71
TR		 540 if (state->fb->pitches[2] != state->fb->pitches[1]) {
541 DRM_ERROR("unsupported UV-plane configuration\n");
542 return -EINVAL;
543 }
544 }
545
47802b09
TR		 546 err = tegra_plane_state_add(tegra, state);
547 if (err < 0)
548 return err;
549
4aa3df71
TR		 550 return 0;
551}
552
a4bfa096
TR		 553static void tegra_plane_atomic_disable(struct drm_plane *plane,
554 struct drm_plane_state *old_state)
80d3eef1 555{
a4bfa096
TR		 556 struct tegra_dc *dc = to_tegra_dc(old_state->crtc);
557 struct tegra_plane *p = to_tegra_plane(plane);
80d3eef1
DO		 558 unsigned long flags;
559 u32 value;
560
a4bfa096
TR		 561 /* rien ne va plus */
562 if (!old_state || !old_state->crtc)
563 return;
564
80d3eef1
DO		 565 spin_lock_irqsave(&dc->lock, flags);
566
a4bfa096 567 value = WINDOW_A_SELECT << p->index;
80d3eef1
DO		 568 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
569
570 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
571 value &= ~WIN_ENABLE;
572 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
573
574 spin_unlock_irqrestore(&dc->lock, flags);
575}
576
4aa3df71
TR		 577static void tegra_plane_atomic_update(struct drm_plane *plane,
578 struct drm_plane_state *old_state)
579{
8f604f8c 580 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
4aa3df71
TR		 581 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
582 struct drm_framebuffer *fb = plane->state->fb;
c7679306 583 struct tegra_plane *p = to_tegra_plane(plane);
c7679306 584 struct tegra_dc_window window;
4aa3df71 585 unsigned int i;
c7679306 586
4aa3df71
TR		 587 /* rien ne va plus */
588 if (!plane->state->crtc || !plane->state->fb)
589 return;
590
80d3eef1 591 if (!plane->state->visible)
a4bfa096 592 return tegra_plane_atomic_disable(plane, old_state);
80d3eef1 593
c7679306 594 memset(&window, 0, sizeof(window));
7d205857
DO		 595 window.src.x = plane->state->src.x1 >> 16;
596 window.src.y = plane->state->src.y1 >> 16;
597 window.src.w = drm_rect_width(&plane->state->src) >> 16;
598 window.src.h = drm_rect_height(&plane->state->src) >> 16;
599 window.dst.x = plane->state->dst.x1;
600 window.dst.y = plane->state->dst.y1;
601 window.dst.w = drm_rect_width(&plane->state->dst);
602 window.dst.h = drm_rect_height(&plane->state->dst);
272725c7 603 window.bits_per_pixel = fb->format->cpp[0] * 8;
c7679306
TR		 604 window.bottom_up = tegra_fb_is_bottom_up(fb);
605
8f604f8c
TR		 606 /* copy from state */
607 window.tiling = state->tiling;
608 window.format = state->format;
609 window.swap = state->swap;
c7679306 610
bcb0b461 611 for (i = 0; i < fb->format->num_planes; i++) {
4aa3df71 612 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
c7679306 613
4aa3df71 614 window.base[i] = bo->paddr + fb->offsets[i];
08ee0178
DO		 615
616 /*
617 * Tegra uses a shared stride for UV planes. Framebuffers are
618 * already checked for this in the tegra_plane_atomic_check()
619 * function, so it's safe to ignore the V-plane pitch here.
620 */
621 if (i < 2)
622 window.stride[i] = fb->pitches[i];
4aa3df71 623 }
10288eea 624
4aa3df71 625 tegra_dc_setup_window(dc, p->index, &window);
10288eea
TR		 626}
627
a4bfa096 628static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
4aa3df71 629 .atomic_check = tegra_plane_atomic_check,
4aa3df71 630 .atomic_disable = tegra_plane_atomic_disable,
a4bfa096 631 .atomic_update = tegra_plane_atomic_update,
c7679306
TR		 632};
633
634static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,
635 struct tegra_dc *dc)
636{
518e6227
TR		 637 /*
638 * Ideally this would use drm_crtc_mask(), but that would require the
639 * CRTC to already be in the mode_config's list of CRTCs. However, it
640 * will only be added to that list in the drm_crtc_init_with_planes()
641 * (in tegra_dc_init()), which in turn requires registration of these
642 * planes. So we have ourselves a nice little chicken and egg problem
643 * here.
644 *
645 * We work around this by manually creating the mask from the number
646 * of CRTCs that have been registered, and should therefore always be
647 * the same as drm_crtc_index() after registration.
648 */
649 unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc;
c7679306
TR		 650 struct tegra_plane *plane;
651 unsigned int num_formats;
652 const u32 *formats;
653 int err;
654
655 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
656 if (!plane)
657 return ERR_PTR(-ENOMEM);
658
659 num_formats = ARRAY_SIZE(tegra_primary_plane_formats);
660 formats = tegra_primary_plane_formats;
661
518e6227 662 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
c7679306 663 &tegra_primary_plane_funcs, formats,
e6fc3b68
BW		 664 num_formats, NULL,
665 DRM_PLANE_TYPE_PRIMARY, NULL);
c7679306
TR		 666 if (err < 0) {
667 kfree(plane);
668 return ERR_PTR(err);
669 }
670
a4bfa096 671 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
4aa3df71 672
c7679306
TR		 673 return &plane->base;
674}
675
676static const u32 tegra_cursor_plane_formats[] = {
677 DRM_FORMAT_RGBA8888,
678};
679
4aa3df71
TR		 680static int tegra_cursor_atomic_check(struct drm_plane *plane,
681 struct drm_plane_state *state)
c7679306 682{
47802b09
TR		 683 struct tegra_plane *tegra = to_tegra_plane(plane);
684 int err;
685
4aa3df71
TR		 686 /* no need for further checks if the plane is being disabled */
687 if (!state->crtc)
688 return 0;
c7679306
TR		 689
690 /* scaling not supported for cursor */
4aa3df71
TR		 691 if ((state->src_w >> 16 != state->crtc_w) ||
692 (state->src_h >> 16 != state->crtc_h))
c7679306
TR		 693 return -EINVAL;
694
695 /* only square cursors supported */
4aa3df71
TR		 696 if (state->src_w != state->src_h)
697 return -EINVAL;
698
699 if (state->crtc_w != 32 && state->crtc_w != 64 &&
700 state->crtc_w != 128 && state->crtc_w != 256)
c7679306
TR		 701 return -EINVAL;
702
47802b09
TR		 703 err = tegra_plane_state_add(tegra, state);
704 if (err < 0)
705 return err;
706
4aa3df71
TR		 707 return 0;
708}
709
710static void tegra_cursor_atomic_update(struct drm_plane *plane,
711 struct drm_plane_state *old_state)
712{
713 struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0);
714 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
715 struct drm_plane_state *state = plane->state;
716 u32 value = CURSOR_CLIP_DISPLAY;
717
718 /* rien ne va plus */
719 if (!plane->state->crtc || !plane->state->fb)
720 return;
721
722 switch (state->crtc_w) {
c7679306
TR		 723 case 32:
724 value |= CURSOR_SIZE_32x32;
725 break;
726
727 case 64:
728 value |= CURSOR_SIZE_64x64;
729 break;
730
731 case 128:
732 value |= CURSOR_SIZE_128x128;
733 break;
734
735 case 256:
736 value |= CURSOR_SIZE_256x256;
737 break;
738
739 default:
4aa3df71
TR		 740 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w,
741 state->crtc_h);
742 return;
c7679306
TR		 743 }
744
745 value |= (bo->paddr >> 10) & 0x3fffff;
746 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
747
748#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
749 value = (bo->paddr >> 32) & 0x3;
750 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
751#endif
752
753 /* enable cursor and set blend mode */
754 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
755 value |= CURSOR_ENABLE;
756 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
757
758 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
759 value &= ~CURSOR_DST_BLEND_MASK;
760 value &= ~CURSOR_SRC_BLEND_MASK;
761 value |= CURSOR_MODE_NORMAL;
762 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
763 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
764 value |= CURSOR_ALPHA;
765 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
766
767 /* position the cursor */
4aa3df71 768 value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
c7679306 769 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
c7679306
TR		 770}
771
4aa3df71
TR		 772static void tegra_cursor_atomic_disable(struct drm_plane *plane,
773 struct drm_plane_state *old_state)
c7679306 774{
4aa3df71 775 struct tegra_dc *dc;
c7679306
TR		 776 u32 value;
777
4aa3df71
TR		 778 /* rien ne va plus */
779 if (!old_state || !old_state->crtc)
780 return;
781
782 dc = to_tegra_dc(old_state->crtc);
c7679306
TR		 783
784 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
785 value &= ~CURSOR_ENABLE;
786 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
c7679306
TR		 787}
788
789static const struct drm_plane_funcs tegra_cursor_plane_funcs = {
07866963
TR		 790 .update_plane = drm_atomic_helper_update_plane,
791 .disable_plane = drm_atomic_helper_disable_plane,
c7679306 792 .destroy = tegra_plane_destroy,
8f604f8c
TR		 793 .reset = tegra_plane_reset,
794 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
795 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
4aa3df71
TR		 796};
797
798static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
4aa3df71
TR		 799 .atomic_check = tegra_cursor_atomic_check,
800 .atomic_update = tegra_cursor_atomic_update,
801 .atomic_disable = tegra_cursor_atomic_disable,
c7679306
TR		 802};
803
804static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
805 struct tegra_dc *dc)
806{
807 struct tegra_plane *plane;
808 unsigned int num_formats;
809 const u32 *formats;
810 int err;
811
812 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
813 if (!plane)
814 return ERR_PTR(-ENOMEM);
815
47802b09 816 /*
a1df3b24
TR		 817 * This index is kind of fake. The cursor isn't a regular plane, but
818 * its update and activation request bits in DC_CMD_STATE_CONTROL do
819 * use the same programming. Setting this fake index here allows the
820 * code in tegra_add_plane_state() to do the right thing without the
821 * need to special-casing the cursor plane.
47802b09
TR		 822 */
823 plane->index = 6;
824
c7679306
TR		 825 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
826 formats = tegra_cursor_plane_formats;
827
828 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
829 &tegra_cursor_plane_funcs, formats,
e6fc3b68
BW		 830 num_formats, NULL,
831 DRM_PLANE_TYPE_CURSOR, NULL);
c7679306
TR		 832 if (err < 0) {
833 kfree(plane);
834 return ERR_PTR(err);
835 }
836
4aa3df71 837 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
f34bc787 838
4aa3df71 839 return &plane->base;
f34bc787
TR		 840}
841
c7679306 842static void tegra_overlay_plane_destroy(struct drm_plane *plane)
f34bc787 843{
c7679306 844 tegra_plane_destroy(plane);
f34bc787
TR		 845}
846
c7679306 847static const struct drm_plane_funcs tegra_overlay_plane_funcs = {
07866963
TR		 848 .update_plane = drm_atomic_helper_update_plane,
849 .disable_plane = drm_atomic_helper_disable_plane,
c7679306 850 .destroy = tegra_overlay_plane_destroy,
8f604f8c
TR		 851 .reset = tegra_plane_reset,
852 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
853 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
f34bc787
TR		 854};
855
c7679306 856static const uint32_t tegra_overlay_plane_formats[] = {
dbe4d9a7 857 DRM_FORMAT_XBGR8888,
f34bc787 858 DRM_FORMAT_XRGB8888,
dbe4d9a7 859 DRM_FORMAT_RGB565,
f34bc787 860 DRM_FORMAT_UYVY,
f925390e 861 DRM_FORMAT_YUYV,
f34bc787
TR		 862 DRM_FORMAT_YUV420,
863 DRM_FORMAT_YUV422,
864};
865
c7679306
TR		 866static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
867 struct tegra_dc *dc,
868 unsigned int index)
f34bc787 869{
c7679306
TR		 870 struct tegra_plane *plane;
871 unsigned int num_formats;
872 const u32 *formats;
873 int err;
f34bc787 874
c7679306
TR		 875 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
876 if (!plane)
877 return ERR_PTR(-ENOMEM);
f34bc787 878
c7679306 879 plane->index = index;
f34bc787 880
c7679306
TR		 881 num_formats = ARRAY_SIZE(tegra_overlay_plane_formats);
882 formats = tegra_overlay_plane_formats;
f34bc787 883
c7679306
TR		 884 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
885 &tegra_overlay_plane_funcs, formats,
e6fc3b68
BW		 886 num_formats, NULL,
887 DRM_PLANE_TYPE_OVERLAY, NULL);
c7679306
TR		 888 if (err < 0) {
889 kfree(plane);
890 return ERR_PTR(err);
891 }
892
a4bfa096 893 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
4aa3df71 894
c7679306
TR		 895 return &plane->base;
896}
897
898static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
899{
900 struct drm_plane *plane;
901 unsigned int i;
902
903 for (i = 0; i < 2; i++) {
904 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
905 if (IS_ERR(plane))
906 return PTR_ERR(plane);
f34bc787
TR		 907 }
908
909 return 0;
910}
911
10437d9b 912static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc)
42e9ce05 913{
10437d9b
SG		 914 struct tegra_dc *dc = to_tegra_dc(crtc);
915
42e9ce05
TR		 916 if (dc->syncpt)
917 return host1x_syncpt_read(dc->syncpt);
918
919 /* fallback to software emulated VBLANK counter */
920 return drm_crtc_vblank_count(&dc->base);
921}
922
10437d9b 923static int tegra_dc_enable_vblank(struct drm_crtc *crtc)
6e5ff998 924{
10437d9b 925 struct tegra_dc *dc = to_tegra_dc(crtc);
6e5ff998
TR		 926 unsigned long value, flags;
927
928 spin_lock_irqsave(&dc->lock, flags);
929
930 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
931 value |= VBLANK_INT;
932 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
933
934 spin_unlock_irqrestore(&dc->lock, flags);
10437d9b
SG		 935
936 return 0;
6e5ff998
TR		 937}
938
10437d9b 939static void tegra_dc_disable_vblank(struct drm_crtc *crtc)
6e5ff998 940{
10437d9b 941 struct tegra_dc *dc = to_tegra_dc(crtc);
6e5ff998
TR		 942 unsigned long value, flags;
943
944 spin_lock_irqsave(&dc->lock, flags);
945
946 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
947 value &= ~VBLANK_INT;
948 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
949
950 spin_unlock_irqrestore(&dc->lock, flags);
951}
952
3c03c46a
TR		 953static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
954{
955 struct drm_device *drm = dc->base.dev;
956 struct drm_crtc *crtc = &dc->base;
3c03c46a 957 unsigned long flags, base;
de2ba664 958 struct tegra_bo *bo;
3c03c46a 959
6b59cc1c
TR		 960 spin_lock_irqsave(&drm->event_lock, flags);
961
962 if (!dc->event) {
963 spin_unlock_irqrestore(&drm->event_lock, flags);
3c03c46a 964 return;
6b59cc1c 965 }
3c03c46a 966
f4510a27 967 bo = tegra_fb_get_plane(crtc->primary->fb, 0);
3c03c46a 968
8643bc6d 969 spin_lock(&dc->lock);
93396d0f 970
3c03c46a 971 /* check if new start address has been latched */
93396d0f 972 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
3c03c46a
TR		 973 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
974 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
975 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
976
8643bc6d 977 spin_unlock(&dc->lock);
93396d0f 978
f4510a27 979 if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
ed7dae58
TR		 980 drm_crtc_send_vblank_event(crtc, dc->event);
981 drm_crtc_vblank_put(crtc);
3c03c46a 982 dc->event = NULL;
3c03c46a 983 }
6b59cc1c
TR		 984
985 spin_unlock_irqrestore(&drm->event_lock, flags);
3c03c46a
TR		 986}
987
f002abc1
TR		 988static void tegra_dc_destroy(struct drm_crtc *crtc)
989{
990 drm_crtc_cleanup(crtc);
f002abc1
TR		 991}
992
ca915b10
TR		 993static void tegra_crtc_reset(struct drm_crtc *crtc)
994{
995 struct tegra_dc_state *state;
996
3b59b7ac 997 if (crtc->state)
ec2dc6a0 998 __drm_atomic_helper_crtc_destroy_state(crtc->state);
3b59b7ac 999
ca915b10
TR		 1000 kfree(crtc->state);
1001 crtc->state = NULL;
1002
1003 state = kzalloc(sizeof(*state), GFP_KERNEL);
332bbe70 1004 if (state) {
ca915b10 1005 crtc->state = &state->base;
332bbe70
TR		 1006 crtc->state->crtc = crtc;
1007 }
31930d4d
TR		 1008
1009 drm_crtc_vblank_reset(crtc);
ca915b10
TR		 1010}
1011
1012static struct drm_crtc_state *
1013tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1014{
1015 struct tegra_dc_state *state = to_dc_state(crtc->state);
1016 struct tegra_dc_state *copy;
1017
3b59b7ac 1018 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
ca915b10
TR		 1019 if (!copy)
1020 return NULL;
1021
3b59b7ac
TR		 1022 __drm_atomic_helper_crtc_duplicate_state(crtc, &copy->base);
1023 copy->clk = state->clk;
1024 copy->pclk = state->pclk;
1025 copy->div = state->div;
1026 copy->planes = state->planes;
ca915b10
TR		 1027
1028 return &copy->base;
1029}
1030
1031static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1032 struct drm_crtc_state *state)
1033{
ec2dc6a0 1034 __drm_atomic_helper_crtc_destroy_state(state);
ca915b10
TR		 1035 kfree(state);
1036}
1037
d8f4a9ed 1038static const struct drm_crtc_funcs tegra_crtc_funcs = {
1503ca47 1039 .page_flip = drm_atomic_helper_page_flip,
74f48791 1040 .set_config = drm_atomic_helper_set_config,
f002abc1 1041 .destroy = tegra_dc_destroy,
ca915b10
TR		 1042 .reset = tegra_crtc_reset,
1043 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1044 .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
10437d9b
SG		 1045 .get_vblank_counter = tegra_dc_get_vblank_counter,
1046 .enable_vblank = tegra_dc_enable_vblank,
1047 .disable_vblank = tegra_dc_disable_vblank,
d8f4a9ed
TR		 1048};
1049
d8f4a9ed
TR		 1050static int tegra_dc_set_timings(struct tegra_dc *dc,
1051 struct drm_display_mode *mode)
1052{
0444c0ff
TR		 1053 unsigned int h_ref_to_sync = 1;
1054 unsigned int v_ref_to_sync = 1;
d8f4a9ed
TR		 1055 unsigned long value;
1056
1057 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1058
1059 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1060 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1061
1062 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1063 ((mode->hsync_end - mode->hsync_start) << 0);
1064 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1065
d8f4a9ed
TR		 1066 value = ((mode->vtotal - mode->vsync_end) << 16) |
1067 ((mode->htotal - mode->hsync_end) << 0);
40495089
LS		 1068 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1069
1070 value = ((mode->vsync_start - mode->vdisplay) << 16) |
1071 ((mode->hsync_start - mode->hdisplay) << 0);
d8f4a9ed
TR		 1072 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1073
1074 value = (mode->vdisplay << 16) | mode->hdisplay;
1075 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1076
1077 return 0;
1078}
1079
9d910b60
TR		 1080/**
1081 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1082 * state
1083 * @dc: display controller
1084 * @crtc_state: CRTC atomic state
1085 * @clk: parent clock for display controller
1086 * @pclk: pixel clock
1087 * @div: shift clock divider
1088 *
1089 * Returns:
1090 * 0 on success or a negative error-code on failure.
1091 */
ca915b10
TR		 1092int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1093 struct drm_crtc_state *crtc_state,
1094 struct clk *clk, unsigned long pclk,
1095 unsigned int div)
1096{
1097 struct tegra_dc_state *state = to_dc_state(crtc_state);
1098
d2982748
TR		 1099 if (!clk_has_parent(dc->clk, clk))
1100 return -EINVAL;
1101
ca915b10
TR		 1102 state->clk = clk;
1103 state->pclk = pclk;
1104 state->div = div;
1105
1106 return 0;
1107}
1108
76d59ed0
TR		 1109static void tegra_dc_commit_state(struct tegra_dc *dc,
1110 struct tegra_dc_state *state)
1111{
1112 u32 value;
1113 int err;
1114
1115 err = clk_set_parent(dc->clk, state->clk);
1116 if (err < 0)
1117 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1118
1119 /*
1120 * Outputs may not want to change the parent clock rate. This is only
1121 * relevant to Tegra20 where only a single display PLL is available.
1122 * Since that PLL would typically be used for HDMI, an internal LVDS
1123 * panel would need to be driven by some other clock such as PLL_P
1124 * which is shared with other peripherals. Changing the clock rate
1125 * should therefore be avoided.
1126 */
1127 if (state->pclk > 0) {
1128 err = clk_set_rate(state->clk, state->pclk);
1129 if (err < 0)
1130 dev_err(dc->dev,
1131 "failed to set clock rate to %lu Hz\n",
1132 state->pclk);
1133 }
1134
1135 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1136 state->div);
1137 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1138
1139 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1140 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
39e08aff
TR		 1141
1142 err = clk_set_rate(dc->clk, state->pclk);
1143 if (err < 0)
1144 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n",
1145 dc->clk, state->pclk, err);
76d59ed0
TR		 1146}
1147
003fc848
TR		 1148static void tegra_dc_stop(struct tegra_dc *dc)
1149{
1150 u32 value;
1151
1152 /* stop the display controller */
1153 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1154 value &= ~DISP_CTRL_MODE_MASK;
1155 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1156
1157 tegra_dc_commit(dc);
1158}
1159
1160static bool tegra_dc_idle(struct tegra_dc *dc)
1161{
1162 u32 value;
1163
1164 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1165
1166 return (value & DISP_CTRL_MODE_MASK) == 0;
1167}
1168
1169static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1170{
1171 timeout = jiffies + msecs_to_jiffies(timeout);
1172
1173 while (time_before(jiffies, timeout)) {
1174 if (tegra_dc_idle(dc))
1175 return 0;
1176
1177 usleep_range(1000, 2000);
1178 }
1179
1180 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1181 return -ETIMEDOUT;
1182}
1183
64581714
LP		 1184static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,
1185 struct drm_crtc_state *old_state)
003fc848
TR		 1186{
1187 struct tegra_dc *dc = to_tegra_dc(crtc);
1188 u32 value;
1189
1190 if (!tegra_dc_idle(dc)) {
1191 tegra_dc_stop(dc);
1192
1193 /*
1194 * Ignore the return value, there isn't anything useful to do
1195 * in case this fails.
1196 */
1197 tegra_dc_wait_idle(dc, 100);
1198 }
1199
1200 /*
1201 * This should really be part of the RGB encoder driver, but clearing
1202 * these bits has the side-effect of stopping the display controller.
1203 * When that happens no VBLANK interrupts will be raised. At the same
1204 * time the encoder is disabled before the display controller, so the
1205 * above code is always going to timeout waiting for the controller
1206 * to go idle.
1207 *
1208 * Given the close coupling between the RGB encoder and the display
1209 * controller doing it here is still kind of okay. None of the other
1210 * encoder drivers require these bits to be cleared.
1211 *
1212 * XXX: Perhaps given that the display controller is switched off at
1213 * this point anyway maybe clearing these bits isn't even useful for
1214 * the RGB encoder?
1215 */
1216 if (dc->rgb) {
1217 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1218 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1219 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1220 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1221 }
1222
1223 tegra_dc_stats_reset(&dc->stats);
1224 drm_crtc_vblank_off(crtc);
33a8eb8d
TR		 1225
1226 pm_runtime_put_sync(dc->dev);
003fc848
TR		 1227}
1228
0b20a0f8
LP		 1229static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
1230 struct drm_crtc_state *old_state)
d8f4a9ed 1231{
4aa3df71 1232 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
76d59ed0 1233 struct tegra_dc_state *state = to_dc_state(crtc->state);
d8f4a9ed 1234 struct tegra_dc *dc = to_tegra_dc(crtc);
dbb3f2f7 1235 u32 value;
d8f4a9ed 1236
33a8eb8d
TR		 1237 pm_runtime_get_sync(dc->dev);
1238
1239 /* initialize display controller */
1240 if (dc->syncpt) {
1241 u32 syncpt = host1x_syncpt_id(dc->syncpt);
1242
1243 value = SYNCPT_CNTRL_NO_STALL;
1244 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1245
1246 value = SYNCPT_VSYNC_ENABLE | syncpt;
1247 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1248 }
1249
1250 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1251 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1252 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1253
1254 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1255 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1256 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1257
1258 /* initialize timer */
1259 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1260 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1261 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1262
1263 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1264 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1265 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1266
1267 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1268 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1269 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1270
1271 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1272 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1273 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1274
1275 if (dc->soc->supports_border_color)
1276 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1277
1278 /* apply PLL and pixel clock changes */
76d59ed0
TR		 1279 tegra_dc_commit_state(dc, state);
1280
d8f4a9ed
TR		 1281 /* program display mode */
1282 tegra_dc_set_timings(dc, mode);
1283
8620fc62
TR		 1284 /* interlacing isn't supported yet, so disable it */
1285 if (dc->soc->supports_interlacing) {
1286 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1287 value &= ~INTERLACE_ENABLE;
1288 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1289 }
666cb873
TR		 1290
1291 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1292 value &= ~DISP_CTRL_MODE_MASK;
1293 value |= DISP_CTRL_MODE_C_DISPLAY;
1294 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1295
1296 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1297 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1298 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1299 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1300
1301 tegra_dc_commit(dc);
d8f4a9ed 1302
8ff64c17 1303 drm_crtc_vblank_on(crtc);
d8f4a9ed
TR		 1304}
1305
4aa3df71
TR		 1306static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
1307 struct drm_crtc_state *state)
1308{
1309 return 0;
1310}
1311
613d2b27
ML		 1312static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1313 struct drm_crtc_state *old_crtc_state)
4aa3df71 1314{
1503ca47
TR		 1315 struct tegra_dc *dc = to_tegra_dc(crtc);
1316
1317 if (crtc->state->event) {
1318 crtc->state->event->pipe = drm_crtc_index(crtc);
1319
1320 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1321
1322 dc->event = crtc->state->event;
1323 crtc->state->event = NULL;
1324 }
4aa3df71
TR		 1325}
1326
613d2b27
ML		 1327static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1328 struct drm_crtc_state *old_crtc_state)
4aa3df71 1329{
47802b09
TR		 1330 struct tegra_dc_state *state = to_dc_state(crtc->state);
1331 struct tegra_dc *dc = to_tegra_dc(crtc);
1332
1333 tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL);
1334 tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL);
4aa3df71
TR		 1335}
1336
d8f4a9ed 1337static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
4aa3df71
TR		 1338 .atomic_check = tegra_crtc_atomic_check,
1339 .atomic_begin = tegra_crtc_atomic_begin,
1340 .atomic_flush = tegra_crtc_atomic_flush,
0b20a0f8 1341 .atomic_enable = tegra_crtc_atomic_enable,
64581714 1342 .atomic_disable = tegra_crtc_atomic_disable,
d8f4a9ed
TR		 1343};
1344
6e5ff998 1345static irqreturn_t tegra_dc_irq(int irq, void *data)
d8f4a9ed
TR		 1346{
1347 struct tegra_dc *dc = data;
1348 unsigned long status;
1349
1350 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1351 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1352
1353 if (status & FRAME_END_INT) {
1354 /*
1355 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1356 */
791ddb1e 1357 dc->stats.frames++;
d8f4a9ed
TR		 1358 }
1359
1360 if (status & VBLANK_INT) {
1361 /*
1362 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1363 */
ed7dae58 1364 drm_crtc_handle_vblank(&dc->base);
3c03c46a 1365 tegra_dc_finish_page_flip(dc);
791ddb1e 1366 dc->stats.vblank++;
d8f4a9ed
TR		 1367 }
1368
1369 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1370 /*
1371 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1372 */
791ddb1e
TR		 1373 dc->stats.underflow++;
1374 }
1375
1376 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
1377 /*
1378 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
1379 */
1380 dc->stats.overflow++;
d8f4a9ed
TR		 1381 }
1382
1383 return IRQ_HANDLED;
1384}
1385
cf6824ac
TR		 1386#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1387
1388static const struct debugfs_reg32 tegra_dc_regs[] = {
1389 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT),
1390 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL),
1391 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR),
1392 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT),
1393 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL),
1394 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR),
1395 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT),
1396 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL),
1397 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR),
1398 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT),
1399 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL),
1400 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR),
1401 DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC),
1402 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0),
1403 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND),
1404 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE),
1405 DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL),
1406 DEBUGFS_REG32(DC_CMD_INT_STATUS),
1407 DEBUGFS_REG32(DC_CMD_INT_MASK),
1408 DEBUGFS_REG32(DC_CMD_INT_ENABLE),
1409 DEBUGFS_REG32(DC_CMD_INT_TYPE),
1410 DEBUGFS_REG32(DC_CMD_INT_POLARITY),
1411 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1),
1412 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2),
1413 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3),
1414 DEBUGFS_REG32(DC_CMD_STATE_ACCESS),
1415 DEBUGFS_REG32(DC_CMD_STATE_CONTROL),
1416 DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER),
1417 DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL),
1418 DEBUGFS_REG32(DC_COM_CRC_CONTROL),
1419 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM),
1420 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)),
1421 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)),
1422 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)),
1423 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)),
1424 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)),
1425 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)),
1426 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)),
1427 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)),
1428 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)),
1429 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)),
1430 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)),
1431 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)),
1432 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)),
1433 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)),
1434 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)),
1435 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)),
1436 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)),
1437 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)),
1438 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)),
1439 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)),
1440 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)),
1441 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)),
1442 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)),
1443 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)),
1444 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)),
1445 DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL),
1446 DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL),
1447 DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE),
1448 DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL),
1449 DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE),
1450 DEBUGFS_REG32(DC_COM_SPI_CONTROL),
1451 DEBUGFS_REG32(DC_COM_SPI_START_BYTE),
1452 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB),
1453 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD),
1454 DEBUGFS_REG32(DC_COM_HSPI_CS_DC),
1455 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A),
1456 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B),
1457 DEBUGFS_REG32(DC_COM_GPIO_CTRL),
1458 DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER),
1459 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED),
1460 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0),
1461 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1),
1462 DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS),
1463 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY),
1464 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER),
1465 DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS),
1466 DEBUGFS_REG32(DC_DISP_REF_TO_SYNC),
1467 DEBUGFS_REG32(DC_DISP_SYNC_WIDTH),
1468 DEBUGFS_REG32(DC_DISP_BACK_PORCH),
1469 DEBUGFS_REG32(DC_DISP_ACTIVE),
1470 DEBUGFS_REG32(DC_DISP_FRONT_PORCH),
1471 DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL),
1472 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A),
1473 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B),
1474 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C),
1475 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D),
1476 DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL),
1477 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A),
1478 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B),
1479 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C),
1480 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D),
1481 DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL),
1482 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A),
1483 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B),
1484 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C),
1485 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D),
1486 DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL),
1487 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A),
1488 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B),
1489 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C),
1490 DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL),
1491 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A),
1492 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B),
1493 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C),
1494 DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL),
1495 DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A),
1496 DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL),
1497 DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A),
1498 DEBUGFS_REG32(DC_DISP_M0_CONTROL),
1499 DEBUGFS_REG32(DC_DISP_M1_CONTROL),
1500 DEBUGFS_REG32(DC_DISP_DI_CONTROL),
1501 DEBUGFS_REG32(DC_DISP_PP_CONTROL),
1502 DEBUGFS_REG32(DC_DISP_PP_SELECT_A),
1503 DEBUGFS_REG32(DC_DISP_PP_SELECT_B),
1504 DEBUGFS_REG32(DC_DISP_PP_SELECT_C),
1505 DEBUGFS_REG32(DC_DISP_PP_SELECT_D),
1506 DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL),
1507 DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL),
1508 DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL),
1509 DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS),
1510 DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS),
1511 DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS),
1512 DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS),
1513 DEBUGFS_REG32(DC_DISP_BORDER_COLOR),
1514 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER),
1515 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER),
1516 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER),
1517 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER),
1518 DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND),
1519 DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND),
1520 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR),
1521 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS),
1522 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION),
1523 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS),
1524 DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL),
1525 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A),
1526 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B),
1527 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C),
1528 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D),
1529 DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL),
1530 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST),
1531 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST),
1532 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST),
1533 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST),
1534 DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL),
1535 DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL),
1536 DEBUGFS_REG32(DC_DISP_SD_CONTROL),
1537 DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF),
1538 DEBUGFS_REG32(DC_DISP_SD_LUT(0)),
1539 DEBUGFS_REG32(DC_DISP_SD_LUT(1)),
1540 DEBUGFS_REG32(DC_DISP_SD_LUT(2)),
1541 DEBUGFS_REG32(DC_DISP_SD_LUT(3)),
1542 DEBUGFS_REG32(DC_DISP_SD_LUT(4)),
1543 DEBUGFS_REG32(DC_DISP_SD_LUT(5)),
1544 DEBUGFS_REG32(DC_DISP_SD_LUT(6)),
1545 DEBUGFS_REG32(DC_DISP_SD_LUT(7)),
1546 DEBUGFS_REG32(DC_DISP_SD_LUT(8)),
1547 DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL),
1548 DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT),
1549 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)),
1550 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)),
1551 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)),
1552 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)),
1553 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)),
1554 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)),
1555 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)),
1556 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)),
1557 DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)),
1558 DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)),
1559 DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)),
1560 DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)),
1561 DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL),
1562 DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES),
1563 DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES),
1564 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI),
1565 DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL),
1566 DEBUGFS_REG32(DC_WIN_WIN_OPTIONS),
1567 DEBUGFS_REG32(DC_WIN_BYTE_SWAP),
1568 DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL),
1569 DEBUGFS_REG32(DC_WIN_COLOR_DEPTH),
1570 DEBUGFS_REG32(DC_WIN_POSITION),
1571 DEBUGFS_REG32(DC_WIN_SIZE),
1572 DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE),
1573 DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA),
1574 DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA),
1575 DEBUGFS_REG32(DC_WIN_DDA_INC),
1576 DEBUGFS_REG32(DC_WIN_LINE_STRIDE),
1577 DEBUGFS_REG32(DC_WIN_BUF_STRIDE),
1578 DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE),
1579 DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE),
1580 DEBUGFS_REG32(DC_WIN_DV_CONTROL),
1581 DEBUGFS_REG32(DC_WIN_BLEND_NOKEY),
1582 DEBUGFS_REG32(DC_WIN_BLEND_1WIN),
1583 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X),
1584 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y),
1585 DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY),
1586 DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL),
1587 DEBUGFS_REG32(DC_WINBUF_START_ADDR),
1588 DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS),
1589 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U),
1590 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS),
1591 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V),
1592 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS),
1593 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET),
1594 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS),
1595 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET),
1596 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS),
1597 DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS),
1598 DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS),
1599 DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS),
1600 DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS),
1601};
1602
d8f4a9ed
TR		 1603static int tegra_dc_show_regs(struct seq_file *s, void *data)
1604{
1605 struct drm_info_node *node = s->private;
1606 struct tegra_dc *dc = node->info_ent->data;
cf6824ac 1607 unsigned int i;
003fc848
TR		 1608 int err = 0;
1609
99612b27 1610 drm_modeset_lock(&dc->base.mutex, NULL);
003fc848
TR		 1611
1612 if (!dc->base.state->active) {
1613 err = -EBUSY;
1614 goto unlock;
1615 }
d8f4a9ed 1616
cf6824ac
TR		 1617 for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) {
1618 unsigned int offset = tegra_dc_regs[i].offset;
1619
1620 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name,
1621 offset, tegra_dc_readl(dc, offset));
1622 }
d8f4a9ed 1623
003fc848 1624unlock:
99612b27 1625 drm_modeset_unlock(&dc->base.mutex);
003fc848 1626 return err;
d8f4a9ed
TR		 1627}
1628
6ca1f62f
TR		 1629static int tegra_dc_show_crc(struct seq_file *s, void *data)
1630{
1631 struct drm_info_node *node = s->private;
1632 struct tegra_dc *dc = node->info_ent->data;
003fc848 1633 int err = 0;
6ca1f62f
TR		 1634 u32 value;
1635
99612b27 1636 drm_modeset_lock(&dc->base.mutex, NULL);
003fc848
TR		 1637
1638 if (!dc->base.state->active) {
1639 err = -EBUSY;
1640 goto unlock;
1641 }
1642
6ca1f62f
TR		 1643 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1644 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1645 tegra_dc_commit(dc);
1646
1647 drm_crtc_wait_one_vblank(&dc->base);
1648 drm_crtc_wait_one_vblank(&dc->base);
1649
1650 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1651 seq_printf(s, "%08x\n", value);
1652
1653 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1654
003fc848 1655unlock:
99612b27 1656 drm_modeset_unlock(&dc->base.mutex);
003fc848 1657 return err;
6ca1f62f
TR		 1658}
1659
791ddb1e
TR		 1660static int tegra_dc_show_stats(struct seq_file *s, void *data)
1661{
1662 struct drm_info_node *node = s->private;
1663 struct tegra_dc *dc = node->info_ent->data;
1664
1665 seq_printf(s, "frames: %lu\n", dc->stats.frames);
1666 seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1667 seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1668 seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1669
d8f4a9ed
TR		 1670 return 0;
1671}
1672
1673static struct drm_info_list debugfs_files[] = {
1674 { "regs", tegra_dc_show_regs, 0, NULL },
6ca1f62f 1675 { "crc", tegra_dc_show_crc, 0, NULL },
791ddb1e 1676 { "stats", tegra_dc_show_stats, 0, NULL },
d8f4a9ed
TR		 1677};
1678
1679static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1680{
1681 unsigned int i;
1682 char *name;
1683 int err;
1684
1685 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1686 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1687 kfree(name);
1688
1689 if (!dc->debugfs)
1690 return -ENOMEM;
1691
1692 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1693 GFP_KERNEL);
1694 if (!dc->debugfs_files) {
1695 err = -ENOMEM;
1696 goto remove;
1697 }
1698
1699 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1700 dc->debugfs_files[i].data = dc;
1701
1702 err = drm_debugfs_create_files(dc->debugfs_files,
1703 ARRAY_SIZE(debugfs_files),
1704 dc->debugfs, minor);
1705 if (err < 0)
1706 goto free;
1707
1708 dc->minor = minor;
1709
1710 return 0;
1711
1712free:
1713 kfree(dc->debugfs_files);
1714 dc->debugfs_files = NULL;
1715remove:
1716 debugfs_remove(dc->debugfs);
1717 dc->debugfs = NULL;
1718
1719 return err;
1720}
1721
1722static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1723{
1724 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1725 dc->minor);
1726 dc->minor = NULL;
1727
1728 kfree(dc->debugfs_files);
1729 dc->debugfs_files = NULL;
1730
1731 debugfs_remove(dc->debugfs);
1732 dc->debugfs = NULL;
1733
1734 return 0;
1735}
1736
53fa7f72 1737static int tegra_dc_init(struct host1x_client *client)
d8f4a9ed 1738{
9910f5c4 1739 struct drm_device *drm = dev_get_drvdata(client->parent);
2bcdcbfa 1740 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
776dc384 1741 struct tegra_dc *dc = host1x_client_to_dc(client);
d1f3e1e0 1742 struct tegra_drm *tegra = drm->dev_private;
c7679306
TR		 1743 struct drm_plane *primary = NULL;
1744 struct drm_plane *cursor = NULL;
d8f4a9ed
TR		 1745 int err;
1746
617dd7cc 1747 dc->syncpt = host1x_syncpt_request(client, flags);
2bcdcbfa
TR		 1748 if (!dc->syncpt)
1749 dev_warn(dc->dev, "failed to allocate syncpoint\n");
1750
df06b759
TR		 1751 if (tegra->domain) {
1752 err = iommu_attach_device(tegra->domain, dc->dev);
1753 if (err < 0) {
1754 dev_err(dc->dev, "failed to attach to domain: %d\n",
1755 err);
1756 return err;
1757 }
1758
1759 dc->domain = tegra->domain;
1760 }
1761
c7679306
TR		 1762 primary = tegra_dc_primary_plane_create(drm, dc);
1763 if (IS_ERR(primary)) {
1764 err = PTR_ERR(primary);
1765 goto cleanup;
1766 }
1767
1768 if (dc->soc->supports_cursor) {
1769 cursor = tegra_dc_cursor_plane_create(drm, dc);
1770 if (IS_ERR(cursor)) {
1771 err = PTR_ERR(cursor);
1772 goto cleanup;
1773 }
1774 }
1775
1776 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
f9882876 1777 &tegra_crtc_funcs, NULL);
c7679306
TR		 1778 if (err < 0)
1779 goto cleanup;
1780
d8f4a9ed
TR		 1781 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1782
d1f3e1e0
TR		 1783 /*
1784 * Keep track of the minimum pitch alignment across all display
1785 * controllers.
1786 */
1787 if (dc->soc->pitch_align > tegra->pitch_align)
1788 tegra->pitch_align = dc->soc->pitch_align;
1789
9910f5c4 1790 err = tegra_dc_rgb_init(drm, dc);
d8f4a9ed
TR		 1791 if (err < 0 && err != -ENODEV) {
1792 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
c7679306 1793 goto cleanup;
d8f4a9ed
TR		 1794 }
1795
9910f5c4 1796 err = tegra_dc_add_planes(drm, dc);
f34bc787 1797 if (err < 0)
c7679306 1798 goto cleanup;
f34bc787 1799
d8f4a9ed 1800 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
9910f5c4 1801 err = tegra_dc_debugfs_init(dc, drm->primary);
d8f4a9ed
TR		 1802 if (err < 0)
1803 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1804 }
1805
6e5ff998 1806 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
d8f4a9ed
TR		 1807 dev_name(dc->dev), dc);
1808 if (err < 0) {
1809 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1810 err);
c7679306 1811 goto cleanup;
d8f4a9ed
TR		 1812 }
1813
1814 return 0;
c7679306
TR		 1815
1816cleanup:
1817 if (cursor)
1818 drm_plane_cleanup(cursor);
1819
1820 if (primary)
1821 drm_plane_cleanup(primary);
1822
1823 if (tegra->domain) {
1824 iommu_detach_device(tegra->domain, dc->dev);
1825 dc->domain = NULL;
1826 }
1827
1828 return err;
d8f4a9ed
TR		 1829}
1830
53fa7f72 1831static int tegra_dc_exit(struct host1x_client *client)
d8f4a9ed 1832{
776dc384 1833 struct tegra_dc *dc = host1x_client_to_dc(client);
d8f4a9ed
TR		 1834 int err;
1835
1836 devm_free_irq(dc->dev, dc->irq, dc);
1837
1838 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1839 err = tegra_dc_debugfs_exit(dc);
1840 if (err < 0)
1841 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1842 }
1843
1844 err = tegra_dc_rgb_exit(dc);
1845 if (err) {
1846 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1847 return err;
1848 }
1849
df06b759
TR		 1850 if (dc->domain) {
1851 iommu_detach_device(dc->domain, dc->dev);
1852 dc->domain = NULL;
1853 }
1854
2bcdcbfa
TR		 1855 host1x_syncpt_free(dc->syncpt);
1856
d8f4a9ed
TR		 1857 return 0;
1858}
1859
1860static const struct host1x_client_ops dc_client_ops = {
53fa7f72
TR		 1861 .init = tegra_dc_init,
1862 .exit = tegra_dc_exit,
d8f4a9ed
TR		 1863};
1864
8620fc62 1865static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
42d0659b 1866 .supports_border_color = true,
8620fc62 1867 .supports_interlacing = false,
e687651b 1868 .supports_cursor = false,
c134f019 1869 .supports_block_linear = false,
d1f3e1e0 1870 .pitch_align = 8,
9c012700 1871 .has_powergate = false,
6ac1571b 1872 .broken_reset = true,
8620fc62
TR		 1873};
1874
1875static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
42d0659b 1876 .supports_border_color = true,
8620fc62 1877 .supports_interlacing = false,
e687651b 1878 .supports_cursor = false,
c134f019 1879 .supports_block_linear = false,
d1f3e1e0 1880 .pitch_align = 8,
9c012700 1881 .has_powergate = false,
6ac1571b 1882 .broken_reset = false,
d1f3e1e0
TR		 1883};
1884
1885static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
42d0659b 1886 .supports_border_color = true,
d1f3e1e0
TR		 1887 .supports_interlacing = false,
1888 .supports_cursor = false,
1889 .supports_block_linear = false,
1890 .pitch_align = 64,
9c012700 1891 .has_powergate = true,
6ac1571b 1892 .broken_reset = false,
8620fc62
TR		 1893};
1894
1895static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
42d0659b 1896 .supports_border_color = false,
8620fc62 1897 .supports_interlacing = true,
e687651b 1898 .supports_cursor = true,
c134f019 1899 .supports_block_linear = true,
d1f3e1e0 1900 .pitch_align = 64,
9c012700 1901 .has_powergate = true,
6ac1571b 1902 .broken_reset = false,
8620fc62
TR		 1903};
1904
5b4f516f
TR		 1905static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
1906 .supports_border_color = false,
1907 .supports_interlacing = true,
1908 .supports_cursor = true,
1909 .supports_block_linear = true,
1910 .pitch_align = 64,
1911 .has_powergate = true,
6ac1571b 1912 .broken_reset = false,
5b4f516f
TR		 1913};
1914
8620fc62
TR		 1915static const struct of_device_id tegra_dc_of_match[] = {
1916 {
5b4f516f
TR		 1917 .compatible = "nvidia,tegra210-dc",
1918 .data = &tegra210_dc_soc_info,
1919 }, {
8620fc62
TR		 1920 .compatible = "nvidia,tegra124-dc",
1921 .data = &tegra124_dc_soc_info,
9c012700
TR		 1922 }, {
1923 .compatible = "nvidia,tegra114-dc",
1924 .data = &tegra114_dc_soc_info,
8620fc62
TR		 1925 }, {
1926 .compatible = "nvidia,tegra30-dc",
1927 .data = &tegra30_dc_soc_info,
1928 }, {
1929 .compatible = "nvidia,tegra20-dc",
1930 .data = &tegra20_dc_soc_info,
1931 }, {
1932 /* sentinel */
1933 }
1934};
ef70728c 1935MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
8620fc62 1936
13411ddd
TR		 1937static int tegra_dc_parse_dt(struct tegra_dc *dc)
1938{
1939 struct device_node *np;
1940 u32 value = 0;
1941 int err;
1942
1943 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1944 if (err < 0) {
1945 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1946
1947 /*
1948 * If the nvidia,head property isn't present, try to find the
1949 * correct head number by looking up the position of this
1950 * display controller's node within the device tree. Assuming
1951 * that the nodes are ordered properly in the DTS file and
1952 * that the translation into a flattened device tree blob
1953 * preserves that ordering this will actually yield the right
1954 * head number.
1955 *
1956 * If those assumptions don't hold, this will still work for
1957 * cases where only a single display controller is used.
1958 */
1959 for_each_matching_node(np, tegra_dc_of_match) {
cf6b1744
JL		 1960 if (np == dc->dev->of_node) {
1961 of_node_put(np);
13411ddd 1962 break;
cf6b1744 1963 }
13411ddd
TR		 1964
1965 value++;
1966 }
1967 }
1968
1969 dc->pipe = value;
1970
1971 return 0;
1972}
1973
d8f4a9ed
TR		 1974static int tegra_dc_probe(struct platform_device *pdev)
1975{
d8f4a9ed
TR		 1976 struct resource *regs;
1977 struct tegra_dc *dc;
1978 int err;
1979
1980 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1981 if (!dc)
1982 return -ENOMEM;
1983
b9ff7aea 1984 dc->soc = of_device_get_match_data(&pdev->dev);
8620fc62 1985
6e5ff998 1986 spin_lock_init(&dc->lock);
d8f4a9ed
TR		 1987 INIT_LIST_HEAD(&dc->list);
1988 dc->dev = &pdev->dev;
1989
13411ddd
TR		 1990 err = tegra_dc_parse_dt(dc);
1991 if (err < 0)
1992 return err;
1993
d8f4a9ed
TR		 1994 dc->clk = devm_clk_get(&pdev->dev, NULL);
1995 if (IS_ERR(dc->clk)) {
1996 dev_err(&pdev->dev, "failed to get clock\n");
1997 return PTR_ERR(dc->clk);
1998 }
1999
ca48080a
SW		 2000 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
2001 if (IS_ERR(dc->rst)) {
2002 dev_err(&pdev->dev, "failed to get reset\n");
2003 return PTR_ERR(dc->rst);
2004 }
2005
a2f2f740
TR		 2006 /* assert reset and disable clock */
2007 if (!dc->soc->broken_reset) {
2008 err = clk_prepare_enable(dc->clk);
2009 if (err < 0)
2010 return err;
2011
2012 usleep_range(2000, 4000);
2013
2014 err = reset_control_assert(dc->rst);
2015 if (err < 0)
2016 return err;
2017
2018 usleep_range(2000, 4000);
2019
2020 clk_disable_unprepare(dc->clk);
2021 }
33a8eb8d 2022
9c012700
TR		 2023 if (dc->soc->has_powergate) {
2024 if (dc->pipe == 0)
2025 dc->powergate = TEGRA_POWERGATE_DIS;
2026 else
2027 dc->powergate = TEGRA_POWERGATE_DISB;
2028
33a8eb8d 2029 tegra_powergate_power_off(dc->powergate);
9c012700 2030 }
d8f4a9ed
TR		 2031
2032 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d4ed6025
TR		 2033 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
2034 if (IS_ERR(dc->regs))
2035 return PTR_ERR(dc->regs);
d8f4a9ed
TR		 2036
2037 dc->irq = platform_get_irq(pdev, 0);
2038 if (dc->irq < 0) {
2039 dev_err(&pdev->dev, "failed to get IRQ\n");
2040 return -ENXIO;
2041 }
2042
d8f4a9ed
TR		 2043 err = tegra_dc_rgb_probe(dc);
2044 if (err < 0 && err != -ENODEV) {
2045 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
2046 return err;
2047 }
2048
33a8eb8d
TR		 2049 platform_set_drvdata(pdev, dc);
2050 pm_runtime_enable(&pdev->dev);
2051
2052 INIT_LIST_HEAD(&dc->client.list);
2053 dc->client.ops = &dc_client_ops;
2054 dc->client.dev = &pdev->dev;
2055
776dc384 2056 err = host1x_client_register(&dc->client);
d8f4a9ed
TR		 2057 if (err < 0) {
2058 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2059 err);
2060 return err;
2061 }
2062
d8f4a9ed
TR		 2063 return 0;
2064}
2065
2066static int tegra_dc_remove(struct platform_device *pdev)
2067{
d8f4a9ed
TR		 2068 struct tegra_dc *dc = platform_get_drvdata(pdev);
2069 int err;
2070
776dc384 2071 err = host1x_client_unregister(&dc->client);
d8f4a9ed
TR		 2072 if (err < 0) {
2073 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2074 err);
2075 return err;
2076 }
2077
59d29c0e
TR		 2078 err = tegra_dc_rgb_remove(dc);
2079 if (err < 0) {
2080 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2081 return err;
2082 }
2083
33a8eb8d
TR		 2084 pm_runtime_disable(&pdev->dev);
2085
2086 return 0;
2087}
2088
2089#ifdef CONFIG_PM
2090static int tegra_dc_suspend(struct device *dev)
2091{
2092 struct tegra_dc *dc = dev_get_drvdata(dev);
2093 int err;
2094
6ac1571b
DO		 2095 if (!dc->soc->broken_reset) {
2096 err = reset_control_assert(dc->rst);
2097 if (err < 0) {
2098 dev_err(dev, "failed to assert reset: %d\n", err);
2099 return err;
2100 }
33a8eb8d 2101 }
9c012700
TR		 2102
2103 if (dc->soc->has_powergate)
2104 tegra_powergate_power_off(dc->powergate);
2105
d8f4a9ed
TR		 2106 clk_disable_unprepare(dc->clk);
2107
2108 return 0;
2109}
2110
33a8eb8d
TR		 2111static int tegra_dc_resume(struct device *dev)
2112{
2113 struct tegra_dc *dc = dev_get_drvdata(dev);
2114 int err;
2115
2116 if (dc->soc->has_powergate) {
2117 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2118 dc->rst);
2119 if (err < 0) {
2120 dev_err(dev, "failed to power partition: %d\n", err);
2121 return err;
2122 }
2123 } else {
2124 err = clk_prepare_enable(dc->clk);
2125 if (err < 0) {
2126 dev_err(dev, "failed to enable clock: %d\n", err);
2127 return err;
2128 }
2129
6ac1571b
DO		 2130 if (!dc->soc->broken_reset) {
2131 err = reset_control_deassert(dc->rst);
2132 if (err < 0) {
2133 dev_err(dev,
2134 "failed to deassert reset: %d\n", err);
2135 return err;
2136 }
33a8eb8d
TR		 2137 }
2138 }
2139
2140 return 0;
2141}
2142#endif
2143
2144static const struct dev_pm_ops tegra_dc_pm_ops = {
2145 SET_RUNTIME_PM_OPS(tegra_dc_suspend, tegra_dc_resume, NULL)
2146};
2147
d8f4a9ed
TR		 2148struct platform_driver tegra_dc_driver = {
2149 .driver = {
2150 .name = "tegra-dc",
d8f4a9ed 2151 .of_match_table = tegra_dc_of_match,
33a8eb8d 2152 .pm = &tegra_dc_pm_ops,
d8f4a9ed
TR		 2153 },
2154 .probe = tegra_dc_probe,
2155 .remove = tegra_dc_remove,
2156};
Linux 6.x block layer and io_uring tree(s)