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drm/tegra: dc: Simplify atomic plane helper functions
[linux-2.6-block.git] / drivers / gpu / drm / tegra / dc.c
CommitLineData
d8f4a9ed
TR		 1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
9eb9b220 11#include <linux/debugfs.h>
df06b759 12#include <linux/iommu.h>
b9ff7aea 13#include <linux/of_device.h>
33a8eb8d 14#include <linux/pm_runtime.h>
ca48080a 15#include <linux/reset.h>
d8f4a9ed 16
9c012700
TR		 17#include <soc/tegra/pmc.h>
18
de2ba664
AM		 19#include "dc.h"
20#include "drm.h"
21#include "gem.h"
d8f4a9ed 22
9d44189f 23#include <drm/drm_atomic.h>
4aa3df71 24#include <drm/drm_atomic_helper.h>
3cb9ae4f
DV		 25#include <drm/drm_plane_helper.h>
26
f34bc787
TR		 27struct tegra_plane {
28 struct drm_plane base;
29 unsigned int index;
d8f4a9ed
TR		 30};
31
f34bc787
TR		 32static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
33{
34 return container_of(plane, struct tegra_plane, base);
35}
36
ca915b10
TR		 37struct tegra_dc_state {
38 struct drm_crtc_state base;
39
40 struct clk *clk;
41 unsigned long pclk;
42 unsigned int div;
47802b09
TR		 43
44 u32 planes;
ca915b10
TR		 45};
46
47static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state)
48{
49 if (state)
50 return container_of(state, struct tegra_dc_state, base);
51
52 return NULL;
53}
54
8f604f8c
TR		 55struct tegra_plane_state {
56 struct drm_plane_state base;
57
58 struct tegra_bo_tiling tiling;
59 u32 format;
60 u32 swap;
61};
62
63static inline struct tegra_plane_state *
64to_tegra_plane_state(struct drm_plane_state *state)
65{
66 if (state)
67 return container_of(state, struct tegra_plane_state, base);
68
69 return NULL;
70}
71
791ddb1e
TR		 72static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
73{
74 stats->frames = 0;
75 stats->vblank = 0;
76 stats->underflow = 0;
77 stats->overflow = 0;
78}
79
86df256f
TR		 80/*
81 * Reads the active copy of a register. This takes the dc->lock spinlock to
82 * prevent races with the VBLANK processing which also needs access to the
83 * active copy of some registers.
84 */
85static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
86{
87 unsigned long flags;
88 u32 value;
89
90 spin_lock_irqsave(&dc->lock, flags);
91
92 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
93 value = tegra_dc_readl(dc, offset);
94 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
95
96 spin_unlock_irqrestore(&dc->lock, flags);
97 return value;
98}
99
d700ba7a
TR		 100/*
101 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
102 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
103 * Latching happens mmediately if the display controller is in STOP mode or
104 * on the next frame boundary otherwise.
105 *
106 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
107 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
108 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
109 * into the ACTIVE copy, either immediately if the display controller is in
110 * STOP mode, or at the next frame boundary otherwise.
111 */
62b9e063 112void tegra_dc_commit(struct tegra_dc *dc)
205d48ed
TR		 113{
114 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
115 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
116}
117
8f604f8c 118static int tegra_dc_format(u32 fourcc, u32 *format, u32 *swap)
10288eea
TR		 119{
120 /* assume no swapping of fetched data */
121 if (swap)
122 *swap = BYTE_SWAP_NOSWAP;
123
8f604f8c 124 switch (fourcc) {
10288eea 125 case DRM_FORMAT_XBGR8888:
8f604f8c
TR		 126 *format = WIN_COLOR_DEPTH_R8G8B8A8;
127 break;
10288eea
TR		 128
129 case DRM_FORMAT_XRGB8888:
8f604f8c
TR		 130 *format = WIN_COLOR_DEPTH_B8G8R8A8;
131 break;
10288eea
TR		 132
133 case DRM_FORMAT_RGB565:
8f604f8c
TR		 134 *format = WIN_COLOR_DEPTH_B5G6R5;
135 break;
10288eea
TR		 136
137 case DRM_FORMAT_UYVY:
8f604f8c
TR		 138 *format = WIN_COLOR_DEPTH_YCbCr422;
139 break;
10288eea
TR		 140
141 case DRM_FORMAT_YUYV:
142 if (swap)
143 *swap = BYTE_SWAP_SWAP2;
144
8f604f8c
TR		 145 *format = WIN_COLOR_DEPTH_YCbCr422;
146 break;
10288eea
TR		 147
148 case DRM_FORMAT_YUV420:
8f604f8c
TR		 149 *format = WIN_COLOR_DEPTH_YCbCr420P;
150 break;
10288eea
TR		 151
152 case DRM_FORMAT_YUV422:
8f604f8c
TR		 153 *format = WIN_COLOR_DEPTH_YCbCr422P;
154 break;
10288eea
TR		 155
156 default:
8f604f8c 157 return -EINVAL;
10288eea
TR		 158 }
159
8f604f8c 160 return 0;
10288eea
TR		 161}
162
163static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
164{
165 switch (format) {
166 case WIN_COLOR_DEPTH_YCbCr422:
167 case WIN_COLOR_DEPTH_YUV422:
168 if (planar)
169 *planar = false;
170
171 return true;
172
173 case WIN_COLOR_DEPTH_YCbCr420P:
174 case WIN_COLOR_DEPTH_YUV420P:
175 case WIN_COLOR_DEPTH_YCbCr422P:
176 case WIN_COLOR_DEPTH_YUV422P:
177 case WIN_COLOR_DEPTH_YCbCr422R:
178 case WIN_COLOR_DEPTH_YUV422R:
179 case WIN_COLOR_DEPTH_YCbCr422RA:
180 case WIN_COLOR_DEPTH_YUV422RA:
181 if (planar)
182 *planar = true;
183
184 return true;
185 }
186
fb35c6b6
TR		 187 if (planar)
188 *planar = false;
189
10288eea
TR		 190 return false;
191}
192
193static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
194 unsigned int bpp)
195{
196 fixed20_12 outf = dfixed_init(out);
197 fixed20_12 inf = dfixed_init(in);
198 u32 dda_inc;
199 int max;
200
201 if (v)
202 max = 15;
203 else {
204 switch (bpp) {
205 case 2:
206 max = 8;
207 break;
208
209 default:
210 WARN_ON_ONCE(1);
211 /* fallthrough */
212 case 4:
213 max = 4;
214 break;
215 }
216 }
217
218 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
219 inf.full -= dfixed_const(1);
220
221 dda_inc = dfixed_div(inf, outf);
222 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
223
224 return dda_inc;
225}
226
227static inline u32 compute_initial_dda(unsigned int in)
228{
229 fixed20_12 inf = dfixed_init(in);
230 return dfixed_frac(inf);
231}
232
4aa3df71
TR		 233static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
234 const struct tegra_dc_window *window)
10288eea
TR		 235{
236 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
93396d0f 237 unsigned long value, flags;
10288eea
TR		 238 bool yuv, planar;
239
240 /*
241 * For YUV planar modes, the number of bytes per pixel takes into
242 * account only the luma component and therefore is 1.
243 */
244 yuv = tegra_dc_format_is_yuv(window->format, &planar);
245 if (!yuv)
246 bpp = window->bits_per_pixel / 8;
247 else
248 bpp = planar ? 1 : 2;
249
93396d0f
SP		 250 spin_lock_irqsave(&dc->lock, flags);
251
10288eea
TR		 252 value = WINDOW_A_SELECT << index;
253 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
254
255 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
256 tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
257
258 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
259 tegra_dc_writel(dc, value, DC_WIN_POSITION);
260
261 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
262 tegra_dc_writel(dc, value, DC_WIN_SIZE);
263
264 h_offset = window->src.x * bpp;
265 v_offset = window->src.y;
266 h_size = window->src.w * bpp;
267 v_size = window->src.h;
268
269 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
270 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
271
272 /*
273 * For DDA computations the number of bytes per pixel for YUV planar
274 * modes needs to take into account all Y, U and V components.
275 */
276 if (yuv && planar)
277 bpp = 2;
278
279 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
280 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
281
282 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
283 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
284
285 h_dda = compute_initial_dda(window->src.x);
286 v_dda = compute_initial_dda(window->src.y);
287
288 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
289 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
290
291 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
292 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
293
294 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
295
296 if (yuv && planar) {
297 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
298 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
299 value = window->stride[1] << 16 | window->stride[0];
300 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
301 } else {
302 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
303 }
304
305 if (window->bottom_up)
306 v_offset += window->src.h - 1;
307
308 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
309 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
310
c134f019
TR		 311 if (dc->soc->supports_block_linear) {
312 unsigned long height = window->tiling.value;
313
314 switch (window->tiling.mode) {
315 case TEGRA_BO_TILING_MODE_PITCH:
316 value = DC_WINBUF_SURFACE_KIND_PITCH;
317 break;
318
319 case TEGRA_BO_TILING_MODE_TILED:
320 value = DC_WINBUF_SURFACE_KIND_TILED;
321 break;
322
323 case TEGRA_BO_TILING_MODE_BLOCK:
324 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
325 DC_WINBUF_SURFACE_KIND_BLOCK;
326 break;
327 }
328
329 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
10288eea 330 } else {
c134f019
TR		 331 switch (window->tiling.mode) {
332 case TEGRA_BO_TILING_MODE_PITCH:
333 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
334 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
335 break;
10288eea 336
c134f019
TR		 337 case TEGRA_BO_TILING_MODE_TILED:
338 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
339 DC_WIN_BUFFER_ADDR_MODE_TILE;
340 break;
341
342 case TEGRA_BO_TILING_MODE_BLOCK:
4aa3df71
TR		 343 /*
344 * No need to handle this here because ->atomic_check
345 * will already have filtered it out.
346 */
347 break;
c134f019
TR		 348 }
349
350 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
351 }
10288eea
TR		 352
353 value = WIN_ENABLE;
354
355 if (yuv) {
356 /* setup default colorspace conversion coefficients */
357 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
358 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
359 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
360 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
361 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
362 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
363 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
364 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
365
366 value |= CSC_ENABLE;
367 } else if (window->bits_per_pixel < 24) {
368 value |= COLOR_EXPAND;
369 }
370
371 if (window->bottom_up)
372 value |= V_DIRECTION;
373
374 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
375
376 /*
377 * Disable blending and assume Window A is the bottom-most window,
378 * Window C is the top-most window and Window B is in the middle.
379 */
380 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
381 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
382
383 switch (index) {
384 case 0:
385 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
386 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
387 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
388 break;
389
390 case 1:
391 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
392 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
393 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
394 break;
395
396 case 2:
397 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
398 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
399 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
400 break;
401 }
402
93396d0f 403 spin_unlock_irqrestore(&dc->lock, flags);
c7679306
TR		 404}
405
406static void tegra_plane_destroy(struct drm_plane *plane)
407{
408 struct tegra_plane *p = to_tegra_plane(plane);
409
410 drm_plane_cleanup(plane);
411 kfree(p);
412}
413
414static const u32 tegra_primary_plane_formats[] = {
415 DRM_FORMAT_XBGR8888,
416 DRM_FORMAT_XRGB8888,
417 DRM_FORMAT_RGB565,
418};
419
4aa3df71 420static void tegra_primary_plane_destroy(struct drm_plane *plane)
c7679306 421{
4aa3df71
TR		 422 tegra_plane_destroy(plane);
423}
424
8f604f8c
TR		 425static void tegra_plane_reset(struct drm_plane *plane)
426{
427 struct tegra_plane_state *state;
428
3b59b7ac 429 if (plane->state)
2f701695 430 __drm_atomic_helper_plane_destroy_state(plane->state);
8f604f8c
TR		 431
432 kfree(plane->state);
433 plane->state = NULL;
434
435 state = kzalloc(sizeof(*state), GFP_KERNEL);
436 if (state) {
437 plane->state = &state->base;
438 plane->state->plane = plane;
439 }
440}
441
442static struct drm_plane_state *tegra_plane_atomic_duplicate_state(struct drm_plane *plane)
443{
444 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
445 struct tegra_plane_state *copy;
446
3b59b7ac 447 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
8f604f8c
TR		 448 if (!copy)
449 return NULL;
450
3b59b7ac
TR		 451 __drm_atomic_helper_plane_duplicate_state(plane, &copy->base);
452 copy->tiling = state->tiling;
453 copy->format = state->format;
454 copy->swap = state->swap;
8f604f8c
TR		 455
456 return &copy->base;
457}
458
459static void tegra_plane_atomic_destroy_state(struct drm_plane *plane,
460 struct drm_plane_state *state)
461{
2f701695 462 __drm_atomic_helper_plane_destroy_state(state);
8f604f8c
TR		 463 kfree(state);
464}
465
4aa3df71 466static const struct drm_plane_funcs tegra_primary_plane_funcs = {
07866963
TR		 467 .update_plane = drm_atomic_helper_update_plane,
468 .disable_plane = drm_atomic_helper_disable_plane,
4aa3df71 469 .destroy = tegra_primary_plane_destroy,
8f604f8c
TR		 470 .reset = tegra_plane_reset,
471 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
472 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
4aa3df71
TR		 473};
474
47802b09
TR		 475static int tegra_plane_state_add(struct tegra_plane *plane,
476 struct drm_plane_state *state)
477{
478 struct drm_crtc_state *crtc_state;
479 struct tegra_dc_state *tegra;
7d205857
DO		 480 struct drm_rect clip;
481 int err;
47802b09
TR		 482
483 /* Propagate errors from allocation or locking failures. */
484 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
485 if (IS_ERR(crtc_state))
486 return PTR_ERR(crtc_state);
487
7d205857
DO		 488 clip.x1 = 0;
489 clip.y1 = 0;
490 clip.x2 = crtc_state->mode.hdisplay;
491 clip.y2 = crtc_state->mode.vdisplay;
492
493 /* Check plane state for visibility and calculate clipping bounds */
494 err = drm_plane_helper_check_state(state, &clip, 0, INT_MAX,
495 true, true);
496 if (err < 0)
497 return err;
498
47802b09
TR		 499 tegra = to_dc_state(crtc_state);
500
501 tegra->planes |= WIN_A_ACT_REQ << plane->index;
502
503 return 0;
504}
505
4aa3df71
TR		 506static int tegra_plane_atomic_check(struct drm_plane *plane,
507 struct drm_plane_state *state)
508{
8f604f8c
TR		 509 struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
510 struct tegra_bo_tiling *tiling = &plane_state->tiling;
47802b09 511 struct tegra_plane *tegra = to_tegra_plane(plane);
4aa3df71 512 struct tegra_dc *dc = to_tegra_dc(state->crtc);
4aa3df71
TR		 513 int err;
514
515 /* no need for further checks if the plane is being disabled */
516 if (!state->crtc)
517 return 0;
518
438b74a5 519 err = tegra_dc_format(state->fb->format->format, &plane_state->format,
8f604f8c 520 &plane_state->swap);
4aa3df71
TR		 521 if (err < 0)
522 return err;
523
8f604f8c
TR		 524 err = tegra_fb_get_tiling(state->fb, tiling);
525 if (err < 0)
526 return err;
527
528 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
4aa3df71
TR		 529 !dc->soc->supports_block_linear) {
530 DRM_ERROR("hardware doesn't support block linear mode\n");
531 return -EINVAL;
532 }
533
534 /*
535 * Tegra doesn't support different strides for U and V planes so we
536 * error out if the user tries to display a framebuffer with such a
537 * configuration.
538 */
bcb0b461 539 if (state->fb->format->num_planes > 2) {
4aa3df71
TR		 540 if (state->fb->pitches[2] != state->fb->pitches[1]) {
541 DRM_ERROR("unsupported UV-plane configuration\n");
542 return -EINVAL;
543 }
544 }
545
47802b09
TR		 546 err = tegra_plane_state_add(tegra, state);
547 if (err < 0)
548 return err;
549
4aa3df71
TR		 550 return 0;
551}
552
a4bfa096
TR		 553static void tegra_plane_atomic_disable(struct drm_plane *plane,
554 struct drm_plane_state *old_state)
80d3eef1 555{
a4bfa096
TR		 556 struct tegra_dc *dc = to_tegra_dc(old_state->crtc);
557 struct tegra_plane *p = to_tegra_plane(plane);
80d3eef1
DO		 558 unsigned long flags;
559 u32 value;
560
a4bfa096
TR		 561 /* rien ne va plus */
562 if (!old_state || !old_state->crtc)
563 return;
564
80d3eef1
DO		 565 spin_lock_irqsave(&dc->lock, flags);
566
a4bfa096 567 value = WINDOW_A_SELECT << p->index;
80d3eef1
DO		 568 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
569
570 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
571 value &= ~WIN_ENABLE;
572 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
573
574 spin_unlock_irqrestore(&dc->lock, flags);
575}
576
4aa3df71
TR		 577static void tegra_plane_atomic_update(struct drm_plane *plane,
578 struct drm_plane_state *old_state)
579{
8f604f8c 580 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
4aa3df71
TR		 581 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
582 struct drm_framebuffer *fb = plane->state->fb;
c7679306 583 struct tegra_plane *p = to_tegra_plane(plane);
c7679306 584 struct tegra_dc_window window;
4aa3df71 585 unsigned int i;
c7679306 586
4aa3df71
TR		 587 /* rien ne va plus */
588 if (!plane->state->crtc || !plane->state->fb)
589 return;
590
80d3eef1 591 if (!plane->state->visible)
a4bfa096 592 return tegra_plane_atomic_disable(plane, old_state);
80d3eef1 593
c7679306 594 memset(&window, 0, sizeof(window));
7d205857
DO		 595 window.src.x = plane->state->src.x1 >> 16;
596 window.src.y = plane->state->src.y1 >> 16;
597 window.src.w = drm_rect_width(&plane->state->src) >> 16;
598 window.src.h = drm_rect_height(&plane->state->src) >> 16;
599 window.dst.x = plane->state->dst.x1;
600 window.dst.y = plane->state->dst.y1;
601 window.dst.w = drm_rect_width(&plane->state->dst);
602 window.dst.h = drm_rect_height(&plane->state->dst);
272725c7 603 window.bits_per_pixel = fb->format->cpp[0] * 8;
c7679306
TR		 604 window.bottom_up = tegra_fb_is_bottom_up(fb);
605
8f604f8c
TR		 606 /* copy from state */
607 window.tiling = state->tiling;
608 window.format = state->format;
609 window.swap = state->swap;
c7679306 610
bcb0b461 611 for (i = 0; i < fb->format->num_planes; i++) {
4aa3df71 612 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
c7679306 613
4aa3df71 614 window.base[i] = bo->paddr + fb->offsets[i];
08ee0178
DO		 615
616 /*
617 * Tegra uses a shared stride for UV planes. Framebuffers are
618 * already checked for this in the tegra_plane_atomic_check()
619 * function, so it's safe to ignore the V-plane pitch here.
620 */
621 if (i < 2)
622 window.stride[i] = fb->pitches[i];
4aa3df71 623 }
10288eea 624
4aa3df71 625 tegra_dc_setup_window(dc, p->index, &window);
10288eea
TR		 626}
627
a4bfa096 628static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
4aa3df71 629 .atomic_check = tegra_plane_atomic_check,
4aa3df71 630 .atomic_disable = tegra_plane_atomic_disable,
a4bfa096 631 .atomic_update = tegra_plane_atomic_update,
c7679306
TR		 632};
633
634static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,
635 struct tegra_dc *dc)
636{
518e6227
TR		 637 /*
638 * Ideally this would use drm_crtc_mask(), but that would require the
639 * CRTC to already be in the mode_config's list of CRTCs. However, it
640 * will only be added to that list in the drm_crtc_init_with_planes()
641 * (in tegra_dc_init()), which in turn requires registration of these
642 * planes. So we have ourselves a nice little chicken and egg problem
643 * here.
644 *
645 * We work around this by manually creating the mask from the number
646 * of CRTCs that have been registered, and should therefore always be
647 * the same as drm_crtc_index() after registration.
648 */
649 unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc;
c7679306
TR		 650 struct tegra_plane *plane;
651 unsigned int num_formats;
652 const u32 *formats;
653 int err;
654
655 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
656 if (!plane)
657 return ERR_PTR(-ENOMEM);
658
659 num_formats = ARRAY_SIZE(tegra_primary_plane_formats);
660 formats = tegra_primary_plane_formats;
661
518e6227 662 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
c7679306 663 &tegra_primary_plane_funcs, formats,
e6fc3b68
BW		 664 num_formats, NULL,
665 DRM_PLANE_TYPE_PRIMARY, NULL);
c7679306
TR		 666 if (err < 0) {
667 kfree(plane);
668 return ERR_PTR(err);
669 }
670
a4bfa096 671 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
4aa3df71 672
c7679306
TR		 673 return &plane->base;
674}
675
676static const u32 tegra_cursor_plane_formats[] = {
677 DRM_FORMAT_RGBA8888,
678};
679
4aa3df71
TR		 680static int tegra_cursor_atomic_check(struct drm_plane *plane,
681 struct drm_plane_state *state)
c7679306 682{
47802b09
TR		 683 struct tegra_plane *tegra = to_tegra_plane(plane);
684 int err;
685
4aa3df71
TR		 686 /* no need for further checks if the plane is being disabled */
687 if (!state->crtc)
688 return 0;
c7679306
TR		 689
690 /* scaling not supported for cursor */
4aa3df71
TR		 691 if ((state->src_w >> 16 != state->crtc_w) ||
692 (state->src_h >> 16 != state->crtc_h))
c7679306
TR		 693 return -EINVAL;
694
695 /* only square cursors supported */
4aa3df71
TR		 696 if (state->src_w != state->src_h)
697 return -EINVAL;
698
699 if (state->crtc_w != 32 && state->crtc_w != 64 &&
700 state->crtc_w != 128 && state->crtc_w != 256)
c7679306
TR		 701 return -EINVAL;
702
47802b09
TR		 703 err = tegra_plane_state_add(tegra, state);
704 if (err < 0)
705 return err;
706
4aa3df71
TR		 707 return 0;
708}
709
710static void tegra_cursor_atomic_update(struct drm_plane *plane,
711 struct drm_plane_state *old_state)
712{
713 struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0);
714 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
715 struct drm_plane_state *state = plane->state;
716 u32 value = CURSOR_CLIP_DISPLAY;
717
718 /* rien ne va plus */
719 if (!plane->state->crtc || !plane->state->fb)
720 return;
721
722 switch (state->crtc_w) {
c7679306
TR		 723 case 32:
724 value |= CURSOR_SIZE_32x32;
725 break;
726
727 case 64:
728 value |= CURSOR_SIZE_64x64;
729 break;
730
731 case 128:
732 value |= CURSOR_SIZE_128x128;
733 break;
734
735 case 256:
736 value |= CURSOR_SIZE_256x256;
737 break;
738
739 default:
4aa3df71
TR		 740 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w,
741 state->crtc_h);
742 return;
c7679306
TR		 743 }
744
745 value |= (bo->paddr >> 10) & 0x3fffff;
746 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
747
748#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
749 value = (bo->paddr >> 32) & 0x3;
750 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
751#endif
752
753 /* enable cursor and set blend mode */
754 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
755 value |= CURSOR_ENABLE;
756 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
757
758 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
759 value &= ~CURSOR_DST_BLEND_MASK;
760 value &= ~CURSOR_SRC_BLEND_MASK;
761 value |= CURSOR_MODE_NORMAL;
762 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
763 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
764 value |= CURSOR_ALPHA;
765 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
766
767 /* position the cursor */
4aa3df71 768 value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
c7679306 769 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
c7679306
TR		 770}
771
4aa3df71
TR		 772static void tegra_cursor_atomic_disable(struct drm_plane *plane,
773 struct drm_plane_state *old_state)
c7679306 774{
4aa3df71 775 struct tegra_dc *dc;
c7679306
TR		 776 u32 value;
777
4aa3df71
TR		 778 /* rien ne va plus */
779 if (!old_state || !old_state->crtc)
780 return;
781
782 dc = to_tegra_dc(old_state->crtc);
c7679306
TR		 783
784 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
785 value &= ~CURSOR_ENABLE;
786 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
c7679306
TR		 787}
788
789static const struct drm_plane_funcs tegra_cursor_plane_funcs = {
07866963
TR		 790 .update_plane = drm_atomic_helper_update_plane,
791 .disable_plane = drm_atomic_helper_disable_plane,
c7679306 792 .destroy = tegra_plane_destroy,
8f604f8c
TR		 793 .reset = tegra_plane_reset,
794 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
795 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
4aa3df71
TR		 796};
797
798static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
4aa3df71
TR		 799 .atomic_check = tegra_cursor_atomic_check,
800 .atomic_update = tegra_cursor_atomic_update,
801 .atomic_disable = tegra_cursor_atomic_disable,
c7679306
TR		 802};
803
804static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
805 struct tegra_dc *dc)
806{
807 struct tegra_plane *plane;
808 unsigned int num_formats;
809 const u32 *formats;
810 int err;
811
812 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
813 if (!plane)
814 return ERR_PTR(-ENOMEM);
815
47802b09 816 /*
a1df3b24
TR		 817 * This index is kind of fake. The cursor isn't a regular plane, but
818 * its update and activation request bits in DC_CMD_STATE_CONTROL do
819 * use the same programming. Setting this fake index here allows the
820 * code in tegra_add_plane_state() to do the right thing without the
821 * need to special-casing the cursor plane.
47802b09
TR		 822 */
823 plane->index = 6;
824
c7679306
TR		 825 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
826 formats = tegra_cursor_plane_formats;
827
828 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
829 &tegra_cursor_plane_funcs, formats,
e6fc3b68
BW		 830 num_formats, NULL,
831 DRM_PLANE_TYPE_CURSOR, NULL);
c7679306
TR		 832 if (err < 0) {
833 kfree(plane);
834 return ERR_PTR(err);
835 }
836
4aa3df71 837 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
f34bc787 838
4aa3df71 839 return &plane->base;
f34bc787
TR		 840}
841
c7679306 842static void tegra_overlay_plane_destroy(struct drm_plane *plane)
f34bc787 843{
c7679306 844 tegra_plane_destroy(plane);
f34bc787
TR		 845}
846
c7679306 847static const struct drm_plane_funcs tegra_overlay_plane_funcs = {
07866963
TR		 848 .update_plane = drm_atomic_helper_update_plane,
849 .disable_plane = drm_atomic_helper_disable_plane,
c7679306 850 .destroy = tegra_overlay_plane_destroy,
8f604f8c
TR		 851 .reset = tegra_plane_reset,
852 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
853 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
f34bc787
TR		 854};
855
c7679306 856static const uint32_t tegra_overlay_plane_formats[] = {
dbe4d9a7 857 DRM_FORMAT_XBGR8888,
f34bc787 858 DRM_FORMAT_XRGB8888,
dbe4d9a7 859 DRM_FORMAT_RGB565,
f34bc787 860 DRM_FORMAT_UYVY,
f925390e 861 DRM_FORMAT_YUYV,
f34bc787
TR		 862 DRM_FORMAT_YUV420,
863 DRM_FORMAT_YUV422,
864};
865
c7679306
TR		 866static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
867 struct tegra_dc *dc,
868 unsigned int index)
f34bc787 869{
c7679306
TR		 870 struct tegra_plane *plane;
871 unsigned int num_formats;
872 const u32 *formats;
873 int err;
f34bc787 874
c7679306
TR		 875 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
876 if (!plane)
877 return ERR_PTR(-ENOMEM);
f34bc787 878
c7679306 879 plane->index = index;
f34bc787 880
c7679306
TR		 881 num_formats = ARRAY_SIZE(tegra_overlay_plane_formats);
882 formats = tegra_overlay_plane_formats;
f34bc787 883
c7679306
TR		 884 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
885 &tegra_overlay_plane_funcs, formats,
e6fc3b68
BW		 886 num_formats, NULL,
887 DRM_PLANE_TYPE_OVERLAY, NULL);
c7679306
TR		 888 if (err < 0) {
889 kfree(plane);
890 return ERR_PTR(err);
891 }
892
a4bfa096 893 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
4aa3df71 894
c7679306
TR		 895 return &plane->base;
896}
897
898static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
899{
900 struct drm_plane *plane;
901 unsigned int i;
902
903 for (i = 0; i < 2; i++) {
904 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
905 if (IS_ERR(plane))
906 return PTR_ERR(plane);
f34bc787
TR		 907 }
908
909 return 0;
910}
911
10437d9b 912static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc)
42e9ce05 913{
10437d9b
SG		 914 struct tegra_dc *dc = to_tegra_dc(crtc);
915
42e9ce05
TR		 916 if (dc->syncpt)
917 return host1x_syncpt_read(dc->syncpt);
918
919 /* fallback to software emulated VBLANK counter */
920 return drm_crtc_vblank_count(&dc->base);
921}
922
10437d9b 923static int tegra_dc_enable_vblank(struct drm_crtc *crtc)
6e5ff998 924{
10437d9b 925 struct tegra_dc *dc = to_tegra_dc(crtc);
6e5ff998
TR		 926 unsigned long value, flags;
927
928 spin_lock_irqsave(&dc->lock, flags);
929
930 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
931 value |= VBLANK_INT;
932 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
933
934 spin_unlock_irqrestore(&dc->lock, flags);
10437d9b
SG		 935
936 return 0;
6e5ff998
TR		 937}
938
10437d9b 939static void tegra_dc_disable_vblank(struct drm_crtc *crtc)
6e5ff998 940{
10437d9b 941 struct tegra_dc *dc = to_tegra_dc(crtc);
6e5ff998
TR		 942 unsigned long value, flags;
943
944 spin_lock_irqsave(&dc->lock, flags);
945
946 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
947 value &= ~VBLANK_INT;
948 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
949
950 spin_unlock_irqrestore(&dc->lock, flags);
951}
952
3c03c46a
TR		 953static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
954{
955 struct drm_device *drm = dc->base.dev;
956 struct drm_crtc *crtc = &dc->base;
3c03c46a 957 unsigned long flags, base;
de2ba664 958 struct tegra_bo *bo;
3c03c46a 959
6b59cc1c
TR		 960 spin_lock_irqsave(&drm->event_lock, flags);
961
962 if (!dc->event) {
963 spin_unlock_irqrestore(&drm->event_lock, flags);
3c03c46a 964 return;
6b59cc1c 965 }
3c03c46a 966
f4510a27 967 bo = tegra_fb_get_plane(crtc->primary->fb, 0);
3c03c46a 968
8643bc6d 969 spin_lock(&dc->lock);
93396d0f 970
3c03c46a 971 /* check if new start address has been latched */
93396d0f 972 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
3c03c46a
TR		 973 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
974 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
975 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
976
8643bc6d 977 spin_unlock(&dc->lock);
93396d0f 978
f4510a27 979 if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
ed7dae58
TR		 980 drm_crtc_send_vblank_event(crtc, dc->event);
981 drm_crtc_vblank_put(crtc);
3c03c46a 982 dc->event = NULL;
3c03c46a 983 }
6b59cc1c
TR		 984
985 spin_unlock_irqrestore(&drm->event_lock, flags);
3c03c46a
TR		 986}
987
f002abc1
TR		 988static void tegra_dc_destroy(struct drm_crtc *crtc)
989{
990 drm_crtc_cleanup(crtc);
f002abc1
TR		 991}
992
ca915b10
TR		 993static void tegra_crtc_reset(struct drm_crtc *crtc)
994{
995 struct tegra_dc_state *state;
996
3b59b7ac 997 if (crtc->state)
ec2dc6a0 998 __drm_atomic_helper_crtc_destroy_state(crtc->state);
3b59b7ac 999
ca915b10
TR		 1000 kfree(crtc->state);
1001 crtc->state = NULL;
1002
1003 state = kzalloc(sizeof(*state), GFP_KERNEL);
332bbe70 1004 if (state) {
ca915b10 1005 crtc->state = &state->base;
332bbe70
TR		 1006 crtc->state->crtc = crtc;
1007 }
31930d4d
TR		 1008
1009 drm_crtc_vblank_reset(crtc);
ca915b10
TR		 1010}
1011
1012static struct drm_crtc_state *
1013tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1014{
1015 struct tegra_dc_state *state = to_dc_state(crtc->state);
1016 struct tegra_dc_state *copy;
1017
3b59b7ac 1018 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
ca915b10
TR		 1019 if (!copy)
1020 return NULL;
1021
3b59b7ac
TR		 1022 __drm_atomic_helper_crtc_duplicate_state(crtc, &copy->base);
1023 copy->clk = state->clk;
1024 copy->pclk = state->pclk;
1025 copy->div = state->div;
1026 copy->planes = state->planes;
ca915b10
TR		 1027
1028 return &copy->base;
1029}
1030
1031static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1032 struct drm_crtc_state *state)
1033{
ec2dc6a0 1034 __drm_atomic_helper_crtc_destroy_state(state);
ca915b10
TR		 1035 kfree(state);
1036}
1037
d8f4a9ed 1038static const struct drm_crtc_funcs tegra_crtc_funcs = {
1503ca47 1039 .page_flip = drm_atomic_helper_page_flip,
74f48791 1040 .set_config = drm_atomic_helper_set_config,
f002abc1 1041 .destroy = tegra_dc_destroy,
ca915b10
TR		 1042 .reset = tegra_crtc_reset,
1043 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1044 .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
10437d9b
SG		 1045 .get_vblank_counter = tegra_dc_get_vblank_counter,
1046 .enable_vblank = tegra_dc_enable_vblank,
1047 .disable_vblank = tegra_dc_disable_vblank,
d8f4a9ed
TR		 1048};
1049
d8f4a9ed
TR		 1050static int tegra_dc_set_timings(struct tegra_dc *dc,
1051 struct drm_display_mode *mode)
1052{
0444c0ff
TR		 1053 unsigned int h_ref_to_sync = 1;
1054 unsigned int v_ref_to_sync = 1;
d8f4a9ed
TR		 1055 unsigned long value;
1056
1057 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1058
1059 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1060 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1061
1062 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1063 ((mode->hsync_end - mode->hsync_start) << 0);
1064 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1065
d8f4a9ed
TR		 1066 value = ((mode->vtotal - mode->vsync_end) << 16) |
1067 ((mode->htotal - mode->hsync_end) << 0);
40495089
LS		 1068 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1069
1070 value = ((mode->vsync_start - mode->vdisplay) << 16) |
1071 ((mode->hsync_start - mode->hdisplay) << 0);
d8f4a9ed
TR		 1072 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1073
1074 value = (mode->vdisplay << 16) | mode->hdisplay;
1075 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1076
1077 return 0;
1078}
1079
9d910b60
TR		 1080/**
1081 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1082 * state
1083 * @dc: display controller
1084 * @crtc_state: CRTC atomic state
1085 * @clk: parent clock for display controller
1086 * @pclk: pixel clock
1087 * @div: shift clock divider
1088 *
1089 * Returns:
1090 * 0 on success or a negative error-code on failure.
1091 */
ca915b10
TR		 1092int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1093 struct drm_crtc_state *crtc_state,
1094 struct clk *clk, unsigned long pclk,
1095 unsigned int div)
1096{
1097 struct tegra_dc_state *state = to_dc_state(crtc_state);
1098
d2982748
TR		 1099 if (!clk_has_parent(dc->clk, clk))
1100 return -EINVAL;
1101
ca915b10
TR		 1102 state->clk = clk;
1103 state->pclk = pclk;
1104 state->div = div;
1105
1106 return 0;
1107}
1108
76d59ed0
TR		 1109static void tegra_dc_commit_state(struct tegra_dc *dc,
1110 struct tegra_dc_state *state)
1111{
1112 u32 value;
1113 int err;
1114
1115 err = clk_set_parent(dc->clk, state->clk);
1116 if (err < 0)
1117 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1118
1119 /*
1120 * Outputs may not want to change the parent clock rate. This is only
1121 * relevant to Tegra20 where only a single display PLL is available.
1122 * Since that PLL would typically be used for HDMI, an internal LVDS
1123 * panel would need to be driven by some other clock such as PLL_P
1124 * which is shared with other peripherals. Changing the clock rate
1125 * should therefore be avoided.
1126 */
1127 if (state->pclk > 0) {
1128 err = clk_set_rate(state->clk, state->pclk);
1129 if (err < 0)
1130 dev_err(dc->dev,
1131 "failed to set clock rate to %lu Hz\n",
1132 state->pclk);
1133 }
1134
1135 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1136 state->div);
1137 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1138
1139 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1140 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1141}
1142
003fc848
TR		 1143static void tegra_dc_stop(struct tegra_dc *dc)
1144{
1145 u32 value;
1146
1147 /* stop the display controller */
1148 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1149 value &= ~DISP_CTRL_MODE_MASK;
1150 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1151
1152 tegra_dc_commit(dc);
1153}
1154
1155static bool tegra_dc_idle(struct tegra_dc *dc)
1156{
1157 u32 value;
1158
1159 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1160
1161 return (value & DISP_CTRL_MODE_MASK) == 0;
1162}
1163
1164static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1165{
1166 timeout = jiffies + msecs_to_jiffies(timeout);
1167
1168 while (time_before(jiffies, timeout)) {
1169 if (tegra_dc_idle(dc))
1170 return 0;
1171
1172 usleep_range(1000, 2000);
1173 }
1174
1175 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1176 return -ETIMEDOUT;
1177}
1178
64581714
LP		 1179static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,
1180 struct drm_crtc_state *old_state)
003fc848
TR		 1181{
1182 struct tegra_dc *dc = to_tegra_dc(crtc);
1183 u32 value;
1184
1185 if (!tegra_dc_idle(dc)) {
1186 tegra_dc_stop(dc);
1187
1188 /*
1189 * Ignore the return value, there isn't anything useful to do
1190 * in case this fails.
1191 */
1192 tegra_dc_wait_idle(dc, 100);
1193 }
1194
1195 /*
1196 * This should really be part of the RGB encoder driver, but clearing
1197 * these bits has the side-effect of stopping the display controller.
1198 * When that happens no VBLANK interrupts will be raised. At the same
1199 * time the encoder is disabled before the display controller, so the
1200 * above code is always going to timeout waiting for the controller
1201 * to go idle.
1202 *
1203 * Given the close coupling between the RGB encoder and the display
1204 * controller doing it here is still kind of okay. None of the other
1205 * encoder drivers require these bits to be cleared.
1206 *
1207 * XXX: Perhaps given that the display controller is switched off at
1208 * this point anyway maybe clearing these bits isn't even useful for
1209 * the RGB encoder?
1210 */
1211 if (dc->rgb) {
1212 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1213 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1214 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1215 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1216 }
1217
1218 tegra_dc_stats_reset(&dc->stats);
1219 drm_crtc_vblank_off(crtc);
33a8eb8d
TR		 1220
1221 pm_runtime_put_sync(dc->dev);
003fc848
TR		 1222}
1223
0b20a0f8
LP		 1224static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
1225 struct drm_crtc_state *old_state)
d8f4a9ed 1226{
4aa3df71 1227 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
76d59ed0 1228 struct tegra_dc_state *state = to_dc_state(crtc->state);
d8f4a9ed 1229 struct tegra_dc *dc = to_tegra_dc(crtc);
dbb3f2f7 1230 u32 value;
d8f4a9ed 1231
33a8eb8d
TR		 1232 pm_runtime_get_sync(dc->dev);
1233
1234 /* initialize display controller */
1235 if (dc->syncpt) {
1236 u32 syncpt = host1x_syncpt_id(dc->syncpt);
1237
1238 value = SYNCPT_CNTRL_NO_STALL;
1239 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1240
1241 value = SYNCPT_VSYNC_ENABLE | syncpt;
1242 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1243 }
1244
1245 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1246 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1247 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1248
1249 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1250 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1251 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1252
1253 /* initialize timer */
1254 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1255 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1256 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1257
1258 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1259 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1260 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1261
1262 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1263 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1264 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1265
1266 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1267 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1268 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1269
1270 if (dc->soc->supports_border_color)
1271 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1272
1273 /* apply PLL and pixel clock changes */
76d59ed0
TR		 1274 tegra_dc_commit_state(dc, state);
1275
d8f4a9ed
TR		 1276 /* program display mode */
1277 tegra_dc_set_timings(dc, mode);
1278
8620fc62
TR		 1279 /* interlacing isn't supported yet, so disable it */
1280 if (dc->soc->supports_interlacing) {
1281 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1282 value &= ~INTERLACE_ENABLE;
1283 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1284 }
666cb873
TR		 1285
1286 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1287 value &= ~DISP_CTRL_MODE_MASK;
1288 value |= DISP_CTRL_MODE_C_DISPLAY;
1289 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1290
1291 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1292 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1293 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1294 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1295
1296 tegra_dc_commit(dc);
d8f4a9ed 1297
8ff64c17 1298 drm_crtc_vblank_on(crtc);
d8f4a9ed
TR		 1299}
1300
4aa3df71
TR		 1301static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
1302 struct drm_crtc_state *state)
1303{
1304 return 0;
1305}
1306
613d2b27
ML		 1307static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1308 struct drm_crtc_state *old_crtc_state)
4aa3df71 1309{
1503ca47
TR		 1310 struct tegra_dc *dc = to_tegra_dc(crtc);
1311
1312 if (crtc->state->event) {
1313 crtc->state->event->pipe = drm_crtc_index(crtc);
1314
1315 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1316
1317 dc->event = crtc->state->event;
1318 crtc->state->event = NULL;
1319 }
4aa3df71
TR		 1320}
1321
613d2b27
ML		 1322static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1323 struct drm_crtc_state *old_crtc_state)
4aa3df71 1324{
47802b09
TR		 1325 struct tegra_dc_state *state = to_dc_state(crtc->state);
1326 struct tegra_dc *dc = to_tegra_dc(crtc);
1327
1328 tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL);
1329 tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL);
4aa3df71
TR		 1330}
1331
d8f4a9ed 1332static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
4aa3df71
TR		 1333 .atomic_check = tegra_crtc_atomic_check,
1334 .atomic_begin = tegra_crtc_atomic_begin,
1335 .atomic_flush = tegra_crtc_atomic_flush,
0b20a0f8 1336 .atomic_enable = tegra_crtc_atomic_enable,
64581714 1337 .atomic_disable = tegra_crtc_atomic_disable,
d8f4a9ed
TR		 1338};
1339
6e5ff998 1340static irqreturn_t tegra_dc_irq(int irq, void *data)
d8f4a9ed
TR		 1341{
1342 struct tegra_dc *dc = data;
1343 unsigned long status;
1344
1345 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1346 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1347
1348 if (status & FRAME_END_INT) {
1349 /*
1350 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1351 */
791ddb1e 1352 dc->stats.frames++;
d8f4a9ed
TR		 1353 }
1354
1355 if (status & VBLANK_INT) {
1356 /*
1357 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1358 */
ed7dae58 1359 drm_crtc_handle_vblank(&dc->base);
3c03c46a 1360 tegra_dc_finish_page_flip(dc);
791ddb1e 1361 dc->stats.vblank++;
d8f4a9ed
TR		 1362 }
1363
1364 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1365 /*
1366 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1367 */
791ddb1e
TR		 1368 dc->stats.underflow++;
1369 }
1370
1371 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
1372 /*
1373 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
1374 */
1375 dc->stats.overflow++;
d8f4a9ed
TR		 1376 }
1377
1378 return IRQ_HANDLED;
1379}
1380
1381static int tegra_dc_show_regs(struct seq_file *s, void *data)
1382{
1383 struct drm_info_node *node = s->private;
1384 struct tegra_dc *dc = node->info_ent->data;
003fc848
TR		 1385 int err = 0;
1386
99612b27 1387 drm_modeset_lock(&dc->base.mutex, NULL);
003fc848
TR		 1388
1389 if (!dc->base.state->active) {
1390 err = -EBUSY;
1391 goto unlock;
1392 }
d8f4a9ed
TR		 1393
1394#define DUMP_REG(name) \
03a60569 1395 seq_printf(s, "%-40s %#05x %08x\n", #name, name, \
d8f4a9ed
TR		 1396 tegra_dc_readl(dc, name))
1397
1398 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
1399 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1400 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
1401 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
1402 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
1403 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
1404 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
1405 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
1406 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
1407 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
1408 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
1409 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
1410 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
1411 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
1412 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
1413 DUMP_REG(DC_CMD_SIGNAL_RAISE);
1414 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
1415 DUMP_REG(DC_CMD_INT_STATUS);
1416 DUMP_REG(DC_CMD_INT_MASK);
1417 DUMP_REG(DC_CMD_INT_ENABLE);
1418 DUMP_REG(DC_CMD_INT_TYPE);
1419 DUMP_REG(DC_CMD_INT_POLARITY);
1420 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
1421 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
1422 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
1423 DUMP_REG(DC_CMD_STATE_ACCESS);
1424 DUMP_REG(DC_CMD_STATE_CONTROL);
1425 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
1426 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
1427 DUMP_REG(DC_COM_CRC_CONTROL);
1428 DUMP_REG(DC_COM_CRC_CHECKSUM);
1429 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1430 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1431 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1432 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1433 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1434 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1435 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1436 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1437 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1438 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1439 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1440 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1441 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1442 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1443 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1444 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1445 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1446 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1447 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1448 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1449 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1450 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1451 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1452 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1453 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1454 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
1455 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
1456 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
1457 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
1458 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
1459 DUMP_REG(DC_COM_SPI_CONTROL);
1460 DUMP_REG(DC_COM_SPI_START_BYTE);
1461 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
1462 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
1463 DUMP_REG(DC_COM_HSPI_CS_DC);
1464 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
1465 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
1466 DUMP_REG(DC_COM_GPIO_CTRL);
1467 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
1468 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
1469 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
1470 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
1471 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
1472 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
1473 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1474 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
1475 DUMP_REG(DC_DISP_REF_TO_SYNC);
1476 DUMP_REG(DC_DISP_SYNC_WIDTH);
1477 DUMP_REG(DC_DISP_BACK_PORCH);
1478 DUMP_REG(DC_DISP_ACTIVE);
1479 DUMP_REG(DC_DISP_FRONT_PORCH);
1480 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
1481 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
1482 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
1483 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
1484 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
1485 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
1486 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
1487 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
1488 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
1489 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
1490 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
1491 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
1492 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
1493 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
1494 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
1495 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
1496 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
1497 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
1498 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
1499 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
1500 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
1501 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
1502 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
1503 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
1504 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
1505 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
1506 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
1507 DUMP_REG(DC_DISP_M0_CONTROL);
1508 DUMP_REG(DC_DISP_M1_CONTROL);
1509 DUMP_REG(DC_DISP_DI_CONTROL);
1510 DUMP_REG(DC_DISP_PP_CONTROL);
1511 DUMP_REG(DC_DISP_PP_SELECT_A);
1512 DUMP_REG(DC_DISP_PP_SELECT_B);
1513 DUMP_REG(DC_DISP_PP_SELECT_C);
1514 DUMP_REG(DC_DISP_PP_SELECT_D);
1515 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
1516 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
1517 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
1518 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
1519 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
1520 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
1521 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
1522 DUMP_REG(DC_DISP_BORDER_COLOR);
1523 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
1524 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
1525 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
1526 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
1527 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
1528 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
1529 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
1530 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
1531 DUMP_REG(DC_DISP_CURSOR_POSITION);
1532 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
1533 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
1534 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
1535 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
1536 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
1537 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
1538 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
1539 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
1540 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
1541 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
1542 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
1543 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
1544 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
1545 DUMP_REG(DC_DISP_SD_CONTROL);
1546 DUMP_REG(DC_DISP_SD_CSC_COEFF);
1547 DUMP_REG(DC_DISP_SD_LUT(0));
1548 DUMP_REG(DC_DISP_SD_LUT(1));
1549 DUMP_REG(DC_DISP_SD_LUT(2));
1550 DUMP_REG(DC_DISP_SD_LUT(3));
1551 DUMP_REG(DC_DISP_SD_LUT(4));
1552 DUMP_REG(DC_DISP_SD_LUT(5));
1553 DUMP_REG(DC_DISP_SD_LUT(6));
1554 DUMP_REG(DC_DISP_SD_LUT(7));
1555 DUMP_REG(DC_DISP_SD_LUT(8));
1556 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
1557 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
1558 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1559 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1560 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1561 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1562 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1563 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1564 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1565 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1566 DUMP_REG(DC_DISP_SD_BL_TF(0));
1567 DUMP_REG(DC_DISP_SD_BL_TF(1));
1568 DUMP_REG(DC_DISP_SD_BL_TF(2));
1569 DUMP_REG(DC_DISP_SD_BL_TF(3));
1570 DUMP_REG(DC_DISP_SD_BL_CONTROL);
1571 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1572 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
e687651b
TR		 1573 DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
1574 DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL);
d8f4a9ed
TR		 1575 DUMP_REG(DC_WIN_WIN_OPTIONS);
1576 DUMP_REG(DC_WIN_BYTE_SWAP);
1577 DUMP_REG(DC_WIN_BUFFER_CONTROL);
1578 DUMP_REG(DC_WIN_COLOR_DEPTH);
1579 DUMP_REG(DC_WIN_POSITION);
1580 DUMP_REG(DC_WIN_SIZE);
1581 DUMP_REG(DC_WIN_PRESCALED_SIZE);
1582 DUMP_REG(DC_WIN_H_INITIAL_DDA);
1583 DUMP_REG(DC_WIN_V_INITIAL_DDA);
1584 DUMP_REG(DC_WIN_DDA_INC);
1585 DUMP_REG(DC_WIN_LINE_STRIDE);
1586 DUMP_REG(DC_WIN_BUF_STRIDE);
1587 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1588 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1589 DUMP_REG(DC_WIN_DV_CONTROL);
1590 DUMP_REG(DC_WIN_BLEND_NOKEY);
1591 DUMP_REG(DC_WIN_BLEND_1WIN);
1592 DUMP_REG(DC_WIN_BLEND_2WIN_X);
1593 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
f34bc787 1594 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
d8f4a9ed
TR		 1595 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1596 DUMP_REG(DC_WINBUF_START_ADDR);
1597 DUMP_REG(DC_WINBUF_START_ADDR_NS);
1598 DUMP_REG(DC_WINBUF_START_ADDR_U);
1599 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1600 DUMP_REG(DC_WINBUF_START_ADDR_V);
1601 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1602 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1603 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1604 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1605 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1606 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1607 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1608 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1609 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1610
1611#undef DUMP_REG
1612
003fc848 1613unlock:
99612b27 1614 drm_modeset_unlock(&dc->base.mutex);
003fc848 1615 return err;
d8f4a9ed
TR		 1616}
1617
6ca1f62f
TR		 1618static int tegra_dc_show_crc(struct seq_file *s, void *data)
1619{
1620 struct drm_info_node *node = s->private;
1621 struct tegra_dc *dc = node->info_ent->data;
003fc848 1622 int err = 0;
6ca1f62f
TR		 1623 u32 value;
1624
99612b27 1625 drm_modeset_lock(&dc->base.mutex, NULL);
003fc848
TR		 1626
1627 if (!dc->base.state->active) {
1628 err = -EBUSY;
1629 goto unlock;
1630 }
1631
6ca1f62f
TR		 1632 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1633 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1634 tegra_dc_commit(dc);
1635
1636 drm_crtc_wait_one_vblank(&dc->base);
1637 drm_crtc_wait_one_vblank(&dc->base);
1638
1639 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1640 seq_printf(s, "%08x\n", value);
1641
1642 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1643
003fc848 1644unlock:
99612b27 1645 drm_modeset_unlock(&dc->base.mutex);
003fc848 1646 return err;
6ca1f62f
TR		 1647}
1648
791ddb1e
TR		 1649static int tegra_dc_show_stats(struct seq_file *s, void *data)
1650{
1651 struct drm_info_node *node = s->private;
1652 struct tegra_dc *dc = node->info_ent->data;
1653
1654 seq_printf(s, "frames: %lu\n", dc->stats.frames);
1655 seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1656 seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1657 seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1658
d8f4a9ed
TR		 1659 return 0;
1660}
1661
1662static struct drm_info_list debugfs_files[] = {
1663 { "regs", tegra_dc_show_regs, 0, NULL },
6ca1f62f 1664 { "crc", tegra_dc_show_crc, 0, NULL },
791ddb1e 1665 { "stats", tegra_dc_show_stats, 0, NULL },
d8f4a9ed
TR		 1666};
1667
1668static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1669{
1670 unsigned int i;
1671 char *name;
1672 int err;
1673
1674 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1675 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1676 kfree(name);
1677
1678 if (!dc->debugfs)
1679 return -ENOMEM;
1680
1681 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1682 GFP_KERNEL);
1683 if (!dc->debugfs_files) {
1684 err = -ENOMEM;
1685 goto remove;
1686 }
1687
1688 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1689 dc->debugfs_files[i].data = dc;
1690
1691 err = drm_debugfs_create_files(dc->debugfs_files,
1692 ARRAY_SIZE(debugfs_files),
1693 dc->debugfs, minor);
1694 if (err < 0)
1695 goto free;
1696
1697 dc->minor = minor;
1698
1699 return 0;
1700
1701free:
1702 kfree(dc->debugfs_files);
1703 dc->debugfs_files = NULL;
1704remove:
1705 debugfs_remove(dc->debugfs);
1706 dc->debugfs = NULL;
1707
1708 return err;
1709}
1710
1711static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1712{
1713 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1714 dc->minor);
1715 dc->minor = NULL;
1716
1717 kfree(dc->debugfs_files);
1718 dc->debugfs_files = NULL;
1719
1720 debugfs_remove(dc->debugfs);
1721 dc->debugfs = NULL;
1722
1723 return 0;
1724}
1725
53fa7f72 1726static int tegra_dc_init(struct host1x_client *client)
d8f4a9ed 1727{
9910f5c4 1728 struct drm_device *drm = dev_get_drvdata(client->parent);
2bcdcbfa 1729 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
776dc384 1730 struct tegra_dc *dc = host1x_client_to_dc(client);
d1f3e1e0 1731 struct tegra_drm *tegra = drm->dev_private;
c7679306
TR		 1732 struct drm_plane *primary = NULL;
1733 struct drm_plane *cursor = NULL;
d8f4a9ed
TR		 1734 int err;
1735
617dd7cc 1736 dc->syncpt = host1x_syncpt_request(client, flags);
2bcdcbfa
TR		 1737 if (!dc->syncpt)
1738 dev_warn(dc->dev, "failed to allocate syncpoint\n");
1739
df06b759
TR		 1740 if (tegra->domain) {
1741 err = iommu_attach_device(tegra->domain, dc->dev);
1742 if (err < 0) {
1743 dev_err(dc->dev, "failed to attach to domain: %d\n",
1744 err);
1745 return err;
1746 }
1747
1748 dc->domain = tegra->domain;
1749 }
1750
c7679306
TR		 1751 primary = tegra_dc_primary_plane_create(drm, dc);
1752 if (IS_ERR(primary)) {
1753 err = PTR_ERR(primary);
1754 goto cleanup;
1755 }
1756
1757 if (dc->soc->supports_cursor) {
1758 cursor = tegra_dc_cursor_plane_create(drm, dc);
1759 if (IS_ERR(cursor)) {
1760 err = PTR_ERR(cursor);
1761 goto cleanup;
1762 }
1763 }
1764
1765 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
f9882876 1766 &tegra_crtc_funcs, NULL);
c7679306
TR		 1767 if (err < 0)
1768 goto cleanup;
1769
d8f4a9ed
TR		 1770 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1771
d1f3e1e0
TR		 1772 /*
1773 * Keep track of the minimum pitch alignment across all display
1774 * controllers.
1775 */
1776 if (dc->soc->pitch_align > tegra->pitch_align)
1777 tegra->pitch_align = dc->soc->pitch_align;
1778
9910f5c4 1779 err = tegra_dc_rgb_init(drm, dc);
d8f4a9ed
TR		 1780 if (err < 0 && err != -ENODEV) {
1781 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
c7679306 1782 goto cleanup;
d8f4a9ed
TR		 1783 }
1784
9910f5c4 1785 err = tegra_dc_add_planes(drm, dc);
f34bc787 1786 if (err < 0)
c7679306 1787 goto cleanup;
f34bc787 1788
d8f4a9ed 1789 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
9910f5c4 1790 err = tegra_dc_debugfs_init(dc, drm->primary);
d8f4a9ed
TR		 1791 if (err < 0)
1792 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1793 }
1794
6e5ff998 1795 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
d8f4a9ed
TR		 1796 dev_name(dc->dev), dc);
1797 if (err < 0) {
1798 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1799 err);
c7679306 1800 goto cleanup;
d8f4a9ed
TR		 1801 }
1802
1803 return 0;
c7679306
TR		 1804
1805cleanup:
1806 if (cursor)
1807 drm_plane_cleanup(cursor);
1808
1809 if (primary)
1810 drm_plane_cleanup(primary);
1811
1812 if (tegra->domain) {
1813 iommu_detach_device(tegra->domain, dc->dev);
1814 dc->domain = NULL;
1815 }
1816
1817 return err;
d8f4a9ed
TR		 1818}
1819
53fa7f72 1820static int tegra_dc_exit(struct host1x_client *client)
d8f4a9ed 1821{
776dc384 1822 struct tegra_dc *dc = host1x_client_to_dc(client);
d8f4a9ed
TR		 1823 int err;
1824
1825 devm_free_irq(dc->dev, dc->irq, dc);
1826
1827 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1828 err = tegra_dc_debugfs_exit(dc);
1829 if (err < 0)
1830 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1831 }
1832
1833 err = tegra_dc_rgb_exit(dc);
1834 if (err) {
1835 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1836 return err;
1837 }
1838
df06b759
TR		 1839 if (dc->domain) {
1840 iommu_detach_device(dc->domain, dc->dev);
1841 dc->domain = NULL;
1842 }
1843
2bcdcbfa
TR		 1844 host1x_syncpt_free(dc->syncpt);
1845
d8f4a9ed
TR		 1846 return 0;
1847}
1848
1849static const struct host1x_client_ops dc_client_ops = {
53fa7f72
TR		 1850 .init = tegra_dc_init,
1851 .exit = tegra_dc_exit,
d8f4a9ed
TR		 1852};
1853
8620fc62 1854static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
42d0659b 1855 .supports_border_color = true,
8620fc62 1856 .supports_interlacing = false,
e687651b 1857 .supports_cursor = false,
c134f019 1858 .supports_block_linear = false,
d1f3e1e0 1859 .pitch_align = 8,
9c012700 1860 .has_powergate = false,
6ac1571b 1861 .broken_reset = true,
8620fc62
TR		 1862};
1863
1864static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
42d0659b 1865 .supports_border_color = true,
8620fc62 1866 .supports_interlacing = false,
e687651b 1867 .supports_cursor = false,
c134f019 1868 .supports_block_linear = false,
d1f3e1e0 1869 .pitch_align = 8,
9c012700 1870 .has_powergate = false,
6ac1571b 1871 .broken_reset = false,
d1f3e1e0
TR		 1872};
1873
1874static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
42d0659b 1875 .supports_border_color = true,
d1f3e1e0
TR		 1876 .supports_interlacing = false,
1877 .supports_cursor = false,
1878 .supports_block_linear = false,
1879 .pitch_align = 64,
9c012700 1880 .has_powergate = true,
6ac1571b 1881 .broken_reset = false,
8620fc62
TR		 1882};
1883
1884static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
42d0659b 1885 .supports_border_color = false,
8620fc62 1886 .supports_interlacing = true,
e687651b 1887 .supports_cursor = true,
c134f019 1888 .supports_block_linear = true,
d1f3e1e0 1889 .pitch_align = 64,
9c012700 1890 .has_powergate = true,
6ac1571b 1891 .broken_reset = false,
8620fc62
TR		 1892};
1893
5b4f516f
TR		 1894static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
1895 .supports_border_color = false,
1896 .supports_interlacing = true,
1897 .supports_cursor = true,
1898 .supports_block_linear = true,
1899 .pitch_align = 64,
1900 .has_powergate = true,
6ac1571b 1901 .broken_reset = false,
5b4f516f
TR		 1902};
1903
8620fc62
TR		 1904static const struct of_device_id tegra_dc_of_match[] = {
1905 {
5b4f516f
TR		 1906 .compatible = "nvidia,tegra210-dc",
1907 .data = &tegra210_dc_soc_info,
1908 }, {
8620fc62
TR		 1909 .compatible = "nvidia,tegra124-dc",
1910 .data = &tegra124_dc_soc_info,
9c012700
TR		 1911 }, {
1912 .compatible = "nvidia,tegra114-dc",
1913 .data = &tegra114_dc_soc_info,
8620fc62
TR		 1914 }, {
1915 .compatible = "nvidia,tegra30-dc",
1916 .data = &tegra30_dc_soc_info,
1917 }, {
1918 .compatible = "nvidia,tegra20-dc",
1919 .data = &tegra20_dc_soc_info,
1920 }, {
1921 /* sentinel */
1922 }
1923};
ef70728c 1924MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
8620fc62 1925
13411ddd
TR		 1926static int tegra_dc_parse_dt(struct tegra_dc *dc)
1927{
1928 struct device_node *np;
1929 u32 value = 0;
1930 int err;
1931
1932 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1933 if (err < 0) {
1934 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1935
1936 /*
1937 * If the nvidia,head property isn't present, try to find the
1938 * correct head number by looking up the position of this
1939 * display controller's node within the device tree. Assuming
1940 * that the nodes are ordered properly in the DTS file and
1941 * that the translation into a flattened device tree blob
1942 * preserves that ordering this will actually yield the right
1943 * head number.
1944 *
1945 * If those assumptions don't hold, this will still work for
1946 * cases where only a single display controller is used.
1947 */
1948 for_each_matching_node(np, tegra_dc_of_match) {
cf6b1744
JL		 1949 if (np == dc->dev->of_node) {
1950 of_node_put(np);
13411ddd 1951 break;
cf6b1744 1952 }
13411ddd
TR		 1953
1954 value++;
1955 }
1956 }
1957
1958 dc->pipe = value;
1959
1960 return 0;
1961}
1962
d8f4a9ed
TR		 1963static int tegra_dc_probe(struct platform_device *pdev)
1964{
d8f4a9ed
TR		 1965 struct resource *regs;
1966 struct tegra_dc *dc;
1967 int err;
1968
1969 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1970 if (!dc)
1971 return -ENOMEM;
1972
b9ff7aea 1973 dc->soc = of_device_get_match_data(&pdev->dev);
8620fc62 1974
6e5ff998 1975 spin_lock_init(&dc->lock);
d8f4a9ed
TR		 1976 INIT_LIST_HEAD(&dc->list);
1977 dc->dev = &pdev->dev;
1978
13411ddd
TR		 1979 err = tegra_dc_parse_dt(dc);
1980 if (err < 0)
1981 return err;
1982
d8f4a9ed
TR		 1983 dc->clk = devm_clk_get(&pdev->dev, NULL);
1984 if (IS_ERR(dc->clk)) {
1985 dev_err(&pdev->dev, "failed to get clock\n");
1986 return PTR_ERR(dc->clk);
1987 }
1988
ca48080a
SW		 1989 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1990 if (IS_ERR(dc->rst)) {
1991 dev_err(&pdev->dev, "failed to get reset\n");
1992 return PTR_ERR(dc->rst);
1993 }
1994
6ac1571b
DO		 1995 if (!dc->soc->broken_reset)
1996 reset_control_assert(dc->rst);
33a8eb8d 1997
9c012700
TR		 1998 if (dc->soc->has_powergate) {
1999 if (dc->pipe == 0)
2000 dc->powergate = TEGRA_POWERGATE_DIS;
2001 else
2002 dc->powergate = TEGRA_POWERGATE_DISB;
2003
33a8eb8d 2004 tegra_powergate_power_off(dc->powergate);
9c012700 2005 }
d8f4a9ed
TR		 2006
2007 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d4ed6025
TR		 2008 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
2009 if (IS_ERR(dc->regs))
2010 return PTR_ERR(dc->regs);
d8f4a9ed
TR		 2011
2012 dc->irq = platform_get_irq(pdev, 0);
2013 if (dc->irq < 0) {
2014 dev_err(&pdev->dev, "failed to get IRQ\n");
2015 return -ENXIO;
2016 }
2017
d8f4a9ed
TR		 2018 err = tegra_dc_rgb_probe(dc);
2019 if (err < 0 && err != -ENODEV) {
2020 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
2021 return err;
2022 }
2023
33a8eb8d
TR		 2024 platform_set_drvdata(pdev, dc);
2025 pm_runtime_enable(&pdev->dev);
2026
2027 INIT_LIST_HEAD(&dc->client.list);
2028 dc->client.ops = &dc_client_ops;
2029 dc->client.dev = &pdev->dev;
2030
776dc384 2031 err = host1x_client_register(&dc->client);
d8f4a9ed
TR		 2032 if (err < 0) {
2033 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2034 err);
2035 return err;
2036 }
2037
d8f4a9ed
TR		 2038 return 0;
2039}
2040
2041static int tegra_dc_remove(struct platform_device *pdev)
2042{
d8f4a9ed
TR		 2043 struct tegra_dc *dc = platform_get_drvdata(pdev);
2044 int err;
2045
776dc384 2046 err = host1x_client_unregister(&dc->client);
d8f4a9ed
TR		 2047 if (err < 0) {
2048 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2049 err);
2050 return err;
2051 }
2052
59d29c0e
TR		 2053 err = tegra_dc_rgb_remove(dc);
2054 if (err < 0) {
2055 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2056 return err;
2057 }
2058
33a8eb8d
TR		 2059 pm_runtime_disable(&pdev->dev);
2060
2061 return 0;
2062}
2063
2064#ifdef CONFIG_PM
2065static int tegra_dc_suspend(struct device *dev)
2066{
2067 struct tegra_dc *dc = dev_get_drvdata(dev);
2068 int err;
2069
6ac1571b
DO		 2070 if (!dc->soc->broken_reset) {
2071 err = reset_control_assert(dc->rst);
2072 if (err < 0) {
2073 dev_err(dev, "failed to assert reset: %d\n", err);
2074 return err;
2075 }
33a8eb8d 2076 }
9c012700
TR		 2077
2078 if (dc->soc->has_powergate)
2079 tegra_powergate_power_off(dc->powergate);
2080
d8f4a9ed
TR		 2081 clk_disable_unprepare(dc->clk);
2082
2083 return 0;
2084}
2085
33a8eb8d
TR		 2086static int tegra_dc_resume(struct device *dev)
2087{
2088 struct tegra_dc *dc = dev_get_drvdata(dev);
2089 int err;
2090
2091 if (dc->soc->has_powergate) {
2092 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2093 dc->rst);
2094 if (err < 0) {
2095 dev_err(dev, "failed to power partition: %d\n", err);
2096 return err;
2097 }
2098 } else {
2099 err = clk_prepare_enable(dc->clk);
2100 if (err < 0) {
2101 dev_err(dev, "failed to enable clock: %d\n", err);
2102 return err;
2103 }
2104
6ac1571b
DO		 2105 if (!dc->soc->broken_reset) {
2106 err = reset_control_deassert(dc->rst);
2107 if (err < 0) {
2108 dev_err(dev,
2109 "failed to deassert reset: %d\n", err);
2110 return err;
2111 }
33a8eb8d
TR		 2112 }
2113 }
2114
2115 return 0;
2116}
2117#endif
2118
2119static const struct dev_pm_ops tegra_dc_pm_ops = {
2120 SET_RUNTIME_PM_OPS(tegra_dc_suspend, tegra_dc_resume, NULL)
2121};
2122
d8f4a9ed
TR		 2123struct platform_driver tegra_dc_driver = {
2124 .driver = {
2125 .name = "tegra-dc",
d8f4a9ed 2126 .of_match_table = tegra_dc_of_match,
33a8eb8d 2127 .pm = &tegra_dc_pm_ops,
d8f4a9ed
TR		 2128 },
2129 .probe = tegra_dc_probe,
2130 .remove = tegra_dc_remove,
2131};
Linux 6.x block layer and io_uring tree(s)