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drm/tegra: dc: Avoid reset asserts on Tegra20
[linux-2.6-block.git] / drivers / gpu / drm / tegra / dc.c
CommitLineData
d8f4a9ed
TR		 1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
9eb9b220 11#include <linux/debugfs.h>
df06b759 12#include <linux/iommu.h>
33a8eb8d 13#include <linux/pm_runtime.h>
ca48080a 14#include <linux/reset.h>
d8f4a9ed 15
9c012700
TR		 16#include <soc/tegra/pmc.h>
17
de2ba664
AM		 18#include "dc.h"
19#include "drm.h"
20#include "gem.h"
d8f4a9ed 21
9d44189f 22#include <drm/drm_atomic.h>
4aa3df71 23#include <drm/drm_atomic_helper.h>
3cb9ae4f
DV		 24#include <drm/drm_plane_helper.h>
25
8620fc62 26struct tegra_dc_soc_info {
42d0659b 27 bool supports_border_color;
8620fc62 28 bool supports_interlacing;
e687651b 29 bool supports_cursor;
c134f019 30 bool supports_block_linear;
d1f3e1e0 31 unsigned int pitch_align;
9c012700 32 bool has_powergate;
6ac1571b 33 bool broken_reset;
8620fc62
TR		 34};
35
f34bc787
TR		 36struct tegra_plane {
37 struct drm_plane base;
38 unsigned int index;
d8f4a9ed
TR		 39};
40
f34bc787
TR		 41static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
42{
43 return container_of(plane, struct tegra_plane, base);
44}
45
ca915b10
TR		 46struct tegra_dc_state {
47 struct drm_crtc_state base;
48
49 struct clk *clk;
50 unsigned long pclk;
51 unsigned int div;
47802b09
TR		 52
53 u32 planes;
ca915b10
TR		 54};
55
56static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state)
57{
58 if (state)
59 return container_of(state, struct tegra_dc_state, base);
60
61 return NULL;
62}
63
8f604f8c
TR		 64struct tegra_plane_state {
65 struct drm_plane_state base;
66
67 struct tegra_bo_tiling tiling;
68 u32 format;
69 u32 swap;
70};
71
72static inline struct tegra_plane_state *
73to_tegra_plane_state(struct drm_plane_state *state)
74{
75 if (state)
76 return container_of(state, struct tegra_plane_state, base);
77
78 return NULL;
79}
80
791ddb1e
TR		 81static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
82{
83 stats->frames = 0;
84 stats->vblank = 0;
85 stats->underflow = 0;
86 stats->overflow = 0;
87}
88
86df256f
TR		 89/*
90 * Reads the active copy of a register. This takes the dc->lock spinlock to
91 * prevent races with the VBLANK processing which also needs access to the
92 * active copy of some registers.
93 */
94static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
95{
96 unsigned long flags;
97 u32 value;
98
99 spin_lock_irqsave(&dc->lock, flags);
100
101 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
102 value = tegra_dc_readl(dc, offset);
103 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
104
105 spin_unlock_irqrestore(&dc->lock, flags);
106 return value;
107}
108
d700ba7a
TR		 109/*
110 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
111 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
112 * Latching happens mmediately if the display controller is in STOP mode or
113 * on the next frame boundary otherwise.
114 *
115 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
116 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
117 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
118 * into the ACTIVE copy, either immediately if the display controller is in
119 * STOP mode, or at the next frame boundary otherwise.
120 */
62b9e063 121void tegra_dc_commit(struct tegra_dc *dc)
205d48ed
TR		 122{
123 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
124 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
125}
126
8f604f8c 127static int tegra_dc_format(u32 fourcc, u32 *format, u32 *swap)
10288eea
TR		 128{
129 /* assume no swapping of fetched data */
130 if (swap)
131 *swap = BYTE_SWAP_NOSWAP;
132
8f604f8c 133 switch (fourcc) {
10288eea 134 case DRM_FORMAT_XBGR8888:
8f604f8c
TR		 135 *format = WIN_COLOR_DEPTH_R8G8B8A8;
136 break;
10288eea
TR		 137
138 case DRM_FORMAT_XRGB8888:
8f604f8c
TR		 139 *format = WIN_COLOR_DEPTH_B8G8R8A8;
140 break;
10288eea
TR		 141
142 case DRM_FORMAT_RGB565:
8f604f8c
TR		 143 *format = WIN_COLOR_DEPTH_B5G6R5;
144 break;
10288eea
TR		 145
146 case DRM_FORMAT_UYVY:
8f604f8c
TR		 147 *format = WIN_COLOR_DEPTH_YCbCr422;
148 break;
10288eea
TR		 149
150 case DRM_FORMAT_YUYV:
151 if (swap)
152 *swap = BYTE_SWAP_SWAP2;
153
8f604f8c
TR		 154 *format = WIN_COLOR_DEPTH_YCbCr422;
155 break;
10288eea
TR		 156
157 case DRM_FORMAT_YUV420:
8f604f8c
TR		 158 *format = WIN_COLOR_DEPTH_YCbCr420P;
159 break;
10288eea
TR		 160
161 case DRM_FORMAT_YUV422:
8f604f8c
TR		 162 *format = WIN_COLOR_DEPTH_YCbCr422P;
163 break;
10288eea
TR		 164
165 default:
8f604f8c 166 return -EINVAL;
10288eea
TR		 167 }
168
8f604f8c 169 return 0;
10288eea
TR		 170}
171
172static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
173{
174 switch (format) {
175 case WIN_COLOR_DEPTH_YCbCr422:
176 case WIN_COLOR_DEPTH_YUV422:
177 if (planar)
178 *planar = false;
179
180 return true;
181
182 case WIN_COLOR_DEPTH_YCbCr420P:
183 case WIN_COLOR_DEPTH_YUV420P:
184 case WIN_COLOR_DEPTH_YCbCr422P:
185 case WIN_COLOR_DEPTH_YUV422P:
186 case WIN_COLOR_DEPTH_YCbCr422R:
187 case WIN_COLOR_DEPTH_YUV422R:
188 case WIN_COLOR_DEPTH_YCbCr422RA:
189 case WIN_COLOR_DEPTH_YUV422RA:
190 if (planar)
191 *planar = true;
192
193 return true;
194 }
195
fb35c6b6
TR		 196 if (planar)
197 *planar = false;
198
10288eea
TR		 199 return false;
200}
201
202static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
203 unsigned int bpp)
204{
205 fixed20_12 outf = dfixed_init(out);
206 fixed20_12 inf = dfixed_init(in);
207 u32 dda_inc;
208 int max;
209
210 if (v)
211 max = 15;
212 else {
213 switch (bpp) {
214 case 2:
215 max = 8;
216 break;
217
218 default:
219 WARN_ON_ONCE(1);
220 /* fallthrough */
221 case 4:
222 max = 4;
223 break;
224 }
225 }
226
227 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
228 inf.full -= dfixed_const(1);
229
230 dda_inc = dfixed_div(inf, outf);
231 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
232
233 return dda_inc;
234}
235
236static inline u32 compute_initial_dda(unsigned int in)
237{
238 fixed20_12 inf = dfixed_init(in);
239 return dfixed_frac(inf);
240}
241
4aa3df71
TR		 242static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
243 const struct tegra_dc_window *window)
10288eea
TR		 244{
245 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
93396d0f 246 unsigned long value, flags;
10288eea
TR		 247 bool yuv, planar;
248
249 /*
250 * For YUV planar modes, the number of bytes per pixel takes into
251 * account only the luma component and therefore is 1.
252 */
253 yuv = tegra_dc_format_is_yuv(window->format, &planar);
254 if (!yuv)
255 bpp = window->bits_per_pixel / 8;
256 else
257 bpp = planar ? 1 : 2;
258
93396d0f
SP		 259 spin_lock_irqsave(&dc->lock, flags);
260
10288eea
TR		 261 value = WINDOW_A_SELECT << index;
262 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
263
264 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
265 tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
266
267 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
268 tegra_dc_writel(dc, value, DC_WIN_POSITION);
269
270 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
271 tegra_dc_writel(dc, value, DC_WIN_SIZE);
272
273 h_offset = window->src.x * bpp;
274 v_offset = window->src.y;
275 h_size = window->src.w * bpp;
276 v_size = window->src.h;
277
278 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
279 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
280
281 /*
282 * For DDA computations the number of bytes per pixel for YUV planar
283 * modes needs to take into account all Y, U and V components.
284 */
285 if (yuv && planar)
286 bpp = 2;
287
288 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
289 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
290
291 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
292 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
293
294 h_dda = compute_initial_dda(window->src.x);
295 v_dda = compute_initial_dda(window->src.y);
296
297 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
298 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
299
300 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
301 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
302
303 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
304
305 if (yuv && planar) {
306 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
307 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
308 value = window->stride[1] << 16 | window->stride[0];
309 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
310 } else {
311 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
312 }
313
314 if (window->bottom_up)
315 v_offset += window->src.h - 1;
316
317 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
318 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
319
c134f019
TR		 320 if (dc->soc->supports_block_linear) {
321 unsigned long height = window->tiling.value;
322
323 switch (window->tiling.mode) {
324 case TEGRA_BO_TILING_MODE_PITCH:
325 value = DC_WINBUF_SURFACE_KIND_PITCH;
326 break;
327
328 case TEGRA_BO_TILING_MODE_TILED:
329 value = DC_WINBUF_SURFACE_KIND_TILED;
330 break;
331
332 case TEGRA_BO_TILING_MODE_BLOCK:
333 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
334 DC_WINBUF_SURFACE_KIND_BLOCK;
335 break;
336 }
337
338 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
10288eea 339 } else {
c134f019
TR		 340 switch (window->tiling.mode) {
341 case TEGRA_BO_TILING_MODE_PITCH:
342 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
343 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
344 break;
10288eea 345
c134f019
TR		 346 case TEGRA_BO_TILING_MODE_TILED:
347 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
348 DC_WIN_BUFFER_ADDR_MODE_TILE;
349 break;
350
351 case TEGRA_BO_TILING_MODE_BLOCK:
4aa3df71
TR		 352 /*
353 * No need to handle this here because ->atomic_check
354 * will already have filtered it out.
355 */
356 break;
c134f019
TR		 357 }
358
359 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
360 }
10288eea
TR		 361
362 value = WIN_ENABLE;
363
364 if (yuv) {
365 /* setup default colorspace conversion coefficients */
366 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
367 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
368 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
369 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
370 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
371 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
372 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
373 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
374
375 value |= CSC_ENABLE;
376 } else if (window->bits_per_pixel < 24) {
377 value |= COLOR_EXPAND;
378 }
379
380 if (window->bottom_up)
381 value |= V_DIRECTION;
382
383 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
384
385 /*
386 * Disable blending and assume Window A is the bottom-most window,
387 * Window C is the top-most window and Window B is in the middle.
388 */
389 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
390 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
391
392 switch (index) {
393 case 0:
394 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
395 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
396 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
397 break;
398
399 case 1:
400 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
401 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
402 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
403 break;
404
405 case 2:
406 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
407 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
408 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
409 break;
410 }
411
93396d0f 412 spin_unlock_irqrestore(&dc->lock, flags);
c7679306
TR		 413}
414
415static void tegra_plane_destroy(struct drm_plane *plane)
416{
417 struct tegra_plane *p = to_tegra_plane(plane);
418
419 drm_plane_cleanup(plane);
420 kfree(p);
421}
422
423static const u32 tegra_primary_plane_formats[] = {
424 DRM_FORMAT_XBGR8888,
425 DRM_FORMAT_XRGB8888,
426 DRM_FORMAT_RGB565,
427};
428
4aa3df71 429static void tegra_primary_plane_destroy(struct drm_plane *plane)
c7679306 430{
4aa3df71
TR		 431 tegra_plane_destroy(plane);
432}
433
8f604f8c
TR		 434static void tegra_plane_reset(struct drm_plane *plane)
435{
436 struct tegra_plane_state *state;
437
3b59b7ac 438 if (plane->state)
2f701695 439 __drm_atomic_helper_plane_destroy_state(plane->state);
8f604f8c
TR		 440
441 kfree(plane->state);
442 plane->state = NULL;
443
444 state = kzalloc(sizeof(*state), GFP_KERNEL);
445 if (state) {
446 plane->state = &state->base;
447 plane->state->plane = plane;
448 }
449}
450
451static struct drm_plane_state *tegra_plane_atomic_duplicate_state(struct drm_plane *plane)
452{
453 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
454 struct tegra_plane_state *copy;
455
3b59b7ac 456 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
8f604f8c
TR		 457 if (!copy)
458 return NULL;
459
3b59b7ac
TR		 460 __drm_atomic_helper_plane_duplicate_state(plane, &copy->base);
461 copy->tiling = state->tiling;
462 copy->format = state->format;
463 copy->swap = state->swap;
8f604f8c
TR		 464
465 return &copy->base;
466}
467
468static void tegra_plane_atomic_destroy_state(struct drm_plane *plane,
469 struct drm_plane_state *state)
470{
2f701695 471 __drm_atomic_helper_plane_destroy_state(state);
8f604f8c
TR		 472 kfree(state);
473}
474
4aa3df71 475static const struct drm_plane_funcs tegra_primary_plane_funcs = {
07866963
TR		 476 .update_plane = drm_atomic_helper_update_plane,
477 .disable_plane = drm_atomic_helper_disable_plane,
4aa3df71 478 .destroy = tegra_primary_plane_destroy,
8f604f8c
TR		 479 .reset = tegra_plane_reset,
480 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
481 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
4aa3df71
TR		 482};
483
47802b09
TR		 484static int tegra_plane_state_add(struct tegra_plane *plane,
485 struct drm_plane_state *state)
486{
487 struct drm_crtc_state *crtc_state;
488 struct tegra_dc_state *tegra;
489
490 /* Propagate errors from allocation or locking failures. */
491 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
492 if (IS_ERR(crtc_state))
493 return PTR_ERR(crtc_state);
494
495 tegra = to_dc_state(crtc_state);
496
497 tegra->planes |= WIN_A_ACT_REQ << plane->index;
498
499 return 0;
500}
501
4aa3df71
TR		 502static int tegra_plane_atomic_check(struct drm_plane *plane,
503 struct drm_plane_state *state)
504{
8f604f8c
TR		 505 struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
506 struct tegra_bo_tiling *tiling = &plane_state->tiling;
47802b09 507 struct tegra_plane *tegra = to_tegra_plane(plane);
4aa3df71 508 struct tegra_dc *dc = to_tegra_dc(state->crtc);
4aa3df71
TR		 509 int err;
510
511 /* no need for further checks if the plane is being disabled */
512 if (!state->crtc)
513 return 0;
514
438b74a5 515 err = tegra_dc_format(state->fb->format->format, &plane_state->format,
8f604f8c 516 &plane_state->swap);
4aa3df71
TR		 517 if (err < 0)
518 return err;
519
8f604f8c
TR		 520 err = tegra_fb_get_tiling(state->fb, tiling);
521 if (err < 0)
522 return err;
523
524 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
4aa3df71
TR		 525 !dc->soc->supports_block_linear) {
526 DRM_ERROR("hardware doesn't support block linear mode\n");
527 return -EINVAL;
528 }
529
530 /*
531 * Tegra doesn't support different strides for U and V planes so we
532 * error out if the user tries to display a framebuffer with such a
533 * configuration.
534 */
bcb0b461 535 if (state->fb->format->num_planes > 2) {
4aa3df71
TR		 536 if (state->fb->pitches[2] != state->fb->pitches[1]) {
537 DRM_ERROR("unsupported UV-plane configuration\n");
538 return -EINVAL;
539 }
540 }
541
47802b09
TR		 542 err = tegra_plane_state_add(tegra, state);
543 if (err < 0)
544 return err;
545
4aa3df71
TR		 546 return 0;
547}
548
549static void tegra_plane_atomic_update(struct drm_plane *plane,
550 struct drm_plane_state *old_state)
551{
8f604f8c 552 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
4aa3df71
TR		 553 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
554 struct drm_framebuffer *fb = plane->state->fb;
c7679306 555 struct tegra_plane *p = to_tegra_plane(plane);
c7679306 556 struct tegra_dc_window window;
4aa3df71 557 unsigned int i;
c7679306 558
4aa3df71
TR		 559 /* rien ne va plus */
560 if (!plane->state->crtc || !plane->state->fb)
561 return;
562
c7679306 563 memset(&window, 0, sizeof(window));
4aa3df71
TR		 564 window.src.x = plane->state->src_x >> 16;
565 window.src.y = plane->state->src_y >> 16;
566 window.src.w = plane->state->src_w >> 16;
567 window.src.h = plane->state->src_h >> 16;
568 window.dst.x = plane->state->crtc_x;
569 window.dst.y = plane->state->crtc_y;
570 window.dst.w = plane->state->crtc_w;
571 window.dst.h = plane->state->crtc_h;
272725c7 572 window.bits_per_pixel = fb->format->cpp[0] * 8;
c7679306
TR		 573 window.bottom_up = tegra_fb_is_bottom_up(fb);
574
8f604f8c
TR		 575 /* copy from state */
576 window.tiling = state->tiling;
577 window.format = state->format;
578 window.swap = state->swap;
c7679306 579
bcb0b461 580 for (i = 0; i < fb->format->num_planes; i++) {
4aa3df71 581 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
c7679306 582
4aa3df71 583 window.base[i] = bo->paddr + fb->offsets[i];
08ee0178
DO		 584
585 /*
586 * Tegra uses a shared stride for UV planes. Framebuffers are
587 * already checked for this in the tegra_plane_atomic_check()
588 * function, so it's safe to ignore the V-plane pitch here.
589 */
590 if (i < 2)
591 window.stride[i] = fb->pitches[i];
4aa3df71 592 }
10288eea 593
4aa3df71 594 tegra_dc_setup_window(dc, p->index, &window);
10288eea
TR		 595}
596
4aa3df71
TR		 597static void tegra_plane_atomic_disable(struct drm_plane *plane,
598 struct drm_plane_state *old_state)
c7679306 599{
4aa3df71
TR		 600 struct tegra_plane *p = to_tegra_plane(plane);
601 struct tegra_dc *dc;
602 unsigned long flags;
603 u32 value;
604
605 /* rien ne va plus */
606 if (!old_state || !old_state->crtc)
607 return;
608
609 dc = to_tegra_dc(old_state->crtc);
610
611 spin_lock_irqsave(&dc->lock, flags);
612
613 value = WINDOW_A_SELECT << p->index;
614 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
615
616 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
617 value &= ~WIN_ENABLE;
618 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
619
4aa3df71 620 spin_unlock_irqrestore(&dc->lock, flags);
c7679306
TR		 621}
622
4aa3df71 623static const struct drm_plane_helper_funcs tegra_primary_plane_helper_funcs = {
4aa3df71
TR		 624 .atomic_check = tegra_plane_atomic_check,
625 .atomic_update = tegra_plane_atomic_update,
626 .atomic_disable = tegra_plane_atomic_disable,
c7679306
TR		 627};
628
629static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,
630 struct tegra_dc *dc)
631{
518e6227
TR		 632 /*
633 * Ideally this would use drm_crtc_mask(), but that would require the
634 * CRTC to already be in the mode_config's list of CRTCs. However, it
635 * will only be added to that list in the drm_crtc_init_with_planes()
636 * (in tegra_dc_init()), which in turn requires registration of these
637 * planes. So we have ourselves a nice little chicken and egg problem
638 * here.
639 *
640 * We work around this by manually creating the mask from the number
641 * of CRTCs that have been registered, and should therefore always be
642 * the same as drm_crtc_index() after registration.
643 */
644 unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc;
c7679306
TR		 645 struct tegra_plane *plane;
646 unsigned int num_formats;
647 const u32 *formats;
648 int err;
649
650 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
651 if (!plane)
652 return ERR_PTR(-ENOMEM);
653
654 num_formats = ARRAY_SIZE(tegra_primary_plane_formats);
655 formats = tegra_primary_plane_formats;
656
518e6227 657 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
c7679306 658 &tegra_primary_plane_funcs, formats,
b0b3b795
VS		 659 num_formats, DRM_PLANE_TYPE_PRIMARY,
660 NULL);
c7679306
TR		 661 if (err < 0) {
662 kfree(plane);
663 return ERR_PTR(err);
664 }
665
4aa3df71
TR		 666 drm_plane_helper_add(&plane->base, &tegra_primary_plane_helper_funcs);
667
c7679306
TR		 668 return &plane->base;
669}
670
671static const u32 tegra_cursor_plane_formats[] = {
672 DRM_FORMAT_RGBA8888,
673};
674
4aa3df71
TR		 675static int tegra_cursor_atomic_check(struct drm_plane *plane,
676 struct drm_plane_state *state)
c7679306 677{
47802b09
TR		 678 struct tegra_plane *tegra = to_tegra_plane(plane);
679 int err;
680
4aa3df71
TR		 681 /* no need for further checks if the plane is being disabled */
682 if (!state->crtc)
683 return 0;
c7679306
TR		 684
685 /* scaling not supported for cursor */
4aa3df71
TR		 686 if ((state->src_w >> 16 != state->crtc_w) ||
687 (state->src_h >> 16 != state->crtc_h))
c7679306
TR		 688 return -EINVAL;
689
690 /* only square cursors supported */
4aa3df71
TR		 691 if (state->src_w != state->src_h)
692 return -EINVAL;
693
694 if (state->crtc_w != 32 && state->crtc_w != 64 &&
695 state->crtc_w != 128 && state->crtc_w != 256)
c7679306
TR		 696 return -EINVAL;
697
47802b09
TR		 698 err = tegra_plane_state_add(tegra, state);
699 if (err < 0)
700 return err;
701
4aa3df71
TR		 702 return 0;
703}
704
705static void tegra_cursor_atomic_update(struct drm_plane *plane,
706 struct drm_plane_state *old_state)
707{
708 struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0);
709 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
710 struct drm_plane_state *state = plane->state;
711 u32 value = CURSOR_CLIP_DISPLAY;
712
713 /* rien ne va plus */
714 if (!plane->state->crtc || !plane->state->fb)
715 return;
716
717 switch (state->crtc_w) {
c7679306
TR		 718 case 32:
719 value |= CURSOR_SIZE_32x32;
720 break;
721
722 case 64:
723 value |= CURSOR_SIZE_64x64;
724 break;
725
726 case 128:
727 value |= CURSOR_SIZE_128x128;
728 break;
729
730 case 256:
731 value |= CURSOR_SIZE_256x256;
732 break;
733
734 default:
4aa3df71
TR		 735 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w,
736 state->crtc_h);
737 return;
c7679306
TR		 738 }
739
740 value |= (bo->paddr >> 10) & 0x3fffff;
741 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
742
743#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
744 value = (bo->paddr >> 32) & 0x3;
745 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
746#endif
747
748 /* enable cursor and set blend mode */
749 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
750 value |= CURSOR_ENABLE;
751 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
752
753 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
754 value &= ~CURSOR_DST_BLEND_MASK;
755 value &= ~CURSOR_SRC_BLEND_MASK;
756 value |= CURSOR_MODE_NORMAL;
757 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
758 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
759 value |= CURSOR_ALPHA;
760 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
761
762 /* position the cursor */
4aa3df71 763 value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
c7679306 764 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
c7679306
TR		 765}
766
4aa3df71
TR		 767static void tegra_cursor_atomic_disable(struct drm_plane *plane,
768 struct drm_plane_state *old_state)
c7679306 769{
4aa3df71 770 struct tegra_dc *dc;
c7679306
TR		 771 u32 value;
772
4aa3df71
TR		 773 /* rien ne va plus */
774 if (!old_state || !old_state->crtc)
775 return;
776
777 dc = to_tegra_dc(old_state->crtc);
c7679306
TR		 778
779 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
780 value &= ~CURSOR_ENABLE;
781 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
c7679306
TR		 782}
783
784static const struct drm_plane_funcs tegra_cursor_plane_funcs = {
07866963
TR		 785 .update_plane = drm_atomic_helper_update_plane,
786 .disable_plane = drm_atomic_helper_disable_plane,
c7679306 787 .destroy = tegra_plane_destroy,
8f604f8c
TR		 788 .reset = tegra_plane_reset,
789 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
790 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
4aa3df71
TR		 791};
792
793static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
4aa3df71
TR		 794 .atomic_check = tegra_cursor_atomic_check,
795 .atomic_update = tegra_cursor_atomic_update,
796 .atomic_disable = tegra_cursor_atomic_disable,
c7679306
TR		 797};
798
799static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
800 struct tegra_dc *dc)
801{
802 struct tegra_plane *plane;
803 unsigned int num_formats;
804 const u32 *formats;
805 int err;
806
807 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
808 if (!plane)
809 return ERR_PTR(-ENOMEM);
810
47802b09 811 /*
a1df3b24
TR		 812 * This index is kind of fake. The cursor isn't a regular plane, but
813 * its update and activation request bits in DC_CMD_STATE_CONTROL do
814 * use the same programming. Setting this fake index here allows the
815 * code in tegra_add_plane_state() to do the right thing without the
816 * need to special-casing the cursor plane.
47802b09
TR		 817 */
818 plane->index = 6;
819
c7679306
TR		 820 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
821 formats = tegra_cursor_plane_formats;
822
823 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
824 &tegra_cursor_plane_funcs, formats,
b0b3b795
VS		 825 num_formats, DRM_PLANE_TYPE_CURSOR,
826 NULL);
c7679306
TR		 827 if (err < 0) {
828 kfree(plane);
829 return ERR_PTR(err);
830 }
831
4aa3df71 832 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
f34bc787 833
4aa3df71 834 return &plane->base;
f34bc787
TR		 835}
836
c7679306 837static void tegra_overlay_plane_destroy(struct drm_plane *plane)
f34bc787 838{
c7679306 839 tegra_plane_destroy(plane);
f34bc787
TR		 840}
841
c7679306 842static const struct drm_plane_funcs tegra_overlay_plane_funcs = {
07866963
TR		 843 .update_plane = drm_atomic_helper_update_plane,
844 .disable_plane = drm_atomic_helper_disable_plane,
c7679306 845 .destroy = tegra_overlay_plane_destroy,
8f604f8c
TR		 846 .reset = tegra_plane_reset,
847 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
848 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
f34bc787
TR		 849};
850
c7679306 851static const uint32_t tegra_overlay_plane_formats[] = {
dbe4d9a7 852 DRM_FORMAT_XBGR8888,
f34bc787 853 DRM_FORMAT_XRGB8888,
dbe4d9a7 854 DRM_FORMAT_RGB565,
f34bc787 855 DRM_FORMAT_UYVY,
f925390e 856 DRM_FORMAT_YUYV,
f34bc787
TR		 857 DRM_FORMAT_YUV420,
858 DRM_FORMAT_YUV422,
859};
860
4aa3df71 861static const struct drm_plane_helper_funcs tegra_overlay_plane_helper_funcs = {
4aa3df71
TR		 862 .atomic_check = tegra_plane_atomic_check,
863 .atomic_update = tegra_plane_atomic_update,
864 .atomic_disable = tegra_plane_atomic_disable,
865};
866
c7679306
TR		 867static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
868 struct tegra_dc *dc,
869 unsigned int index)
f34bc787 870{
c7679306
TR		 871 struct tegra_plane *plane;
872 unsigned int num_formats;
873 const u32 *formats;
874 int err;
f34bc787 875
c7679306
TR		 876 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
877 if (!plane)
878 return ERR_PTR(-ENOMEM);
f34bc787 879
c7679306 880 plane->index = index;
f34bc787 881
c7679306
TR		 882 num_formats = ARRAY_SIZE(tegra_overlay_plane_formats);
883 formats = tegra_overlay_plane_formats;
f34bc787 884
c7679306
TR		 885 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
886 &tegra_overlay_plane_funcs, formats,
b0b3b795
VS		 887 num_formats, DRM_PLANE_TYPE_OVERLAY,
888 NULL);
c7679306
TR		 889 if (err < 0) {
890 kfree(plane);
891 return ERR_PTR(err);
892 }
893
4aa3df71
TR		 894 drm_plane_helper_add(&plane->base, &tegra_overlay_plane_helper_funcs);
895
c7679306
TR		 896 return &plane->base;
897}
898
899static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
900{
901 struct drm_plane *plane;
902 unsigned int i;
903
904 for (i = 0; i < 2; i++) {
905 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
906 if (IS_ERR(plane))
907 return PTR_ERR(plane);
f34bc787
TR		 908 }
909
910 return 0;
911}
912
10437d9b 913static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc)
42e9ce05 914{
10437d9b
SG		 915 struct tegra_dc *dc = to_tegra_dc(crtc);
916
42e9ce05
TR		 917 if (dc->syncpt)
918 return host1x_syncpt_read(dc->syncpt);
919
920 /* fallback to software emulated VBLANK counter */
921 return drm_crtc_vblank_count(&dc->base);
922}
923
10437d9b 924static int tegra_dc_enable_vblank(struct drm_crtc *crtc)
6e5ff998 925{
10437d9b 926 struct tegra_dc *dc = to_tegra_dc(crtc);
6e5ff998
TR		 927 unsigned long value, flags;
928
929 spin_lock_irqsave(&dc->lock, flags);
930
931 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
932 value |= VBLANK_INT;
933 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
934
935 spin_unlock_irqrestore(&dc->lock, flags);
10437d9b
SG		 936
937 return 0;
6e5ff998
TR		 938}
939
10437d9b 940static void tegra_dc_disable_vblank(struct drm_crtc *crtc)
6e5ff998 941{
10437d9b 942 struct tegra_dc *dc = to_tegra_dc(crtc);
6e5ff998
TR		 943 unsigned long value, flags;
944
945 spin_lock_irqsave(&dc->lock, flags);
946
947 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
948 value &= ~VBLANK_INT;
949 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
950
951 spin_unlock_irqrestore(&dc->lock, flags);
952}
953
3c03c46a
TR		 954static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
955{
956 struct drm_device *drm = dc->base.dev;
957 struct drm_crtc *crtc = &dc->base;
3c03c46a 958 unsigned long flags, base;
de2ba664 959 struct tegra_bo *bo;
3c03c46a 960
6b59cc1c
TR		 961 spin_lock_irqsave(&drm->event_lock, flags);
962
963 if (!dc->event) {
964 spin_unlock_irqrestore(&drm->event_lock, flags);
3c03c46a 965 return;
6b59cc1c 966 }
3c03c46a 967
f4510a27 968 bo = tegra_fb_get_plane(crtc->primary->fb, 0);
3c03c46a 969
8643bc6d 970 spin_lock(&dc->lock);
93396d0f 971
3c03c46a 972 /* check if new start address has been latched */
93396d0f 973 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
3c03c46a
TR		 974 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
975 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
976 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
977
8643bc6d 978 spin_unlock(&dc->lock);
93396d0f 979
f4510a27 980 if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
ed7dae58
TR		 981 drm_crtc_send_vblank_event(crtc, dc->event);
982 drm_crtc_vblank_put(crtc);
3c03c46a 983 dc->event = NULL;
3c03c46a 984 }
6b59cc1c
TR		 985
986 spin_unlock_irqrestore(&drm->event_lock, flags);
3c03c46a
TR		 987}
988
f002abc1
TR		 989static void tegra_dc_destroy(struct drm_crtc *crtc)
990{
991 drm_crtc_cleanup(crtc);
f002abc1
TR		 992}
993
ca915b10
TR		 994static void tegra_crtc_reset(struct drm_crtc *crtc)
995{
996 struct tegra_dc_state *state;
997
3b59b7ac 998 if (crtc->state)
ec2dc6a0 999 __drm_atomic_helper_crtc_destroy_state(crtc->state);
3b59b7ac 1000
ca915b10
TR		 1001 kfree(crtc->state);
1002 crtc->state = NULL;
1003
1004 state = kzalloc(sizeof(*state), GFP_KERNEL);
332bbe70 1005 if (state) {
ca915b10 1006 crtc->state = &state->base;
332bbe70
TR		 1007 crtc->state->crtc = crtc;
1008 }
31930d4d
TR		 1009
1010 drm_crtc_vblank_reset(crtc);
ca915b10
TR		 1011}
1012
1013static struct drm_crtc_state *
1014tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1015{
1016 struct tegra_dc_state *state = to_dc_state(crtc->state);
1017 struct tegra_dc_state *copy;
1018
3b59b7ac 1019 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
ca915b10
TR		 1020 if (!copy)
1021 return NULL;
1022
3b59b7ac
TR		 1023 __drm_atomic_helper_crtc_duplicate_state(crtc, &copy->base);
1024 copy->clk = state->clk;
1025 copy->pclk = state->pclk;
1026 copy->div = state->div;
1027 copy->planes = state->planes;
ca915b10
TR		 1028
1029 return &copy->base;
1030}
1031
1032static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1033 struct drm_crtc_state *state)
1034{
ec2dc6a0 1035 __drm_atomic_helper_crtc_destroy_state(state);
ca915b10
TR		 1036 kfree(state);
1037}
1038
d8f4a9ed 1039static const struct drm_crtc_funcs tegra_crtc_funcs = {
1503ca47 1040 .page_flip = drm_atomic_helper_page_flip,
74f48791 1041 .set_config = drm_atomic_helper_set_config,
f002abc1 1042 .destroy = tegra_dc_destroy,
ca915b10
TR		 1043 .reset = tegra_crtc_reset,
1044 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1045 .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
10437d9b
SG		 1046 .get_vblank_counter = tegra_dc_get_vblank_counter,
1047 .enable_vblank = tegra_dc_enable_vblank,
1048 .disable_vblank = tegra_dc_disable_vblank,
d8f4a9ed
TR		 1049};
1050
d8f4a9ed
TR		 1051static int tegra_dc_set_timings(struct tegra_dc *dc,
1052 struct drm_display_mode *mode)
1053{
0444c0ff
TR		 1054 unsigned int h_ref_to_sync = 1;
1055 unsigned int v_ref_to_sync = 1;
d8f4a9ed
TR		 1056 unsigned long value;
1057
1058 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1059
1060 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1061 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1062
1063 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1064 ((mode->hsync_end - mode->hsync_start) << 0);
1065 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1066
d8f4a9ed
TR		 1067 value = ((mode->vtotal - mode->vsync_end) << 16) |
1068 ((mode->htotal - mode->hsync_end) << 0);
40495089
LS		 1069 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1070
1071 value = ((mode->vsync_start - mode->vdisplay) << 16) |
1072 ((mode->hsync_start - mode->hdisplay) << 0);
d8f4a9ed
TR		 1073 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1074
1075 value = (mode->vdisplay << 16) | mode->hdisplay;
1076 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1077
1078 return 0;
1079}
1080
9d910b60
TR		 1081/**
1082 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1083 * state
1084 * @dc: display controller
1085 * @crtc_state: CRTC atomic state
1086 * @clk: parent clock for display controller
1087 * @pclk: pixel clock
1088 * @div: shift clock divider
1089 *
1090 * Returns:
1091 * 0 on success or a negative error-code on failure.
1092 */
ca915b10
TR		 1093int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1094 struct drm_crtc_state *crtc_state,
1095 struct clk *clk, unsigned long pclk,
1096 unsigned int div)
1097{
1098 struct tegra_dc_state *state = to_dc_state(crtc_state);
1099
d2982748
TR		 1100 if (!clk_has_parent(dc->clk, clk))
1101 return -EINVAL;
1102
ca915b10
TR		 1103 state->clk = clk;
1104 state->pclk = pclk;
1105 state->div = div;
1106
1107 return 0;
1108}
1109
76d59ed0
TR		 1110static void tegra_dc_commit_state(struct tegra_dc *dc,
1111 struct tegra_dc_state *state)
1112{
1113 u32 value;
1114 int err;
1115
1116 err = clk_set_parent(dc->clk, state->clk);
1117 if (err < 0)
1118 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1119
1120 /*
1121 * Outputs may not want to change the parent clock rate. This is only
1122 * relevant to Tegra20 where only a single display PLL is available.
1123 * Since that PLL would typically be used for HDMI, an internal LVDS
1124 * panel would need to be driven by some other clock such as PLL_P
1125 * which is shared with other peripherals. Changing the clock rate
1126 * should therefore be avoided.
1127 */
1128 if (state->pclk > 0) {
1129 err = clk_set_rate(state->clk, state->pclk);
1130 if (err < 0)
1131 dev_err(dc->dev,
1132 "failed to set clock rate to %lu Hz\n",
1133 state->pclk);
1134 }
1135
1136 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1137 state->div);
1138 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1139
1140 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1141 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1142}
1143
003fc848
TR		 1144static void tegra_dc_stop(struct tegra_dc *dc)
1145{
1146 u32 value;
1147
1148 /* stop the display controller */
1149 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1150 value &= ~DISP_CTRL_MODE_MASK;
1151 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1152
1153 tegra_dc_commit(dc);
1154}
1155
1156static bool tegra_dc_idle(struct tegra_dc *dc)
1157{
1158 u32 value;
1159
1160 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1161
1162 return (value & DISP_CTRL_MODE_MASK) == 0;
1163}
1164
1165static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1166{
1167 timeout = jiffies + msecs_to_jiffies(timeout);
1168
1169 while (time_before(jiffies, timeout)) {
1170 if (tegra_dc_idle(dc))
1171 return 0;
1172
1173 usleep_range(1000, 2000);
1174 }
1175
1176 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1177 return -ETIMEDOUT;
1178}
1179
1180static void tegra_crtc_disable(struct drm_crtc *crtc)
1181{
1182 struct tegra_dc *dc = to_tegra_dc(crtc);
1183 u32 value;
1184
1185 if (!tegra_dc_idle(dc)) {
1186 tegra_dc_stop(dc);
1187
1188 /*
1189 * Ignore the return value, there isn't anything useful to do
1190 * in case this fails.
1191 */
1192 tegra_dc_wait_idle(dc, 100);
1193 }
1194
1195 /*
1196 * This should really be part of the RGB encoder driver, but clearing
1197 * these bits has the side-effect of stopping the display controller.
1198 * When that happens no VBLANK interrupts will be raised. At the same
1199 * time the encoder is disabled before the display controller, so the
1200 * above code is always going to timeout waiting for the controller
1201 * to go idle.
1202 *
1203 * Given the close coupling between the RGB encoder and the display
1204 * controller doing it here is still kind of okay. None of the other
1205 * encoder drivers require these bits to be cleared.
1206 *
1207 * XXX: Perhaps given that the display controller is switched off at
1208 * this point anyway maybe clearing these bits isn't even useful for
1209 * the RGB encoder?
1210 */
1211 if (dc->rgb) {
1212 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1213 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1214 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1215 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1216 }
1217
1218 tegra_dc_stats_reset(&dc->stats);
1219 drm_crtc_vblank_off(crtc);
33a8eb8d
TR		 1220
1221 pm_runtime_put_sync(dc->dev);
003fc848
TR		 1222}
1223
1224static void tegra_crtc_enable(struct drm_crtc *crtc)
d8f4a9ed 1225{
4aa3df71 1226 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
76d59ed0 1227 struct tegra_dc_state *state = to_dc_state(crtc->state);
d8f4a9ed 1228 struct tegra_dc *dc = to_tegra_dc(crtc);
dbb3f2f7 1229 u32 value;
d8f4a9ed 1230
33a8eb8d
TR		 1231 pm_runtime_get_sync(dc->dev);
1232
1233 /* initialize display controller */
1234 if (dc->syncpt) {
1235 u32 syncpt = host1x_syncpt_id(dc->syncpt);
1236
1237 value = SYNCPT_CNTRL_NO_STALL;
1238 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1239
1240 value = SYNCPT_VSYNC_ENABLE | syncpt;
1241 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1242 }
1243
1244 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1245 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1246 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1247
1248 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1249 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1250 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1251
1252 /* initialize timer */
1253 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1254 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1255 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1256
1257 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1258 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1259 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1260
1261 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1262 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1263 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1264
1265 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1266 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1267 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1268
1269 if (dc->soc->supports_border_color)
1270 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1271
1272 /* apply PLL and pixel clock changes */
76d59ed0
TR		 1273 tegra_dc_commit_state(dc, state);
1274
d8f4a9ed
TR		 1275 /* program display mode */
1276 tegra_dc_set_timings(dc, mode);
1277
8620fc62
TR		 1278 /* interlacing isn't supported yet, so disable it */
1279 if (dc->soc->supports_interlacing) {
1280 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1281 value &= ~INTERLACE_ENABLE;
1282 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1283 }
666cb873
TR		 1284
1285 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1286 value &= ~DISP_CTRL_MODE_MASK;
1287 value |= DISP_CTRL_MODE_C_DISPLAY;
1288 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1289
1290 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1291 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1292 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1293 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1294
1295 tegra_dc_commit(dc);
d8f4a9ed 1296
8ff64c17 1297 drm_crtc_vblank_on(crtc);
d8f4a9ed
TR		 1298}
1299
4aa3df71
TR		 1300static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
1301 struct drm_crtc_state *state)
1302{
1303 return 0;
1304}
1305
613d2b27
ML		 1306static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1307 struct drm_crtc_state *old_crtc_state)
4aa3df71 1308{
1503ca47
TR		 1309 struct tegra_dc *dc = to_tegra_dc(crtc);
1310
1311 if (crtc->state->event) {
1312 crtc->state->event->pipe = drm_crtc_index(crtc);
1313
1314 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1315
1316 dc->event = crtc->state->event;
1317 crtc->state->event = NULL;
1318 }
4aa3df71
TR		 1319}
1320
613d2b27
ML		 1321static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1322 struct drm_crtc_state *old_crtc_state)
4aa3df71 1323{
47802b09
TR		 1324 struct tegra_dc_state *state = to_dc_state(crtc->state);
1325 struct tegra_dc *dc = to_tegra_dc(crtc);
1326
1327 tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL);
1328 tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL);
4aa3df71
TR		 1329}
1330
d8f4a9ed 1331static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
f34bc787 1332 .disable = tegra_crtc_disable,
003fc848 1333 .enable = tegra_crtc_enable,
4aa3df71
TR		 1334 .atomic_check = tegra_crtc_atomic_check,
1335 .atomic_begin = tegra_crtc_atomic_begin,
1336 .atomic_flush = tegra_crtc_atomic_flush,
d8f4a9ed
TR		 1337};
1338
6e5ff998 1339static irqreturn_t tegra_dc_irq(int irq, void *data)
d8f4a9ed
TR		 1340{
1341 struct tegra_dc *dc = data;
1342 unsigned long status;
1343
1344 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1345 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1346
1347 if (status & FRAME_END_INT) {
1348 /*
1349 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1350 */
791ddb1e 1351 dc->stats.frames++;
d8f4a9ed
TR		 1352 }
1353
1354 if (status & VBLANK_INT) {
1355 /*
1356 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1357 */
ed7dae58 1358 drm_crtc_handle_vblank(&dc->base);
3c03c46a 1359 tegra_dc_finish_page_flip(dc);
791ddb1e 1360 dc->stats.vblank++;
d8f4a9ed
TR		 1361 }
1362
1363 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1364 /*
1365 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1366 */
791ddb1e
TR		 1367 dc->stats.underflow++;
1368 }
1369
1370 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
1371 /*
1372 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
1373 */
1374 dc->stats.overflow++;
d8f4a9ed
TR		 1375 }
1376
1377 return IRQ_HANDLED;
1378}
1379
1380static int tegra_dc_show_regs(struct seq_file *s, void *data)
1381{
1382 struct drm_info_node *node = s->private;
1383 struct tegra_dc *dc = node->info_ent->data;
003fc848
TR		 1384 int err = 0;
1385
99612b27 1386 drm_modeset_lock(&dc->base.mutex, NULL);
003fc848
TR		 1387
1388 if (!dc->base.state->active) {
1389 err = -EBUSY;
1390 goto unlock;
1391 }
d8f4a9ed
TR		 1392
1393#define DUMP_REG(name) \
03a60569 1394 seq_printf(s, "%-40s %#05x %08x\n", #name, name, \
d8f4a9ed
TR		 1395 tegra_dc_readl(dc, name))
1396
1397 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
1398 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1399 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
1400 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
1401 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
1402 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
1403 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
1404 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
1405 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
1406 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
1407 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
1408 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
1409 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
1410 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
1411 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
1412 DUMP_REG(DC_CMD_SIGNAL_RAISE);
1413 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
1414 DUMP_REG(DC_CMD_INT_STATUS);
1415 DUMP_REG(DC_CMD_INT_MASK);
1416 DUMP_REG(DC_CMD_INT_ENABLE);
1417 DUMP_REG(DC_CMD_INT_TYPE);
1418 DUMP_REG(DC_CMD_INT_POLARITY);
1419 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
1420 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
1421 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
1422 DUMP_REG(DC_CMD_STATE_ACCESS);
1423 DUMP_REG(DC_CMD_STATE_CONTROL);
1424 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
1425 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
1426 DUMP_REG(DC_COM_CRC_CONTROL);
1427 DUMP_REG(DC_COM_CRC_CHECKSUM);
1428 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1429 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1430 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1431 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1432 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1433 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1434 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1435 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1436 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1437 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1438 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1439 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1440 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1441 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1442 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1443 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1444 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1445 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1446 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1447 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1448 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1449 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1450 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1451 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1452 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1453 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
1454 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
1455 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
1456 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
1457 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
1458 DUMP_REG(DC_COM_SPI_CONTROL);
1459 DUMP_REG(DC_COM_SPI_START_BYTE);
1460 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
1461 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
1462 DUMP_REG(DC_COM_HSPI_CS_DC);
1463 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
1464 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
1465 DUMP_REG(DC_COM_GPIO_CTRL);
1466 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
1467 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
1468 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
1469 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
1470 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
1471 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
1472 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1473 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
1474 DUMP_REG(DC_DISP_REF_TO_SYNC);
1475 DUMP_REG(DC_DISP_SYNC_WIDTH);
1476 DUMP_REG(DC_DISP_BACK_PORCH);
1477 DUMP_REG(DC_DISP_ACTIVE);
1478 DUMP_REG(DC_DISP_FRONT_PORCH);
1479 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
1480 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
1481 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
1482 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
1483 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
1484 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
1485 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
1486 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
1487 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
1488 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
1489 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
1490 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
1491 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
1492 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
1493 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
1494 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
1495 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
1496 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
1497 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
1498 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
1499 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
1500 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
1501 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
1502 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
1503 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
1504 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
1505 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
1506 DUMP_REG(DC_DISP_M0_CONTROL);
1507 DUMP_REG(DC_DISP_M1_CONTROL);
1508 DUMP_REG(DC_DISP_DI_CONTROL);
1509 DUMP_REG(DC_DISP_PP_CONTROL);
1510 DUMP_REG(DC_DISP_PP_SELECT_A);
1511 DUMP_REG(DC_DISP_PP_SELECT_B);
1512 DUMP_REG(DC_DISP_PP_SELECT_C);
1513 DUMP_REG(DC_DISP_PP_SELECT_D);
1514 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
1515 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
1516 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
1517 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
1518 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
1519 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
1520 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
1521 DUMP_REG(DC_DISP_BORDER_COLOR);
1522 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
1523 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
1524 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
1525 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
1526 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
1527 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
1528 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
1529 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
1530 DUMP_REG(DC_DISP_CURSOR_POSITION);
1531 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
1532 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
1533 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
1534 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
1535 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
1536 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
1537 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
1538 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
1539 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
1540 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
1541 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
1542 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
1543 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
1544 DUMP_REG(DC_DISP_SD_CONTROL);
1545 DUMP_REG(DC_DISP_SD_CSC_COEFF);
1546 DUMP_REG(DC_DISP_SD_LUT(0));
1547 DUMP_REG(DC_DISP_SD_LUT(1));
1548 DUMP_REG(DC_DISP_SD_LUT(2));
1549 DUMP_REG(DC_DISP_SD_LUT(3));
1550 DUMP_REG(DC_DISP_SD_LUT(4));
1551 DUMP_REG(DC_DISP_SD_LUT(5));
1552 DUMP_REG(DC_DISP_SD_LUT(6));
1553 DUMP_REG(DC_DISP_SD_LUT(7));
1554 DUMP_REG(DC_DISP_SD_LUT(8));
1555 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
1556 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
1557 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1558 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1559 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1560 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1561 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1562 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1563 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1564 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1565 DUMP_REG(DC_DISP_SD_BL_TF(0));
1566 DUMP_REG(DC_DISP_SD_BL_TF(1));
1567 DUMP_REG(DC_DISP_SD_BL_TF(2));
1568 DUMP_REG(DC_DISP_SD_BL_TF(3));
1569 DUMP_REG(DC_DISP_SD_BL_CONTROL);
1570 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1571 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
e687651b
TR		 1572 DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
1573 DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL);
d8f4a9ed
TR		 1574 DUMP_REG(DC_WIN_WIN_OPTIONS);
1575 DUMP_REG(DC_WIN_BYTE_SWAP);
1576 DUMP_REG(DC_WIN_BUFFER_CONTROL);
1577 DUMP_REG(DC_WIN_COLOR_DEPTH);
1578 DUMP_REG(DC_WIN_POSITION);
1579 DUMP_REG(DC_WIN_SIZE);
1580 DUMP_REG(DC_WIN_PRESCALED_SIZE);
1581 DUMP_REG(DC_WIN_H_INITIAL_DDA);
1582 DUMP_REG(DC_WIN_V_INITIAL_DDA);
1583 DUMP_REG(DC_WIN_DDA_INC);
1584 DUMP_REG(DC_WIN_LINE_STRIDE);
1585 DUMP_REG(DC_WIN_BUF_STRIDE);
1586 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1587 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1588 DUMP_REG(DC_WIN_DV_CONTROL);
1589 DUMP_REG(DC_WIN_BLEND_NOKEY);
1590 DUMP_REG(DC_WIN_BLEND_1WIN);
1591 DUMP_REG(DC_WIN_BLEND_2WIN_X);
1592 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
f34bc787 1593 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
d8f4a9ed
TR		 1594 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1595 DUMP_REG(DC_WINBUF_START_ADDR);
1596 DUMP_REG(DC_WINBUF_START_ADDR_NS);
1597 DUMP_REG(DC_WINBUF_START_ADDR_U);
1598 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1599 DUMP_REG(DC_WINBUF_START_ADDR_V);
1600 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1601 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1602 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1603 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1604 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1605 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1606 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1607 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1608 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1609
1610#undef DUMP_REG
1611
003fc848 1612unlock:
99612b27 1613 drm_modeset_unlock(&dc->base.mutex);
003fc848 1614 return err;
d8f4a9ed
TR		 1615}
1616
6ca1f62f
TR		 1617static int tegra_dc_show_crc(struct seq_file *s, void *data)
1618{
1619 struct drm_info_node *node = s->private;
1620 struct tegra_dc *dc = node->info_ent->data;
003fc848 1621 int err = 0;
6ca1f62f
TR		 1622 u32 value;
1623
99612b27 1624 drm_modeset_lock(&dc->base.mutex, NULL);
003fc848
TR		 1625
1626 if (!dc->base.state->active) {
1627 err = -EBUSY;
1628 goto unlock;
1629 }
1630
6ca1f62f
TR		 1631 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1632 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1633 tegra_dc_commit(dc);
1634
1635 drm_crtc_wait_one_vblank(&dc->base);
1636 drm_crtc_wait_one_vblank(&dc->base);
1637
1638 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1639 seq_printf(s, "%08x\n", value);
1640
1641 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1642
003fc848 1643unlock:
99612b27 1644 drm_modeset_unlock(&dc->base.mutex);
003fc848 1645 return err;
6ca1f62f
TR		 1646}
1647
791ddb1e
TR		 1648static int tegra_dc_show_stats(struct seq_file *s, void *data)
1649{
1650 struct drm_info_node *node = s->private;
1651 struct tegra_dc *dc = node->info_ent->data;
1652
1653 seq_printf(s, "frames: %lu\n", dc->stats.frames);
1654 seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1655 seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1656 seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1657
d8f4a9ed
TR		 1658 return 0;
1659}
1660
1661static struct drm_info_list debugfs_files[] = {
1662 { "regs", tegra_dc_show_regs, 0, NULL },
6ca1f62f 1663 { "crc", tegra_dc_show_crc, 0, NULL },
791ddb1e 1664 { "stats", tegra_dc_show_stats, 0, NULL },
d8f4a9ed
TR		 1665};
1666
1667static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1668{
1669 unsigned int i;
1670 char *name;
1671 int err;
1672
1673 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1674 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1675 kfree(name);
1676
1677 if (!dc->debugfs)
1678 return -ENOMEM;
1679
1680 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1681 GFP_KERNEL);
1682 if (!dc->debugfs_files) {
1683 err = -ENOMEM;
1684 goto remove;
1685 }
1686
1687 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1688 dc->debugfs_files[i].data = dc;
1689
1690 err = drm_debugfs_create_files(dc->debugfs_files,
1691 ARRAY_SIZE(debugfs_files),
1692 dc->debugfs, minor);
1693 if (err < 0)
1694 goto free;
1695
1696 dc->minor = minor;
1697
1698 return 0;
1699
1700free:
1701 kfree(dc->debugfs_files);
1702 dc->debugfs_files = NULL;
1703remove:
1704 debugfs_remove(dc->debugfs);
1705 dc->debugfs = NULL;
1706
1707 return err;
1708}
1709
1710static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1711{
1712 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1713 dc->minor);
1714 dc->minor = NULL;
1715
1716 kfree(dc->debugfs_files);
1717 dc->debugfs_files = NULL;
1718
1719 debugfs_remove(dc->debugfs);
1720 dc->debugfs = NULL;
1721
1722 return 0;
1723}
1724
53fa7f72 1725static int tegra_dc_init(struct host1x_client *client)
d8f4a9ed 1726{
9910f5c4 1727 struct drm_device *drm = dev_get_drvdata(client->parent);
2bcdcbfa 1728 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
776dc384 1729 struct tegra_dc *dc = host1x_client_to_dc(client);
d1f3e1e0 1730 struct tegra_drm *tegra = drm->dev_private;
c7679306
TR		 1731 struct drm_plane *primary = NULL;
1732 struct drm_plane *cursor = NULL;
d8f4a9ed
TR		 1733 int err;
1734
2bcdcbfa
TR		 1735 dc->syncpt = host1x_syncpt_request(dc->dev, flags);
1736 if (!dc->syncpt)
1737 dev_warn(dc->dev, "failed to allocate syncpoint\n");
1738
df06b759
TR		 1739 if (tegra->domain) {
1740 err = iommu_attach_device(tegra->domain, dc->dev);
1741 if (err < 0) {
1742 dev_err(dc->dev, "failed to attach to domain: %d\n",
1743 err);
1744 return err;
1745 }
1746
1747 dc->domain = tegra->domain;
1748 }
1749
c7679306
TR		 1750 primary = tegra_dc_primary_plane_create(drm, dc);
1751 if (IS_ERR(primary)) {
1752 err = PTR_ERR(primary);
1753 goto cleanup;
1754 }
1755
1756 if (dc->soc->supports_cursor) {
1757 cursor = tegra_dc_cursor_plane_create(drm, dc);
1758 if (IS_ERR(cursor)) {
1759 err = PTR_ERR(cursor);
1760 goto cleanup;
1761 }
1762 }
1763
1764 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
f9882876 1765 &tegra_crtc_funcs, NULL);
c7679306
TR		 1766 if (err < 0)
1767 goto cleanup;
1768
d8f4a9ed
TR		 1769 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1770
d1f3e1e0
TR		 1771 /*
1772 * Keep track of the minimum pitch alignment across all display
1773 * controllers.
1774 */
1775 if (dc->soc->pitch_align > tegra->pitch_align)
1776 tegra->pitch_align = dc->soc->pitch_align;
1777
9910f5c4 1778 err = tegra_dc_rgb_init(drm, dc);
d8f4a9ed
TR		 1779 if (err < 0 && err != -ENODEV) {
1780 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
c7679306 1781 goto cleanup;
d8f4a9ed
TR		 1782 }
1783
9910f5c4 1784 err = tegra_dc_add_planes(drm, dc);
f34bc787 1785 if (err < 0)
c7679306 1786 goto cleanup;
f34bc787 1787
d8f4a9ed 1788 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
9910f5c4 1789 err = tegra_dc_debugfs_init(dc, drm->primary);
d8f4a9ed
TR		 1790 if (err < 0)
1791 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1792 }
1793
6e5ff998 1794 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
d8f4a9ed
TR		 1795 dev_name(dc->dev), dc);
1796 if (err < 0) {
1797 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1798 err);
c7679306 1799 goto cleanup;
d8f4a9ed
TR		 1800 }
1801
1802 return 0;
c7679306
TR		 1803
1804cleanup:
1805 if (cursor)
1806 drm_plane_cleanup(cursor);
1807
1808 if (primary)
1809 drm_plane_cleanup(primary);
1810
1811 if (tegra->domain) {
1812 iommu_detach_device(tegra->domain, dc->dev);
1813 dc->domain = NULL;
1814 }
1815
1816 return err;
d8f4a9ed
TR		 1817}
1818
53fa7f72 1819static int tegra_dc_exit(struct host1x_client *client)
d8f4a9ed 1820{
776dc384 1821 struct tegra_dc *dc = host1x_client_to_dc(client);
d8f4a9ed
TR		 1822 int err;
1823
1824 devm_free_irq(dc->dev, dc->irq, dc);
1825
1826 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1827 err = tegra_dc_debugfs_exit(dc);
1828 if (err < 0)
1829 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1830 }
1831
1832 err = tegra_dc_rgb_exit(dc);
1833 if (err) {
1834 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1835 return err;
1836 }
1837
df06b759
TR		 1838 if (dc->domain) {
1839 iommu_detach_device(dc->domain, dc->dev);
1840 dc->domain = NULL;
1841 }
1842
2bcdcbfa
TR		 1843 host1x_syncpt_free(dc->syncpt);
1844
d8f4a9ed
TR		 1845 return 0;
1846}
1847
1848static const struct host1x_client_ops dc_client_ops = {
53fa7f72
TR		 1849 .init = tegra_dc_init,
1850 .exit = tegra_dc_exit,
d8f4a9ed
TR		 1851};
1852
8620fc62 1853static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
42d0659b 1854 .supports_border_color = true,
8620fc62 1855 .supports_interlacing = false,
e687651b 1856 .supports_cursor = false,
c134f019 1857 .supports_block_linear = false,
d1f3e1e0 1858 .pitch_align = 8,
9c012700 1859 .has_powergate = false,
6ac1571b 1860 .broken_reset = true,
8620fc62
TR		 1861};
1862
1863static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
42d0659b 1864 .supports_border_color = true,
8620fc62 1865 .supports_interlacing = false,
e687651b 1866 .supports_cursor = false,
c134f019 1867 .supports_block_linear = false,
d1f3e1e0 1868 .pitch_align = 8,
9c012700 1869 .has_powergate = false,
6ac1571b 1870 .broken_reset = false,
d1f3e1e0
TR		 1871};
1872
1873static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
42d0659b 1874 .supports_border_color = true,
d1f3e1e0
TR		 1875 .supports_interlacing = false,
1876 .supports_cursor = false,
1877 .supports_block_linear = false,
1878 .pitch_align = 64,
9c012700 1879 .has_powergate = true,
6ac1571b 1880 .broken_reset = false,
8620fc62
TR		 1881};
1882
1883static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
42d0659b 1884 .supports_border_color = false,
8620fc62 1885 .supports_interlacing = true,
e687651b 1886 .supports_cursor = true,
c134f019 1887 .supports_block_linear = true,
d1f3e1e0 1888 .pitch_align = 64,
9c012700 1889 .has_powergate = true,
6ac1571b 1890 .broken_reset = false,
8620fc62
TR		 1891};
1892
5b4f516f
TR		 1893static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
1894 .supports_border_color = false,
1895 .supports_interlacing = true,
1896 .supports_cursor = true,
1897 .supports_block_linear = true,
1898 .pitch_align = 64,
1899 .has_powergate = true,
6ac1571b 1900 .broken_reset = false,
5b4f516f
TR		 1901};
1902
8620fc62
TR		 1903static const struct of_device_id tegra_dc_of_match[] = {
1904 {
5b4f516f
TR		 1905 .compatible = "nvidia,tegra210-dc",
1906 .data = &tegra210_dc_soc_info,
1907 }, {
8620fc62
TR		 1908 .compatible = "nvidia,tegra124-dc",
1909 .data = &tegra124_dc_soc_info,
9c012700
TR		 1910 }, {
1911 .compatible = "nvidia,tegra114-dc",
1912 .data = &tegra114_dc_soc_info,
8620fc62
TR		 1913 }, {
1914 .compatible = "nvidia,tegra30-dc",
1915 .data = &tegra30_dc_soc_info,
1916 }, {
1917 .compatible = "nvidia,tegra20-dc",
1918 .data = &tegra20_dc_soc_info,
1919 }, {
1920 /* sentinel */
1921 }
1922};
ef70728c 1923MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
8620fc62 1924
13411ddd
TR		 1925static int tegra_dc_parse_dt(struct tegra_dc *dc)
1926{
1927 struct device_node *np;
1928 u32 value = 0;
1929 int err;
1930
1931 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1932 if (err < 0) {
1933 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1934
1935 /*
1936 * If the nvidia,head property isn't present, try to find the
1937 * correct head number by looking up the position of this
1938 * display controller's node within the device tree. Assuming
1939 * that the nodes are ordered properly in the DTS file and
1940 * that the translation into a flattened device tree blob
1941 * preserves that ordering this will actually yield the right
1942 * head number.
1943 *
1944 * If those assumptions don't hold, this will still work for
1945 * cases where only a single display controller is used.
1946 */
1947 for_each_matching_node(np, tegra_dc_of_match) {
cf6b1744
JL		 1948 if (np == dc->dev->of_node) {
1949 of_node_put(np);
13411ddd 1950 break;
cf6b1744 1951 }
13411ddd
TR		 1952
1953 value++;
1954 }
1955 }
1956
1957 dc->pipe = value;
1958
1959 return 0;
1960}
1961
d8f4a9ed
TR		 1962static int tegra_dc_probe(struct platform_device *pdev)
1963{
8620fc62 1964 const struct of_device_id *id;
d8f4a9ed
TR		 1965 struct resource *regs;
1966 struct tegra_dc *dc;
1967 int err;
1968
1969 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1970 if (!dc)
1971 return -ENOMEM;
1972
8620fc62
TR		 1973 id = of_match_node(tegra_dc_of_match, pdev->dev.of_node);
1974 if (!id)
1975 return -ENODEV;
1976
6e5ff998 1977 spin_lock_init(&dc->lock);
d8f4a9ed
TR		 1978 INIT_LIST_HEAD(&dc->list);
1979 dc->dev = &pdev->dev;
8620fc62 1980 dc->soc = id->data;
d8f4a9ed 1981
13411ddd
TR		 1982 err = tegra_dc_parse_dt(dc);
1983 if (err < 0)
1984 return err;
1985
d8f4a9ed
TR		 1986 dc->clk = devm_clk_get(&pdev->dev, NULL);
1987 if (IS_ERR(dc->clk)) {
1988 dev_err(&pdev->dev, "failed to get clock\n");
1989 return PTR_ERR(dc->clk);
1990 }
1991
ca48080a
SW		 1992 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1993 if (IS_ERR(dc->rst)) {
1994 dev_err(&pdev->dev, "failed to get reset\n");
1995 return PTR_ERR(dc->rst);
1996 }
1997
6ac1571b
DO		 1998 if (!dc->soc->broken_reset)
1999 reset_control_assert(dc->rst);
33a8eb8d 2000
9c012700
TR		 2001 if (dc->soc->has_powergate) {
2002 if (dc->pipe == 0)
2003 dc->powergate = TEGRA_POWERGATE_DIS;
2004 else
2005 dc->powergate = TEGRA_POWERGATE_DISB;
2006
33a8eb8d 2007 tegra_powergate_power_off(dc->powergate);
9c012700 2008 }
d8f4a9ed
TR		 2009
2010 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d4ed6025
TR		 2011 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
2012 if (IS_ERR(dc->regs))
2013 return PTR_ERR(dc->regs);
d8f4a9ed
TR		 2014
2015 dc->irq = platform_get_irq(pdev, 0);
2016 if (dc->irq < 0) {
2017 dev_err(&pdev->dev, "failed to get IRQ\n");
2018 return -ENXIO;
2019 }
2020
d8f4a9ed
TR		 2021 err = tegra_dc_rgb_probe(dc);
2022 if (err < 0 && err != -ENODEV) {
2023 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
2024 return err;
2025 }
2026
33a8eb8d
TR		 2027 platform_set_drvdata(pdev, dc);
2028 pm_runtime_enable(&pdev->dev);
2029
2030 INIT_LIST_HEAD(&dc->client.list);
2031 dc->client.ops = &dc_client_ops;
2032 dc->client.dev = &pdev->dev;
2033
776dc384 2034 err = host1x_client_register(&dc->client);
d8f4a9ed
TR		 2035 if (err < 0) {
2036 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2037 err);
2038 return err;
2039 }
2040
d8f4a9ed
TR		 2041 return 0;
2042}
2043
2044static int tegra_dc_remove(struct platform_device *pdev)
2045{
d8f4a9ed
TR		 2046 struct tegra_dc *dc = platform_get_drvdata(pdev);
2047 int err;
2048
776dc384 2049 err = host1x_client_unregister(&dc->client);
d8f4a9ed
TR		 2050 if (err < 0) {
2051 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2052 err);
2053 return err;
2054 }
2055
59d29c0e
TR		 2056 err = tegra_dc_rgb_remove(dc);
2057 if (err < 0) {
2058 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2059 return err;
2060 }
2061
33a8eb8d
TR		 2062 pm_runtime_disable(&pdev->dev);
2063
2064 return 0;
2065}
2066
2067#ifdef CONFIG_PM
2068static int tegra_dc_suspend(struct device *dev)
2069{
2070 struct tegra_dc *dc = dev_get_drvdata(dev);
2071 int err;
2072
6ac1571b
DO		 2073 if (!dc->soc->broken_reset) {
2074 err = reset_control_assert(dc->rst);
2075 if (err < 0) {
2076 dev_err(dev, "failed to assert reset: %d\n", err);
2077 return err;
2078 }
33a8eb8d 2079 }
9c012700
TR		 2080
2081 if (dc->soc->has_powergate)
2082 tegra_powergate_power_off(dc->powergate);
2083
d8f4a9ed
TR		 2084 clk_disable_unprepare(dc->clk);
2085
2086 return 0;
2087}
2088
33a8eb8d
TR		 2089static int tegra_dc_resume(struct device *dev)
2090{
2091 struct tegra_dc *dc = dev_get_drvdata(dev);
2092 int err;
2093
2094 if (dc->soc->has_powergate) {
2095 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2096 dc->rst);
2097 if (err < 0) {
2098 dev_err(dev, "failed to power partition: %d\n", err);
2099 return err;
2100 }
2101 } else {
2102 err = clk_prepare_enable(dc->clk);
2103 if (err < 0) {
2104 dev_err(dev, "failed to enable clock: %d\n", err);
2105 return err;
2106 }
2107
6ac1571b
DO		 2108 if (!dc->soc->broken_reset) {
2109 err = reset_control_deassert(dc->rst);
2110 if (err < 0) {
2111 dev_err(dev,
2112 "failed to deassert reset: %d\n", err);
2113 return err;
2114 }
33a8eb8d
TR		 2115 }
2116 }
2117
2118 return 0;
2119}
2120#endif
2121
2122static const struct dev_pm_ops tegra_dc_pm_ops = {
2123 SET_RUNTIME_PM_OPS(tegra_dc_suspend, tegra_dc_resume, NULL)
2124};
2125
d8f4a9ed
TR		 2126struct platform_driver tegra_dc_driver = {
2127 .driver = {
2128 .name = "tegra-dc",
d8f4a9ed 2129 .of_match_table = tegra_dc_of_match,
33a8eb8d 2130 .pm = &tegra_dc_pm_ops,
d8f4a9ed
TR		 2131 },
2132 .probe = tegra_dc_probe,
2133 .remove = tegra_dc_remove,
2134};
Linux 6.x block layer and io_uring tree(s)