[linux-block.git] / drivers / gpu / drm / sun4i / sun8i_mixer.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
 */

#ifndef _SUN8I_MIXER_H_
#define _SUN8I_MIXER_H_

#include <linux/clk.h>
#include <linux/regmap.h>
#include <linux/reset.h>

#include "sun8i_csc.h"
#include "sunxi_engine.h"

#define SUN8I_MIXER_SIZE(w, h)			(((h) - 1) << 16 | ((w) - 1))
#define SUN8I_MIXER_COORD(x, y)			((y) << 16 | (x))

#define SUN8I_MIXER_GLOBAL_CTL			0x0
#define SUN8I_MIXER_GLOBAL_STATUS		0x4
#define SUN8I_MIXER_GLOBAL_DBUFF		0x8
#define SUN8I_MIXER_GLOBAL_SIZE			0xc

#define SUN8I_MIXER_GLOBAL_CTL_RT_EN		BIT(0)

#define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE		BIT(0)

#define DE2_MIXER_UNIT_SIZE			0x6000
#define DE3_MIXER_UNIT_SIZE			0x3000

#define DE2_BLD_BASE				0x1000
#define DE2_CH_BASE				0x2000
#define DE2_CH_SIZE				0x1000

#define DE3_BLD_BASE				0x0800
#define DE3_CH_BASE				0x1000
#define DE3_CH_SIZE				0x0800

#define SUN8I_MIXER_BLEND_PIPE_CTL(base)	((base) + 0)
#define SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, x)	((base) + 0x4 + 0x10 * (x))
#define SUN8I_MIXER_BLEND_ATTR_INSIZE(base, x)	((base) + 0x8 + 0x10 * (x))
#define SUN8I_MIXER_BLEND_ATTR_COORD(base, x)	((base) + 0xc + 0x10 * (x))
#define SUN8I_MIXER_BLEND_ROUTE(base)		((base) + 0x80)
#define SUN8I_MIXER_BLEND_PREMULTIPLY(base)	((base) + 0x84)
#define SUN8I_MIXER_BLEND_BKCOLOR(base)		((base) + 0x88)
#define SUN8I_MIXER_BLEND_OUTSIZE(base)		((base) + 0x8c)
#define SUN8I_MIXER_BLEND_MODE(base, x)		((base) + 0x90 + 0x04 * (x))
#define SUN8I_MIXER_BLEND_CK_CTL(base)		((base) + 0xb0)
#define SUN8I_MIXER_BLEND_CK_CFG(base)		((base) + 0xb4)
#define SUN8I_MIXER_BLEND_CK_MAX(base, x)	((base) + 0xc0 + 0x04 * (x))
#define SUN8I_MIXER_BLEND_CK_MIN(base, x)	((base) + 0xe0 + 0x04 * (x))
#define SUN8I_MIXER_BLEND_OUTCTL(base)		((base) + 0xfc)
#define SUN50I_MIXER_BLEND_CSC_CTL(base)	((base) + 0x100)
#define SUN50I_MIXER_BLEND_CSC_COEFF(base, layer, x, y) \
	((base) + 0x110 + (layer) * 0x30 +  (x) * 0x10 + 4 * (y))
#define SUN50I_MIXER_BLEND_CSC_CONST(base, layer, i) \
	((base) + 0x110 + (layer) * 0x30 +  (i) * 0x10 + 0x0c)

#define SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK	GENMASK(12, 8)
#define SUN8I_MIXER_BLEND_PIPE_CTL_EN(pipe)	BIT(8 + pipe)
#define SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(pipe)	BIT(pipe)

/* colors are always in AARRGGBB format */
#define SUN8I_MIXER_BLEND_COLOR_BLACK		0xff000000
/* The following numbers are some still unknown magic numbers */
#define SUN8I_MIXER_BLEND_MODE_DEF		0x03010301

#define SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(n)	(0xf << ((n) << 2))
#define SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(n)	((n) << 2)

#define SUN8I_MIXER_BLEND_OUTCTL_INTERLACED	BIT(1)

#define SUN50I_MIXER_BLEND_CSC_CTL_EN(ch)	BIT(ch)
#define SUN50I_MIXER_BLEND_CSC_CONST_VAL(d, c)	(((d) << 16) | ((c) & 0xffff))

#define SUN8I_MIXER_FBFMT_ARGB8888	0
#define SUN8I_MIXER_FBFMT_ABGR8888	1
#define SUN8I_MIXER_FBFMT_RGBA8888	2
#define SUN8I_MIXER_FBFMT_BGRA8888	3
#define SUN8I_MIXER_FBFMT_XRGB8888	4
#define SUN8I_MIXER_FBFMT_XBGR8888	5
#define SUN8I_MIXER_FBFMT_RGBX8888	6
#define SUN8I_MIXER_FBFMT_BGRX8888	7
#define SUN8I_MIXER_FBFMT_RGB888	8
#define SUN8I_MIXER_FBFMT_BGR888	9
#define SUN8I_MIXER_FBFMT_RGB565	10
#define SUN8I_MIXER_FBFMT_BGR565	11
#define SUN8I_MIXER_FBFMT_ARGB4444	12
#define SUN8I_MIXER_FBFMT_ABGR4444	13
#define SUN8I_MIXER_FBFMT_RGBA4444	14
#define SUN8I_MIXER_FBFMT_BGRA4444	15
#define SUN8I_MIXER_FBFMT_ARGB1555	16
#define SUN8I_MIXER_FBFMT_ABGR1555	17
#define SUN8I_MIXER_FBFMT_RGBA5551	18
#define SUN8I_MIXER_FBFMT_BGRA5551	19
#define SUN8I_MIXER_FBFMT_ARGB2101010	20
#define SUN8I_MIXER_FBFMT_ABGR2101010	21
#define SUN8I_MIXER_FBFMT_RGBA1010102	22
#define SUN8I_MIXER_FBFMT_BGRA1010102	23

#define SUN8I_MIXER_FBFMT_YUYV		0
#define SUN8I_MIXER_FBFMT_UYVY		1
#define SUN8I_MIXER_FBFMT_YVYU		2
#define SUN8I_MIXER_FBFMT_VYUY		3
#define SUN8I_MIXER_FBFMT_NV16		4
#define SUN8I_MIXER_FBFMT_NV61		5
#define SUN8I_MIXER_FBFMT_YUV422	6
/* format 7 doesn't exist */
#define SUN8I_MIXER_FBFMT_NV12		8
#define SUN8I_MIXER_FBFMT_NV21		9
#define SUN8I_MIXER_FBFMT_YUV420	10
/* format 11 doesn't exist */
/* format 12 is semi-planar YUV411 UVUV */
/* format 13 is semi-planar YUV411 VUVU */
#define SUN8I_MIXER_FBFMT_YUV411	14
/* format 15 doesn't exist */
/* format 16 is P010 YVU */
#define SUN8I_MIXER_FBFMT_P010_YUV	17
/* format 18 is P210 YVU */
#define SUN8I_MIXER_FBFMT_P210_YUV	19
/* format 20 is packed YVU444 10-bit */
/* format 21 is packed YUV444 10-bit */

/*
 * Sub-engines listed bellow are unused for now. The EN registers are here only
 * to be used to disable these sub-engines.
 */
#define SUN8I_MIXER_FCE_EN			0xa0000
#define SUN8I_MIXER_BWS_EN			0xa2000
#define SUN8I_MIXER_LTI_EN			0xa4000
#define SUN8I_MIXER_PEAK_EN			0xa6000
#define SUN8I_MIXER_ASE_EN			0xa8000
#define SUN8I_MIXER_FCC_EN			0xaa000
#define SUN8I_MIXER_DCSC_EN			0xb0000

#define SUN50I_MIXER_FCE_EN			0x70000
#define SUN50I_MIXER_PEAK_EN			0x70800
#define SUN50I_MIXER_LCTI_EN			0x71000
#define SUN50I_MIXER_BLS_EN			0x71800
#define SUN50I_MIXER_FCC_EN			0x72000
#define SUN50I_MIXER_DNS_EN			0x80000
#define SUN50I_MIXER_DRC_EN			0xa0000
#define SUN50I_MIXER_FMT_EN			0xa8000
#define SUN50I_MIXER_CDC0_EN			0xd0000
#define SUN50I_MIXER_CDC1_EN			0xd8000

struct de2_fmt_info {
	u32			drm_fmt;
	u32			de2_fmt;
	bool			rgb;
	enum sun8i_csc_mode	csc;
};

/**
 * struct sun8i_mixer_cfg - mixer HW configuration
 * @vi_num: number of VI channels
 * @ui_num: number of UI channels
 * @scaler_mask: bitmask which tells which channel supports scaling
 *	First, scaler supports for VI channels is defined and after that, scaler
 *	support for UI channels. For example, if mixer has 2 VI channels without
 *	scaler and 2 UI channels with scaler, bitmask would be 0xC.
 * @ccsc: select set of CCSC base addresses
 *	Set value to 0 if this is first mixer or second mixer with VEP support.
 *	Set value to 1 if this is second mixer without VEP support. Other values
 *	are invalid.
 * @mod_rate: module clock rate that needs to be set in order to have
 *	a functional block.
 * @is_de3: true, if this is next gen display engine 3.0, false otherwise.
 * @scaline_yuv: size of a scanline for VI scaler for YUV formats.
 */
struct sun8i_mixer_cfg {
	int		vi_num;
	int		ui_num;
	int		scaler_mask;
	int		ccsc;
	unsigned long	mod_rate;
	unsigned int	is_de3 : 1;
	unsigned int	scanline_yuv;
};

struct sun8i_mixer {
	struct sunxi_engine		engine;

	const struct sun8i_mixer_cfg	*cfg;

	struct reset_control		*reset;

	struct clk			*bus_clk;
	struct clk			*mod_clk;
};

static inline struct sun8i_mixer *
engine_to_sun8i_mixer(struct sunxi_engine *engine)
{
	return container_of(engine, struct sun8i_mixer, engine);
}

static inline u32
sun8i_blender_base(struct sun8i_mixer *mixer)
{
	return mixer->cfg->is_de3 ? DE3_BLD_BASE : DE2_BLD_BASE;
}

static inline u32
sun8i_channel_base(struct sun8i_mixer *mixer, int channel)
{
	if (mixer->cfg->is_de3)
		return DE3_CH_BASE + channel * DE3_CH_SIZE;
	else
		return DE2_CH_BASE + channel * DE2_CH_SIZE;
}

const struct de2_fmt_info *sun8i_mixer_format_info(u32 format);
#endif /* _SUN8I_MIXER_H_ */
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
9d75b8c0 IZ	2	/*
9d75b8c0 IZ	3	* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
9d75b8c0 IZ	4	*/
	5
	6	#ifndef _SUN8I_MIXER_H_
	7	#define _SUN8I_MIXER_H_
	8
	9	#include <linux/clk.h>
	10	#include <linux/regmap.h>
	11	#include <linux/reset.h>
	12
60a3dcf9	13	#include "sun8i_csc.h"
9d75b8c0 IZ	14	#include "sunxi_engine.h"
9d75b8c0 IZ	15
9d75b8c0 IZ	16	#define SUN8I_MIXER_SIZE(w, h) (((h) - 1) << 16 \| ((w) - 1))
	17	#define SUN8I_MIXER_COORD(x, y) ((y) << 16 \| (x))
	18
	19	#define SUN8I_MIXER_GLOBAL_CTL 0x0
	20	#define SUN8I_MIXER_GLOBAL_STATUS 0x4
	21	#define SUN8I_MIXER_GLOBAL_DBUFF 0x8
	22	#define SUN8I_MIXER_GLOBAL_SIZE 0xc
	23
bb940be7	24	#define SUN8I_MIXER_GLOBAL_CTL_RT_EN BIT(0)
9d75b8c0	25
bb940be7	26	#define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE BIT(0)
9d75b8c0	27
218d6a3c	28	#define DE2_MIXER_UNIT_SIZE 0x6000
c50519e6	29	#define DE3_MIXER_UNIT_SIZE 0x3000
218d6a3c	30
4b09c073 JS	31	#define DE2_BLD_BASE 0x1000
	32	#define DE2_CH_BASE 0x2000
	33	#define DE2_CH_SIZE 0x1000
	34
c50519e6 JS	35	#define DE3_BLD_BASE 0x0800
	36	#define DE3_CH_BASE 0x1000
	37	#define DE3_CH_SIZE 0x0800
	38
4b09c073 JS	39	#define SUN8I_MIXER_BLEND_PIPE_CTL(base) ((base) + 0)
	40	#define SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, x) ((base) + 0x4 + 0x10 * (x))
	41	#define SUN8I_MIXER_BLEND_ATTR_INSIZE(base, x) ((base) + 0x8 + 0x10 * (x))
	42	#define SUN8I_MIXER_BLEND_ATTR_COORD(base, x) ((base) + 0xc + 0x10 * (x))
	43	#define SUN8I_MIXER_BLEND_ROUTE(base) ((base) + 0x80)
	44	#define SUN8I_MIXER_BLEND_PREMULTIPLY(base) ((base) + 0x84)
	45	#define SUN8I_MIXER_BLEND_BKCOLOR(base) ((base) + 0x88)
	46	#define SUN8I_MIXER_BLEND_OUTSIZE(base) ((base) + 0x8c)
	47	#define SUN8I_MIXER_BLEND_MODE(base, x) ((base) + 0x90 + 0x04 * (x))
	48	#define SUN8I_MIXER_BLEND_CK_CTL(base) ((base) + 0xb0)
	49	#define SUN8I_MIXER_BLEND_CK_CFG(base) ((base) + 0xb4)
	50	#define SUN8I_MIXER_BLEND_CK_MAX(base, x) ((base) + 0xc0 + 0x04 * (x))
	51	#define SUN8I_MIXER_BLEND_CK_MIN(base, x) ((base) + 0xe0 + 0x04 * (x))
	52	#define SUN8I_MIXER_BLEND_OUTCTL(base) ((base) + 0xfc)
c50519e6 JS	53	#define SUN50I_MIXER_BLEND_CSC_CTL(base) ((base) + 0x100)
	54	#define SUN50I_MIXER_BLEND_CSC_COEFF(base, layer, x, y) \
	55	((base) + 0x110 + (layer) * 0x30 + (x) * 0x10 + 4 * (y))
	56	#define SUN50I_MIXER_BLEND_CSC_CONST(base, layer, i) \
	57	((base) + 0x110 + (layer) * 0x30 + (i) * 0x10 + 0x0c)
9d75b8c0	58
f88c5ee7	59	#define SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK GENMASK(12, 8)
bb940be7 JS	60	#define SUN8I_MIXER_BLEND_PIPE_CTL_EN(pipe) BIT(8 + pipe)
bb940be7 JS	61	#define SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(pipe) BIT(pipe)
c50519e6	62
2f4cffe4 JS	63	/* colors are always in AARRGGBB format */
2f4cffe4 JS	64	#define SUN8I_MIXER_BLEND_COLOR_BLACK 0xff000000
9d75b8c0	65	/* The following numbers are some still unknown magic numbers */
9d75b8c0	66	#define SUN8I_MIXER_BLEND_MODE_DEF 0x03010301
9d75b8c0	67
f88c5ee7 JS	68	#define SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(n) (0xf << ((n) << 2))
	69	#define SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(n) ((n) << 2)
	70
9d75b8c0 IZ	71	#define SUN8I_MIXER_BLEND_OUTCTL_INTERLACED BIT(1)
9d75b8c0 IZ	72
c50519e6 JS	73	#define SUN50I_MIXER_BLEND_CSC_CTL_EN(ch) BIT(ch)
	74	#define SUN50I_MIXER_BLEND_CSC_CONST_VAL(d, c) (((d) << 16) \| ((c) & 0xffff))
	75
cbd2b690	76	#define SUN8I_MIXER_FBFMT_ARGB8888 0
fba4955e JS	77	#define SUN8I_MIXER_FBFMT_ABGR8888 1
	78	#define SUN8I_MIXER_FBFMT_RGBA8888 2
	79	#define SUN8I_MIXER_FBFMT_BGRA8888 3
cbd2b690	80	#define SUN8I_MIXER_FBFMT_XRGB8888 4
fba4955e JS	81	#define SUN8I_MIXER_FBFMT_XBGR8888 5
	82	#define SUN8I_MIXER_FBFMT_RGBX8888 6
	83	#define SUN8I_MIXER_FBFMT_BGRX8888 7
cbd2b690	84	#define SUN8I_MIXER_FBFMT_RGB888 8
fba4955e JS	85	#define SUN8I_MIXER_FBFMT_BGR888 9
	86	#define SUN8I_MIXER_FBFMT_RGB565 10
	87	#define SUN8I_MIXER_FBFMT_BGR565 11
	88	#define SUN8I_MIXER_FBFMT_ARGB4444 12
	89	#define SUN8I_MIXER_FBFMT_ABGR4444 13
	90	#define SUN8I_MIXER_FBFMT_RGBA4444 14
	91	#define SUN8I_MIXER_FBFMT_BGRA4444 15
	92	#define SUN8I_MIXER_FBFMT_ARGB1555 16
	93	#define SUN8I_MIXER_FBFMT_ABGR1555 17
	94	#define SUN8I_MIXER_FBFMT_RGBA5551 18
	95	#define SUN8I_MIXER_FBFMT_BGRA5551 19
169ca4b3 JS	96	#define SUN8I_MIXER_FBFMT_ARGB2101010 20
	97	#define SUN8I_MIXER_FBFMT_ABGR2101010 21
	98	#define SUN8I_MIXER_FBFMT_RGBA1010102 22
	99	#define SUN8I_MIXER_FBFMT_BGRA1010102 23
cbd2b690	100
60a3dcf9 JS	101	#define SUN8I_MIXER_FBFMT_YUYV 0
	102	#define SUN8I_MIXER_FBFMT_UYVY 1
	103	#define SUN8I_MIXER_FBFMT_YVYU 2
	104	#define SUN8I_MIXER_FBFMT_VYUY 3
	105	#define SUN8I_MIXER_FBFMT_NV16 4
	106	#define SUN8I_MIXER_FBFMT_NV61 5
	107	#define SUN8I_MIXER_FBFMT_YUV422 6
	108	/* format 7 doesn't exist */
	109	#define SUN8I_MIXER_FBFMT_NV12 8
	110	#define SUN8I_MIXER_FBFMT_NV21 9
	111	#define SUN8I_MIXER_FBFMT_YUV420 10
	112	/* format 11 doesn't exist */
	113	/* format 12 is semi-planar YUV411 UVUV */
	114	/* format 13 is semi-planar YUV411 VUVU */
	115	#define SUN8I_MIXER_FBFMT_YUV411 14
169ca4b3 JS	116	/* format 15 doesn't exist */
	117	/* format 16 is P010 YVU */
	118	#define SUN8I_MIXER_FBFMT_P010_YUV 17
	119	/* format 18 is P210 YVU */
	120	#define SUN8I_MIXER_FBFMT_P210_YUV 19
	121	/* format 20 is packed YVU444 10-bit */
	122	/* format 21 is packed YUV444 10-bit */
60a3dcf9	123
9d75b8c0	124	/*
97eb57fe JS	125	* Sub-engines listed bellow are unused for now. The EN registers are here only
97eb57fe JS	126	* to be used to disable these sub-engines.
9d75b8c0	127	*/
9d75b8c0 IZ	128	#define SUN8I_MIXER_FCE_EN 0xa0000
	129	#define SUN8I_MIXER_BWS_EN 0xa2000
	130	#define SUN8I_MIXER_LTI_EN 0xa4000
	131	#define SUN8I_MIXER_PEAK_EN 0xa6000
	132	#define SUN8I_MIXER_ASE_EN 0xa8000
	133	#define SUN8I_MIXER_FCC_EN 0xaa000
	134	#define SUN8I_MIXER_DCSC_EN 0xb0000
	135
c50519e6 JS	136	#define SUN50I_MIXER_FCE_EN 0x70000
	137	#define SUN50I_MIXER_PEAK_EN 0x70800
	138	#define SUN50I_MIXER_LCTI_EN 0x71000
	139	#define SUN50I_MIXER_BLS_EN 0x71800
	140	#define SUN50I_MIXER_FCC_EN 0x72000
	141	#define SUN50I_MIXER_DNS_EN 0x80000
	142	#define SUN50I_MIXER_DRC_EN 0xa0000
	143	#define SUN50I_MIXER_FMT_EN 0xa8000
	144	#define SUN50I_MIXER_CDC0_EN 0xd0000
	145	#define SUN50I_MIXER_CDC1_EN 0xd8000
	146
5bb5f5da	147	struct de2_fmt_info {
60a3dcf9 JS	148	u32 drm_fmt;
	149	u32 de2_fmt;
	150	bool rgb;
	151	enum sun8i_csc_mode csc;
5bb5f5da JS	152	};
5bb5f5da JS	153
5b1f8367 JS	154	/**
	155	* struct sun8i_mixer_cfg - mixer HW configuration
	156	* @vi_num: number of VI channels
	157	* @ui_num: number of UI channels
	158	* @scaler_mask: bitmask which tells which channel supports scaling
	159	* First, scaler supports for VI channels is defined and after that, scaler
	160	* support for UI channels. For example, if mixer has 2 VI channels without
	161	* scaler and 2 UI channels with scaler, bitmask would be 0xC.
bd3bcb91 JS	162	* @ccsc: select set of CCSC base addresses
	163	* Set value to 0 if this is first mixer or second mixer with VEP support.
	164	* Set value to 1 if this is second mixer without VEP support. Other values
	165	* are invalid.
edea372b MR	166	* @mod_rate: module clock rate that needs to be set in order to have
edea372b MR	167	* a functional block.
c50519e6	168	* @is_de3: true, if this is next gen display engine 3.0, false otherwise.
2586de70	169	* @scaline_yuv: size of a scanline for VI scaler for YUV formats.
5b1f8367	170	*/
9d75b8c0 IZ	171	struct sun8i_mixer_cfg {
	172	int vi_num;
	173	int ui_num;
5b1f8367	174	int scaler_mask;
bd3bcb91	175	int ccsc;
edea372b	176	unsigned long mod_rate;
c50519e6	177	unsigned int is_de3 : 1;
2586de70	178	unsigned int scanline_yuv;
9d75b8c0 IZ	179	};
	180
	181	struct sun8i_mixer {
	182	struct sunxi_engine engine;
	183
	184	const struct sun8i_mixer_cfg *cfg;
	185
	186	struct reset_control *reset;
	187
	188	struct clk *bus_clk;
	189	struct clk *mod_clk;
	190	};
	191
	192	static inline struct sun8i_mixer *
	193	engine_to_sun8i_mixer(struct sunxi_engine *engine)
	194	{
	195	return container_of(engine, struct sun8i_mixer, engine);
	196	}
	197
4b09c073 JS	198	static inline u32
	199	sun8i_blender_base(struct sun8i_mixer *mixer)
	200	{
c50519e6	201	return mixer->cfg->is_de3 ? DE3_BLD_BASE : DE2_BLD_BASE;
4b09c073 JS	202	}
	203
	204	static inline u32
	205	sun8i_channel_base(struct sun8i_mixer *mixer, int channel)
	206	{
c50519e6 JS	207	if (mixer->cfg->is_de3)
	208	return DE3_CH_BASE + channel * DE3_CH_SIZE;
	209	else
	210	return DE2_CH_BASE + channel * DE2_CH_SIZE;
4b09c073 JS	211	}
4b09c073 JS	212
5bb5f5da	213	const struct de2_fmt_info *sun8i_mixer_format_info(u32 format);
9d75b8c0	214	#endif /* _SUN8I_MIXER_H_ */