[linux-2.6-block.git] / drivers / gpu / drm / sun4i / sun4i_hdmi.h

/*
 * Copyright (C) 2016 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 */

#ifndef _SUN4I_HDMI_H_
#define _SUN4I_HDMI_H_

#include <drm/drm_connector.h>
#include <drm/drm_encoder.h>

#include <media/cec-pin.h>

#define SUN4I_HDMI_CTRL_REG		0x004
#define SUN4I_HDMI_CTRL_ENABLE			BIT(31)

#define SUN4I_HDMI_IRQ_REG		0x008
#define SUN4I_HDMI_IRQ_STA_MASK			0x73
#define SUN4I_HDMI_IRQ_STA_FIFO_OF		BIT(1)
#define SUN4I_HDMI_IRQ_STA_FIFO_UF		BIT(0)

#define SUN4I_HDMI_HPD_REG		0x00c
#define SUN4I_HDMI_HPD_HIGH			BIT(0)

#define SUN4I_HDMI_VID_CTRL_REG		0x010
#define SUN4I_HDMI_VID_CTRL_ENABLE		BIT(31)
#define SUN4I_HDMI_VID_CTRL_HDMI_MODE		BIT(30)

#define SUN4I_HDMI_VID_TIMING_ACT_REG	0x014
#define SUN4I_HDMI_VID_TIMING_BP_REG	0x018
#define SUN4I_HDMI_VID_TIMING_FP_REG	0x01c
#define SUN4I_HDMI_VID_TIMING_SPW_REG	0x020

#define SUN4I_HDMI_VID_TIMING_X(x)		((((x) - 1) & GENMASK(11, 0)))
#define SUN4I_HDMI_VID_TIMING_Y(y)		((((y) - 1) & GENMASK(11, 0)) << 16)

#define SUN4I_HDMI_VID_TIMING_POL_REG	0x024
#define SUN4I_HDMI_VID_TIMING_POL_TX_CLK        (0x3e0 << 16)
#define SUN4I_HDMI_VID_TIMING_POL_VSYNC		BIT(1)
#define SUN4I_HDMI_VID_TIMING_POL_HSYNC		BIT(0)

#define SUN4I_HDMI_AVI_INFOFRAME_REG(n)	(0x080 + (n))

#define SUN4I_HDMI_PAD_CTRL0_REG	0x200
#define SUN4I_HDMI_PAD_CTRL0_BIASEN		BIT(31)
#define SUN4I_HDMI_PAD_CTRL0_LDOCEN		BIT(30)
#define SUN4I_HDMI_PAD_CTRL0_LDODEN		BIT(29)
#define SUN4I_HDMI_PAD_CTRL0_PWENC		BIT(28)
#define SUN4I_HDMI_PAD_CTRL0_PWEND		BIT(27)
#define SUN4I_HDMI_PAD_CTRL0_PWENG		BIT(26)
#define SUN4I_HDMI_PAD_CTRL0_CKEN		BIT(25)
#define SUN4I_HDMI_PAD_CTRL0_TXEN		BIT(23)

#define SUN4I_HDMI_PAD_CTRL1_REG	0x204
#define SUN4I_HDMI_PAD_CTRL1_AMP_OPT		BIT(23)
#define SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT		BIT(22)
#define SUN4I_HDMI_PAD_CTRL1_EMP_OPT		BIT(20)
#define SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT		BIT(19)
#define SUN4I_HDMI_PAD_CTRL1_REG_DEN		BIT(15)
#define SUN4I_HDMI_PAD_CTRL1_REG_DENCK		BIT(14)
#define SUN4I_HDMI_PAD_CTRL1_REG_EMP(n)		(((n) & 7) << 10)
#define SUN4I_HDMI_PAD_CTRL1_HALVE_CLK		BIT(6)
#define SUN4I_HDMI_PAD_CTRL1_REG_AMP(n)		(((n) & 7) << 3)

#define SUN4I_HDMI_PLL_CTRL_REG		0x208
#define SUN4I_HDMI_PLL_CTRL_PLL_EN		BIT(31)
#define SUN4I_HDMI_PLL_CTRL_BWS			BIT(30)
#define SUN4I_HDMI_PLL_CTRL_HV_IS_33		BIT(29)
#define SUN4I_HDMI_PLL_CTRL_LDO1_EN		BIT(28)
#define SUN4I_HDMI_PLL_CTRL_LDO2_EN		BIT(27)
#define SUN4I_HDMI_PLL_CTRL_SDIV2		BIT(25)
#define SUN4I_HDMI_PLL_CTRL_VCO_GAIN(n)		(((n) & 7) << 20)
#define SUN4I_HDMI_PLL_CTRL_S(n)		(((n) & 7) << 17)
#define SUN4I_HDMI_PLL_CTRL_CP_S(n)		(((n) & 0x1f) << 12)
#define SUN4I_HDMI_PLL_CTRL_CS(n)		(((n) & 0xf) << 8)
#define SUN4I_HDMI_PLL_CTRL_DIV(n)		(((n) & 0xf) << 4)
#define SUN4I_HDMI_PLL_CTRL_DIV_MASK		GENMASK(7, 4)
#define SUN4I_HDMI_PLL_CTRL_VCO_S(n)		((n) & 0xf)

#define SUN4I_HDMI_PLL_DBG0_REG		0x20c
#define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT(n)	(((n) & 1) << 21)
#define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_MASK	BIT(21)
#define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_SHIFT	21

#define SUN4I_HDMI_CEC			0x214
#define SUN4I_HDMI_CEC_ENABLE			BIT(11)
#define SUN4I_HDMI_CEC_TX			BIT(9)
#define SUN4I_HDMI_CEC_RX			BIT(8)

#define SUN4I_HDMI_PKT_CTRL_REG(n)	(0x2f0 + (4 * (n)))
#define SUN4I_HDMI_PKT_CTRL_TYPE(n, t)		((t) << (((n) % 4) * 4))

#define SUN4I_HDMI_UNKNOWN_REG		0x300
#define SUN4I_HDMI_UNKNOWN_INPUT_SYNC		BIT(27)

#define SUN4I_HDMI_DDC_CTRL_REG		0x500
#define SUN4I_HDMI_DDC_CTRL_ENABLE		BIT(31)
#define SUN4I_HDMI_DDC_CTRL_START_CMD		BIT(30)
#define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_MASK	BIT(8)
#define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_WRITE	(1 << 8)
#define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_READ	(0 << 8)
#define SUN4I_HDMI_DDC_CTRL_RESET		BIT(0)

#define SUN4I_HDMI_DDC_ADDR_REG		0x504
#define SUN4I_HDMI_DDC_ADDR_SEGMENT(seg)	(((seg) & 0xff) << 24)
#define SUN4I_HDMI_DDC_ADDR_EDDC(addr)		(((addr) & 0xff) << 16)
#define SUN4I_HDMI_DDC_ADDR_OFFSET(off)		(((off) & 0xff) << 8)
#define SUN4I_HDMI_DDC_ADDR_SLAVE(addr)		((addr) & 0xff)

#define SUN4I_HDMI_DDC_INT_STATUS_REG		0x50c
#define SUN4I_HDMI_DDC_INT_STATUS_ILLEGAL_FIFO_OPERATION	BIT(7)
#define SUN4I_HDMI_DDC_INT_STATUS_DDC_RX_FIFO_UNDERFLOW		BIT(6)
#define SUN4I_HDMI_DDC_INT_STATUS_DDC_TX_FIFO_OVERFLOW		BIT(5)
#define SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST			BIT(4)
#define SUN4I_HDMI_DDC_INT_STATUS_ARBITRATION_ERROR		BIT(3)
#define SUN4I_HDMI_DDC_INT_STATUS_ACK_ERROR			BIT(2)
#define SUN4I_HDMI_DDC_INT_STATUS_BUS_ERROR			BIT(1)
#define SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE		BIT(0)

#define SUN4I_HDMI_DDC_FIFO_CTRL_REG	0x510
#define SUN4I_HDMI_DDC_FIFO_CTRL_CLEAR		BIT(31)
#define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES(n)	(((n) & 0xf) << 4)
#define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MASK	GENMASK(7, 4)
#define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MAX	(BIT(4) - 1)
#define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES(n)	((n) & 0xf)
#define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MASK	GENMASK(3, 0)
#define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MAX	(BIT(4) - 1)

#define SUN4I_HDMI_DDC_FIFO_DATA_REG	0x518

#define SUN4I_HDMI_DDC_BYTE_COUNT_REG	0x51c
#define SUN4I_HDMI_DDC_BYTE_COUNT_MAX		(BIT(10) - 1)

#define SUN4I_HDMI_DDC_CMD_REG		0x520
#define SUN4I_HDMI_DDC_CMD_EXPLICIT_EDDC_READ	6
#define SUN4I_HDMI_DDC_CMD_IMPLICIT_READ	5
#define SUN4I_HDMI_DDC_CMD_IMPLICIT_WRITE	3

#define SUN4I_HDMI_DDC_CLK_REG		0x528
#define SUN4I_HDMI_DDC_CLK_M(m)			(((m) & 0x7) << 3)
#define SUN4I_HDMI_DDC_CLK_N(n)			((n) & 0x7)

#define SUN4I_HDMI_DDC_LINE_CTRL_REG	0x540
#define SUN4I_HDMI_DDC_LINE_CTRL_SDA_ENABLE	BIT(9)
#define SUN4I_HDMI_DDC_LINE_CTRL_SCL_ENABLE	BIT(8)

#define SUN4I_HDMI_DDC_FIFO_SIZE	16

enum sun4i_hdmi_pkt_type {
	SUN4I_HDMI_PKT_AVI = 2,
	SUN4I_HDMI_PKT_END = 15,
};

struct sun4i_hdmi {
	struct drm_connector	connector;
	struct drm_encoder	encoder;
	struct device		*dev;

	void __iomem		*base;

	/* Parent clocks */
	struct clk		*bus_clk;
	struct clk		*mod_clk;
	struct clk		*pll0_clk;
	struct clk		*pll1_clk;

	/* And the clocks we create */
	struct clk		*ddc_clk;
	struct clk		*tmds_clk;

	struct i2c_adapter	*i2c;

	struct sun4i_drv	*drv;

	bool			hdmi_monitor;
	struct cec_adapter	*cec_adap;
};

int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *clk);
int sun4i_tmds_create(struct sun4i_hdmi *hdmi);
int sun4i_hdmi_i2c_create(struct device *dev, struct sun4i_hdmi *hdmi);

#endif /* _SUN4I_HDMI_H_ */
Commit	Line	Data
9c568101 MR	1	/*
	2	* Copyright (C) 2016 Maxime Ripard
	3	*
	4	* Maxime Ripard <maxime.ripard@free-electrons.com>
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*/
	11
	12	#ifndef _SUN4I_HDMI_H_
	13	#define _SUN4I_HDMI_H_
	14
	15	#include <drm/drm_connector.h>
	16	#include <drm/drm_encoder.h>
	17
4ba72fc0	18	#include <media/cec-pin.h>
998140d2	19
9c568101 MR	20	#define SUN4I_HDMI_CTRL_REG 0x004
	21	#define SUN4I_HDMI_CTRL_ENABLE BIT(31)
	22
	23	#define SUN4I_HDMI_IRQ_REG 0x008
	24	#define SUN4I_HDMI_IRQ_STA_MASK 0x73
	25	#define SUN4I_HDMI_IRQ_STA_FIFO_OF BIT(1)
	26	#define SUN4I_HDMI_IRQ_STA_FIFO_UF BIT(0)
	27
	28	#define SUN4I_HDMI_HPD_REG 0x00c
	29	#define SUN4I_HDMI_HPD_HIGH BIT(0)
	30
	31	#define SUN4I_HDMI_VID_CTRL_REG 0x010
	32	#define SUN4I_HDMI_VID_CTRL_ENABLE BIT(31)
	33	#define SUN4I_HDMI_VID_CTRL_HDMI_MODE BIT(30)
	34
	35	#define SUN4I_HDMI_VID_TIMING_ACT_REG 0x014
	36	#define SUN4I_HDMI_VID_TIMING_BP_REG 0x018
	37	#define SUN4I_HDMI_VID_TIMING_FP_REG 0x01c
	38	#define SUN4I_HDMI_VID_TIMING_SPW_REG 0x020
	39
	40	#define SUN4I_HDMI_VID_TIMING_X(x) ((((x) - 1) & GENMASK(11, 0)))
	41	#define SUN4I_HDMI_VID_TIMING_Y(y) ((((y) - 1) & GENMASK(11, 0)) << 16)
	42
	43	#define SUN4I_HDMI_VID_TIMING_POL_REG 0x024
	44	#define SUN4I_HDMI_VID_TIMING_POL_TX_CLK (0x3e0 << 16)
	45	#define SUN4I_HDMI_VID_TIMING_POL_VSYNC BIT(1)
	46	#define SUN4I_HDMI_VID_TIMING_POL_HSYNC BIT(0)
	47
	48	#define SUN4I_HDMI_AVI_INFOFRAME_REG(n) (0x080 + (n))
	49
	50	#define SUN4I_HDMI_PAD_CTRL0_REG 0x200
	51	#define SUN4I_HDMI_PAD_CTRL0_BIASEN BIT(31)
	52	#define SUN4I_HDMI_PAD_CTRL0_LDOCEN BIT(30)
	53	#define SUN4I_HDMI_PAD_CTRL0_LDODEN BIT(29)
	54	#define SUN4I_HDMI_PAD_CTRL0_PWENC BIT(28)
	55	#define SUN4I_HDMI_PAD_CTRL0_PWEND BIT(27)
	56	#define SUN4I_HDMI_PAD_CTRL0_PWENG BIT(26)
	57	#define SUN4I_HDMI_PAD_CTRL0_CKEN BIT(25)
	58	#define SUN4I_HDMI_PAD_CTRL0_TXEN BIT(23)
	59
	60	#define SUN4I_HDMI_PAD_CTRL1_REG 0x204
	61	#define SUN4I_HDMI_PAD_CTRL1_AMP_OPT BIT(23)
	62	#define SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT BIT(22)
	63	#define SUN4I_HDMI_PAD_CTRL1_EMP_OPT BIT(20)
	64	#define SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT BIT(19)
	65	#define SUN4I_HDMI_PAD_CTRL1_REG_DEN BIT(15)
	66	#define SUN4I_HDMI_PAD_CTRL1_REG_DENCK BIT(14)
	67	#define SUN4I_HDMI_PAD_CTRL1_REG_EMP(n) (((n) & 7) << 10)
	68	#define SUN4I_HDMI_PAD_CTRL1_HALVE_CLK BIT(6)
	69	#define SUN4I_HDMI_PAD_CTRL1_REG_AMP(n) (((n) & 7) << 3)
	70
	71	#define SUN4I_HDMI_PLL_CTRL_REG 0x208
	72	#define SUN4I_HDMI_PLL_CTRL_PLL_EN BIT(31)
	73	#define SUN4I_HDMI_PLL_CTRL_BWS BIT(30)
	74	#define SUN4I_HDMI_PLL_CTRL_HV_IS_33 BIT(29)
	75	#define SUN4I_HDMI_PLL_CTRL_LDO1_EN BIT(28)
	76	#define SUN4I_HDMI_PLL_CTRL_LDO2_EN BIT(27)
	77	#define SUN4I_HDMI_PLL_CTRL_SDIV2 BIT(25)
	78	#define SUN4I_HDMI_PLL_CTRL_VCO_GAIN(n) (((n) & 7) << 20)
	79	#define SUN4I_HDMI_PLL_CTRL_S(n) (((n) & 7) << 17)
	80	#define SUN4I_HDMI_PLL_CTRL_CP_S(n) (((n) & 0x1f) << 12)
	81	#define SUN4I_HDMI_PLL_CTRL_CS(n) (((n) & 0xf) << 8)
	82	#define SUN4I_HDMI_PLL_CTRL_DIV(n) (((n) & 0xf) << 4)
	83	#define SUN4I_HDMI_PLL_CTRL_DIV_MASK GENMASK(7, 4)
84	#define SUN4I_HDMI_PLL_CTRL_VCO_S(n) ((n) & 0xf)
85
86	#define SUN4I_HDMI_PLL_DBG0_REG 0x20c
87	#define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT(n) (((n) & 1) << 21)
88	#define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_MASK BIT(21)
89	#define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_SHIFT 21
90
998140d2 HV	91	#define SUN4I_HDMI_CEC 0x214
	92	#define SUN4I_HDMI_CEC_ENABLE BIT(11)
	93	#define SUN4I_HDMI_CEC_TX BIT(9)
	94	#define SUN4I_HDMI_CEC_RX BIT(8)
	95
9c568101 MR	96	#define SUN4I_HDMI_PKT_CTRL_REG(n) (0x2f0 + (4 * (n)))
	97	#define SUN4I_HDMI_PKT_CTRL_TYPE(n, t) ((t) << (((n) % 4) * 4))
	98
	99	#define SUN4I_HDMI_UNKNOWN_REG 0x300
	100	#define SUN4I_HDMI_UNKNOWN_INPUT_SYNC BIT(27)
	101
	102	#define SUN4I_HDMI_DDC_CTRL_REG 0x500
	103	#define SUN4I_HDMI_DDC_CTRL_ENABLE BIT(31)
	104	#define SUN4I_HDMI_DDC_CTRL_START_CMD BIT(30)
	105	#define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_MASK BIT(8)
f0a3dd33	106	#define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_WRITE (1 << 8)
9c568101 MR	107	#define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_READ (0 << 8)
	108	#define SUN4I_HDMI_DDC_CTRL_RESET BIT(0)
	109
	110	#define SUN4I_HDMI_DDC_ADDR_REG 0x504
	111	#define SUN4I_HDMI_DDC_ADDR_SEGMENT(seg) (((seg) & 0xff) << 24)
	112	#define SUN4I_HDMI_DDC_ADDR_EDDC(addr) (((addr) & 0xff) << 16)
	113	#define SUN4I_HDMI_DDC_ADDR_OFFSET(off) (((off) & 0xff) << 8)
	114	#define SUN4I_HDMI_DDC_ADDR_SLAVE(addr) ((addr) & 0xff)
	115
f0a3dd33 JL	116	#define SUN4I_HDMI_DDC_INT_STATUS_REG 0x50c
	117	#define SUN4I_HDMI_DDC_INT_STATUS_ILLEGAL_FIFO_OPERATION BIT(7)
	118	#define SUN4I_HDMI_DDC_INT_STATUS_DDC_RX_FIFO_UNDERFLOW BIT(6)
	119	#define SUN4I_HDMI_DDC_INT_STATUS_DDC_TX_FIFO_OVERFLOW BIT(5)
	120	#define SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST BIT(4)
	121	#define SUN4I_HDMI_DDC_INT_STATUS_ARBITRATION_ERROR BIT(3)
	122	#define SUN4I_HDMI_DDC_INT_STATUS_ACK_ERROR BIT(2)
	123	#define SUN4I_HDMI_DDC_INT_STATUS_BUS_ERROR BIT(1)
	124	#define SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE BIT(0)
	125
9c568101 MR	126	#define SUN4I_HDMI_DDC_FIFO_CTRL_REG 0x510
9c568101 MR	127	#define SUN4I_HDMI_DDC_FIFO_CTRL_CLEAR BIT(31)
f0a3dd33 JL	128	#define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES(n) (((n) & 0xf) << 4)
	129	#define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MASK GENMASK(7, 4)
	130	#define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MAX (BIT(4) - 1)
	131	#define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES(n) ((n) & 0xf)
	132	#define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MASK GENMASK(3, 0)
	133	#define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MAX (BIT(4) - 1)
9c568101 MR	134
9c568101 MR	135	#define SUN4I_HDMI_DDC_FIFO_DATA_REG 0x518
f0a3dd33	136
9c568101	137	#define SUN4I_HDMI_DDC_BYTE_COUNT_REG 0x51c
f0a3dd33	138	#define SUN4I_HDMI_DDC_BYTE_COUNT_MAX (BIT(10) - 1)
9c568101 MR	139
	140	#define SUN4I_HDMI_DDC_CMD_REG 0x520
	141	#define SUN4I_HDMI_DDC_CMD_EXPLICIT_EDDC_READ 6
f0a3dd33 JL	142	#define SUN4I_HDMI_DDC_CMD_IMPLICIT_READ 5
f0a3dd33 JL	143	#define SUN4I_HDMI_DDC_CMD_IMPLICIT_WRITE 3
9c568101 MR	144
	145	#define SUN4I_HDMI_DDC_CLK_REG 0x528
	146	#define SUN4I_HDMI_DDC_CLK_M(m) (((m) & 0x7) << 3)
	147	#define SUN4I_HDMI_DDC_CLK_N(n) ((n) & 0x7)
	148
	149	#define SUN4I_HDMI_DDC_LINE_CTRL_REG 0x540
	150	#define SUN4I_HDMI_DDC_LINE_CTRL_SDA_ENABLE BIT(9)
	151	#define SUN4I_HDMI_DDC_LINE_CTRL_SCL_ENABLE BIT(8)
	152
	153	#define SUN4I_HDMI_DDC_FIFO_SIZE 16
	154
	155	enum sun4i_hdmi_pkt_type {
	156	SUN4I_HDMI_PKT_AVI = 2,
	157	SUN4I_HDMI_PKT_END = 15,
	158	};
	159
	160	struct sun4i_hdmi {
	161	struct drm_connector connector;
	162	struct drm_encoder encoder;
	163	struct device *dev;
	164
	165	void __iomem *base;
	166
	167	/* Parent clocks */
	168	struct clk *bus_clk;
	169	struct clk *mod_clk;
	170	struct clk *pll0_clk;
	171	struct clk *pll1_clk;
	172
	173	/* And the clocks we create */
	174	struct clk *ddc_clk;
	175	struct clk *tmds_clk;
	176
f0a3dd33 JL	177	struct i2c_adapter *i2c;
f0a3dd33 JL	178
9c568101 MR	179	struct sun4i_drv *drv;
	180
	181	bool hdmi_monitor;
998140d2	182	struct cec_adapter *cec_adap;
9c568101 MR	183	};
	184
	185	int sun4i_ddc_create(struct sun4i_hdmi hdmi, struct clk clk);
	186	int sun4i_tmds_create(struct sun4i_hdmi *hdmi);
f0a3dd33	187	int sun4i_hdmi_i2c_create(struct device dev, struct sun4i_hdmi hdmi);
9c568101 MR	188
9c568101 MR	189	#endif /* _SUN4I_HDMI_H_ */