[linux-block.git] / drivers / gpu / drm / sun4i / sun4i_crtc.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (C) 2015 Free Electrons
 * Copyright (C) 2015 NextThing Co
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 */

#include <linux/clk-provider.h>
#include <linux/ioport.h>
#include <linux/of_address.h>
#include <linux/of_graph.h>
#include <linux/of_irq.h>
#include <linux/regmap.h>

#include <video/videomode.h>

#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_modes.h>
#include <drm/drm_print.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_vblank.h>

#include "sun4i_backend.h"
#include "sun4i_crtc.h"
#include "sun4i_drv.h"
#include "sunxi_engine.h"
#include "sun4i_tcon.h"

/*
 * While this isn't really working in the DRM theory, in practice we
 * can only ever have one encoder per TCON since we have a mux in our
 * TCON.
 */
static struct drm_encoder *sun4i_crtc_get_encoder(struct drm_crtc *crtc)
{
	struct drm_encoder *encoder;

	drm_for_each_encoder(encoder, crtc->dev)
		if (encoder->crtc == crtc)
			return encoder;

	return NULL;
}

static int sun4i_crtc_atomic_check(struct drm_crtc *crtc,
				    struct drm_atomic_state *state)
{
	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
									  crtc);
	struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);
	struct sunxi_engine *engine = scrtc->engine;
	int ret = 0;

	if (engine && engine->ops && engine->ops->atomic_check)
		ret = engine->ops->atomic_check(engine, crtc_state);

	return ret;
}

static void sun4i_crtc_atomic_begin(struct drm_crtc *crtc,
				    struct drm_atomic_state *state)
{
	struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,
									 crtc);
	struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct sunxi_engine *engine = scrtc->engine;
	unsigned long flags;

	if (crtc->state->event) {
		WARN_ON(drm_crtc_vblank_get(crtc) != 0);

		spin_lock_irqsave(&dev->event_lock, flags);
		scrtc->event = crtc->state->event;
		spin_unlock_irqrestore(&dev->event_lock, flags);
		crtc->state->event = NULL;
	}

	if (engine->ops->atomic_begin)
		engine->ops->atomic_begin(engine, old_state);
}

static void sun4i_crtc_atomic_flush(struct drm_crtc *crtc,
				    struct drm_atomic_state *state)
{
	struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);
	struct drm_pending_vblank_event *event = crtc->state->event;

	DRM_DEBUG_DRIVER("Committing plane changes\n");

	sunxi_engine_commit(scrtc->engine);

	if (event) {
		crtc->state->event = NULL;

		spin_lock_irq(&crtc->dev->event_lock);
		if (drm_crtc_vblank_get(crtc) == 0)
			drm_crtc_arm_vblank_event(crtc, event);
		else
			drm_crtc_send_vblank_event(crtc, event);
		spin_unlock_irq(&crtc->dev->event_lock);
	}
}

static void sun4i_crtc_atomic_disable(struct drm_crtc *crtc,
				      struct drm_atomic_state *state)
{
	struct drm_encoder *encoder = sun4i_crtc_get_encoder(crtc);
	struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);

	DRM_DEBUG_DRIVER("Disabling the CRTC\n");

	drm_crtc_vblank_off(crtc);

	sun4i_tcon_set_status(scrtc->tcon, encoder, false);

	if (crtc->state->event && !crtc->state->active) {
		spin_lock_irq(&crtc->dev->event_lock);
		drm_crtc_send_vblank_event(crtc, crtc->state->event);
		spin_unlock_irq(&crtc->dev->event_lock);

		crtc->state->event = NULL;
	}
}

static void sun4i_crtc_atomic_enable(struct drm_crtc *crtc,
				     struct drm_atomic_state *state)
{
	struct drm_encoder *encoder = sun4i_crtc_get_encoder(crtc);
	struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);

	DRM_DEBUG_DRIVER("Enabling the CRTC\n");

	sun4i_tcon_set_status(scrtc->tcon, encoder, true);

	drm_crtc_vblank_on(crtc);
}

static void sun4i_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
	struct drm_encoder *encoder = sun4i_crtc_get_encoder(crtc);
	struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);

	sun4i_tcon_mode_set(scrtc->tcon, encoder, mode);
	sunxi_engine_mode_set(scrtc->engine, mode);
}

static const struct drm_crtc_helper_funcs sun4i_crtc_helper_funcs = {
	.atomic_check	= sun4i_crtc_atomic_check,
	.atomic_begin	= sun4i_crtc_atomic_begin,
	.atomic_flush	= sun4i_crtc_atomic_flush,
	.atomic_enable	= sun4i_crtc_atomic_enable,
	.atomic_disable	= sun4i_crtc_atomic_disable,
	.mode_set_nofb	= sun4i_crtc_mode_set_nofb,
};

static int sun4i_crtc_enable_vblank(struct drm_crtc *crtc)
{
	struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);

	DRM_DEBUG_DRIVER("Enabling VBLANK on crtc %p\n", crtc);

	sun4i_tcon_enable_vblank(scrtc->tcon, true);

	return 0;
}

static void sun4i_crtc_disable_vblank(struct drm_crtc *crtc)
{
	struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);

	DRM_DEBUG_DRIVER("Disabling VBLANK on crtc %p\n", crtc);

	sun4i_tcon_enable_vblank(scrtc->tcon, false);
}

static const struct drm_crtc_funcs sun4i_crtc_funcs = {
	.atomic_destroy_state	= drm_atomic_helper_crtc_destroy_state,
	.atomic_duplicate_state	= drm_atomic_helper_crtc_duplicate_state,
	.destroy		= drm_crtc_cleanup,
	.page_flip		= drm_atomic_helper_page_flip,
	.reset			= drm_atomic_helper_crtc_reset,
	.set_config		= drm_atomic_helper_set_config,
	.enable_vblank		= sun4i_crtc_enable_vblank,
	.disable_vblank		= sun4i_crtc_disable_vblank,
};

struct sun4i_crtc *sun4i_crtc_init(struct drm_device *drm,
				   struct sunxi_engine *engine,
				   struct sun4i_tcon *tcon)
{
	struct sun4i_crtc *scrtc;
	struct drm_plane **planes;
	struct drm_plane *primary = NULL, *cursor = NULL;
	int ret, i;

	scrtc = devm_kzalloc(drm->dev, sizeof(*scrtc), GFP_KERNEL);
	if (!scrtc)
		return ERR_PTR(-ENOMEM);
	scrtc->engine = engine;
	scrtc->tcon = tcon;

	/* Create our layers */
	planes = sunxi_engine_layers_init(drm, engine);
	if (IS_ERR(planes)) {
		dev_err(drm->dev, "Couldn't create the planes\n");
		return NULL;
	}

	/* find primary and cursor planes for drm_crtc_init_with_planes */
	for (i = 0; planes[i]; i++) {
		struct drm_plane *plane = planes[i];

		switch (plane->type) {
		case DRM_PLANE_TYPE_PRIMARY:
			primary = plane;
			break;
		case DRM_PLANE_TYPE_CURSOR:
			cursor = plane;
			break;
		default:
			break;
		}
	}

	ret = drm_crtc_init_with_planes(drm, &scrtc->crtc,
					primary,
					cursor,
					&sun4i_crtc_funcs,
					NULL);
	if (ret) {
		dev_err(drm->dev, "Couldn't init DRM CRTC\n");
		return ERR_PTR(ret);
	}

	drm_crtc_helper_add(&scrtc->crtc, &sun4i_crtc_helper_funcs);

	/* Set crtc.port to output port node of the tcon */
	scrtc->crtc.port = of_graph_get_port_by_id(scrtc->tcon->dev->of_node,
						   1);

	/* Set possible_crtcs to this crtc for overlay planes */
	for (i = 0; planes[i]; i++) {
		uint32_t possible_crtcs = drm_crtc_mask(&scrtc->crtc);
		struct drm_plane *plane = planes[i];

		if (plane->type == DRM_PLANE_TYPE_OVERLAY)
			plane->possible_crtcs = possible_crtcs;
	}

	return scrtc;
}
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
9026e0d1 MR	2	/*
	3	* Copyright (C) 2015 Free Electrons
	4	* Copyright (C) 2015 NextThing Co
	5	*
	6	* Maxime Ripard <maxime.ripard@free-electrons.com>
9026e0d1 MR	7	*/
9026e0d1 MR	8
9026e0d1 MR	9	#include <linux/clk-provider.h>
	10	#include <linux/ioport.h>
	11	#include <linux/of_address.h>
75448607	12	#include <linux/of_graph.h>
9026e0d1 MR	13	#include <linux/of_irq.h>
	14	#include <linux/regmap.h>
	15
	16	#include <video/videomode.h>
	17
29b77ad7	18	#include <drm/drm_atomic.h>
9c25a297 SR	19	#include <drm/drm_atomic_helper.h>
	20	#include <drm/drm_crtc.h>
	21	#include <drm/drm_modes.h>
	22	#include <drm/drm_print.h>
	23	#include <drm/drm_probe_helper.h>
	24	#include <drm/drm_vblank.h>
	25
ca07b210	26	#include "sun4i_backend.h"
9026e0d1 MR	27	#include "sun4i_crtc.h"
9026e0d1 MR	28	#include "sun4i_drv.h"
87969338	29	#include "sunxi_engine.h"
9026e0d1 MR	30	#include "sun4i_tcon.h"
9026e0d1 MR	31
45e88f99 MR	32	/*
	33	* While this isn't really working in the DRM theory, in practice we
	34	* can only ever have one encoder per TCON since we have a mux in our
	35	* TCON.
	36	*/
	37	static struct drm_encoder sun4i_crtc_get_encoder(struct drm_crtc crtc)
	38	{
	39	struct drm_encoder *encoder;
	40
	41	drm_for_each_encoder(encoder, crtc->dev)
	42	if (encoder->crtc == crtc)
	43	return encoder;
	44
	45	return NULL;
	46	}
	47
656e5f65	48	static int sun4i_crtc_atomic_check(struct drm_crtc *crtc,
29b77ad7	49	struct drm_atomic_state *state)
656e5f65	50	{
29b77ad7 MR	51	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
29b77ad7 MR	52	crtc);
656e5f65 MR	53	struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);
	54	struct sunxi_engine *engine = scrtc->engine;
	55	int ret = 0;
	56
	57	if (engine && engine->ops && engine->ops->atomic_check)
29b77ad7	58	ret = engine->ops->atomic_check(engine, crtc_state);
656e5f65 MR	59
	60	return ret;
	61	}
	62
9026e0d1	63	static void sun4i_crtc_atomic_begin(struct drm_crtc *crtc,
f6ebe9f9	64	struct drm_atomic_state *state)
9026e0d1	65	{
f6ebe9f9 MR	66	struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,
f6ebe9f9 MR	67	crtc);
9026e0d1 MR	68	struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);
9026e0d1 MR	69	struct drm_device *dev = crtc->dev;
6b8562c8	70	struct sunxi_engine *engine = scrtc->engine;
9026e0d1 MR	71	unsigned long flags;
	72
	73	if (crtc->state->event) {
	74	WARN_ON(drm_crtc_vblank_get(crtc) != 0);
	75
	76	spin_lock_irqsave(&dev->event_lock, flags);
	77	scrtc->event = crtc->state->event;
	78	spin_unlock_irqrestore(&dev->event_lock, flags);
	79	crtc->state->event = NULL;
6b8562c8 MR	80	}
	81
	82	if (engine->ops->atomic_begin)
	83	engine->ops->atomic_begin(engine, old_state);
9026e0d1 MR	84	}
	85
	86	static void sun4i_crtc_atomic_flush(struct drm_crtc *crtc,
f6ebe9f9	87	struct drm_atomic_state *state)
9026e0d1 MR	88	{
9026e0d1 MR	89	struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);
a33e93db	90	struct drm_pending_vblank_event *event = crtc->state->event;
9026e0d1 MR	91
	92	DRM_DEBUG_DRIVER("Committing plane changes\n");
	93
87969338	94	sunxi_engine_commit(scrtc->engine);
a33e93db DV	95
	96	if (event) {
	97	crtc->state->event = NULL;
	98
	99	spin_lock_irq(&crtc->dev->event_lock);
	100	if (drm_crtc_vblank_get(crtc) == 0)
	101	drm_crtc_arm_vblank_event(crtc, event);
	102	else
	103	drm_crtc_send_vblank_event(crtc, event);
	104	spin_unlock_irq(&crtc->dev->event_lock);
	105	}
9026e0d1 MR	106	}
9026e0d1 MR	107
64581714	108	static void sun4i_crtc_atomic_disable(struct drm_crtc *crtc,
351f950d	109	struct drm_atomic_state *state)
9026e0d1	110	{
45e88f99	111	struct drm_encoder *encoder = sun4i_crtc_get_encoder(crtc);
9026e0d1	112	struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);
9026e0d1 MR	113
	114	DRM_DEBUG_DRIVER("Disabling the CRTC\n");
	115
fd00c4ee MR	116	drm_crtc_vblank_off(crtc);
fd00c4ee MR	117
45e88f99	118	sun4i_tcon_set_status(scrtc->tcon, encoder, false);
2cd36830 MR	119
	120	if (crtc->state->event && !crtc->state->active) {
	121	spin_lock_irq(&crtc->dev->event_lock);
	122	drm_crtc_send_vblank_event(crtc, crtc->state->event);
	123	spin_unlock_irq(&crtc->dev->event_lock);
	124
	125	crtc->state->event = NULL;
	126	}
9026e0d1 MR	127	}
9026e0d1 MR	128
0b20a0f8	129	static void sun4i_crtc_atomic_enable(struct drm_crtc *crtc,
351f950d	130	struct drm_atomic_state *state)
9026e0d1	131	{
45e88f99	132	struct drm_encoder *encoder = sun4i_crtc_get_encoder(crtc);
9026e0d1	133	struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);
9026e0d1 MR	134
	135	DRM_DEBUG_DRIVER("Enabling the CRTC\n");
	136
45e88f99	137	sun4i_tcon_set_status(scrtc->tcon, encoder, true);
fd00c4ee MR	138
fd00c4ee MR	139	drm_crtc_vblank_on(crtc);
9026e0d1 MR	140	}
9026e0d1 MR	141
5b8f0910 MR	142	static void sun4i_crtc_mode_set_nofb(struct drm_crtc *crtc)
	143	{
	144	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
	145	struct drm_encoder *encoder = sun4i_crtc_get_encoder(crtc);
	146	struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);
	147
	148	sun4i_tcon_mode_set(scrtc->tcon, encoder, mode);
f7e974a3	149	sunxi_engine_mode_set(scrtc->engine, mode);
5b8f0910 MR	150	}
5b8f0910 MR	151
9026e0d1	152	static const struct drm_crtc_helper_funcs sun4i_crtc_helper_funcs = {
656e5f65	153	.atomic_check = sun4i_crtc_atomic_check,
9026e0d1 MR	154	.atomic_begin = sun4i_crtc_atomic_begin,
9026e0d1 MR	155	.atomic_flush = sun4i_crtc_atomic_flush,
0b20a0f8	156	.atomic_enable = sun4i_crtc_atomic_enable,
64581714	157	.atomic_disable = sun4i_crtc_atomic_disable,
5b8f0910	158	.mode_set_nofb = sun4i_crtc_mode_set_nofb,
9026e0d1 MR	159	};
9026e0d1 MR	160
50480a78 SG	161	static int sun4i_crtc_enable_vblank(struct drm_crtc *crtc)
	162	{
	163	struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);
50480a78 SG	164
	165	DRM_DEBUG_DRIVER("Enabling VBLANK on crtc %p\n", crtc);
	166
3c64fb37	167	sun4i_tcon_enable_vblank(scrtc->tcon, true);
50480a78 SG	168
	169	return 0;
	170	}
	171
	172	static void sun4i_crtc_disable_vblank(struct drm_crtc *crtc)
	173	{
	174	struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);
50480a78 SG	175
	176	DRM_DEBUG_DRIVER("Disabling VBLANK on crtc %p\n", crtc);
	177
3c64fb37	178	sun4i_tcon_enable_vblank(scrtc->tcon, false);
50480a78 SG	179	}
50480a78 SG	180
9026e0d1 MR	181	static const struct drm_crtc_funcs sun4i_crtc_funcs = {
	182	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
	183	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
	184	.destroy = drm_crtc_cleanup,
	185	.page_flip = drm_atomic_helper_page_flip,
	186	.reset = drm_atomic_helper_crtc_reset,
	187	.set_config = drm_atomic_helper_set_config,
50480a78 SG	188	.enable_vblank = sun4i_crtc_enable_vblank,
50480a78 SG	189	.disable_vblank = sun4i_crtc_disable_vblank,
9026e0d1 MR	190	};
9026e0d1 MR	191
18c3b300	192	struct sun4i_crtc sun4i_crtc_init(struct drm_device drm,
87969338	193	struct sunxi_engine *engine,
18c3b300	194	struct sun4i_tcon *tcon)
9026e0d1	195	{
9026e0d1	196	struct sun4i_crtc *scrtc;
7921e147	197	struct drm_plane **planes;
dcd21580 CYT	198	struct drm_plane primary = NULL, cursor = NULL;
dcd21580 CYT	199	int ret, i;
9026e0d1 MR	200
	201	scrtc = devm_kzalloc(drm->dev, sizeof(*scrtc), GFP_KERNEL);
	202	if (!scrtc)
ea411fd2	203	return ERR_PTR(-ENOMEM);
87969338	204	scrtc->engine = engine;
18c3b300	205	scrtc->tcon = tcon;
9026e0d1	206
b3f266e4	207	/* Create our layers */
87969338	208	planes = sunxi_engine_layers_init(drm, engine);
7921e147	209	if (IS_ERR(planes)) {
b3f266e4	210	dev_err(drm->dev, "Couldn't create the planes\n");
dcd21580 CYT	211	return NULL;
	212	}
	213
	214	/* find primary and cursor planes for drm_crtc_init_with_planes */
7921e147 IZ	215	for (i = 0; planes[i]; i++) {
7921e147 IZ	216	struct drm_plane *plane = planes[i];
dcd21580	217
7921e147	218	switch (plane->type) {
dcd21580	219	case DRM_PLANE_TYPE_PRIMARY:
7921e147	220	primary = plane;
dcd21580 CYT	221	break;
dcd21580 CYT	222	case DRM_PLANE_TYPE_CURSOR:
7921e147	223	cursor = plane;
dcd21580 CYT	224	break;
	225	default:
	226	break;
	227	}
b3f266e4 CYT	228	}
b3f266e4 CYT	229
9026e0d1	230	ret = drm_crtc_init_with_planes(drm, &scrtc->crtc,
dcd21580 CYT	231	primary,
dcd21580 CYT	232	cursor,
9026e0d1 MR	233	&sun4i_crtc_funcs,
	234	NULL);
	235	if (ret) {
	236	dev_err(drm->dev, "Couldn't init DRM CRTC\n");
ea411fd2	237	return ERR_PTR(ret);
9026e0d1 MR	238	}
	239
	240	drm_crtc_helper_add(&scrtc->crtc, &sun4i_crtc_helper_funcs);
	241
75448607	242	/* Set crtc.port to output port node of the tcon */
e4cdcb7c	243	scrtc->crtc.port = of_graph_get_port_by_id(scrtc->tcon->dev->of_node,
75448607 CYT	244	1);
75448607 CYT	245
a5154a4d	246	/* Set possible_crtcs to this crtc for overlay planes */
7921e147	247	for (i = 0; planes[i]; i++) {
dbf8f9e4	248	uint32_t possible_crtcs = drm_crtc_mask(&scrtc->crtc);
7921e147	249	struct drm_plane *plane = planes[i];
a5154a4d	250
7921e147 IZ	251	if (plane->type == DRM_PLANE_TYPE_OVERLAY)
7921e147 IZ	252	plane->possible_crtcs = possible_crtcs;
a5154a4d CYT	253	}
a5154a4d CYT	254
9026e0d1 MR	255	return scrtc;
9026e0d1 MR	256	}