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9026e0d1 MR |
1 | /* |
2 | * Copyright (C) 2015 Free Electrons | |
3 | * Copyright (C) 2015 NextThing Co | |
4 | * | |
5 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <drm/drmP.h> | |
96180dde | 14 | #include <drm/drm_atomic.h> |
9026e0d1 MR |
15 | #include <drm/drm_atomic_helper.h> |
16 | #include <drm/drm_crtc.h> | |
17 | #include <drm/drm_crtc_helper.h> | |
18 | #include <drm/drm_fb_cma_helper.h> | |
19 | #include <drm/drm_gem_cma_helper.h> | |
20 | #include <drm/drm_plane_helper.h> | |
21 | ||
22 | #include <linux/component.h> | |
80a58240 | 23 | #include <linux/list.h> |
f55c83d3 | 24 | #include <linux/of_device.h> |
da3a1c30 | 25 | #include <linux/of_graph.h> |
9026e0d1 MR |
26 | #include <linux/reset.h> |
27 | ||
28 | #include "sun4i_backend.h" | |
29 | #include "sun4i_drv.h" | |
ca07b210 | 30 | #include "sun4i_frontend.h" |
87969338 IZ |
31 | #include "sun4i_layer.h" |
32 | #include "sunxi_engine.h" | |
9026e0d1 | 33 | |
f55c83d3 CYT |
34 | struct sun4i_backend_quirks { |
35 | /* backend <-> TCON muxing selection done in backend */ | |
36 | bool needs_output_muxing; | |
dcf496a6 PK |
37 | |
38 | /* alpha at the lowest z position is not always supported */ | |
39 | bool supports_lowest_plane_alpha; | |
f55c83d3 CYT |
40 | }; |
41 | ||
a6fbffb0 | 42 | static const u32 sunxi_rgb2yuv_coef[12] = { |
9026e0d1 MR |
43 | 0x00000107, 0x00000204, 0x00000064, 0x00000108, |
44 | 0x00003f69, 0x00003ed6, 0x000001c1, 0x00000808, | |
45 | 0x000001c1, 0x00003e88, 0x00003fb8, 0x00000808 | |
46 | }; | |
47 | ||
ddc389f5 MR |
48 | /* |
49 | * These coefficients are taken from the A33 BSP from Allwinner. | |
50 | * | |
dc7d4b65 PK |
51 | * The first three values of each row are coded as 13-bit signed fixed-point |
52 | * numbers, with 10 bits for the fractional part. The fourth value is a | |
53 | * constant coded as a 14-bit signed fixed-point number with 4 bits for the | |
54 | * fractional part. | |
55 | * | |
56 | * The values in table order give the following colorspace translation: | |
ddc389f5 MR |
57 | * G = 1.164 * Y - 0.391 * U - 0.813 * V + 135 |
58 | * R = 1.164 * Y + 1.596 * V - 222 | |
59 | * B = 1.164 * Y + 2.018 * U + 276 | |
60 | * | |
61 | * This seems to be a conversion from Y[16:235] UV[16:240] to RGB[0:255], | |
62 | * following the BT601 spec. | |
63 | */ | |
64 | static const u32 sunxi_bt601_yuv2rgb_coef[12] = { | |
65 | 0x000004a7, 0x00001e6f, 0x00001cbf, 0x00000877, | |
66 | 0x000004a7, 0x00000000, 0x00000662, 0x00003211, | |
67 | 0x000004a7, 0x00000812, 0x00000000, 0x00002eb1, | |
68 | }; | |
69 | ||
87969338 | 70 | static void sun4i_backend_apply_color_correction(struct sunxi_engine *engine) |
9026e0d1 MR |
71 | { |
72 | int i; | |
73 | ||
74 | DRM_DEBUG_DRIVER("Applying RGB to YUV color correction\n"); | |
75 | ||
76 | /* Set color correction */ | |
87969338 | 77 | regmap_write(engine->regs, SUN4I_BACKEND_OCCTL_REG, |
9026e0d1 MR |
78 | SUN4I_BACKEND_OCCTL_ENABLE); |
79 | ||
80 | for (i = 0; i < 12; i++) | |
87969338 | 81 | regmap_write(engine->regs, SUN4I_BACKEND_OCRCOEF_REG(i), |
9026e0d1 MR |
82 | sunxi_rgb2yuv_coef[i]); |
83 | } | |
9026e0d1 | 84 | |
87969338 | 85 | static void sun4i_backend_disable_color_correction(struct sunxi_engine *engine) |
9026e0d1 MR |
86 | { |
87 | DRM_DEBUG_DRIVER("Disabling color correction\n"); | |
88 | ||
89 | /* Disable color correction */ | |
87969338 | 90 | regmap_update_bits(engine->regs, SUN4I_BACKEND_OCCTL_REG, |
9026e0d1 MR |
91 | SUN4I_BACKEND_OCCTL_ENABLE, 0); |
92 | } | |
9026e0d1 | 93 | |
87969338 | 94 | static void sun4i_backend_commit(struct sunxi_engine *engine) |
9026e0d1 MR |
95 | { |
96 | DRM_DEBUG_DRIVER("Committing changes\n"); | |
97 | ||
87969338 | 98 | regmap_write(engine->regs, SUN4I_BACKEND_REGBUFFCTL_REG, |
9026e0d1 MR |
99 | SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS | |
100 | SUN4I_BACKEND_REGBUFFCTL_LOADCTL); | |
101 | } | |
9026e0d1 MR |
102 | |
103 | void sun4i_backend_layer_enable(struct sun4i_backend *backend, | |
104 | int layer, bool enable) | |
105 | { | |
106 | u32 val; | |
107 | ||
cf80aeef CYT |
108 | DRM_DEBUG_DRIVER("%sabling layer %d\n", enable ? "En" : "Dis", |
109 | layer); | |
9026e0d1 MR |
110 | |
111 | if (enable) | |
112 | val = SUN4I_BACKEND_MODCTL_LAY_EN(layer); | |
113 | else | |
114 | val = 0; | |
115 | ||
87969338 | 116 | regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG, |
9026e0d1 MR |
117 | SUN4I_BACKEND_MODCTL_LAY_EN(layer), val); |
118 | } | |
9026e0d1 | 119 | |
35152d11 | 120 | static int sun4i_backend_drm_format_to_layer(u32 format, u32 *mode) |
9026e0d1 MR |
121 | { |
122 | switch (format) { | |
123 | case DRM_FORMAT_ARGB8888: | |
124 | *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB8888; | |
125 | break; | |
126 | ||
47d7fbb3 MR |
127 | case DRM_FORMAT_ARGB4444: |
128 | *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB4444; | |
129 | break; | |
130 | ||
131 | case DRM_FORMAT_ARGB1555: | |
132 | *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB1555; | |
133 | break; | |
134 | ||
135 | case DRM_FORMAT_RGBA5551: | |
136 | *mode = SUN4I_BACKEND_LAY_FBFMT_RGBA5551; | |
137 | break; | |
138 | ||
139 | case DRM_FORMAT_RGBA4444: | |
140 | *mode = SUN4I_BACKEND_LAY_FBFMT_RGBA4444; | |
141 | break; | |
142 | ||
9026e0d1 MR |
143 | case DRM_FORMAT_XRGB8888: |
144 | *mode = SUN4I_BACKEND_LAY_FBFMT_XRGB8888; | |
145 | break; | |
146 | ||
147 | case DRM_FORMAT_RGB888: | |
148 | *mode = SUN4I_BACKEND_LAY_FBFMT_RGB888; | |
149 | break; | |
150 | ||
47d7fbb3 MR |
151 | case DRM_FORMAT_RGB565: |
152 | *mode = SUN4I_BACKEND_LAY_FBFMT_RGB565; | |
153 | break; | |
154 | ||
9026e0d1 MR |
155 | default: |
156 | return -EINVAL; | |
157 | } | |
158 | ||
159 | return 0; | |
160 | } | |
161 | ||
3d4265f8 PK |
162 | static const uint32_t sun4i_backend_formats[] = { |
163 | DRM_FORMAT_ARGB1555, | |
164 | DRM_FORMAT_ARGB4444, | |
165 | DRM_FORMAT_ARGB8888, | |
166 | DRM_FORMAT_BGRX8888, | |
167 | DRM_FORMAT_RGB565, | |
168 | DRM_FORMAT_RGB888, | |
169 | DRM_FORMAT_RGBA4444, | |
170 | DRM_FORMAT_RGBA5551, | |
171 | DRM_FORMAT_UYVY, | |
172 | DRM_FORMAT_VYUY, | |
173 | DRM_FORMAT_XRGB8888, | |
174 | DRM_FORMAT_YUYV, | |
175 | DRM_FORMAT_YVYU, | |
176 | }; | |
177 | ||
02a3ce3c | 178 | bool sun4i_backend_format_is_supported(uint32_t fmt, uint64_t modifier) |
3d4265f8 PK |
179 | { |
180 | unsigned int i; | |
181 | ||
02a3ce3c PK |
182 | if (modifier != DRM_FORMAT_MOD_LINEAR) |
183 | return false; | |
184 | ||
3d4265f8 PK |
185 | for (i = 0; i < ARRAY_SIZE(sun4i_backend_formats); i++) |
186 | if (sun4i_backend_formats[i] == fmt) | |
187 | return true; | |
188 | ||
189 | return false; | |
190 | } | |
191 | ||
9026e0d1 MR |
192 | int sun4i_backend_update_layer_coord(struct sun4i_backend *backend, |
193 | int layer, struct drm_plane *plane) | |
194 | { | |
195 | struct drm_plane_state *state = plane->state; | |
9026e0d1 MR |
196 | |
197 | DRM_DEBUG_DRIVER("Updating layer %d\n", layer); | |
198 | ||
199 | if (plane->type == DRM_PLANE_TYPE_PRIMARY) { | |
200 | DRM_DEBUG_DRIVER("Primary layer, updating global size W: %u H: %u\n", | |
201 | state->crtc_w, state->crtc_h); | |
87969338 | 202 | regmap_write(backend->engine.regs, SUN4I_BACKEND_DISSIZE_REG, |
9026e0d1 MR |
203 | SUN4I_BACKEND_DISSIZE(state->crtc_w, |
204 | state->crtc_h)); | |
205 | } | |
206 | ||
9026e0d1 MR |
207 | /* Set height and width */ |
208 | DRM_DEBUG_DRIVER("Layer size W: %u H: %u\n", | |
209 | state->crtc_w, state->crtc_h); | |
87969338 | 210 | regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYSIZE_REG(layer), |
9026e0d1 MR |
211 | SUN4I_BACKEND_LAYSIZE(state->crtc_w, |
212 | state->crtc_h)); | |
213 | ||
214 | /* Set base coordinates */ | |
215 | DRM_DEBUG_DRIVER("Layer coordinates X: %d Y: %d\n", | |
216 | state->crtc_x, state->crtc_y); | |
87969338 | 217 | regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYCOOR_REG(layer), |
9026e0d1 MR |
218 | SUN4I_BACKEND_LAYCOOR(state->crtc_x, |
219 | state->crtc_y)); | |
220 | ||
221 | return 0; | |
222 | } | |
9026e0d1 | 223 | |
ddc389f5 MR |
224 | static int sun4i_backend_update_yuv_format(struct sun4i_backend *backend, |
225 | int layer, struct drm_plane *plane) | |
226 | { | |
227 | struct drm_plane_state *state = plane->state; | |
228 | struct drm_framebuffer *fb = state->fb; | |
2aafafab AKH |
229 | const struct drm_format_info *format = fb->format; |
230 | const uint32_t fmt = format->format; | |
ddc389f5 MR |
231 | u32 val = SUN4I_BACKEND_IYUVCTL_EN; |
232 | int i; | |
233 | ||
234 | for (i = 0; i < ARRAY_SIZE(sunxi_bt601_yuv2rgb_coef); i++) | |
235 | regmap_write(backend->engine.regs, | |
236 | SUN4I_BACKEND_YGCOEF_REG(i), | |
237 | sunxi_bt601_yuv2rgb_coef[i]); | |
238 | ||
239 | /* | |
240 | * We should do that only for a single plane, but the | |
241 | * framebuffer's atomic_check has our back on this. | |
242 | */ | |
243 | regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer), | |
244 | SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN, | |
245 | SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN); | |
246 | ||
247 | /* TODO: Add support for the multi-planar YUV formats */ | |
2aafafab | 248 | if (format->num_planes == 1) |
ddc389f5 MR |
249 | val |= SUN4I_BACKEND_IYUVCTL_FBFMT_PACKED_YUV422; |
250 | else | |
2aafafab | 251 | DRM_DEBUG_DRIVER("Unsupported YUV format (0x%x)\n", fmt); |
ddc389f5 MR |
252 | |
253 | /* | |
254 | * Allwinner seems to list the pixel sequence from right to left, while | |
255 | * DRM lists it from left to right. | |
256 | */ | |
2aafafab | 257 | switch (fmt) { |
ddc389f5 MR |
258 | case DRM_FORMAT_YUYV: |
259 | val |= SUN4I_BACKEND_IYUVCTL_FBPS_VYUY; | |
260 | break; | |
261 | case DRM_FORMAT_YVYU: | |
262 | val |= SUN4I_BACKEND_IYUVCTL_FBPS_UYVY; | |
263 | break; | |
264 | case DRM_FORMAT_UYVY: | |
265 | val |= SUN4I_BACKEND_IYUVCTL_FBPS_YVYU; | |
266 | break; | |
267 | case DRM_FORMAT_VYUY: | |
268 | val |= SUN4I_BACKEND_IYUVCTL_FBPS_YUYV; | |
269 | break; | |
270 | default: | |
271 | DRM_DEBUG_DRIVER("Unsupported YUV pixel sequence (0x%x)\n", | |
2aafafab | 272 | fmt); |
ddc389f5 MR |
273 | } |
274 | ||
275 | regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVCTL_REG, val); | |
276 | ||
277 | return 0; | |
278 | } | |
279 | ||
9026e0d1 MR |
280 | int sun4i_backend_update_layer_formats(struct sun4i_backend *backend, |
281 | int layer, struct drm_plane *plane) | |
282 | { | |
283 | struct drm_plane_state *state = plane->state; | |
284 | struct drm_framebuffer *fb = state->fb; | |
285 | bool interlaced = false; | |
286 | u32 val; | |
287 | int ret; | |
288 | ||
ddc389f5 MR |
289 | /* Clear the YUV mode */ |
290 | regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer), | |
291 | SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN, 0); | |
292 | ||
9026e0d1 MR |
293 | if (plane->state->crtc) |
294 | interlaced = plane->state->crtc->state->adjusted_mode.flags | |
295 | & DRM_MODE_FLAG_INTERLACE; | |
296 | ||
87969338 | 297 | regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG, |
9026e0d1 MR |
298 | SUN4I_BACKEND_MODCTL_ITLMOD_EN, |
299 | interlaced ? SUN4I_BACKEND_MODCTL_ITLMOD_EN : 0); | |
300 | ||
301 | DRM_DEBUG_DRIVER("Switching display backend interlaced mode %s\n", | |
302 | interlaced ? "on" : "off"); | |
303 | ||
d99008aa MR |
304 | val = SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA(state->alpha >> 8); |
305 | if (state->alpha != DRM_BLEND_ALPHA_OPAQUE) | |
306 | val |= SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN; | |
307 | regmap_update_bits(backend->engine.regs, | |
308 | SUN4I_BACKEND_ATTCTL_REG0(layer), | |
309 | SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_MASK | | |
310 | SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN, | |
311 | val); | |
312 | ||
979c11ef | 313 | if (fb->format->is_yuv) |
ddc389f5 MR |
314 | return sun4i_backend_update_yuv_format(backend, layer, plane); |
315 | ||
35152d11 | 316 | ret = sun4i_backend_drm_format_to_layer(fb->format->format, &val); |
9026e0d1 MR |
317 | if (ret) { |
318 | DRM_DEBUG_DRIVER("Invalid format\n"); | |
0f0861e3 | 319 | return ret; |
9026e0d1 MR |
320 | } |
321 | ||
87969338 IZ |
322 | regmap_update_bits(backend->engine.regs, |
323 | SUN4I_BACKEND_ATTCTL_REG1(layer), | |
9026e0d1 MR |
324 | SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val); |
325 | ||
326 | return 0; | |
327 | } | |
9026e0d1 | 328 | |
ca07b210 MR |
329 | int sun4i_backend_update_layer_frontend(struct sun4i_backend *backend, |
330 | int layer, uint32_t fmt) | |
331 | { | |
332 | u32 val; | |
333 | int ret; | |
334 | ||
35152d11 | 335 | ret = sun4i_backend_drm_format_to_layer(fmt, &val); |
ca07b210 MR |
336 | if (ret) { |
337 | DRM_DEBUG_DRIVER("Invalid format\n"); | |
338 | return ret; | |
339 | } | |
340 | ||
341 | regmap_update_bits(backend->engine.regs, | |
342 | SUN4I_BACKEND_ATTCTL_REG0(layer), | |
343 | SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN, | |
344 | SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN); | |
345 | ||
346 | regmap_update_bits(backend->engine.regs, | |
347 | SUN4I_BACKEND_ATTCTL_REG1(layer), | |
348 | SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val); | |
349 | ||
350 | return 0; | |
351 | } | |
352 | ||
ddc389f5 MR |
353 | static int sun4i_backend_update_yuv_buffer(struct sun4i_backend *backend, |
354 | struct drm_framebuffer *fb, | |
355 | dma_addr_t paddr) | |
356 | { | |
357 | /* TODO: Add support for the multi-planar YUV formats */ | |
358 | DRM_DEBUG_DRIVER("Setting packed YUV buffer address to %pad\n", &paddr); | |
359 | regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVADD_REG(0), paddr); | |
360 | ||
361 | DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8); | |
362 | regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVLINEWIDTH_REG(0), | |
363 | fb->pitches[0] * 8); | |
364 | ||
365 | return 0; | |
366 | } | |
367 | ||
9026e0d1 MR |
368 | int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend, |
369 | int layer, struct drm_plane *plane) | |
370 | { | |
371 | struct drm_plane_state *state = plane->state; | |
372 | struct drm_framebuffer *fb = state->fb; | |
9026e0d1 MR |
373 | u32 lo_paddr, hi_paddr; |
374 | dma_addr_t paddr; | |
9026e0d1 | 375 | |
f5870879 MR |
376 | /* Set the line width */ |
377 | DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8); | |
378 | regmap_write(backend->engine.regs, | |
379 | SUN4I_BACKEND_LAYLINEWIDTH_REG(layer), | |
380 | fb->pitches[0] * 8); | |
381 | ||
cff2192f CYT |
382 | /* Get the start of the displayed memory */ |
383 | paddr = drm_fb_cma_get_gem_addr(fb, state, 0); | |
f1b78f0e | 384 | DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr); |
9026e0d1 | 385 | |
4690803b CYT |
386 | /* |
387 | * backend DMA accesses DRAM directly, bypassing the system | |
388 | * bus. As such, the address range is different and the buffer | |
389 | * address needs to be corrected. | |
390 | */ | |
391 | paddr -= PHYS_OFFSET; | |
392 | ||
979c11ef | 393 | if (fb->format->is_yuv) |
ddc389f5 MR |
394 | return sun4i_backend_update_yuv_buffer(backend, fb, paddr); |
395 | ||
9026e0d1 MR |
396 | /* Write the 32 lower bits of the address (in bits) */ |
397 | lo_paddr = paddr << 3; | |
398 | DRM_DEBUG_DRIVER("Setting address lower bits to 0x%x\n", lo_paddr); | |
87969338 IZ |
399 | regmap_write(backend->engine.regs, |
400 | SUN4I_BACKEND_LAYFB_L32ADD_REG(layer), | |
9026e0d1 MR |
401 | lo_paddr); |
402 | ||
403 | /* And the upper bits */ | |
404 | hi_paddr = paddr >> 29; | |
405 | DRM_DEBUG_DRIVER("Setting address high bits to 0x%x\n", hi_paddr); | |
87969338 | 406 | regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_LAYFB_H4ADD_REG, |
9026e0d1 MR |
407 | SUN4I_BACKEND_LAYFB_H4ADD_MSK(layer), |
408 | SUN4I_BACKEND_LAYFB_H4ADD(layer, hi_paddr)); | |
409 | ||
410 | return 0; | |
411 | } | |
9026e0d1 | 412 | |
47a05f4a MR |
413 | int sun4i_backend_update_layer_zpos(struct sun4i_backend *backend, int layer, |
414 | struct drm_plane *plane) | |
415 | { | |
416 | struct drm_plane_state *state = plane->state; | |
8f1f2553 | 417 | struct sun4i_layer_state *p_state = state_to_sun4i_layer_state(state); |
47a05f4a | 418 | unsigned int priority = state->normalized_zpos; |
8f1f2553 | 419 | unsigned int pipe = p_state->pipe; |
47a05f4a | 420 | |
8f1f2553 MR |
421 | DRM_DEBUG_DRIVER("Setting layer %d's priority to %d and pipe %d\n", |
422 | layer, priority, pipe); | |
47a05f4a | 423 | regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer), |
8f1f2553 | 424 | SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL_MASK | |
47a05f4a | 425 | SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL_MASK, |
8f1f2553 | 426 | SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL(p_state->pipe) | |
47a05f4a MR |
427 | SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL(priority)); |
428 | ||
429 | return 0; | |
430 | } | |
431 | ||
686d2638 PK |
432 | void sun4i_backend_cleanup_layer(struct sun4i_backend *backend, |
433 | int layer) | |
434 | { | |
435 | regmap_update_bits(backend->engine.regs, | |
436 | SUN4I_BACKEND_ATTCTL_REG0(layer), | |
437 | SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN | | |
438 | SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN, 0); | |
439 | } | |
440 | ||
96180dde MR |
441 | static bool sun4i_backend_plane_uses_scaler(struct drm_plane_state *state) |
442 | { | |
443 | u16 src_h = state->src_h >> 16; | |
444 | u16 src_w = state->src_w >> 16; | |
445 | ||
446 | DRM_DEBUG_DRIVER("Input size %dx%d, output size %dx%d\n", | |
447 | src_w, src_h, state->crtc_w, state->crtc_h); | |
448 | ||
449 | if ((state->crtc_h != src_h) || (state->crtc_w != src_w)) | |
450 | return true; | |
451 | ||
452 | return false; | |
453 | } | |
454 | ||
455 | static bool sun4i_backend_plane_uses_frontend(struct drm_plane_state *state) | |
456 | { | |
457 | struct sun4i_layer *layer = plane_to_sun4i_layer(state->plane); | |
458 | struct sun4i_backend *backend = layer->backend; | |
aaf3880b | 459 | uint32_t format = state->fb->format->format; |
02a3ce3c | 460 | uint64_t modifier = state->fb->modifier; |
96180dde MR |
461 | |
462 | if (IS_ERR(backend->frontend)) | |
463 | return false; | |
464 | ||
02a3ce3c | 465 | if (!sun4i_frontend_format_is_supported(format, modifier)) |
aaf3880b PK |
466 | return false; |
467 | ||
02a3ce3c | 468 | if (!sun4i_backend_format_is_supported(format, modifier)) |
aaf3880b PK |
469 | return true; |
470 | ||
ad25d073 PK |
471 | /* |
472 | * TODO: The backend alone allows 2x and 4x integer scaling, including | |
473 | * support for an alpha component (which the frontend doesn't support). | |
aaf3880b PK |
474 | * Use the backend directly instead of the frontend in this case, with |
475 | * another test to return false. | |
476 | */ | |
477 | ||
478 | if (sun4i_backend_plane_uses_scaler(state)) | |
479 | return true; | |
480 | ||
481 | /* | |
482 | * Here the format is supported by both the frontend and the backend | |
483 | * and no frontend scaling is required, so use the backend directly. | |
ad25d073 | 484 | */ |
aaf3880b | 485 | return false; |
96180dde MR |
486 | } |
487 | ||
ab698510 PK |
488 | static bool sun4i_backend_plane_is_supported(struct drm_plane_state *state, |
489 | bool *uses_frontend) | |
490 | { | |
491 | if (sun4i_backend_plane_uses_frontend(state)) { | |
492 | *uses_frontend = true; | |
493 | return true; | |
494 | } | |
495 | ||
496 | *uses_frontend = false; | |
497 | ||
498 | /* Scaling is not supported without the frontend. */ | |
499 | if (sun4i_backend_plane_uses_scaler(state)) | |
500 | return false; | |
501 | ||
502 | return true; | |
503 | } | |
504 | ||
dd63250c MR |
505 | static void sun4i_backend_atomic_begin(struct sunxi_engine *engine, |
506 | struct drm_crtc_state *old_state) | |
507 | { | |
508 | u32 val; | |
509 | ||
510 | WARN_ON(regmap_read_poll_timeout(engine->regs, | |
511 | SUN4I_BACKEND_REGBUFFCTL_REG, | |
512 | val, !(val & SUN4I_BACKEND_REGBUFFCTL_LOADCTL), | |
513 | 100, 50000)); | |
514 | } | |
515 | ||
96180dde MR |
516 | static int sun4i_backend_atomic_check(struct sunxi_engine *engine, |
517 | struct drm_crtc_state *crtc_state) | |
518 | { | |
8f1f2553 | 519 | struct drm_plane_state *plane_states[SUN4I_BACKEND_NUM_LAYERS] = { 0 }; |
dcf496a6 | 520 | struct sun4i_backend *backend = engine_to_sun4i_backend(engine); |
96180dde MR |
521 | struct drm_atomic_state *state = crtc_state->state; |
522 | struct drm_device *drm = state->dev; | |
523 | struct drm_plane *plane; | |
65f7fa3a MR |
524 | unsigned int num_planes = 0; |
525 | unsigned int num_alpha_planes = 0; | |
96180dde | 526 | unsigned int num_frontend_planes = 0; |
dcf496a6 | 527 | unsigned int num_alpha_planes_max = 1; |
32463556 | 528 | unsigned int num_yuv_planes = 0; |
8f1f2553 MR |
529 | unsigned int current_pipe = 0; |
530 | unsigned int i; | |
96180dde MR |
531 | |
532 | DRM_DEBUG_DRIVER("Starting checking our planes\n"); | |
533 | ||
534 | if (!crtc_state->planes_changed) | |
535 | return 0; | |
536 | ||
537 | drm_for_each_plane_mask(plane, drm, crtc_state->plane_mask) { | |
538 | struct drm_plane_state *plane_state = | |
539 | drm_atomic_get_plane_state(state, plane); | |
540 | struct sun4i_layer_state *layer_state = | |
541 | state_to_sun4i_layer_state(plane_state); | |
65f7fa3a MR |
542 | struct drm_framebuffer *fb = plane_state->fb; |
543 | struct drm_format_name_buf format_name; | |
96180dde | 544 | |
ab698510 PK |
545 | if (!sun4i_backend_plane_is_supported(plane_state, |
546 | &layer_state->uses_frontend)) | |
547 | return -EINVAL; | |
548 | ||
549 | if (layer_state->uses_frontend) { | |
96180dde MR |
550 | DRM_DEBUG_DRIVER("Using the frontend for plane %d\n", |
551 | plane->index); | |
96180dde | 552 | num_frontend_planes++; |
ae56bfbd PK |
553 | } else { |
554 | if (fb->format->is_yuv) { | |
555 | DRM_DEBUG_DRIVER("Plane FB format is YUV\n"); | |
556 | num_yuv_planes++; | |
557 | } | |
96180dde | 558 | } |
65f7fa3a MR |
559 | |
560 | DRM_DEBUG_DRIVER("Plane FB format is %s\n", | |
561 | drm_get_format_name(fb->format->format, | |
562 | &format_name)); | |
d99008aa | 563 | if (fb->format->has_alpha || (plane_state->alpha != DRM_BLEND_ALPHA_OPAQUE)) |
65f7fa3a MR |
564 | num_alpha_planes++; |
565 | ||
8f1f2553 MR |
566 | DRM_DEBUG_DRIVER("Plane zpos is %d\n", |
567 | plane_state->normalized_zpos); | |
568 | ||
569 | /* Sort our planes by Zpos */ | |
570 | plane_states[plane_state->normalized_zpos] = plane_state; | |
571 | ||
65f7fa3a MR |
572 | num_planes++; |
573 | } | |
574 | ||
8f1f2553 MR |
575 | /* All our planes were disabled, bail out */ |
576 | if (!num_planes) | |
577 | return 0; | |
578 | ||
65f7fa3a MR |
579 | /* |
580 | * The hardware is a bit unusual here. | |
581 | * | |
582 | * Even though it supports 4 layers, it does the composition | |
583 | * in two separate steps. | |
584 | * | |
585 | * The first one is assigning a layer to one of its two | |
586 | * pipes. If more that 1 layer is assigned to the same pipe, | |
587 | * and if pixels overlaps, the pipe will take the pixel from | |
588 | * the layer with the highest priority. | |
589 | * | |
590 | * The second step is the actual alpha blending, that takes | |
dcf496a6 | 591 | * the two pipes as input, and uses the potential alpha |
65f7fa3a MR |
592 | * component to do the transparency between the two. |
593 | * | |
dcf496a6 | 594 | * This two-step scenario makes us unable to guarantee a |
65f7fa3a MR |
595 | * robust alpha blending between the 4 layers in all |
596 | * situations, since this means that we need to have one layer | |
597 | * with alpha at the lowest position of our two pipes. | |
598 | * | |
dcf496a6 PK |
599 | * However, we cannot even do that on every platform, since |
600 | * the hardware has a bug where the lowest plane of the lowest | |
601 | * pipe (pipe 0, priority 0), if it has any alpha, will | |
602 | * discard the pixel data entirely and just display the pixels | |
603 | * in the background color (black by default). | |
65f7fa3a | 604 | * |
dcf496a6 PK |
605 | * This means that on the affected platforms, we effectively |
606 | * have only three valid configurations with alpha, all of | |
607 | * them with the alpha being on pipe1 with the lowest | |
608 | * position, which can be 1, 2 or 3 depending on the number of | |
609 | * planes and their zpos. | |
65f7fa3a | 610 | */ |
dcf496a6 PK |
611 | |
612 | /* For platforms that are not affected by the issue described above. */ | |
613 | if (backend->quirks->supports_lowest_plane_alpha) | |
614 | num_alpha_planes_max++; | |
615 | ||
616 | if (num_alpha_planes > num_alpha_planes_max) { | |
65f7fa3a MR |
617 | DRM_DEBUG_DRIVER("Too many planes with alpha, rejecting...\n"); |
618 | return -EINVAL; | |
96180dde MR |
619 | } |
620 | ||
8f1f2553 | 621 | /* We can't have an alpha plane at the lowest position */ |
dcf496a6 PK |
622 | if (!backend->quirks->supports_lowest_plane_alpha && |
623 | (plane_states[0]->fb->format->has_alpha || | |
624 | (plane_states[0]->alpha != DRM_BLEND_ALPHA_OPAQUE))) | |
8f1f2553 MR |
625 | return -EINVAL; |
626 | ||
627 | for (i = 1; i < num_planes; i++) { | |
628 | struct drm_plane_state *p_state = plane_states[i]; | |
629 | struct drm_framebuffer *fb = p_state->fb; | |
630 | struct sun4i_layer_state *s_state = state_to_sun4i_layer_state(p_state); | |
631 | ||
632 | /* | |
633 | * The only alpha position is the lowest plane of the | |
634 | * second pipe. | |
635 | */ | |
d99008aa | 636 | if (fb->format->has_alpha || (p_state->alpha != DRM_BLEND_ALPHA_OPAQUE)) |
8f1f2553 MR |
637 | current_pipe++; |
638 | ||
639 | s_state->pipe = current_pipe; | |
640 | } | |
641 | ||
32463556 MR |
642 | /* We can only have a single YUV plane at a time */ |
643 | if (num_yuv_planes > SUN4I_BACKEND_NUM_YUV_PLANES) { | |
644 | DRM_DEBUG_DRIVER("Too many planes with YUV, rejecting...\n"); | |
645 | return -EINVAL; | |
646 | } | |
647 | ||
96180dde MR |
648 | if (num_frontend_planes > SUN4I_BACKEND_NUM_FRONTEND_LAYERS) { |
649 | DRM_DEBUG_DRIVER("Too many planes going through the frontend, rejecting\n"); | |
650 | return -EINVAL; | |
651 | } | |
652 | ||
32463556 MR |
653 | DRM_DEBUG_DRIVER("State valid with %u planes, %u alpha, %u video, %u YUV\n", |
654 | num_planes, num_alpha_planes, num_frontend_planes, | |
655 | num_yuv_planes); | |
65f7fa3a | 656 | |
96180dde MR |
657 | return 0; |
658 | } | |
659 | ||
ca07b210 MR |
660 | static void sun4i_backend_vblank_quirk(struct sunxi_engine *engine) |
661 | { | |
662 | struct sun4i_backend *backend = engine_to_sun4i_backend(engine); | |
663 | struct sun4i_frontend *frontend = backend->frontend; | |
664 | ||
665 | if (!frontend) | |
666 | return; | |
667 | ||
668 | /* | |
669 | * In a teardown scenario with the frontend involved, we have | |
670 | * to keep the frontend enabled until the next vblank, and | |
671 | * only then disable it. | |
672 | * | |
673 | * This is due to the fact that the backend will not take into | |
674 | * account the new configuration (with the plane that used to | |
675 | * be fed by the frontend now disabled) until we write to the | |
676 | * commit bit and the hardware fetches the new configuration | |
677 | * during the next vblank. | |
678 | * | |
679 | * So we keep the frontend around in order to prevent any | |
680 | * visual artifacts. | |
681 | */ | |
682 | spin_lock(&backend->frontend_lock); | |
683 | if (backend->frontend_teardown) { | |
684 | sun4i_frontend_exit(frontend); | |
685 | backend->frontend_teardown = false; | |
686 | } | |
687 | spin_unlock(&backend->frontend_lock); | |
688 | }; | |
689 | ||
440d2c7b MR |
690 | static int sun4i_backend_init_sat(struct device *dev) { |
691 | struct sun4i_backend *backend = dev_get_drvdata(dev); | |
692 | int ret; | |
693 | ||
694 | backend->sat_reset = devm_reset_control_get(dev, "sat"); | |
695 | if (IS_ERR(backend->sat_reset)) { | |
696 | dev_err(dev, "Couldn't get the SAT reset line\n"); | |
697 | return PTR_ERR(backend->sat_reset); | |
698 | } | |
699 | ||
700 | ret = reset_control_deassert(backend->sat_reset); | |
701 | if (ret) { | |
702 | dev_err(dev, "Couldn't deassert the SAT reset line\n"); | |
703 | return ret; | |
704 | } | |
705 | ||
706 | backend->sat_clk = devm_clk_get(dev, "sat"); | |
707 | if (IS_ERR(backend->sat_clk)) { | |
708 | dev_err(dev, "Couldn't get our SAT clock\n"); | |
709 | ret = PTR_ERR(backend->sat_clk); | |
710 | goto err_assert_reset; | |
711 | } | |
712 | ||
713 | ret = clk_prepare_enable(backend->sat_clk); | |
714 | if (ret) { | |
715 | dev_err(dev, "Couldn't enable the SAT clock\n"); | |
716 | return ret; | |
717 | } | |
718 | ||
719 | return 0; | |
720 | ||
721 | err_assert_reset: | |
722 | reset_control_assert(backend->sat_reset); | |
723 | return ret; | |
724 | } | |
725 | ||
726 | static int sun4i_backend_free_sat(struct device *dev) { | |
727 | struct sun4i_backend *backend = dev_get_drvdata(dev); | |
728 | ||
729 | clk_disable_unprepare(backend->sat_clk); | |
730 | reset_control_assert(backend->sat_reset); | |
731 | ||
732 | return 0; | |
733 | } | |
734 | ||
da3a1c30 CYT |
735 | /* |
736 | * The display backend can take video output from the display frontend, or | |
737 | * the display enhancement unit on the A80, as input for one it its layers. | |
738 | * This relationship within the display pipeline is encoded in the device | |
739 | * tree with of_graph, and we use it here to figure out which backend, if | |
740 | * there are 2 or more, we are currently probing. The number would be in | |
741 | * the "reg" property of the upstream output port endpoint. | |
742 | */ | |
743 | static int sun4i_backend_of_get_id(struct device_node *node) | |
744 | { | |
745 | struct device_node *port, *ep; | |
746 | int ret = -EINVAL; | |
747 | ||
748 | /* input is port 0 */ | |
749 | port = of_graph_get_port_by_id(node, 0); | |
750 | if (!port) | |
751 | return -EINVAL; | |
752 | ||
753 | /* try finding an upstream endpoint */ | |
754 | for_each_available_child_of_node(port, ep) { | |
755 | struct device_node *remote; | |
756 | u32 reg; | |
757 | ||
0bd46d70 | 758 | remote = of_graph_get_remote_endpoint(ep); |
da3a1c30 CYT |
759 | if (!remote) |
760 | continue; | |
761 | ||
762 | ret = of_property_read_u32(remote, "reg", ®); | |
763 | if (ret) | |
764 | continue; | |
765 | ||
766 | ret = reg; | |
767 | } | |
768 | ||
769 | of_node_put(port); | |
770 | ||
771 | return ret; | |
772 | } | |
773 | ||
ca07b210 MR |
774 | /* TODO: This needs to take multiple pipelines into account */ |
775 | static struct sun4i_frontend *sun4i_backend_find_frontend(struct sun4i_drv *drv, | |
776 | struct device_node *node) | |
777 | { | |
778 | struct device_node *port, *ep, *remote; | |
779 | struct sun4i_frontend *frontend; | |
780 | ||
781 | port = of_graph_get_port_by_id(node, 0); | |
782 | if (!port) | |
783 | return ERR_PTR(-EINVAL); | |
784 | ||
785 | for_each_available_child_of_node(port, ep) { | |
786 | remote = of_graph_get_remote_port_parent(ep); | |
787 | if (!remote) | |
788 | continue; | |
4bb0e6d7 | 789 | of_node_put(remote); |
ca07b210 MR |
790 | |
791 | /* does this node match any registered engines? */ | |
792 | list_for_each_entry(frontend, &drv->frontend_list, list) { | |
793 | if (remote == frontend->node) { | |
ca07b210 | 794 | of_node_put(port); |
4bb0e6d7 | 795 | of_node_put(ep); |
ca07b210 MR |
796 | return frontend; |
797 | } | |
798 | } | |
799 | } | |
4bb0e6d7 | 800 | of_node_put(port); |
ca07b210 MR |
801 | return ERR_PTR(-EINVAL); |
802 | } | |
803 | ||
87969338 | 804 | static const struct sunxi_engine_ops sun4i_backend_engine_ops = { |
dd63250c | 805 | .atomic_begin = sun4i_backend_atomic_begin, |
96180dde | 806 | .atomic_check = sun4i_backend_atomic_check, |
87969338 IZ |
807 | .commit = sun4i_backend_commit, |
808 | .layers_init = sun4i_layers_init, | |
809 | .apply_color_correction = sun4i_backend_apply_color_correction, | |
810 | .disable_color_correction = sun4i_backend_disable_color_correction, | |
ca07b210 | 811 | .vblank_quirk = sun4i_backend_vblank_quirk, |
87969338 IZ |
812 | }; |
813 | ||
9026e0d1 MR |
814 | static struct regmap_config sun4i_backend_regmap_config = { |
815 | .reg_bits = 32, | |
816 | .val_bits = 32, | |
817 | .reg_stride = 4, | |
818 | .max_register = 0x5800, | |
819 | }; | |
820 | ||
821 | static int sun4i_backend_bind(struct device *dev, struct device *master, | |
822 | void *data) | |
823 | { | |
824 | struct platform_device *pdev = to_platform_device(dev); | |
825 | struct drm_device *drm = data; | |
826 | struct sun4i_drv *drv = drm->dev_private; | |
827 | struct sun4i_backend *backend; | |
f55c83d3 | 828 | const struct sun4i_backend_quirks *quirks; |
9026e0d1 MR |
829 | struct resource *res; |
830 | void __iomem *regs; | |
831 | int i, ret; | |
832 | ||
833 | backend = devm_kzalloc(dev, sizeof(*backend), GFP_KERNEL); | |
834 | if (!backend) | |
835 | return -ENOMEM; | |
836 | dev_set_drvdata(dev, backend); | |
ca07b210 | 837 | spin_lock_init(&backend->frontend_lock); |
9026e0d1 | 838 | |
87969338 IZ |
839 | backend->engine.node = dev->of_node; |
840 | backend->engine.ops = &sun4i_backend_engine_ops; | |
841 | backend->engine.id = sun4i_backend_of_get_id(dev->of_node); | |
842 | if (backend->engine.id < 0) | |
843 | return backend->engine.id; | |
da3a1c30 | 844 | |
ca07b210 MR |
845 | backend->frontend = sun4i_backend_find_frontend(drv, dev->of_node); |
846 | if (IS_ERR(backend->frontend)) | |
847 | dev_warn(dev, "Couldn't find matching frontend, frontend features disabled\n"); | |
848 | ||
9026e0d1 MR |
849 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
850 | regs = devm_ioremap_resource(dev, res); | |
9a8aa939 | 851 | if (IS_ERR(regs)) |
9026e0d1 | 852 | return PTR_ERR(regs); |
9026e0d1 | 853 | |
9026e0d1 MR |
854 | backend->reset = devm_reset_control_get(dev, NULL); |
855 | if (IS_ERR(backend->reset)) { | |
856 | dev_err(dev, "Couldn't get our reset line\n"); | |
857 | return PTR_ERR(backend->reset); | |
858 | } | |
859 | ||
860 | ret = reset_control_deassert(backend->reset); | |
861 | if (ret) { | |
862 | dev_err(dev, "Couldn't deassert our reset line\n"); | |
863 | return ret; | |
864 | } | |
865 | ||
866 | backend->bus_clk = devm_clk_get(dev, "ahb"); | |
867 | if (IS_ERR(backend->bus_clk)) { | |
868 | dev_err(dev, "Couldn't get the backend bus clock\n"); | |
869 | ret = PTR_ERR(backend->bus_clk); | |
870 | goto err_assert_reset; | |
871 | } | |
872 | clk_prepare_enable(backend->bus_clk); | |
873 | ||
874 | backend->mod_clk = devm_clk_get(dev, "mod"); | |
875 | if (IS_ERR(backend->mod_clk)) { | |
876 | dev_err(dev, "Couldn't get the backend module clock\n"); | |
877 | ret = PTR_ERR(backend->mod_clk); | |
878 | goto err_disable_bus_clk; | |
879 | } | |
880 | clk_prepare_enable(backend->mod_clk); | |
881 | ||
882 | backend->ram_clk = devm_clk_get(dev, "ram"); | |
883 | if (IS_ERR(backend->ram_clk)) { | |
884 | dev_err(dev, "Couldn't get the backend RAM clock\n"); | |
885 | ret = PTR_ERR(backend->ram_clk); | |
886 | goto err_disable_mod_clk; | |
887 | } | |
888 | clk_prepare_enable(backend->ram_clk); | |
889 | ||
440d2c7b MR |
890 | if (of_device_is_compatible(dev->of_node, |
891 | "allwinner,sun8i-a33-display-backend")) { | |
892 | ret = sun4i_backend_init_sat(dev); | |
893 | if (ret) { | |
894 | dev_err(dev, "Couldn't init SAT resources\n"); | |
895 | goto err_disable_ram_clk; | |
896 | } | |
897 | } | |
898 | ||
8270249f CYT |
899 | backend->engine.regs = devm_regmap_init_mmio(dev, regs, |
900 | &sun4i_backend_regmap_config); | |
901 | if (IS_ERR(backend->engine.regs)) { | |
902 | dev_err(dev, "Couldn't create the backend regmap\n"); | |
903 | return PTR_ERR(backend->engine.regs); | |
904 | } | |
905 | ||
87969338 | 906 | list_add_tail(&backend->engine.list, &drv->engine_list); |
80a58240 | 907 | |
936598d1 CYT |
908 | /* |
909 | * Many of the backend's layer configuration registers have | |
910 | * undefined default values. This poses a risk as we use | |
911 | * regmap_update_bits in some places, and don't overwrite | |
912 | * the whole register. | |
913 | * | |
914 | * Clear the registers here to have something predictable. | |
915 | */ | |
9026e0d1 | 916 | for (i = 0x800; i < 0x1000; i += 4) |
87969338 | 917 | regmap_write(backend->engine.regs, i, 0); |
9026e0d1 MR |
918 | |
919 | /* Disable registers autoloading */ | |
87969338 | 920 | regmap_write(backend->engine.regs, SUN4I_BACKEND_REGBUFFCTL_REG, |
9026e0d1 MR |
921 | SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS); |
922 | ||
923 | /* Enable the backend */ | |
87969338 | 924 | regmap_write(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG, |
9026e0d1 MR |
925 | SUN4I_BACKEND_MODCTL_DEBE_EN | |
926 | SUN4I_BACKEND_MODCTL_START_CTL); | |
927 | ||
f55c83d3 CYT |
928 | /* Set output selection if needed */ |
929 | quirks = of_device_get_match_data(dev); | |
930 | if (quirks->needs_output_muxing) { | |
931 | /* | |
932 | * We assume there is no dynamic muxing of backends | |
933 | * and TCONs, so we select the backend with same ID. | |
934 | * | |
935 | * While dynamic selection might be interesting, since | |
936 | * the CRTC is tied to the TCON, while the layers are | |
937 | * tied to the backends, this means, we will need to | |
938 | * switch between groups of layers. There might not be | |
939 | * a way to represent this constraint in DRM. | |
940 | */ | |
941 | regmap_update_bits(backend->engine.regs, | |
942 | SUN4I_BACKEND_MODCTL_REG, | |
943 | SUN4I_BACKEND_MODCTL_OUT_SEL, | |
944 | (backend->engine.id | |
945 | ? SUN4I_BACKEND_MODCTL_OUT_LCD1 | |
946 | : SUN4I_BACKEND_MODCTL_OUT_LCD0)); | |
947 | } | |
948 | ||
e527cd9e PK |
949 | backend->quirks = quirks; |
950 | ||
9026e0d1 MR |
951 | return 0; |
952 | ||
440d2c7b MR |
953 | err_disable_ram_clk: |
954 | clk_disable_unprepare(backend->ram_clk); | |
9026e0d1 MR |
955 | err_disable_mod_clk: |
956 | clk_disable_unprepare(backend->mod_clk); | |
957 | err_disable_bus_clk: | |
958 | clk_disable_unprepare(backend->bus_clk); | |
959 | err_assert_reset: | |
960 | reset_control_assert(backend->reset); | |
961 | return ret; | |
962 | } | |
963 | ||
964 | static void sun4i_backend_unbind(struct device *dev, struct device *master, | |
965 | void *data) | |
966 | { | |
967 | struct sun4i_backend *backend = dev_get_drvdata(dev); | |
968 | ||
87969338 | 969 | list_del(&backend->engine.list); |
80a58240 | 970 | |
440d2c7b MR |
971 | if (of_device_is_compatible(dev->of_node, |
972 | "allwinner,sun8i-a33-display-backend")) | |
973 | sun4i_backend_free_sat(dev); | |
974 | ||
9026e0d1 MR |
975 | clk_disable_unprepare(backend->ram_clk); |
976 | clk_disable_unprepare(backend->mod_clk); | |
977 | clk_disable_unprepare(backend->bus_clk); | |
978 | reset_control_assert(backend->reset); | |
979 | } | |
980 | ||
dfeb693d | 981 | static const struct component_ops sun4i_backend_ops = { |
9026e0d1 MR |
982 | .bind = sun4i_backend_bind, |
983 | .unbind = sun4i_backend_unbind, | |
984 | }; | |
985 | ||
986 | static int sun4i_backend_probe(struct platform_device *pdev) | |
987 | { | |
988 | return component_add(&pdev->dev, &sun4i_backend_ops); | |
989 | } | |
990 | ||
991 | static int sun4i_backend_remove(struct platform_device *pdev) | |
992 | { | |
993 | component_del(&pdev->dev, &sun4i_backend_ops); | |
994 | ||
995 | return 0; | |
996 | } | |
997 | ||
9a8187c0 CYT |
998 | static const struct sun4i_backend_quirks sun4i_backend_quirks = { |
999 | .needs_output_muxing = true, | |
1000 | }; | |
1001 | ||
f55c83d3 CYT |
1002 | static const struct sun4i_backend_quirks sun5i_backend_quirks = { |
1003 | }; | |
1004 | ||
1005 | static const struct sun4i_backend_quirks sun6i_backend_quirks = { | |
1006 | }; | |
1007 | ||
aaddb6d2 JL |
1008 | static const struct sun4i_backend_quirks sun7i_backend_quirks = { |
1009 | .needs_output_muxing = true, | |
dcf496a6 | 1010 | .supports_lowest_plane_alpha = true, |
aaddb6d2 JL |
1011 | }; |
1012 | ||
f55c83d3 | 1013 | static const struct sun4i_backend_quirks sun8i_a33_backend_quirks = { |
dcf496a6 | 1014 | .supports_lowest_plane_alpha = true, |
f55c83d3 CYT |
1015 | }; |
1016 | ||
33478959 CYT |
1017 | static const struct sun4i_backend_quirks sun9i_backend_quirks = { |
1018 | }; | |
1019 | ||
9026e0d1 | 1020 | static const struct of_device_id sun4i_backend_of_table[] = { |
9a8187c0 CYT |
1021 | { |
1022 | .compatible = "allwinner,sun4i-a10-display-backend", | |
1023 | .data = &sun4i_backend_quirks, | |
1024 | }, | |
f55c83d3 CYT |
1025 | { |
1026 | .compatible = "allwinner,sun5i-a13-display-backend", | |
1027 | .data = &sun5i_backend_quirks, | |
1028 | }, | |
1029 | { | |
1030 | .compatible = "allwinner,sun6i-a31-display-backend", | |
1031 | .data = &sun6i_backend_quirks, | |
1032 | }, | |
aaddb6d2 JL |
1033 | { |
1034 | .compatible = "allwinner,sun7i-a20-display-backend", | |
1035 | .data = &sun7i_backend_quirks, | |
1036 | }, | |
f55c83d3 CYT |
1037 | { |
1038 | .compatible = "allwinner,sun8i-a33-display-backend", | |
1039 | .data = &sun8i_a33_backend_quirks, | |
1040 | }, | |
33478959 CYT |
1041 | { |
1042 | .compatible = "allwinner,sun9i-a80-display-backend", | |
1043 | .data = &sun9i_backend_quirks, | |
1044 | }, | |
9026e0d1 MR |
1045 | { } |
1046 | }; | |
1047 | MODULE_DEVICE_TABLE(of, sun4i_backend_of_table); | |
1048 | ||
1049 | static struct platform_driver sun4i_backend_platform_driver = { | |
1050 | .probe = sun4i_backend_probe, | |
1051 | .remove = sun4i_backend_remove, | |
1052 | .driver = { | |
1053 | .name = "sun4i-backend", | |
1054 | .of_match_table = sun4i_backend_of_table, | |
1055 | }, | |
1056 | }; | |
1057 | module_platform_driver(sun4i_backend_platform_driver); | |
1058 | ||
1059 | MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); | |
1060 | MODULE_DESCRIPTION("Allwinner A10 Display Backend Driver"); | |
1061 | MODULE_LICENSE("GPL"); |