[linux-block.git] / drivers / gpu / drm / sti / sti_mixer.c

/*
 * Copyright (C) STMicroelectronics SA 2014
 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
 *          Fabien Dessenne <fabien.dessenne@st.com>
 *          for STMicroelectronics.
 * License terms:  GNU General Public License (GPL), version 2
 */

#include "sti_compositor.h"
#include "sti_mixer.h"
#include "sti_vtg.h"

/* Identity: G=Y , B=Cb , R=Cr */
static const u32 mixerColorSpaceMatIdentity[] = {
	0x10000000, 0x00000000, 0x10000000, 0x00001000,
	0x00000000, 0x00000000, 0x00000000, 0x00000000
};

/* regs offset */
#define GAM_MIXER_CTL      0x00
#define GAM_MIXER_BKC      0x04
#define GAM_MIXER_BCO      0x0C
#define GAM_MIXER_BCS      0x10
#define GAM_MIXER_AVO      0x28
#define GAM_MIXER_AVS      0x2C
#define GAM_MIXER_CRB      0x34
#define GAM_MIXER_ACT      0x38
#define GAM_MIXER_MBP      0x3C
#define GAM_MIXER_MX0      0x80

/* id for depth of CRB reg */
#define GAM_DEPTH_VID0_ID  1
#define GAM_DEPTH_VID1_ID  2
#define GAM_DEPTH_GDP0_ID  3
#define GAM_DEPTH_GDP1_ID  4
#define GAM_DEPTH_GDP2_ID  5
#define GAM_DEPTH_GDP3_ID  6
#define GAM_DEPTH_MASK_ID  7

/* mask in CTL reg */
#define GAM_CTL_BACK_MASK  BIT(0)
#define GAM_CTL_VID0_MASK  BIT(1)
#define GAM_CTL_VID1_MASK  BIT(2)
#define GAM_CTL_GDP0_MASK  BIT(3)
#define GAM_CTL_GDP1_MASK  BIT(4)
#define GAM_CTL_GDP2_MASK  BIT(5)
#define GAM_CTL_GDP3_MASK  BIT(6)
#define GAM_CTL_CURSOR_MASK BIT(9)

const char *sti_mixer_to_str(struct sti_mixer *mixer)
{
	switch (mixer->id) {
	case STI_MIXER_MAIN:
		return "MAIN_MIXER";
	case STI_MIXER_AUX:
		return "AUX_MIXER";
	default:
		return "<UNKNOWN MIXER>";
	}
}

static inline u32 sti_mixer_reg_read(struct sti_mixer *mixer, u32 reg_id)
{
	return readl(mixer->regs + reg_id);
}

static inline void sti_mixer_reg_write(struct sti_mixer *mixer,
				       u32 reg_id, u32 val)
{
	writel(val, mixer->regs + reg_id);
}

void sti_mixer_set_background_status(struct sti_mixer *mixer, bool enable)
{
	u32 val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL);

	val &= ~GAM_CTL_BACK_MASK;
	val |= enable;
	sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
}

static void sti_mixer_set_background_color(struct sti_mixer *mixer,
					   u8 red, u8 green, u8 blue)
{
	u32 val = (red << 16) | (green << 8) | blue;

	sti_mixer_reg_write(mixer, GAM_MIXER_BKC, val);
}

static void sti_mixer_set_background_area(struct sti_mixer *mixer,
					  struct drm_display_mode *mode)
{
	u32 ydo, xdo, yds, xds;

	ydo = sti_vtg_get_line_number(*mode, 0);
	yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
	xdo = sti_vtg_get_pixel_number(*mode, 0);
	xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);

	sti_mixer_reg_write(mixer, GAM_MIXER_BCO, ydo << 16 | xdo);
	sti_mixer_reg_write(mixer, GAM_MIXER_BCS, yds << 16 | xds);
}

int sti_mixer_set_layer_depth(struct sti_mixer *mixer, struct sti_layer *layer)
{
	int layer_id, depth = layer->zorder;
	unsigned int i;
	u32 mask, val;

	if ((depth < 1) || (depth > GAM_MIXER_NB_DEPTH_LEVEL))
		return 1;

	switch (layer->desc) {
	case STI_GDP_0:
		layer_id = GAM_DEPTH_GDP0_ID;
		break;
	case STI_GDP_1:
		layer_id = GAM_DEPTH_GDP1_ID;
		break;
	case STI_GDP_2:
		layer_id = GAM_DEPTH_GDP2_ID;
		break;
	case STI_GDP_3:
		layer_id = GAM_DEPTH_GDP3_ID;
		break;
	case STI_VID_0:
	case STI_HQVDP_0:
		layer_id = GAM_DEPTH_VID0_ID;
		break;
	case STI_VID_1:
		layer_id = GAM_DEPTH_VID1_ID;
		break;
	case STI_CURSOR:
		/* no need to set depth for cursor */
		return 0;
	default:
		DRM_ERROR("Unknown layer %d\n", layer->desc);
		return 1;
	}

	/* Search if a previous depth was already assigned to the layer */
	val = sti_mixer_reg_read(mixer, GAM_MIXER_CRB);
	for (i = 0; i < GAM_MIXER_NB_DEPTH_LEVEL; i++) {
		mask = GAM_DEPTH_MASK_ID << (3 * i);
		if ((val & mask) == layer_id << (3 * i))
			break;
	}

	mask |= GAM_DEPTH_MASK_ID << (3 * (depth - 1));
	layer_id = layer_id << (3 * (depth - 1));

	DRM_DEBUG_DRIVER("%s %s depth=%d\n", sti_mixer_to_str(mixer),
			 sti_layer_to_str(layer), depth);
	dev_dbg(mixer->dev, "GAM_MIXER_CRB val 0x%x mask 0x%x\n",
		layer_id, mask);

	val &= ~mask;
	val |= layer_id;
	sti_mixer_reg_write(mixer, GAM_MIXER_CRB, val);

	dev_dbg(mixer->dev, "Read GAM_MIXER_CRB 0x%x\n",
		sti_mixer_reg_read(mixer, GAM_MIXER_CRB));
	return 0;
}

int sti_mixer_active_video_area(struct sti_mixer *mixer,
				struct drm_display_mode *mode)
{
	u32 ydo, xdo, yds, xds;

	ydo = sti_vtg_get_line_number(*mode, 0);
	yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
	xdo = sti_vtg_get_pixel_number(*mode, 0);
	xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);

	DRM_DEBUG_DRIVER("%s active video area xdo:%d ydo:%d xds:%d yds:%d\n",
			 sti_mixer_to_str(mixer), xdo, ydo, xds, yds);
	sti_mixer_reg_write(mixer, GAM_MIXER_AVO, ydo << 16 | xdo);
	sti_mixer_reg_write(mixer, GAM_MIXER_AVS, yds << 16 | xds);

	sti_mixer_set_background_color(mixer, 0xFF, 0, 0);

	sti_mixer_set_background_area(mixer, mode);
	sti_mixer_set_background_status(mixer, true);
	return 0;
}

static u32 sti_mixer_get_layer_mask(struct sti_layer *layer)
{
	switch (layer->desc) {
	case STI_BACK:
		return GAM_CTL_BACK_MASK;
	case STI_GDP_0:
		return GAM_CTL_GDP0_MASK;
	case STI_GDP_1:
		return GAM_CTL_GDP1_MASK;
	case STI_GDP_2:
		return GAM_CTL_GDP2_MASK;
	case STI_GDP_3:
		return GAM_CTL_GDP3_MASK;
	case STI_VID_0:
	case STI_HQVDP_0:
		return GAM_CTL_VID0_MASK;
	case STI_VID_1:
		return GAM_CTL_VID1_MASK;
	case STI_CURSOR:
		return GAM_CTL_CURSOR_MASK;
	default:
		return 0;
	}
}

int sti_mixer_set_layer_status(struct sti_mixer *mixer,
			       struct sti_layer *layer, bool status)
{
	u32 mask, val;

	DRM_DEBUG_DRIVER("%s %s %s\n", status ? "enable" : "disable",
			 sti_mixer_to_str(mixer), sti_layer_to_str(layer));

	mask = sti_mixer_get_layer_mask(layer);
	if (!mask) {
		DRM_ERROR("Can not find layer mask\n");
		return -EINVAL;
	}

	val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL);
	val &= ~mask;
	val |= status ? mask : 0;
	sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);

	return 0;
}

void sti_mixer_clear_all_layers(struct sti_mixer *mixer)
{
	u32 val;

	DRM_DEBUG_DRIVER("%s clear all layer\n", sti_mixer_to_str(mixer));
	val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL) & 0xFFFF0000;
	sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
}

void sti_mixer_set_matrix(struct sti_mixer *mixer)
{
	unsigned int i;

	for (i = 0; i < ARRAY_SIZE(mixerColorSpaceMatIdentity); i++)
		sti_mixer_reg_write(mixer, GAM_MIXER_MX0 + (i * 4),
				    mixerColorSpaceMatIdentity[i]);
}

struct sti_mixer *sti_mixer_create(struct device *dev, int id,
				   void __iomem *baseaddr)
{
	struct sti_mixer *mixer = devm_kzalloc(dev, sizeof(*mixer), GFP_KERNEL);
	struct device_node *np = dev->of_node;

	dev_dbg(dev, "%s\n", __func__);
	if (!mixer) {
		DRM_ERROR("Failed to allocated memory for mixer\n");
		return NULL;
	}
	mixer->regs = baseaddr;
	mixer->dev = dev;
	mixer->id = id;

	if (of_device_is_compatible(np, "st,stih416-compositor"))
		sti_mixer_set_matrix(mixer);

	DRM_DEBUG_DRIVER("%s created. Regs=%p\n",
			 sti_mixer_to_str(mixer), mixer->regs);

	return mixer;
}
Commit	Line	Data
e21e2193 BG	1	/*
	2	* Copyright (C) STMicroelectronics SA 2014
	3	* Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
	4	* Fabien Dessenne <fabien.dessenne@st.com>
	5	* for STMicroelectronics.
	6	* License terms: GNU General Public License (GPL), version 2
	7	*/
	8
d219673d	9	#include "sti_compositor.h"
e21e2193 BG	10	#include "sti_mixer.h"
	11	#include "sti_vtg.h"
	12
	13	/* Identity: G=Y , B=Cb , R=Cr */
	14	static const u32 mixerColorSpaceMatIdentity[] = {
	15	0x10000000, 0x00000000, 0x10000000, 0x00001000,
	16	0x00000000, 0x00000000, 0x00000000, 0x00000000
	17	};
	18
	19	/* regs offset */
	20	#define GAM_MIXER_CTL 0x00
	21	#define GAM_MIXER_BKC 0x04
	22	#define GAM_MIXER_BCO 0x0C
	23	#define GAM_MIXER_BCS 0x10
	24	#define GAM_MIXER_AVO 0x28
	25	#define GAM_MIXER_AVS 0x2C
	26	#define GAM_MIXER_CRB 0x34
	27	#define GAM_MIXER_ACT 0x38
	28	#define GAM_MIXER_MBP 0x3C
	29	#define GAM_MIXER_MX0 0x80
	30
	31	/* id for depth of CRB reg */
	32	#define GAM_DEPTH_VID0_ID 1
	33	#define GAM_DEPTH_VID1_ID 2
	34	#define GAM_DEPTH_GDP0_ID 3
	35	#define GAM_DEPTH_GDP1_ID 4
	36	#define GAM_DEPTH_GDP2_ID 5
	37	#define GAM_DEPTH_GDP3_ID 6
	38	#define GAM_DEPTH_MASK_ID 7
	39
	40	/* mask in CTL reg */
	41	#define GAM_CTL_BACK_MASK BIT(0)
	42	#define GAM_CTL_VID0_MASK BIT(1)
	43	#define GAM_CTL_VID1_MASK BIT(2)
	44	#define GAM_CTL_GDP0_MASK BIT(3)
	45	#define GAM_CTL_GDP1_MASK BIT(4)
	46	#define GAM_CTL_GDP2_MASK BIT(5)
	47	#define GAM_CTL_GDP3_MASK BIT(6)
96006a77	48	#define GAM_CTL_CURSOR_MASK BIT(9)
e21e2193 BG	49
	50	const char sti_mixer_to_str(struct sti_mixer mixer)
	51	{
	52	switch (mixer->id) {
	53	case STI_MIXER_MAIN:
	54	return "MAIN_MIXER";
	55	case STI_MIXER_AUX:
	56	return "AUX_MIXER";
	57	default:
	58	return "<UNKNOWN MIXER>";
	59	}
	60	}
	61
	62	static inline u32 sti_mixer_reg_read(struct sti_mixer *mixer, u32 reg_id)
	63	{
	64	return readl(mixer->regs + reg_id);
	65	}
	66
	67	static inline void sti_mixer_reg_write(struct sti_mixer *mixer,
	68	u32 reg_id, u32 val)
	69	{
	70	writel(val, mixer->regs + reg_id);
	71	}
	72
	73	void sti_mixer_set_background_status(struct sti_mixer *mixer, bool enable)
	74	{
	75	u32 val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL);
	76
	77	val &= ~GAM_CTL_BACK_MASK;
	78	val \|= enable;
	79	sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
	80	}
	81
	82	static void sti_mixer_set_background_color(struct sti_mixer *mixer,
	83	u8 red, u8 green, u8 blue)
	84	{
	85	u32 val = (red << 16) \| (green << 8) \| blue;
	86
	87	sti_mixer_reg_write(mixer, GAM_MIXER_BKC, val);
	88	}
	89
	90	static void sti_mixer_set_background_area(struct sti_mixer *mixer,
	91	struct drm_display_mode *mode)
	92	{
	93	u32 ydo, xdo, yds, xds;
	94
	95	ydo = sti_vtg_get_line_number(*mode, 0);
	96	yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
	97	xdo = sti_vtg_get_pixel_number(*mode, 0);
	98	xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
	99
	100	sti_mixer_reg_write(mixer, GAM_MIXER_BCO, ydo << 16 \| xdo);
	101	sti_mixer_reg_write(mixer, GAM_MIXER_BCS, yds << 16 \| xds);
	102	}
	103
	104	int sti_mixer_set_layer_depth(struct sti_mixer mixer, struct sti_layer layer)
	105	{
bf60b29f VA	106	int layer_id, depth = layer->zorder;
bf60b29f VA	107	unsigned int i;
e21e2193 BG	108	u32 mask, val;
e21e2193 BG	109
bf60b29f	110	if ((depth < 1) \|\| (depth > GAM_MIXER_NB_DEPTH_LEVEL))
e21e2193 BG	111	return 1;
	112
	113	switch (layer->desc) {
	114	case STI_GDP_0:
	115	layer_id = GAM_DEPTH_GDP0_ID;
	116	break;
	117	case STI_GDP_1:
	118	layer_id = GAM_DEPTH_GDP1_ID;
	119	break;
	120	case STI_GDP_2:
	121	layer_id = GAM_DEPTH_GDP2_ID;
	122	break;
	123	case STI_GDP_3:
	124	layer_id = GAM_DEPTH_GDP3_ID;
	125	break;
	126	case STI_VID_0:
4fdbc678	127	case STI_HQVDP_0:
e21e2193 BG	128	layer_id = GAM_DEPTH_VID0_ID;
	129	break;
	130	case STI_VID_1:
	131	layer_id = GAM_DEPTH_VID1_ID;
	132	break;
96006a77 BG	133	case STI_CURSOR:
	134	/* no need to set depth for cursor */
	135	return 0;
e21e2193 BG	136	default:
	137	DRM_ERROR("Unknown layer %d\n", layer->desc);
	138	return 1;
	139	}
bf60b29f VA	140
	141	/* Search if a previous depth was already assigned to the layer */
	142	val = sti_mixer_reg_read(mixer, GAM_MIXER_CRB);
	143	for (i = 0; i < GAM_MIXER_NB_DEPTH_LEVEL; i++) {
	144	mask = GAM_DEPTH_MASK_ID << (3 * i);
	145	if ((val & mask) == layer_id << (3 * i))
	146	break;
	147	}
	148
	149	mask \|= GAM_DEPTH_MASK_ID << (3 * (depth - 1));
	150	layer_id = layer_id << (3 * (depth - 1));
e21e2193	151
d219673d BG	152	DRM_DEBUG_DRIVER("%s %s depth=%d\n", sti_mixer_to_str(mixer),
d219673d BG	153	sti_layer_to_str(layer), depth);
e21e2193 BG	154	dev_dbg(mixer->dev, "GAM_MIXER_CRB val 0x%x mask 0x%x\n",
	155	layer_id, mask);
	156
e21e2193 BG	157	val &= ~mask;
	158	val \|= layer_id;
	159	sti_mixer_reg_write(mixer, GAM_MIXER_CRB, val);
	160
	161	dev_dbg(mixer->dev, "Read GAM_MIXER_CRB 0x%x\n",
	162	sti_mixer_reg_read(mixer, GAM_MIXER_CRB));
	163	return 0;
	164	}
	165
	166	int sti_mixer_active_video_area(struct sti_mixer *mixer,
	167	struct drm_display_mode *mode)
	168	{
	169	u32 ydo, xdo, yds, xds;
	170
	171	ydo = sti_vtg_get_line_number(*mode, 0);
	172	yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
	173	xdo = sti_vtg_get_pixel_number(*mode, 0);
	174	xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
	175
	176	DRM_DEBUG_DRIVER("%s active video area xdo:%d ydo:%d xds:%d yds:%d\n",
	177	sti_mixer_to_str(mixer), xdo, ydo, xds, yds);
	178	sti_mixer_reg_write(mixer, GAM_MIXER_AVO, ydo << 16 \| xdo);
	179	sti_mixer_reg_write(mixer, GAM_MIXER_AVS, yds << 16 \| xds);
	180
	181	sti_mixer_set_background_color(mixer, 0xFF, 0, 0);
	182
	183	sti_mixer_set_background_area(mixer, mode);
	184	sti_mixer_set_background_status(mixer, true);
	185	return 0;
	186	}
	187
	188	static u32 sti_mixer_get_layer_mask(struct sti_layer *layer)
	189	{
	190	switch (layer->desc) {
	191	case STI_BACK:
	192	return GAM_CTL_BACK_MASK;
	193	case STI_GDP_0:
	194	return GAM_CTL_GDP0_MASK;
	195	case STI_GDP_1:
	196	return GAM_CTL_GDP1_MASK;
	197	case STI_GDP_2:
	198	return GAM_CTL_GDP2_MASK;
	199	case STI_GDP_3:
	200	return GAM_CTL_GDP3_MASK;
	201	case STI_VID_0:
4fdbc678	202	case STI_HQVDP_0:
e21e2193 BG	203	return GAM_CTL_VID0_MASK;
	204	case STI_VID_1:
	205	return GAM_CTL_VID1_MASK;
96006a77 BG	206	case STI_CURSOR:
96006a77 BG	207	return GAM_CTL_CURSOR_MASK;
e21e2193 BG	208	default:
	209	return 0;
	210	}
	211	}
	212
	213	int sti_mixer_set_layer_status(struct sti_mixer *mixer,
	214	struct sti_layer *layer, bool status)
	215	{
	216	u32 mask, val;
	217
d219673d BG	218	DRM_DEBUG_DRIVER("%s %s %s\n", status ? "enable" : "disable",
	219	sti_mixer_to_str(mixer), sti_layer_to_str(layer));
	220
e21e2193 BG	221	mask = sti_mixer_get_layer_mask(layer);
	222	if (!mask) {
	223	DRM_ERROR("Can not find layer mask\n");
	224	return -EINVAL;
	225	}
	226
	227	val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL);
	228	val &= ~mask;
	229	val \|= status ? mask : 0;
	230	sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
	231
	232	return 0;
	233	}
	234
2f7d0e82 BG	235	void sti_mixer_clear_all_layers(struct sti_mixer *mixer)
	236	{
	237	u32 val;
	238
	239	DRM_DEBUG_DRIVER("%s clear all layer\n", sti_mixer_to_str(mixer));
	240	val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL) & 0xFFFF0000;
	241	sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
	242	}
	243
e21e2193 BG	244	void sti_mixer_set_matrix(struct sti_mixer *mixer)
	245	{
	246	unsigned int i;
	247
	248	for (i = 0; i < ARRAY_SIZE(mixerColorSpaceMatIdentity); i++)
	249	sti_mixer_reg_write(mixer, GAM_MIXER_MX0 + (i * 4),
	250	mixerColorSpaceMatIdentity[i]);
	251	}
	252
	253	struct sti_mixer sti_mixer_create(struct device dev, int id,
	254	void __iomem *baseaddr)
	255	{
	256	struct sti_mixer mixer = devm_kzalloc(dev, sizeof(mixer), GFP_KERNEL);
	257	struct device_node *np = dev->of_node;
	258
	259	dev_dbg(dev, "%s\n", __func__);
	260	if (!mixer) {
	261	DRM_ERROR("Failed to allocated memory for mixer\n");
	262	return NULL;
	263	}
	264	mixer->regs = baseaddr;
	265	mixer->dev = dev;
	266	mixer->id = id;
	267
	268	if (of_device_is_compatible(np, "st,stih416-compositor"))
	269	sti_mixer_set_matrix(mixer);
	270
	271	DRM_DEBUG_DRIVER("%s created. Regs=%p\n",
	272	sti_mixer_to_str(mixer), mixer->regs);
	273
	274	return mixer;
	275	}