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Merge tag 'gpio-v5.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux...
[linux-2.6-block.git] / drivers / gpu / drm / sti / sti_hdmi.c
CommitLineData
e2842570 1// SPDX-License-Identifier: GPL-2.0
5402626c
BG		 2/*
3 * Copyright (C) STMicroelectronics SA 2014
4 * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics.
5402626c
BG		 5 */
6
7#include <linux/clk.h>
8#include <linux/component.h>
7ea6e6e4 9#include <linux/debugfs.h>
5402626c
BG		 10#include <linux/hdmi.h>
11#include <linux/module.h>
acff2f86 12#include <linux/io.h>
5402626c
BG		 13#include <linux/platform_device.h>
14#include <linux/reset.h>
15
de4b00b0 16#include <drm/drm_atomic_helper.h>
ee68c743 17#include <drm/drm_bridge.h>
5e2f97a9
SR		 18#include <drm/drm_debugfs.h>
19#include <drm/drm_drv.h>
5402626c 20#include <drm/drm_edid.h>
5e2f97a9
SR		 21#include <drm/drm_file.h>
22#include <drm/drm_print.h>
fcd70cd3 23#include <drm/drm_probe_helper.h>
5402626c 24
2c348e50
AP		 25#include <sound/hdmi-codec.h>
26
5402626c
BG		 27#include "sti_hdmi.h"
28#include "sti_hdmi_tx3g4c28phy.h"
5402626c
BG		 29#include "sti_vtg.h"
30
31#define HDMI_CFG 0x0000
32#define HDMI_INT_EN 0x0004
33#define HDMI_INT_STA 0x0008
34#define HDMI_INT_CLR 0x000C
35#define HDMI_STA 0x0010
36#define HDMI_ACTIVE_VID_XMIN 0x0100
37#define HDMI_ACTIVE_VID_XMAX 0x0104
38#define HDMI_ACTIVE_VID_YMIN 0x0108
39#define HDMI_ACTIVE_VID_YMAX 0x010C
40#define HDMI_DFLT_CHL0_DAT 0x0110
41#define HDMI_DFLT_CHL1_DAT 0x0114
42#define HDMI_DFLT_CHL2_DAT 0x0118
2c348e50
AP		 43#define HDMI_AUDIO_CFG 0x0200
44#define HDMI_SPDIF_FIFO_STATUS 0x0204
5402626c
BG		 45#define HDMI_SW_DI_1_HEAD_WORD 0x0210
46#define HDMI_SW_DI_1_PKT_WORD0 0x0214
47#define HDMI_SW_DI_1_PKT_WORD1 0x0218
48#define HDMI_SW_DI_1_PKT_WORD2 0x021C
49#define HDMI_SW_DI_1_PKT_WORD3 0x0220
50#define HDMI_SW_DI_1_PKT_WORD4 0x0224
51#define HDMI_SW_DI_1_PKT_WORD5 0x0228
52#define HDMI_SW_DI_1_PKT_WORD6 0x022C
53#define HDMI_SW_DI_CFG 0x0230
2c348e50
AP		 54#define HDMI_SAMPLE_FLAT_MASK 0x0244
55#define HDMI_AUDN 0x0400
56#define HDMI_AUD_CTS 0x0404
cffe1e89
AP		 57#define HDMI_SW_DI_2_HEAD_WORD 0x0600
58#define HDMI_SW_DI_2_PKT_WORD0 0x0604
59#define HDMI_SW_DI_2_PKT_WORD1 0x0608
60#define HDMI_SW_DI_2_PKT_WORD2 0x060C
61#define HDMI_SW_DI_2_PKT_WORD3 0x0610
62#define HDMI_SW_DI_2_PKT_WORD4 0x0614
63#define HDMI_SW_DI_2_PKT_WORD5 0x0618
64#define HDMI_SW_DI_2_PKT_WORD6 0x061C
e42e7bd7
VA		 65#define HDMI_SW_DI_3_HEAD_WORD 0x0620
66#define HDMI_SW_DI_3_PKT_WORD0 0x0624
67#define HDMI_SW_DI_3_PKT_WORD1 0x0628
68#define HDMI_SW_DI_3_PKT_WORD2 0x062C
69#define HDMI_SW_DI_3_PKT_WORD3 0x0630
70#define HDMI_SW_DI_3_PKT_WORD4 0x0634
71#define HDMI_SW_DI_3_PKT_WORD5 0x0638
72#define HDMI_SW_DI_3_PKT_WORD6 0x063C
5402626c
BG		 73
74#define HDMI_IFRAME_SLOT_AVI 1
cffe1e89 75#define HDMI_IFRAME_SLOT_AUDIO 2
e42e7bd7 76#define HDMI_IFRAME_SLOT_VENDOR 3
5402626c
BG		 77
78#define XCAT(prefix, x, suffix) prefix ## x ## suffix
79#define HDMI_SW_DI_N_HEAD_WORD(x) XCAT(HDMI_SW_DI_, x, _HEAD_WORD)
80#define HDMI_SW_DI_N_PKT_WORD0(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD0)
81#define HDMI_SW_DI_N_PKT_WORD1(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD1)
82#define HDMI_SW_DI_N_PKT_WORD2(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD2)
83#define HDMI_SW_DI_N_PKT_WORD3(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD3)
84#define HDMI_SW_DI_N_PKT_WORD4(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD4)
85#define HDMI_SW_DI_N_PKT_WORD5(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD5)
86#define HDMI_SW_DI_N_PKT_WORD6(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD6)
87
181975a2
VA		 88#define HDMI_SW_DI_MAX_WORD 7
89
5402626c
BG		 90#define HDMI_IFRAME_DISABLED 0x0
91#define HDMI_IFRAME_SINGLE_SHOT 0x1
92#define HDMI_IFRAME_FIELD 0x2
93#define HDMI_IFRAME_FRAME 0x3
94#define HDMI_IFRAME_MASK 0x3
95#define HDMI_IFRAME_CFG_DI_N(x, n) ((x) << ((n-1)*4)) /* n from 1 to 6 */
96
97#define HDMI_CFG_DEVICE_EN BIT(0)
98#define HDMI_CFG_HDMI_NOT_DVI BIT(1)
99#define HDMI_CFG_HDCP_EN BIT(2)
100#define HDMI_CFG_ESS_NOT_OESS BIT(3)
101#define HDMI_CFG_H_SYNC_POL_NEG BIT(4)
5402626c
BG		 102#define HDMI_CFG_V_SYNC_POL_NEG BIT(6)
103#define HDMI_CFG_422_EN BIT(8)
104#define HDMI_CFG_FIFO_OVERRUN_CLR BIT(12)
105#define HDMI_CFG_FIFO_UNDERRUN_CLR BIT(13)
106#define HDMI_CFG_SW_RST_EN BIT(31)
107
108#define HDMI_INT_GLOBAL BIT(0)
109#define HDMI_INT_SW_RST BIT(1)
110#define HDMI_INT_PIX_CAP BIT(3)
111#define HDMI_INT_HOT_PLUG BIT(4)
112#define HDMI_INT_DLL_LCK BIT(5)
113#define HDMI_INT_NEW_FRAME BIT(6)
114#define HDMI_INT_GENCTRL_PKT BIT(7)
2c348e50 115#define HDMI_INT_AUDIO_FIFO_XRUN BIT(8)
5402626c
BG		 116#define HDMI_INT_SINK_TERM_PRESENT BIT(11)
117
118#define HDMI_DEFAULT_INT (HDMI_INT_SINK_TERM_PRESENT \
119 | HDMI_INT_DLL_LCK \
120 | HDMI_INT_HOT_PLUG \
121 | HDMI_INT_GLOBAL)
122
123#define HDMI_WORKING_INT (HDMI_INT_SINK_TERM_PRESENT \
2c348e50 124 | HDMI_INT_AUDIO_FIFO_XRUN \
5402626c
BG		 125 | HDMI_INT_GENCTRL_PKT \
126 | HDMI_INT_NEW_FRAME \
127 | HDMI_INT_DLL_LCK \
128 | HDMI_INT_HOT_PLUG \
129 | HDMI_INT_PIX_CAP \
130 | HDMI_INT_SW_RST \
131 | HDMI_INT_GLOBAL)
132
133#define HDMI_STA_SW_RST BIT(1)
134
2c348e50
AP		 135#define HDMI_AUD_CFG_8CH BIT(0)
136#define HDMI_AUD_CFG_SPDIF_DIV_2 BIT(1)
137#define HDMI_AUD_CFG_SPDIF_DIV_3 BIT(2)
138#define HDMI_AUD_CFG_SPDIF_CLK_DIV_4 (BIT(1) | BIT(2))
139#define HDMI_AUD_CFG_CTS_CLK_256FS BIT(12)
140#define HDMI_AUD_CFG_DTS_INVALID BIT(16)
141#define HDMI_AUD_CFG_ONE_BIT_INVALID (BIT(18) | BIT(19) | BIT(20) | BIT(21))
142#define HDMI_AUD_CFG_CH12_VALID BIT(28)
143#define HDMI_AUD_CFG_CH34_VALID BIT(29)
144#define HDMI_AUD_CFG_CH56_VALID BIT(30)
145#define HDMI_AUD_CFG_CH78_VALID BIT(31)
146
147/* sample flat mask */
148#define HDMI_SAMPLE_FLAT_NO 0
149#define HDMI_SAMPLE_FLAT_SP0 BIT(0)
150#define HDMI_SAMPLE_FLAT_SP1 BIT(1)
151#define HDMI_SAMPLE_FLAT_SP2 BIT(2)
152#define HDMI_SAMPLE_FLAT_SP3 BIT(3)
153#define HDMI_SAMPLE_FLAT_ALL (HDMI_SAMPLE_FLAT_SP0 | HDMI_SAMPLE_FLAT_SP1 |\
154 HDMI_SAMPLE_FLAT_SP2 | HDMI_SAMPLE_FLAT_SP3)
155
cffe1e89
AP		 156#define HDMI_INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0)
157#define HDMI_INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8)
158#define HDMI_INFOFRAME_HEADER_LEN(x) (((x) & 0x0f) << 16)
159
5402626c
BG		 160struct sti_hdmi_connector {
161 struct drm_connector drm_connector;
162 struct drm_encoder *encoder;
163 struct sti_hdmi *hdmi;
5671cefb 164 struct drm_property *colorspace_property;
5402626c
BG		 165};
166
167#define to_sti_hdmi_connector(x) \
168 container_of(x, struct sti_hdmi_connector, drm_connector)
169
170u32 hdmi_read(struct sti_hdmi *hdmi, int offset)
171{
172 return readl(hdmi->regs + offset);
173}
174
175void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset)
176{
177 writel(val, hdmi->regs + offset);
178}
179
180/**
181 * HDMI interrupt handler threaded
182 *
183 * @irq: irq number
184 * @arg: connector structure
185 */
186static irqreturn_t hdmi_irq_thread(int irq, void *arg)
187{
188 struct sti_hdmi *hdmi = arg;
189
190 /* Hot plug/unplug IRQ */
191 if (hdmi->irq_status & HDMI_INT_HOT_PLUG) {
76569207 192 hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG;
5402626c
BG		 193 if (hdmi->drm_dev)
194 drm_helper_hpd_irq_event(hdmi->drm_dev);
195 }
196
197 /* Sw reset and PLL lock are exclusive so we can use the same
198 * event to signal them
199 */
200 if (hdmi->irq_status & (HDMI_INT_SW_RST | HDMI_INT_DLL_LCK)) {
201 hdmi->event_received = true;
202 wake_up_interruptible(&hdmi->wait_event);
203 }
204
2c348e50
AP		 205 /* Audio FIFO underrun IRQ */
206 if (hdmi->irq_status & HDMI_INT_AUDIO_FIFO_XRUN)
29ffa776 207 DRM_INFO("Warning: audio FIFO underrun occurs!\n");
2c348e50 208
5402626c
BG		 209 return IRQ_HANDLED;
210}
211
212/**
213 * HDMI interrupt handler
214 *
215 * @irq: irq number
216 * @arg: connector structure
217 */
218static irqreturn_t hdmi_irq(int irq, void *arg)
219{
220 struct sti_hdmi *hdmi = arg;
221
222 /* read interrupt status */
223 hdmi->irq_status = hdmi_read(hdmi, HDMI_INT_STA);
224
225 /* clear interrupt status */
226 hdmi_write(hdmi, hdmi->irq_status, HDMI_INT_CLR);
227
228 /* force sync bus write */
229 hdmi_read(hdmi, HDMI_INT_STA);
230
231 return IRQ_WAKE_THREAD;
232}
233
234/**
235 * Set hdmi active area depending on the drm display mode selected
236 *
237 * @hdmi: pointer on the hdmi internal structure
238 */
239static void hdmi_active_area(struct sti_hdmi *hdmi)
240{
241 u32 xmin, xmax;
242 u32 ymin, ymax;
243
8661532a
VA		 244 xmin = sti_vtg_get_pixel_number(hdmi->mode, 1);
245 xmax = sti_vtg_get_pixel_number(hdmi->mode, hdmi->mode.hdisplay);
5402626c
BG		 246 ymin = sti_vtg_get_line_number(hdmi->mode, 0);
247 ymax = sti_vtg_get_line_number(hdmi->mode, hdmi->mode.vdisplay - 1);
248
249 hdmi_write(hdmi, xmin, HDMI_ACTIVE_VID_XMIN);
250 hdmi_write(hdmi, xmax, HDMI_ACTIVE_VID_XMAX);
251 hdmi_write(hdmi, ymin, HDMI_ACTIVE_VID_YMIN);
252 hdmi_write(hdmi, ymax, HDMI_ACTIVE_VID_YMAX);
253}
254
255/**
256 * Overall hdmi configuration
257 *
258 * @hdmi: pointer on the hdmi internal structure
259 */
260static void hdmi_config(struct sti_hdmi *hdmi)
261{
262 u32 conf;
263
264 DRM_DEBUG_DRIVER("\n");
265
266 /* Clear overrun and underrun fifo */
267 conf = HDMI_CFG_FIFO_OVERRUN_CLR | HDMI_CFG_FIFO_UNDERRUN_CLR;
268
ffc4a6a1
VA		 269 /* Select encryption type and the framing mode */
270 conf |= HDMI_CFG_ESS_NOT_OESS;
97d7c576 271 if (hdmi->hdmi_monitor)
ffc4a6a1 272 conf |= HDMI_CFG_HDMI_NOT_DVI;
5402626c 273
5402626c
BG		 274 /* Set Hsync polarity */
275 if (hdmi->mode.flags & DRM_MODE_FLAG_NHSYNC) {
276 DRM_DEBUG_DRIVER("H Sync Negative\n");
277 conf |= HDMI_CFG_H_SYNC_POL_NEG;
278 }
279
280 /* Set Vsync polarity */
281 if (hdmi->mode.flags & DRM_MODE_FLAG_NVSYNC) {
282 DRM_DEBUG_DRIVER("V Sync Negative\n");
283 conf |= HDMI_CFG_V_SYNC_POL_NEG;
284 }
285
286 /* Enable HDMI */
287 conf |= HDMI_CFG_DEVICE_EN;
288
289 hdmi_write(hdmi, conf, HDMI_CFG);
290}
291
181975a2
VA		 292/*
293 * Helper to reset info frame
294 *
295 * @hdmi: pointer on the hdmi internal structure
296 * @slot: infoframe to reset
297 */
298static void hdmi_infoframe_reset(struct sti_hdmi *hdmi,
299 u32 slot)
300{
301 u32 val, i;
302 u32 head_offset, pack_offset;
303
304 switch (slot) {
305 case HDMI_IFRAME_SLOT_AVI:
306 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI);
307 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI);
308 break;
309 case HDMI_IFRAME_SLOT_AUDIO:
310 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AUDIO);
311 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AUDIO);
312 break;
e42e7bd7
VA		 313 case HDMI_IFRAME_SLOT_VENDOR:
314 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_VENDOR);
315 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_VENDOR);
316 break;
181975a2
VA		 317 default:
318 DRM_ERROR("unsupported infoframe slot: %#x\n", slot);
319 return;
320 }
321
322 /* Disable transmission for the selected slot */
323 val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
324 val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, slot);
325 hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
326
327 /* Reset info frame registers */
328 hdmi_write(hdmi, 0x0, head_offset);
329 for (i = 0; i < HDMI_SW_DI_MAX_WORD; i += sizeof(u32))
330 hdmi_write(hdmi, 0x0, pack_offset + i);
331}
332
cffe1e89
AP		 333/**
334 * Helper to concatenate infoframe in 32 bits word
335 *
336 * @ptr: pointer on the hdmi internal structure
cffe1e89
AP		 337 * @size: size to write
338 */
339static inline unsigned int hdmi_infoframe_subpack(const u8 *ptr, size_t size)
340{
341 unsigned long value = 0;
342 size_t i;
343
344 for (i = size; i > 0; i--)
345 value = (value << 8) | ptr[i - 1];
346
347 return value;
348}
349
350/**
351 * Helper to write info frame
352 *
353 * @hdmi: pointer on the hdmi internal structure
354 * @data: infoframe to write
355 * @size: size to write
356 */
e42e7bd7
VA		 357static void hdmi_infoframe_write_infopack(struct sti_hdmi *hdmi,
358 const u8 *data,
359 size_t size)
cffe1e89
AP		 360{
361 const u8 *ptr = data;
362 u32 val, slot, mode, i;
363 u32 head_offset, pack_offset;
cffe1e89
AP		 364
365 switch (*ptr) {
366 case HDMI_INFOFRAME_TYPE_AVI:
367 slot = HDMI_IFRAME_SLOT_AVI;
368 mode = HDMI_IFRAME_FIELD;
369 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI);
370 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI);
cffe1e89 371 break;
cffe1e89
AP		 372 case HDMI_INFOFRAME_TYPE_AUDIO:
373 slot = HDMI_IFRAME_SLOT_AUDIO;
374 mode = HDMI_IFRAME_FRAME;
375 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AUDIO);
376 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AUDIO);
cffe1e89 377 break;
e42e7bd7
VA		 378 case HDMI_INFOFRAME_TYPE_VENDOR:
379 slot = HDMI_IFRAME_SLOT_VENDOR;
380 mode = HDMI_IFRAME_FRAME;
381 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_VENDOR);
382 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_VENDOR);
383 break;
cffe1e89
AP		 384 default:
385 DRM_ERROR("unsupported infoframe type: %#x\n", *ptr);
386 return;
387 }
388
389 /* Disable transmission slot for updated infoframe */
390 val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
391 val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, slot);
392 hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
393
394 val = HDMI_INFOFRAME_HEADER_TYPE(*ptr++);
395 val |= HDMI_INFOFRAME_HEADER_VERSION(*ptr++);
396 val |= HDMI_INFOFRAME_HEADER_LEN(*ptr++);
397 writel(val, hdmi->regs + head_offset);
398
399 /*
400 * Each subpack contains 4 bytes
401 * The First Bytes of the first subpacket must contain the checksum
e42e7bd7 402 * Packet size is increase by one.
cffe1e89 403 */
e42e7bd7 404 size = size - HDMI_INFOFRAME_HEADER_SIZE + 1;
cffe1e89
AP		 405 for (i = 0; i < size; i += sizeof(u32)) {
406 size_t num;
407
408 num = min_t(size_t, size - i, sizeof(u32));
409 val = hdmi_infoframe_subpack(ptr, num);
410 ptr += sizeof(u32);
411 writel(val, hdmi->regs + pack_offset + i);
412 }
413
414 /* Enable transmission slot for updated infoframe */
415 val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
50f2138a 416 val |= HDMI_IFRAME_CFG_DI_N(mode, slot);
cffe1e89
AP		 417 hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
418}
419
5402626c
BG		 420/**
421 * Prepare and configure the AVI infoframe
422 *
423 * AVI infoframe are transmitted at least once per two video field and
424 * contains information about HDMI transmission mode such as color space,
425 * colorimetry, ...
426 *
427 * @hdmi: pointer on the hdmi internal structure
428 *
429 * Return negative value if error occurs
430 */
431static int hdmi_avi_infoframe_config(struct sti_hdmi *hdmi)
432{
433 struct drm_display_mode *mode = &hdmi->mode;
434 struct hdmi_avi_infoframe infoframe;
435 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
5402626c
BG		 436 int ret;
437
438 DRM_DEBUG_DRIVER("\n");
439
13d0add3
VS		 440 ret = drm_hdmi_avi_infoframe_from_display_mode(&infoframe,
441 hdmi->drm_connector, mode);
5402626c
BG		 442 if (ret < 0) {
443 DRM_ERROR("failed to setup AVI infoframe: %d\n", ret);
444 return ret;
445 }
446
447 /* fixed infoframe configuration not linked to the mode */
5671cefb 448 infoframe.colorspace = hdmi->colorspace;
5402626c
BG		 449 infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
450 infoframe.colorimetry = HDMI_COLORIMETRY_NONE;
451
452 ret = hdmi_avi_infoframe_pack(&infoframe, buffer, sizeof(buffer));
453 if (ret < 0) {
454 DRM_ERROR("failed to pack AVI infoframe: %d\n", ret);
455 return ret;
456 }
457
e42e7bd7 458 hdmi_infoframe_write_infopack(hdmi, buffer, ret);
5402626c 459
cffe1e89
AP		 460 return 0;
461}
462
463/**
464 * Prepare and configure the AUDIO infoframe
465 *
466 * AUDIO infoframe are transmitted once per frame and
467 * contains information about HDMI transmission mode such as audio codec,
468 * sample size, ...
469 *
470 * @hdmi: pointer on the hdmi internal structure
471 *
472 * Return negative value if error occurs
473 */
474static int hdmi_audio_infoframe_config(struct sti_hdmi *hdmi)
475{
2c348e50 476 struct hdmi_audio_params *audio = &hdmi->audio;
cffe1e89 477 u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
2c348e50
AP		 478 int ret, val;
479
480 DRM_DEBUG_DRIVER("enter %s, AIF %s\n", __func__,
481 audio->enabled ? "enable" : "disable");
482 if (audio->enabled) {
483 /* set audio parameters stored*/
484 ret = hdmi_audio_infoframe_pack(&audio->cea, buffer,
485 sizeof(buffer));
486 if (ret < 0) {
487 DRM_ERROR("failed to pack audio infoframe: %d\n", ret);
488 return ret;
489 }
490 hdmi_infoframe_write_infopack(hdmi, buffer, ret);
491 } else {
492 /*disable audio info frame transmission */
493 val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
494 val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK,
495 HDMI_IFRAME_SLOT_AUDIO);
496 hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
cffe1e89
AP		 497 }
498
e42e7bd7
VA		 499 return 0;
500}
501
502/*
503 * Prepare and configure the VS infoframe
504 *
505 * Vendor Specific infoframe are transmitted once per frame and
506 * contains vendor specific information.
507 *
508 * @hdmi: pointer on the hdmi internal structure
509 *
510 * Return negative value if error occurs
511 */
512#define HDMI_VENDOR_INFOFRAME_MAX_SIZE 6
513static int hdmi_vendor_infoframe_config(struct sti_hdmi *hdmi)
514{
515 struct drm_display_mode *mode = &hdmi->mode;
516 struct hdmi_vendor_infoframe infoframe;
517 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_VENDOR_INFOFRAME_MAX_SIZE];
518 int ret;
519
520 DRM_DEBUG_DRIVER("\n");
521
f1781e9b
VS		 522 ret = drm_hdmi_vendor_infoframe_from_display_mode(&infoframe,
523 hdmi->drm_connector,
524 mode);
e42e7bd7
VA		 525 if (ret < 0) {
526 /*
527 * Going into that statement does not means vendor infoframe
528 * fails. It just informed us that vendor infoframe is not
529 * needed for the selected mode. Only 4k or stereoscopic 3D
530 * mode requires vendor infoframe. So just simply return 0.
531 */
532 return 0;
533 }
534
535 ret = hdmi_vendor_infoframe_pack(&infoframe, buffer, sizeof(buffer));
536 if (ret < 0) {
537 DRM_ERROR("failed to pack VS infoframe: %d\n", ret);
538 return ret;
539 }
540
541 hdmi_infoframe_write_infopack(hdmi, buffer, ret);
5402626c
BG		 542
543 return 0;
544}
545
5dec1aff
BG		 546#define HDMI_TIMEOUT_SWRESET 100 /*milliseconds */
547
5402626c
BG		 548/**
549 * Software reset of the hdmi subsystem
550 *
551 * @hdmi: pointer on the hdmi internal structure
552 *
553 */
5402626c
BG		 554static void hdmi_swreset(struct sti_hdmi *hdmi)
555{
556 u32 val;
557
558 DRM_DEBUG_DRIVER("\n");
559
560 /* Enable hdmi_audio clock only during hdmi reset */
561 if (clk_prepare_enable(hdmi->clk_audio))
562 DRM_INFO("Failed to prepare/enable hdmi_audio clk\n");
563
564 /* Sw reset */
565 hdmi->event_received = false;
566
567 val = hdmi_read(hdmi, HDMI_CFG);
568 val |= HDMI_CFG_SW_RST_EN;
569 hdmi_write(hdmi, val, HDMI_CFG);
570
571 /* Wait reset completed */
572 wait_event_interruptible_timeout(hdmi->wait_event,
7c0ca70b 573 hdmi->event_received,
5402626c
BG		 574 msecs_to_jiffies
575 (HDMI_TIMEOUT_SWRESET));
576
577 /*
578 * HDMI_STA_SW_RST bit is set to '1' when SW_RST bit in HDMI_CFG is
579 * set to '1' and clk_audio is running.
580 */
581 if ((hdmi_read(hdmi, HDMI_STA) & HDMI_STA_SW_RST) == 0)
582 DRM_DEBUG_DRIVER("Warning: HDMI sw reset timeout occurs\n");
583
584 val = hdmi_read(hdmi, HDMI_CFG);
585 val &= ~HDMI_CFG_SW_RST_EN;
586 hdmi_write(hdmi, val, HDMI_CFG);
587
588 /* Disable hdmi_audio clock. Not used anymore for drm purpose */
589 clk_disable_unprepare(hdmi->clk_audio);
590}
591
7ea6e6e4
VA		 592#define DBGFS_PRINT_STR(str1, str2) seq_printf(s, "%-24s %s\n", str1, str2)
593#define DBGFS_PRINT_INT(str1, int2) seq_printf(s, "%-24s %d\n", str1, int2)
594#define DBGFS_DUMP(str, reg) seq_printf(s, "%s %-25s 0x%08X", str, #reg, \
595 hdmi_read(hdmi, reg))
596#define DBGFS_DUMP_DI(reg, slot) DBGFS_DUMP("\n", reg(slot))
597
598static void hdmi_dbg_cfg(struct seq_file *s, int val)
599{
600 int tmp;
601
e9635133 602 seq_putc(s, '\t');
7ea6e6e4
VA		 603 tmp = val & HDMI_CFG_HDMI_NOT_DVI;
604 DBGFS_PRINT_STR("mode:", tmp ? "HDMI" : "DVI");
605 seq_puts(s, "\t\t\t\t\t");
606 tmp = val & HDMI_CFG_HDCP_EN;
607 DBGFS_PRINT_STR("HDCP:", tmp ? "enable" : "disable");
608 seq_puts(s, "\t\t\t\t\t");
609 tmp = val & HDMI_CFG_ESS_NOT_OESS;
610 DBGFS_PRINT_STR("HDCP mode:", tmp ? "ESS enable" : "OESS enable");
611 seq_puts(s, "\t\t\t\t\t");
7ea6e6e4
VA		 612 tmp = val & HDMI_CFG_H_SYNC_POL_NEG;
613 DBGFS_PRINT_STR("Hsync polarity:", tmp ? "inverted" : "normal");
614 seq_puts(s, "\t\t\t\t\t");
615 tmp = val & HDMI_CFG_V_SYNC_POL_NEG;
616 DBGFS_PRINT_STR("Vsync polarity:", tmp ? "inverted" : "normal");
617 seq_puts(s, "\t\t\t\t\t");
618 tmp = val & HDMI_CFG_422_EN;
619 DBGFS_PRINT_STR("YUV422 format:", tmp ? "enable" : "disable");
620}
621
622static void hdmi_dbg_sta(struct seq_file *s, int val)
623{
624 int tmp;
625
e9635133 626 seq_putc(s, '\t');
7ea6e6e4
VA		 627 tmp = (val & HDMI_STA_DLL_LCK);
628 DBGFS_PRINT_STR("pll:", tmp ? "locked" : "not locked");
629 seq_puts(s, "\t\t\t\t\t");
630 tmp = (val & HDMI_STA_HOT_PLUG);
631 DBGFS_PRINT_STR("hdmi cable:", tmp ? "connected" : "not connected");
632}
633
634static void hdmi_dbg_sw_di_cfg(struct seq_file *s, int val)
635{
636 int tmp;
637 char *const en_di[] = {"no transmission",
638 "single transmission",
639 "once every field",
640 "once every frame"};
641
e9635133 642 seq_putc(s, '\t');
7ea6e6e4
VA		 643 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 1));
644 DBGFS_PRINT_STR("Data island 1:", en_di[tmp]);
645 seq_puts(s, "\t\t\t\t\t");
646 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 2)) >> 4;
647 DBGFS_PRINT_STR("Data island 2:", en_di[tmp]);
648 seq_puts(s, "\t\t\t\t\t");
649 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 3)) >> 8;
650 DBGFS_PRINT_STR("Data island 3:", en_di[tmp]);
651 seq_puts(s, "\t\t\t\t\t");
652 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 4)) >> 12;
653 DBGFS_PRINT_STR("Data island 4:", en_di[tmp]);
654 seq_puts(s, "\t\t\t\t\t");
655 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 5)) >> 16;
656 DBGFS_PRINT_STR("Data island 5:", en_di[tmp]);
657 seq_puts(s, "\t\t\t\t\t");
658 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 6)) >> 20;
659 DBGFS_PRINT_STR("Data island 6:", en_di[tmp]);
660}
661
662static int hdmi_dbg_show(struct seq_file *s, void *data)
663{
664 struct drm_info_node *node = s->private;
665 struct sti_hdmi *hdmi = (struct sti_hdmi *)node->info_ent->data;
7ea6e6e4
VA		 666
667 seq_printf(s, "HDMI: (vaddr = 0x%p)", hdmi->regs);
668 DBGFS_DUMP("\n", HDMI_CFG);
669 hdmi_dbg_cfg(s, hdmi_read(hdmi, HDMI_CFG));
670 DBGFS_DUMP("", HDMI_INT_EN);
671 DBGFS_DUMP("\n", HDMI_STA);
672 hdmi_dbg_sta(s, hdmi_read(hdmi, HDMI_STA));
673 DBGFS_DUMP("", HDMI_ACTIVE_VID_XMIN);
e9635133 674 seq_putc(s, '\t');
7ea6e6e4
VA		 675 DBGFS_PRINT_INT("Xmin:", hdmi_read(hdmi, HDMI_ACTIVE_VID_XMIN));
676 DBGFS_DUMP("", HDMI_ACTIVE_VID_XMAX);
e9635133 677 seq_putc(s, '\t');
7ea6e6e4
VA		 678 DBGFS_PRINT_INT("Xmax:", hdmi_read(hdmi, HDMI_ACTIVE_VID_XMAX));
679 DBGFS_DUMP("", HDMI_ACTIVE_VID_YMIN);
e9635133 680 seq_putc(s, '\t');
7ea6e6e4
VA		 681 DBGFS_PRINT_INT("Ymin:", hdmi_read(hdmi, HDMI_ACTIVE_VID_YMIN));
682 DBGFS_DUMP("", HDMI_ACTIVE_VID_YMAX);
e9635133 683 seq_putc(s, '\t');
7ea6e6e4
VA		 684 DBGFS_PRINT_INT("Ymax:", hdmi_read(hdmi, HDMI_ACTIVE_VID_YMAX));
685 DBGFS_DUMP("", HDMI_SW_DI_CFG);
686 hdmi_dbg_sw_di_cfg(s, hdmi_read(hdmi, HDMI_SW_DI_CFG));
687
2c348e50
AP		 688 DBGFS_DUMP("\n", HDMI_AUDIO_CFG);
689 DBGFS_DUMP("\n", HDMI_SPDIF_FIFO_STATUS);
690 DBGFS_DUMP("\n", HDMI_AUDN);
691
7ea6e6e4
VA		 692 seq_printf(s, "\n AVI Infoframe (Data Island slot N=%d):",
693 HDMI_IFRAME_SLOT_AVI);
694 DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_AVI);
695 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_AVI);
696 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_AVI);
697 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_AVI);
698 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_AVI);
699 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_AVI);
700 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_AVI);
701 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_AVI);
ecf79d15 702 seq_printf(s, "\n\n AUDIO Infoframe (Data Island slot N=%d):",
7ea6e6e4
VA		 703 HDMI_IFRAME_SLOT_AUDIO);
704 DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_AUDIO);
705 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_AUDIO);
706 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_AUDIO);
707 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_AUDIO);
708 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_AUDIO);
709 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_AUDIO);
710 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_AUDIO);
711 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_AUDIO);
ecf79d15 712 seq_printf(s, "\n\n VENDOR SPECIFIC Infoframe (Data Island slot N=%d):",
7ea6e6e4
VA		 713 HDMI_IFRAME_SLOT_VENDOR);
714 DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_VENDOR);
715 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_VENDOR);
716 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_VENDOR);
717 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_VENDOR);
718 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_VENDOR);
719 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_VENDOR);
720 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_VENDOR);
721 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_VENDOR);
e9635133 722 seq_putc(s, '\n');
7ea6e6e4
VA		 723 return 0;
724}
725
726static struct drm_info_list hdmi_debugfs_files[] = {
727 { "hdmi", hdmi_dbg_show, 0, NULL },
728};
729
54ac836b 730static void hdmi_debugfs_init(struct sti_hdmi *hdmi, struct drm_minor *minor)
7ea6e6e4
VA		 731{
732 unsigned int i;
733
734 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_files); i++)
735 hdmi_debugfs_files[i].data = hdmi;
736
54ac836b
WK		 737 drm_debugfs_create_files(hdmi_debugfs_files,
738 ARRAY_SIZE(hdmi_debugfs_files),
739 minor->debugfs_root, minor);
7ea6e6e4
VA		 740}
741
5402626c
BG		 742static void sti_hdmi_disable(struct drm_bridge *bridge)
743{
744 struct sti_hdmi *hdmi = bridge->driver_private;
745
746 u32 val = hdmi_read(hdmi, HDMI_CFG);
747
748 if (!hdmi->enabled)
749 return;
750
751 DRM_DEBUG_DRIVER("\n");
752
753 /* Disable HDMI */
754 val &= ~HDMI_CFG_DEVICE_EN;
755 hdmi_write(hdmi, val, HDMI_CFG);
756
757 hdmi_write(hdmi, 0xffffffff, HDMI_INT_CLR);
758
759 /* Stop the phy */
760 hdmi->phy_ops->stop(hdmi);
761
181975a2
VA		 762 /* Reset info frame transmission */
763 hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_AVI);
764 hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_AUDIO);
e42e7bd7 765 hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_VENDOR);
181975a2 766
5402626c
BG		 767 /* Set the default channel data to be a dark red */
768 hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL0_DAT);
769 hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL1_DAT);
770 hdmi_write(hdmi, 0x0060, HDMI_DFLT_CHL2_DAT);
771
772 /* Disable/unprepare hdmi clock */
773 clk_disable_unprepare(hdmi->clk_phy);
774 clk_disable_unprepare(hdmi->clk_tmds);
775 clk_disable_unprepare(hdmi->clk_pix);
776
777 hdmi->enabled = false;
bca55958
BG		 778
779 cec_notifier_set_phys_addr(hdmi->notifier, CEC_PHYS_ADDR_INVALID);
5402626c
BG		 780}
781
dd841870
AP		 782/**
783 * sti_hdmi_audio_get_non_coherent_n() - get N parameter for non-coherent
784 * clocks. None-coherent clocks means that audio and TMDS clocks have not the
785 * same source (drifts between clocks). In this case assumption is that CTS is
786 * automatically calculated by hardware.
787 *
788 * @audio_fs: audio frame clock frequency in Hz
789 *
790 * Values computed are based on table described in HDMI specification 1.4b
791 *
792 * Returns n value.
793 */
794static int sti_hdmi_audio_get_non_coherent_n(unsigned int audio_fs)
795{
796 unsigned int n;
797
798 switch (audio_fs) {
799 case 32000:
800 n = 4096;
801 break;
802 case 44100:
803 n = 6272;
804 break;
805 case 48000:
806 n = 6144;
807 break;
808 case 88200:
809 n = 6272 * 2;
810 break;
811 case 96000:
812 n = 6144 * 2;
813 break;
814 case 176400:
815 n = 6272 * 4;
816 break;
817 case 192000:
818 n = 6144 * 4;
819 break;
820 default:
821 /* Not pre-defined, recommended value: 128 * fs / 1000 */
822 n = (audio_fs * 128) / 1000;
823 }
824
825 return n;
826}
827
828static int hdmi_audio_configure(struct sti_hdmi *hdmi)
829{
830 int audio_cfg, n;
831 struct hdmi_audio_params *params = &hdmi->audio;
832 struct hdmi_audio_infoframe *info = &params->cea;
833
834 DRM_DEBUG_DRIVER("\n");
835
836 if (!hdmi->enabled)
837 return 0;
838
839 /* update N parameter */
840 n = sti_hdmi_audio_get_non_coherent_n(params->sample_rate);
841
842 DRM_DEBUG_DRIVER("Audio rate = %d Hz, TMDS clock = %d Hz, n = %d\n",
843 params->sample_rate, hdmi->mode.clock * 1000, n);
844 hdmi_write(hdmi, n, HDMI_AUDN);
845
846 /* update HDMI registers according to configuration */
847 audio_cfg = HDMI_AUD_CFG_SPDIF_DIV_2 | HDMI_AUD_CFG_DTS_INVALID |
848 HDMI_AUD_CFG_ONE_BIT_INVALID;
849
850 switch (info->channels) {
851 case 8:
852 audio_cfg |= HDMI_AUD_CFG_CH78_VALID;
df561f66 853 fallthrough;
dd841870
AP		 854 case 6:
855 audio_cfg |= HDMI_AUD_CFG_CH56_VALID;
df561f66 856 fallthrough;
dd841870
AP		 857 case 4:
858 audio_cfg |= HDMI_AUD_CFG_CH34_VALID | HDMI_AUD_CFG_8CH;
df561f66 859 fallthrough;
dd841870
AP		 860 case 2:
861 audio_cfg |= HDMI_AUD_CFG_CH12_VALID;
862 break;
863 default:
864 DRM_ERROR("ERROR: Unsupported number of channels (%d)!\n",
865 info->channels);
866 return -EINVAL;
867 }
868
869 hdmi_write(hdmi, audio_cfg, HDMI_AUDIO_CFG);
870
871 return hdmi_audio_infoframe_config(hdmi);
872}
873
5402626c
BG		 874static void sti_hdmi_pre_enable(struct drm_bridge *bridge)
875{
876 struct sti_hdmi *hdmi = bridge->driver_private;
877
878 DRM_DEBUG_DRIVER("\n");
879
880 if (hdmi->enabled)
881 return;
882
883 /* Prepare/enable clocks */
884 if (clk_prepare_enable(hdmi->clk_pix))
885 DRM_ERROR("Failed to prepare/enable hdmi_pix clk\n");
886 if (clk_prepare_enable(hdmi->clk_tmds))
887 DRM_ERROR("Failed to prepare/enable hdmi_tmds clk\n");
888 if (clk_prepare_enable(hdmi->clk_phy))
889 DRM_ERROR("Failed to prepare/enable hdmi_rejec_pll clk\n");
890
891 hdmi->enabled = true;
892
893 /* Program hdmi serializer and start phy */
894 if (!hdmi->phy_ops->start(hdmi)) {
895 DRM_ERROR("Unable to start hdmi phy\n");
896 return;
897 }
898
899 /* Program hdmi active area */
900 hdmi_active_area(hdmi);
901
902 /* Enable working interrupts */
903 hdmi_write(hdmi, HDMI_WORKING_INT, HDMI_INT_EN);
904
905 /* Program hdmi config */
906 hdmi_config(hdmi);
907
908 /* Program AVI infoframe */
909 if (hdmi_avi_infoframe_config(hdmi))
910 DRM_ERROR("Unable to configure AVI infoframe\n");
911
dd841870
AP		 912 if (hdmi->audio.enabled) {
913 if (hdmi_audio_configure(hdmi))
914 DRM_ERROR("Unable to configure audio\n");
915 } else {
916 hdmi_audio_infoframe_config(hdmi);
917 }
cffe1e89 918
e42e7bd7
VA		 919 /* Program VS infoframe */
920 if (hdmi_vendor_infoframe_config(hdmi))
921 DRM_ERROR("Unable to configure VS infoframe\n");
922
5402626c
BG		 923 /* Sw reset */
924 hdmi_swreset(hdmi);
925}
926
927static void sti_hdmi_set_mode(struct drm_bridge *bridge,
63f8f3ba
LP		 928 const struct drm_display_mode *mode,
929 const struct drm_display_mode *adjusted_mode)
5402626c
BG		 930{
931 struct sti_hdmi *hdmi = bridge->driver_private;
932 int ret;
933
934 DRM_DEBUG_DRIVER("\n");
935
936 /* Copy the drm display mode in the connector local structure */
937 memcpy(&hdmi->mode, mode, sizeof(struct drm_display_mode));
938
939 /* Update clock framerate according to the selected mode */
940 ret = clk_set_rate(hdmi->clk_pix, mode->clock * 1000);
941 if (ret < 0) {
942 DRM_ERROR("Cannot set rate (%dHz) for hdmi_pix clk\n",
943 mode->clock * 1000);
944 return;
945 }
946 ret = clk_set_rate(hdmi->clk_phy, mode->clock * 1000);
947 if (ret < 0) {
948 DRM_ERROR("Cannot set rate (%dHz) for hdmi_rejection_pll clk\n",
949 mode->clock * 1000);
950 return;
951 }
952}
953
954static void sti_hdmi_bridge_nope(struct drm_bridge *bridge)
955{
956 /* do nothing */
957}
958
5402626c
BG		 959static const struct drm_bridge_funcs sti_hdmi_bridge_funcs = {
960 .pre_enable = sti_hdmi_pre_enable,
961 .enable = sti_hdmi_bridge_nope,
962 .disable = sti_hdmi_disable,
963 .post_disable = sti_hdmi_bridge_nope,
964 .mode_set = sti_hdmi_set_mode,
5402626c
BG		 965};
966
967static int sti_hdmi_connector_get_modes(struct drm_connector *connector)
968{
41a14623
BG		 969 struct sti_hdmi_connector *hdmi_connector
970 = to_sti_hdmi_connector(connector);
971 struct sti_hdmi *hdmi = hdmi_connector->hdmi;
5402626c
BG		 972 struct edid *edid;
973 int count;
974
975 DRM_DEBUG_DRIVER("\n");
976
41a14623 977 edid = drm_get_edid(connector, hdmi->ddc_adapt);
5402626c
BG		 978 if (!edid)
979 goto fail;
980
97d7c576
VA		 981 hdmi->hdmi_monitor = drm_detect_hdmi_monitor(edid);
982 DRM_DEBUG_KMS("%s : %dx%d cm\n",
983 (hdmi->hdmi_monitor ? "hdmi monitor" : "dvi monitor"),
984 edid->width_cm, edid->height_cm);
bca55958 985 cec_notifier_set_phys_addr_from_edid(hdmi->notifier, edid);
97d7c576 986
5402626c 987 count = drm_add_edid_modes(connector, edid);
c555f023 988 drm_connector_update_edid_property(connector, edid);
5402626c
BG		 989
990 kfree(edid);
991 return count;
992
993fail:
871bcdfe 994 DRM_ERROR("Can't read HDMI EDID\n");
5402626c
BG		 995 return 0;
996}
997
998#define CLK_TOLERANCE_HZ 50
999
1000static int sti_hdmi_connector_mode_valid(struct drm_connector *connector,
1001 struct drm_display_mode *mode)
1002{
1003 int target = mode->clock * 1000;
1004 int target_min = target - CLK_TOLERANCE_HZ;
1005 int target_max = target + CLK_TOLERANCE_HZ;
1006 int result;
1007 struct sti_hdmi_connector *hdmi_connector
1008 = to_sti_hdmi_connector(connector);
1009 struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1010
1011
1012 result = clk_round_rate(hdmi->clk_pix, target);
1013
1014 DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n",
1015 target, result);
1016
1017 if ((result < target_min) || (result > target_max)) {
1018 DRM_DEBUG_DRIVER("hdmi pixclk=%d not supported\n", target);
1019 return MODE_BAD;
1020 }
1021
1022 return MODE_OK;
1023}
1024
c5de4853
VS		 1025static const
1026struct drm_connector_helper_funcs sti_hdmi_connector_helper_funcs = {
5402626c
BG		 1027 .get_modes = sti_hdmi_connector_get_modes,
1028 .mode_valid = sti_hdmi_connector_mode_valid,
5402626c
BG		 1029};
1030
1031/* get detection status of display device */
1032static enum drm_connector_status
1033sti_hdmi_connector_detect(struct drm_connector *connector, bool force)
1034{
1035 struct sti_hdmi_connector *hdmi_connector
1036 = to_sti_hdmi_connector(connector);
1037 struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1038
1039 DRM_DEBUG_DRIVER("\n");
1040
1041 if (hdmi->hpd) {
1042 DRM_DEBUG_DRIVER("hdmi cable connected\n");
1043 return connector_status_connected;
1044 }
1045
1046 DRM_DEBUG_DRIVER("hdmi cable disconnected\n");
bca55958 1047 cec_notifier_set_phys_addr(hdmi->notifier, CEC_PHYS_ADDR_INVALID);
5402626c
BG		 1048 return connector_status_disconnected;
1049}
1050
5671cefb
VA		 1051static void sti_hdmi_connector_init_property(struct drm_device *drm_dev,
1052 struct drm_connector *connector)
1053{
1054 struct sti_hdmi_connector *hdmi_connector
1055 = to_sti_hdmi_connector(connector);
1056 struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1057 struct drm_property *prop;
1058
1059 /* colorspace property */
1060 hdmi->colorspace = DEFAULT_COLORSPACE_MODE;
1061 prop = drm_property_create_enum(drm_dev, 0, "colorspace",
1062 colorspace_mode_names,
1063 ARRAY_SIZE(colorspace_mode_names));
1064 if (!prop) {
1065 DRM_ERROR("fails to create colorspace property\n");
1066 return;
1067 }
1068 hdmi_connector->colorspace_property = prop;
1069 drm_object_attach_property(&connector->base, prop, hdmi->colorspace);
1070}
1071
1072static int
1073sti_hdmi_connector_set_property(struct drm_connector *connector,
1074 struct drm_connector_state *state,
1075 struct drm_property *property,
1076 uint64_t val)
1077{
1078 struct sti_hdmi_connector *hdmi_connector
1079 = to_sti_hdmi_connector(connector);
1080 struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1081
1082 if (property == hdmi_connector->colorspace_property) {
1083 hdmi->colorspace = val;
1084 return 0;
1085 }
1086
1087 DRM_ERROR("failed to set hdmi connector property\n");
1088 return -EINVAL;
1089}
1090
1091static int
1092sti_hdmi_connector_get_property(struct drm_connector *connector,
1093 const struct drm_connector_state *state,
1094 struct drm_property *property,
1095 uint64_t *val)
1096{
1097 struct sti_hdmi_connector *hdmi_connector
1098 = to_sti_hdmi_connector(connector);
1099 struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1100
1101 if (property == hdmi_connector->colorspace_property) {
1102 *val = hdmi->colorspace;
1103 return 0;
1104 }
1105
1106 DRM_ERROR("failed to get hdmi connector property\n");
1107 return -EINVAL;
1108}
1109
83af0a48
BG		 1110static int sti_hdmi_late_register(struct drm_connector *connector)
1111{
1112 struct sti_hdmi_connector *hdmi_connector
1113 = to_sti_hdmi_connector(connector);
1114 struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1115
54ac836b 1116 hdmi_debugfs_init(hdmi, hdmi->drm_dev->primary);
83af0a48
BG		 1117
1118 return 0;
1119}
1120
c5de4853 1121static const struct drm_connector_funcs sti_hdmi_connector_funcs = {
5402626c
BG		 1122 .fill_modes = drm_helper_probe_single_connector_modes,
1123 .detect = sti_hdmi_connector_detect,
84601dbd 1124 .destroy = drm_connector_cleanup,
de4b00b0 1125 .reset = drm_atomic_helper_connector_reset,
5671cefb
VA		 1126 .atomic_set_property = sti_hdmi_connector_set_property,
1127 .atomic_get_property = sti_hdmi_connector_get_property,
de4b00b0
BG		 1128 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1129 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
83af0a48 1130 .late_register = sti_hdmi_late_register,
5402626c
BG		 1131};
1132
1133static struct drm_encoder *sti_hdmi_find_encoder(struct drm_device *dev)
1134{
1135 struct drm_encoder *encoder;
1136
1137 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1138 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1139 return encoder;
1140 }
1141
1142 return NULL;
1143}
1144
5dd0775e 1145static void hdmi_audio_shutdown(struct device *dev, void *data)
2c348e50
AP		 1146{
1147 struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1148 int audio_cfg;
1149
1150 DRM_DEBUG_DRIVER("\n");
1151
1152 /* disable audio */
1153 audio_cfg = HDMI_AUD_CFG_SPDIF_DIV_2 | HDMI_AUD_CFG_DTS_INVALID |
1154 HDMI_AUD_CFG_ONE_BIT_INVALID;
1155 hdmi_write(hdmi, audio_cfg, HDMI_AUDIO_CFG);
1156
7c0ca70b 1157 hdmi->audio.enabled = false;
2c348e50
AP		 1158 hdmi_audio_infoframe_config(hdmi);
1159}
1160
1161static int hdmi_audio_hw_params(struct device *dev,
5dd0775e 1162 void *data,
2c348e50
AP		 1163 struct hdmi_codec_daifmt *daifmt,
1164 struct hdmi_codec_params *params)
1165{
1166 struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1167 int ret;
2c348e50
AP		 1168
1169 DRM_DEBUG_DRIVER("\n");
1170
2c348e50
AP		 1171 if ((daifmt->fmt != HDMI_I2S) || daifmt->bit_clk_inv ||
1172 daifmt->frame_clk_inv || daifmt->bit_clk_master ||
1173 daifmt->frame_clk_master) {
1174 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__,
1175 daifmt->bit_clk_inv, daifmt->frame_clk_inv,
1176 daifmt->bit_clk_master,
1177 daifmt->frame_clk_master);
1178 return -EINVAL;
1179 }
1180
dd841870
AP		 1181 hdmi->audio.sample_width = params->sample_width;
1182 hdmi->audio.sample_rate = params->sample_rate;
1183 hdmi->audio.cea = params->cea;
1184
1185 hdmi->audio.enabled = true;
2c348e50 1186
dd841870 1187 ret = hdmi_audio_configure(hdmi);
2c348e50
AP		 1188 if (ret < 0)
1189 return ret;
1190
1191 return 0;
1192}
1193
d789710f
KM		 1194static int hdmi_audio_mute(struct device *dev, void *data,
1195 bool enable, int direction)
2c348e50
AP		 1196{
1197 struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1198
1199 DRM_DEBUG_DRIVER("%s\n", enable ? "enable" : "disable");
1200
1201 if (enable)
1202 hdmi_write(hdmi, HDMI_SAMPLE_FLAT_ALL, HDMI_SAMPLE_FLAT_MASK);
1203 else
1204 hdmi_write(hdmi, HDMI_SAMPLE_FLAT_NO, HDMI_SAMPLE_FLAT_MASK);
1205
1206 return 0;
1207}
1208
5dd0775e 1209static int hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
2c348e50
AP		 1210{
1211 struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1212 struct drm_connector *connector = hdmi->drm_connector;
1213
1214 DRM_DEBUG_DRIVER("\n");
1215 memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
1216
1217 return 0;
1218}
1219
1220static const struct hdmi_codec_ops audio_codec_ops = {
1221 .hw_params = hdmi_audio_hw_params,
1222 .audio_shutdown = hdmi_audio_shutdown,
d789710f 1223 .mute_stream = hdmi_audio_mute,
2c348e50 1224 .get_eld = hdmi_audio_get_eld,
d789710f 1225 .no_capture_mute = 1,
2c348e50
AP		 1226};
1227
1228static int sti_hdmi_register_audio_driver(struct device *dev,
1229 struct sti_hdmi *hdmi)
1230{
1231 struct hdmi_codec_pdata codec_data = {
1232 .ops = &audio_codec_ops,
1233 .max_i2s_channels = 8,
1234 .i2s = 1,
1235 };
1236
1237 DRM_DEBUG_DRIVER("\n");
1238
7c0ca70b 1239 hdmi->audio.enabled = false;
2c348e50
AP		 1240
1241 hdmi->audio_pdev = platform_device_register_data(
1242 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
1243 &codec_data, sizeof(codec_data));
1244
1245 if (IS_ERR(hdmi->audio_pdev))
1246 return PTR_ERR(hdmi->audio_pdev);
1247
1248 DRM_INFO("%s Driver bound %s\n", HDMI_CODEC_DRV_NAME, dev_name(dev));
1249
1250 return 0;
1251}
1252
5402626c
BG		 1253static int sti_hdmi_bind(struct device *dev, struct device *master, void *data)
1254{
1255 struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1256 struct drm_device *drm_dev = data;
1257 struct drm_encoder *encoder;
1258 struct sti_hdmi_connector *connector;
536cce14 1259 struct cec_connector_info conn_info;
5402626c
BG		 1260 struct drm_connector *drm_connector;
1261 struct drm_bridge *bridge;
5402626c
BG		 1262 int err;
1263
5402626c
BG		 1264 /* Set the drm device handle */
1265 hdmi->drm_dev = drm_dev;
1266
1267 encoder = sti_hdmi_find_encoder(drm_dev);
1268 if (!encoder)
807642d7 1269 return -EINVAL;
5402626c
BG		 1270
1271 connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL);
1272 if (!connector)
807642d7 1273 return -EINVAL;
5402626c
BG		 1274
1275 connector->hdmi = hdmi;
1276
1277 bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
1278 if (!bridge)
807642d7 1279 return -EINVAL;
5402626c
BG		 1280
1281 bridge->driver_private = hdmi;
b07b90fd 1282 bridge->funcs = &sti_hdmi_bridge_funcs;
a25b988f 1283 drm_bridge_attach(encoder, bridge, NULL, 0);
5402626c 1284
5402626c
BG		 1285 connector->encoder = encoder;
1286
1287 drm_connector = (struct drm_connector *)connector;
1288
1289 drm_connector->polled = DRM_CONNECTOR_POLL_HPD;
1290
7058e766
AP		 1291 drm_connector_init_with_ddc(drm_dev, drm_connector,
1292 &sti_hdmi_connector_funcs,
1293 DRM_MODE_CONNECTOR_HDMIA,
1294 hdmi->ddc_adapt);
5402626c
BG		 1295 drm_connector_helper_add(drm_connector,
1296 &sti_hdmi_connector_helper_funcs);
1297
5671cefb
VA		 1298 /* initialise property */
1299 sti_hdmi_connector_init_property(drm_dev, drm_connector);
1300
2c348e50
AP		 1301 hdmi->drm_connector = drm_connector;
1302
cde4c44d 1303 err = drm_connector_attach_encoder(drm_connector, encoder);
5402626c
BG		 1304 if (err) {
1305 DRM_ERROR("Failed to attach a connector to a encoder\n");
1306 goto err_sysfs;
1307 }
1308
2c348e50
AP		 1309 err = sti_hdmi_register_audio_driver(dev, hdmi);
1310 if (err) {
1311 DRM_ERROR("Failed to attach an audio codec\n");
1312 goto err_sysfs;
1313 }
1314
1315 /* Initialize audio infoframe */
1316 err = hdmi_audio_infoframe_init(&hdmi->audio.cea);
1317 if (err) {
1318 DRM_ERROR("Failed to init audio infoframe\n");
1319 goto err_sysfs;
1320 }
1321
536cce14
DM		 1322 cec_fill_conn_info_from_drm(&conn_info, drm_connector);
1323 hdmi->notifier = cec_notifier_conn_register(&hdmi->dev, NULL,
1324 &conn_info);
1325 if (!hdmi->notifier) {
1326 hdmi->drm_connector = NULL;
1327 return -ENOMEM;
1328 }
1329
5402626c
BG		 1330 /* Enable default interrupts */
1331 hdmi_write(hdmi, HDMI_DEFAULT_INT, HDMI_INT_EN);
1332
1333 return 0;
1334
1335err_sysfs:
2c348e50 1336 hdmi->drm_connector = NULL;
5402626c
BG		 1337 return -EINVAL;
1338}
1339
1340static void sti_hdmi_unbind(struct device *dev,
1341 struct device *master, void *data)
1342{
536cce14
DM		 1343 struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1344
1345 cec_notifier_conn_unregister(hdmi->notifier);
5402626c
BG		 1346}
1347
1348static const struct component_ops sti_hdmi_ops = {
1349 .bind = sti_hdmi_bind,
1350 .unbind = sti_hdmi_unbind,
1351};
1352
8e932cf0 1353static const struct of_device_id hdmi_of_match[] = {
5402626c 1354 {
5402626c
BG		 1355 .compatible = "st,stih407-hdmi",
1356 .data = &tx3g4c28phy_ops,
1357 }, {
1358 /* end node */
1359 }
1360};
1361MODULE_DEVICE_TABLE(of, hdmi_of_match);
1362
1363static int sti_hdmi_probe(struct platform_device *pdev)
1364{
1365 struct device *dev = &pdev->dev;
1366 struct sti_hdmi *hdmi;
1367 struct device_node *np = dev->of_node;
1368 struct resource *res;
53bdcf5f 1369 struct device_node *ddc;
5402626c
BG		 1370 int ret;
1371
1372 DRM_INFO("%s\n", __func__);
1373
1374 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1375 if (!hdmi)
1376 return -ENOMEM;
1377
53bdcf5f
BG		 1378 ddc = of_parse_phandle(pdev->dev.of_node, "ddc", 0);
1379 if (ddc) {
4d5821a7 1380 hdmi->ddc_adapt = of_get_i2c_adapter_by_node(ddc);
53bdcf5f 1381 of_node_put(ddc);
4d5821a7
VZ		 1382 if (!hdmi->ddc_adapt)
1383 return -EPROBE_DEFER;
53bdcf5f
BG		 1384 }
1385
5402626c
BG		 1386 hdmi->dev = pdev->dev;
1387
1388 /* Get resources */
1389 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi-reg");
1390 if (!res) {
1391 DRM_ERROR("Invalid hdmi resource\n");
807642d7
VZ		 1392 ret = -ENOMEM;
1393 goto release_adapter;
5402626c 1394 }
4bdc0d67 1395 hdmi->regs = devm_ioremap(dev, res->start, resource_size(res));
807642d7
VZ		 1396 if (!hdmi->regs) {
1397 ret = -ENOMEM;
1398 goto release_adapter;
1399 }
5402626c 1400
5402626c
BG		 1401 hdmi->phy_ops = (struct hdmi_phy_ops *)
1402 of_match_node(hdmi_of_match, np)->data;
1403
1404 /* Get clock resources */
1405 hdmi->clk_pix = devm_clk_get(dev, "pix");
1406 if (IS_ERR(hdmi->clk_pix)) {
1407 DRM_ERROR("Cannot get hdmi_pix clock\n");
807642d7
VZ		 1408 ret = PTR_ERR(hdmi->clk_pix);
1409 goto release_adapter;
5402626c
BG		 1410 }
1411
1412 hdmi->clk_tmds = devm_clk_get(dev, "tmds");
1413 if (IS_ERR(hdmi->clk_tmds)) {
1414 DRM_ERROR("Cannot get hdmi_tmds clock\n");
807642d7
VZ		 1415 ret = PTR_ERR(hdmi->clk_tmds);
1416 goto release_adapter;
5402626c
BG		 1417 }
1418
1419 hdmi->clk_phy = devm_clk_get(dev, "phy");
1420 if (IS_ERR(hdmi->clk_phy)) {
1421 DRM_ERROR("Cannot get hdmi_phy clock\n");
807642d7
VZ		 1422 ret = PTR_ERR(hdmi->clk_phy);
1423 goto release_adapter;
5402626c
BG		 1424 }
1425
1426 hdmi->clk_audio = devm_clk_get(dev, "audio");
1427 if (IS_ERR(hdmi->clk_audio)) {
1428 DRM_ERROR("Cannot get hdmi_audio clock\n");
807642d7
VZ		 1429 ret = PTR_ERR(hdmi->clk_audio);
1430 goto release_adapter;
5402626c
BG		 1431 }
1432
76569207 1433 hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG;
5402626c
BG		 1434
1435 init_waitqueue_head(&hdmi->wait_event);
1436
1437 hdmi->irq = platform_get_irq_byname(pdev, "irq");
c83ecfa5
AY		 1438 if (hdmi->irq < 0) {
1439 DRM_ERROR("Cannot get HDMI irq\n");
1440 ret = hdmi->irq;
1441 goto release_adapter;
1442 }
5402626c
BG		 1443
1444 ret = devm_request_threaded_irq(dev, hdmi->irq, hdmi_irq,
1445 hdmi_irq_thread, IRQF_ONESHOT, dev_name(dev), hdmi);
1446 if (ret) {
1447 DRM_ERROR("Failed to register HDMI interrupt\n");
807642d7 1448 goto release_adapter;
5402626c
BG		 1449 }
1450
1451 hdmi->reset = devm_reset_control_get(dev, "hdmi");
1452 /* Take hdmi out of reset */
1453 if (!IS_ERR(hdmi->reset))
1454 reset_control_deassert(hdmi->reset);
1455
1456 platform_set_drvdata(pdev, hdmi);
1457
1458 return component_add(&pdev->dev, &sti_hdmi_ops);
807642d7
VZ		 1459
1460 release_adapter:
4d5821a7 1461 i2c_put_adapter(hdmi->ddc_adapt);
807642d7
VZ		 1462
1463 return ret;
5402626c
BG		 1464}
1465
1466static int sti_hdmi_remove(struct platform_device *pdev)
1467{
41a14623
BG		 1468 struct sti_hdmi *hdmi = dev_get_drvdata(&pdev->dev);
1469
4d5821a7 1470 i2c_put_adapter(hdmi->ddc_adapt);
2c348e50
AP		 1471 if (hdmi->audio_pdev)
1472 platform_device_unregister(hdmi->audio_pdev);
5402626c 1473 component_del(&pdev->dev, &sti_hdmi_ops);
4d5821a7 1474
5402626c
BG		 1475 return 0;
1476}
1477
1478struct platform_driver sti_hdmi_driver = {
1479 .driver = {
1480 .name = "sti-hdmi",
1481 .owner = THIS_MODULE,
1482 .of_match_table = hdmi_of_match,
1483 },
1484 .probe = sti_hdmi_probe,
1485 .remove = sti_hdmi_remove,
1486};
1487
5402626c
BG		 1488MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
1489MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
1490MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)