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5402626c BG |
1 | /* |
2 | * Copyright (C) STMicroelectronics SA 2014 | |
3 | * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics. | |
4 | * License terms: GNU General Public License (GPL), version 2 | |
5 | */ | |
6 | ||
7 | #include <linux/clk.h> | |
8 | #include <linux/component.h> | |
7ea6e6e4 | 9 | #include <linux/debugfs.h> |
5402626c BG |
10 | #include <linux/hdmi.h> |
11 | #include <linux/module.h> | |
12 | #include <linux/of_gpio.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/reset.h> | |
15 | ||
16 | #include <drm/drmP.h> | |
de4b00b0 | 17 | #include <drm/drm_atomic_helper.h> |
5402626c BG |
18 | #include <drm/drm_crtc_helper.h> |
19 | #include <drm/drm_edid.h> | |
20 | ||
2c348e50 AP |
21 | #include <sound/hdmi-codec.h> |
22 | ||
5402626c BG |
23 | #include "sti_hdmi.h" |
24 | #include "sti_hdmi_tx3g4c28phy.h" | |
5402626c BG |
25 | #include "sti_vtg.h" |
26 | ||
27 | #define HDMI_CFG 0x0000 | |
28 | #define HDMI_INT_EN 0x0004 | |
29 | #define HDMI_INT_STA 0x0008 | |
30 | #define HDMI_INT_CLR 0x000C | |
31 | #define HDMI_STA 0x0010 | |
32 | #define HDMI_ACTIVE_VID_XMIN 0x0100 | |
33 | #define HDMI_ACTIVE_VID_XMAX 0x0104 | |
34 | #define HDMI_ACTIVE_VID_YMIN 0x0108 | |
35 | #define HDMI_ACTIVE_VID_YMAX 0x010C | |
36 | #define HDMI_DFLT_CHL0_DAT 0x0110 | |
37 | #define HDMI_DFLT_CHL1_DAT 0x0114 | |
38 | #define HDMI_DFLT_CHL2_DAT 0x0118 | |
2c348e50 AP |
39 | #define HDMI_AUDIO_CFG 0x0200 |
40 | #define HDMI_SPDIF_FIFO_STATUS 0x0204 | |
5402626c BG |
41 | #define HDMI_SW_DI_1_HEAD_WORD 0x0210 |
42 | #define HDMI_SW_DI_1_PKT_WORD0 0x0214 | |
43 | #define HDMI_SW_DI_1_PKT_WORD1 0x0218 | |
44 | #define HDMI_SW_DI_1_PKT_WORD2 0x021C | |
45 | #define HDMI_SW_DI_1_PKT_WORD3 0x0220 | |
46 | #define HDMI_SW_DI_1_PKT_WORD4 0x0224 | |
47 | #define HDMI_SW_DI_1_PKT_WORD5 0x0228 | |
48 | #define HDMI_SW_DI_1_PKT_WORD6 0x022C | |
49 | #define HDMI_SW_DI_CFG 0x0230 | |
2c348e50 AP |
50 | #define HDMI_SAMPLE_FLAT_MASK 0x0244 |
51 | #define HDMI_AUDN 0x0400 | |
52 | #define HDMI_AUD_CTS 0x0404 | |
cffe1e89 AP |
53 | #define HDMI_SW_DI_2_HEAD_WORD 0x0600 |
54 | #define HDMI_SW_DI_2_PKT_WORD0 0x0604 | |
55 | #define HDMI_SW_DI_2_PKT_WORD1 0x0608 | |
56 | #define HDMI_SW_DI_2_PKT_WORD2 0x060C | |
57 | #define HDMI_SW_DI_2_PKT_WORD3 0x0610 | |
58 | #define HDMI_SW_DI_2_PKT_WORD4 0x0614 | |
59 | #define HDMI_SW_DI_2_PKT_WORD5 0x0618 | |
60 | #define HDMI_SW_DI_2_PKT_WORD6 0x061C | |
e42e7bd7 VA |
61 | #define HDMI_SW_DI_3_HEAD_WORD 0x0620 |
62 | #define HDMI_SW_DI_3_PKT_WORD0 0x0624 | |
63 | #define HDMI_SW_DI_3_PKT_WORD1 0x0628 | |
64 | #define HDMI_SW_DI_3_PKT_WORD2 0x062C | |
65 | #define HDMI_SW_DI_3_PKT_WORD3 0x0630 | |
66 | #define HDMI_SW_DI_3_PKT_WORD4 0x0634 | |
67 | #define HDMI_SW_DI_3_PKT_WORD5 0x0638 | |
68 | #define HDMI_SW_DI_3_PKT_WORD6 0x063C | |
5402626c BG |
69 | |
70 | #define HDMI_IFRAME_SLOT_AVI 1 | |
cffe1e89 | 71 | #define HDMI_IFRAME_SLOT_AUDIO 2 |
e42e7bd7 | 72 | #define HDMI_IFRAME_SLOT_VENDOR 3 |
5402626c BG |
73 | |
74 | #define XCAT(prefix, x, suffix) prefix ## x ## suffix | |
75 | #define HDMI_SW_DI_N_HEAD_WORD(x) XCAT(HDMI_SW_DI_, x, _HEAD_WORD) | |
76 | #define HDMI_SW_DI_N_PKT_WORD0(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD0) | |
77 | #define HDMI_SW_DI_N_PKT_WORD1(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD1) | |
78 | #define HDMI_SW_DI_N_PKT_WORD2(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD2) | |
79 | #define HDMI_SW_DI_N_PKT_WORD3(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD3) | |
80 | #define HDMI_SW_DI_N_PKT_WORD4(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD4) | |
81 | #define HDMI_SW_DI_N_PKT_WORD5(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD5) | |
82 | #define HDMI_SW_DI_N_PKT_WORD6(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD6) | |
83 | ||
181975a2 VA |
84 | #define HDMI_SW_DI_MAX_WORD 7 |
85 | ||
5402626c BG |
86 | #define HDMI_IFRAME_DISABLED 0x0 |
87 | #define HDMI_IFRAME_SINGLE_SHOT 0x1 | |
88 | #define HDMI_IFRAME_FIELD 0x2 | |
89 | #define HDMI_IFRAME_FRAME 0x3 | |
90 | #define HDMI_IFRAME_MASK 0x3 | |
91 | #define HDMI_IFRAME_CFG_DI_N(x, n) ((x) << ((n-1)*4)) /* n from 1 to 6 */ | |
92 | ||
93 | #define HDMI_CFG_DEVICE_EN BIT(0) | |
94 | #define HDMI_CFG_HDMI_NOT_DVI BIT(1) | |
95 | #define HDMI_CFG_HDCP_EN BIT(2) | |
96 | #define HDMI_CFG_ESS_NOT_OESS BIT(3) | |
97 | #define HDMI_CFG_H_SYNC_POL_NEG BIT(4) | |
98 | #define HDMI_CFG_SINK_TERM_DET_EN BIT(5) | |
99 | #define HDMI_CFG_V_SYNC_POL_NEG BIT(6) | |
100 | #define HDMI_CFG_422_EN BIT(8) | |
101 | #define HDMI_CFG_FIFO_OVERRUN_CLR BIT(12) | |
102 | #define HDMI_CFG_FIFO_UNDERRUN_CLR BIT(13) | |
103 | #define HDMI_CFG_SW_RST_EN BIT(31) | |
104 | ||
105 | #define HDMI_INT_GLOBAL BIT(0) | |
106 | #define HDMI_INT_SW_RST BIT(1) | |
107 | #define HDMI_INT_PIX_CAP BIT(3) | |
108 | #define HDMI_INT_HOT_PLUG BIT(4) | |
109 | #define HDMI_INT_DLL_LCK BIT(5) | |
110 | #define HDMI_INT_NEW_FRAME BIT(6) | |
111 | #define HDMI_INT_GENCTRL_PKT BIT(7) | |
2c348e50 | 112 | #define HDMI_INT_AUDIO_FIFO_XRUN BIT(8) |
5402626c BG |
113 | #define HDMI_INT_SINK_TERM_PRESENT BIT(11) |
114 | ||
115 | #define HDMI_DEFAULT_INT (HDMI_INT_SINK_TERM_PRESENT \ | |
116 | | HDMI_INT_DLL_LCK \ | |
117 | | HDMI_INT_HOT_PLUG \ | |
118 | | HDMI_INT_GLOBAL) | |
119 | ||
120 | #define HDMI_WORKING_INT (HDMI_INT_SINK_TERM_PRESENT \ | |
2c348e50 | 121 | | HDMI_INT_AUDIO_FIFO_XRUN \ |
5402626c BG |
122 | | HDMI_INT_GENCTRL_PKT \ |
123 | | HDMI_INT_NEW_FRAME \ | |
124 | | HDMI_INT_DLL_LCK \ | |
125 | | HDMI_INT_HOT_PLUG \ | |
126 | | HDMI_INT_PIX_CAP \ | |
127 | | HDMI_INT_SW_RST \ | |
128 | | HDMI_INT_GLOBAL) | |
129 | ||
130 | #define HDMI_STA_SW_RST BIT(1) | |
131 | ||
2c348e50 AP |
132 | #define HDMI_AUD_CFG_8CH BIT(0) |
133 | #define HDMI_AUD_CFG_SPDIF_DIV_2 BIT(1) | |
134 | #define HDMI_AUD_CFG_SPDIF_DIV_3 BIT(2) | |
135 | #define HDMI_AUD_CFG_SPDIF_CLK_DIV_4 (BIT(1) | BIT(2)) | |
136 | #define HDMI_AUD_CFG_CTS_CLK_256FS BIT(12) | |
137 | #define HDMI_AUD_CFG_DTS_INVALID BIT(16) | |
138 | #define HDMI_AUD_CFG_ONE_BIT_INVALID (BIT(18) | BIT(19) | BIT(20) | BIT(21)) | |
139 | #define HDMI_AUD_CFG_CH12_VALID BIT(28) | |
140 | #define HDMI_AUD_CFG_CH34_VALID BIT(29) | |
141 | #define HDMI_AUD_CFG_CH56_VALID BIT(30) | |
142 | #define HDMI_AUD_CFG_CH78_VALID BIT(31) | |
143 | ||
144 | /* sample flat mask */ | |
145 | #define HDMI_SAMPLE_FLAT_NO 0 | |
146 | #define HDMI_SAMPLE_FLAT_SP0 BIT(0) | |
147 | #define HDMI_SAMPLE_FLAT_SP1 BIT(1) | |
148 | #define HDMI_SAMPLE_FLAT_SP2 BIT(2) | |
149 | #define HDMI_SAMPLE_FLAT_SP3 BIT(3) | |
150 | #define HDMI_SAMPLE_FLAT_ALL (HDMI_SAMPLE_FLAT_SP0 | HDMI_SAMPLE_FLAT_SP1 |\ | |
151 | HDMI_SAMPLE_FLAT_SP2 | HDMI_SAMPLE_FLAT_SP3) | |
152 | ||
cffe1e89 AP |
153 | #define HDMI_INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0) |
154 | #define HDMI_INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8) | |
155 | #define HDMI_INFOFRAME_HEADER_LEN(x) (((x) & 0x0f) << 16) | |
156 | ||
5402626c BG |
157 | struct sti_hdmi_connector { |
158 | struct drm_connector drm_connector; | |
159 | struct drm_encoder *encoder; | |
160 | struct sti_hdmi *hdmi; | |
5671cefb | 161 | struct drm_property *colorspace_property; |
ffc4a6a1 | 162 | struct drm_property *hdmi_mode_property; |
5402626c BG |
163 | }; |
164 | ||
165 | #define to_sti_hdmi_connector(x) \ | |
166 | container_of(x, struct sti_hdmi_connector, drm_connector) | |
167 | ||
168 | u32 hdmi_read(struct sti_hdmi *hdmi, int offset) | |
169 | { | |
170 | return readl(hdmi->regs + offset); | |
171 | } | |
172 | ||
173 | void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset) | |
174 | { | |
175 | writel(val, hdmi->regs + offset); | |
176 | } | |
177 | ||
178 | /** | |
179 | * HDMI interrupt handler threaded | |
180 | * | |
181 | * @irq: irq number | |
182 | * @arg: connector structure | |
183 | */ | |
184 | static irqreturn_t hdmi_irq_thread(int irq, void *arg) | |
185 | { | |
186 | struct sti_hdmi *hdmi = arg; | |
187 | ||
188 | /* Hot plug/unplug IRQ */ | |
189 | if (hdmi->irq_status & HDMI_INT_HOT_PLUG) { | |
76569207 | 190 | hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG; |
5402626c BG |
191 | if (hdmi->drm_dev) |
192 | drm_helper_hpd_irq_event(hdmi->drm_dev); | |
193 | } | |
194 | ||
195 | /* Sw reset and PLL lock are exclusive so we can use the same | |
196 | * event to signal them | |
197 | */ | |
198 | if (hdmi->irq_status & (HDMI_INT_SW_RST | HDMI_INT_DLL_LCK)) { | |
199 | hdmi->event_received = true; | |
200 | wake_up_interruptible(&hdmi->wait_event); | |
201 | } | |
202 | ||
2c348e50 AP |
203 | /* Audio FIFO underrun IRQ */ |
204 | if (hdmi->irq_status & HDMI_INT_AUDIO_FIFO_XRUN) | |
29ffa776 | 205 | DRM_INFO("Warning: audio FIFO underrun occurs!\n"); |
2c348e50 | 206 | |
5402626c BG |
207 | return IRQ_HANDLED; |
208 | } | |
209 | ||
210 | /** | |
211 | * HDMI interrupt handler | |
212 | * | |
213 | * @irq: irq number | |
214 | * @arg: connector structure | |
215 | */ | |
216 | static irqreturn_t hdmi_irq(int irq, void *arg) | |
217 | { | |
218 | struct sti_hdmi *hdmi = arg; | |
219 | ||
220 | /* read interrupt status */ | |
221 | hdmi->irq_status = hdmi_read(hdmi, HDMI_INT_STA); | |
222 | ||
223 | /* clear interrupt status */ | |
224 | hdmi_write(hdmi, hdmi->irq_status, HDMI_INT_CLR); | |
225 | ||
226 | /* force sync bus write */ | |
227 | hdmi_read(hdmi, HDMI_INT_STA); | |
228 | ||
229 | return IRQ_WAKE_THREAD; | |
230 | } | |
231 | ||
232 | /** | |
233 | * Set hdmi active area depending on the drm display mode selected | |
234 | * | |
235 | * @hdmi: pointer on the hdmi internal structure | |
236 | */ | |
237 | static void hdmi_active_area(struct sti_hdmi *hdmi) | |
238 | { | |
239 | u32 xmin, xmax; | |
240 | u32 ymin, ymax; | |
241 | ||
8661532a VA |
242 | xmin = sti_vtg_get_pixel_number(hdmi->mode, 1); |
243 | xmax = sti_vtg_get_pixel_number(hdmi->mode, hdmi->mode.hdisplay); | |
5402626c BG |
244 | ymin = sti_vtg_get_line_number(hdmi->mode, 0); |
245 | ymax = sti_vtg_get_line_number(hdmi->mode, hdmi->mode.vdisplay - 1); | |
246 | ||
247 | hdmi_write(hdmi, xmin, HDMI_ACTIVE_VID_XMIN); | |
248 | hdmi_write(hdmi, xmax, HDMI_ACTIVE_VID_XMAX); | |
249 | hdmi_write(hdmi, ymin, HDMI_ACTIVE_VID_YMIN); | |
250 | hdmi_write(hdmi, ymax, HDMI_ACTIVE_VID_YMAX); | |
251 | } | |
252 | ||
253 | /** | |
254 | * Overall hdmi configuration | |
255 | * | |
256 | * @hdmi: pointer on the hdmi internal structure | |
257 | */ | |
258 | static void hdmi_config(struct sti_hdmi *hdmi) | |
259 | { | |
260 | u32 conf; | |
261 | ||
262 | DRM_DEBUG_DRIVER("\n"); | |
263 | ||
264 | /* Clear overrun and underrun fifo */ | |
265 | conf = HDMI_CFG_FIFO_OVERRUN_CLR | HDMI_CFG_FIFO_UNDERRUN_CLR; | |
266 | ||
ffc4a6a1 VA |
267 | /* Select encryption type and the framing mode */ |
268 | conf |= HDMI_CFG_ESS_NOT_OESS; | |
269 | if (hdmi->hdmi_mode == HDMI_MODE_HDMI) | |
270 | conf |= HDMI_CFG_HDMI_NOT_DVI; | |
5402626c BG |
271 | |
272 | /* Enable sink term detection */ | |
273 | conf |= HDMI_CFG_SINK_TERM_DET_EN; | |
274 | ||
275 | /* Set Hsync polarity */ | |
276 | if (hdmi->mode.flags & DRM_MODE_FLAG_NHSYNC) { | |
277 | DRM_DEBUG_DRIVER("H Sync Negative\n"); | |
278 | conf |= HDMI_CFG_H_SYNC_POL_NEG; | |
279 | } | |
280 | ||
281 | /* Set Vsync polarity */ | |
282 | if (hdmi->mode.flags & DRM_MODE_FLAG_NVSYNC) { | |
283 | DRM_DEBUG_DRIVER("V Sync Negative\n"); | |
284 | conf |= HDMI_CFG_V_SYNC_POL_NEG; | |
285 | } | |
286 | ||
287 | /* Enable HDMI */ | |
288 | conf |= HDMI_CFG_DEVICE_EN; | |
289 | ||
290 | hdmi_write(hdmi, conf, HDMI_CFG); | |
291 | } | |
292 | ||
181975a2 VA |
293 | /* |
294 | * Helper to reset info frame | |
295 | * | |
296 | * @hdmi: pointer on the hdmi internal structure | |
297 | * @slot: infoframe to reset | |
298 | */ | |
299 | static void hdmi_infoframe_reset(struct sti_hdmi *hdmi, | |
300 | u32 slot) | |
301 | { | |
302 | u32 val, i; | |
303 | u32 head_offset, pack_offset; | |
304 | ||
305 | switch (slot) { | |
306 | case HDMI_IFRAME_SLOT_AVI: | |
307 | head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI); | |
308 | pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI); | |
309 | break; | |
310 | case HDMI_IFRAME_SLOT_AUDIO: | |
311 | head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AUDIO); | |
312 | pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AUDIO); | |
313 | break; | |
e42e7bd7 VA |
314 | case HDMI_IFRAME_SLOT_VENDOR: |
315 | head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_VENDOR); | |
316 | pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_VENDOR); | |
317 | break; | |
181975a2 VA |
318 | default: |
319 | DRM_ERROR("unsupported infoframe slot: %#x\n", slot); | |
320 | return; | |
321 | } | |
322 | ||
323 | /* Disable transmission for the selected slot */ | |
324 | val = hdmi_read(hdmi, HDMI_SW_DI_CFG); | |
325 | val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, slot); | |
326 | hdmi_write(hdmi, val, HDMI_SW_DI_CFG); | |
327 | ||
328 | /* Reset info frame registers */ | |
329 | hdmi_write(hdmi, 0x0, head_offset); | |
330 | for (i = 0; i < HDMI_SW_DI_MAX_WORD; i += sizeof(u32)) | |
331 | hdmi_write(hdmi, 0x0, pack_offset + i); | |
332 | } | |
333 | ||
cffe1e89 AP |
334 | /** |
335 | * Helper to concatenate infoframe in 32 bits word | |
336 | * | |
337 | * @ptr: pointer on the hdmi internal structure | |
338 | * @data: infoframe to write | |
339 | * @size: size to write | |
340 | */ | |
341 | static inline unsigned int hdmi_infoframe_subpack(const u8 *ptr, size_t size) | |
342 | { | |
343 | unsigned long value = 0; | |
344 | size_t i; | |
345 | ||
346 | for (i = size; i > 0; i--) | |
347 | value = (value << 8) | ptr[i - 1]; | |
348 | ||
349 | return value; | |
350 | } | |
351 | ||
352 | /** | |
353 | * Helper to write info frame | |
354 | * | |
355 | * @hdmi: pointer on the hdmi internal structure | |
356 | * @data: infoframe to write | |
357 | * @size: size to write | |
358 | */ | |
e42e7bd7 VA |
359 | static void hdmi_infoframe_write_infopack(struct sti_hdmi *hdmi, |
360 | const u8 *data, | |
361 | size_t size) | |
cffe1e89 AP |
362 | { |
363 | const u8 *ptr = data; | |
364 | u32 val, slot, mode, i; | |
365 | u32 head_offset, pack_offset; | |
cffe1e89 AP |
366 | |
367 | switch (*ptr) { | |
368 | case HDMI_INFOFRAME_TYPE_AVI: | |
369 | slot = HDMI_IFRAME_SLOT_AVI; | |
370 | mode = HDMI_IFRAME_FIELD; | |
371 | head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI); | |
372 | pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI); | |
cffe1e89 | 373 | break; |
cffe1e89 AP |
374 | case HDMI_INFOFRAME_TYPE_AUDIO: |
375 | slot = HDMI_IFRAME_SLOT_AUDIO; | |
376 | mode = HDMI_IFRAME_FRAME; | |
377 | head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AUDIO); | |
378 | pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AUDIO); | |
cffe1e89 | 379 | break; |
e42e7bd7 VA |
380 | case HDMI_INFOFRAME_TYPE_VENDOR: |
381 | slot = HDMI_IFRAME_SLOT_VENDOR; | |
382 | mode = HDMI_IFRAME_FRAME; | |
383 | head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_VENDOR); | |
384 | pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_VENDOR); | |
385 | break; | |
cffe1e89 AP |
386 | default: |
387 | DRM_ERROR("unsupported infoframe type: %#x\n", *ptr); | |
388 | return; | |
389 | } | |
390 | ||
391 | /* Disable transmission slot for updated infoframe */ | |
392 | val = hdmi_read(hdmi, HDMI_SW_DI_CFG); | |
393 | val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, slot); | |
394 | hdmi_write(hdmi, val, HDMI_SW_DI_CFG); | |
395 | ||
396 | val = HDMI_INFOFRAME_HEADER_TYPE(*ptr++); | |
397 | val |= HDMI_INFOFRAME_HEADER_VERSION(*ptr++); | |
398 | val |= HDMI_INFOFRAME_HEADER_LEN(*ptr++); | |
399 | writel(val, hdmi->regs + head_offset); | |
400 | ||
401 | /* | |
402 | * Each subpack contains 4 bytes | |
403 | * The First Bytes of the first subpacket must contain the checksum | |
e42e7bd7 | 404 | * Packet size is increase by one. |
cffe1e89 | 405 | */ |
e42e7bd7 | 406 | size = size - HDMI_INFOFRAME_HEADER_SIZE + 1; |
cffe1e89 AP |
407 | for (i = 0; i < size; i += sizeof(u32)) { |
408 | size_t num; | |
409 | ||
410 | num = min_t(size_t, size - i, sizeof(u32)); | |
411 | val = hdmi_infoframe_subpack(ptr, num); | |
412 | ptr += sizeof(u32); | |
413 | writel(val, hdmi->regs + pack_offset + i); | |
414 | } | |
415 | ||
416 | /* Enable transmission slot for updated infoframe */ | |
417 | val = hdmi_read(hdmi, HDMI_SW_DI_CFG); | |
50f2138a | 418 | val |= HDMI_IFRAME_CFG_DI_N(mode, slot); |
cffe1e89 AP |
419 | hdmi_write(hdmi, val, HDMI_SW_DI_CFG); |
420 | } | |
421 | ||
5402626c BG |
422 | /** |
423 | * Prepare and configure the AVI infoframe | |
424 | * | |
425 | * AVI infoframe are transmitted at least once per two video field and | |
426 | * contains information about HDMI transmission mode such as color space, | |
427 | * colorimetry, ... | |
428 | * | |
429 | * @hdmi: pointer on the hdmi internal structure | |
430 | * | |
431 | * Return negative value if error occurs | |
432 | */ | |
433 | static int hdmi_avi_infoframe_config(struct sti_hdmi *hdmi) | |
434 | { | |
435 | struct drm_display_mode *mode = &hdmi->mode; | |
436 | struct hdmi_avi_infoframe infoframe; | |
437 | u8 buffer[HDMI_INFOFRAME_SIZE(AVI)]; | |
5402626c BG |
438 | int ret; |
439 | ||
440 | DRM_DEBUG_DRIVER("\n"); | |
441 | ||
442 | ret = drm_hdmi_avi_infoframe_from_display_mode(&infoframe, mode); | |
443 | if (ret < 0) { | |
444 | DRM_ERROR("failed to setup AVI infoframe: %d\n", ret); | |
445 | return ret; | |
446 | } | |
447 | ||
448 | /* fixed infoframe configuration not linked to the mode */ | |
5671cefb | 449 | infoframe.colorspace = hdmi->colorspace; |
5402626c BG |
450 | infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; |
451 | infoframe.colorimetry = HDMI_COLORIMETRY_NONE; | |
452 | ||
453 | ret = hdmi_avi_infoframe_pack(&infoframe, buffer, sizeof(buffer)); | |
454 | if (ret < 0) { | |
455 | DRM_ERROR("failed to pack AVI infoframe: %d\n", ret); | |
456 | return ret; | |
457 | } | |
458 | ||
e42e7bd7 | 459 | hdmi_infoframe_write_infopack(hdmi, buffer, ret); |
5402626c | 460 | |
cffe1e89 AP |
461 | return 0; |
462 | } | |
463 | ||
464 | /** | |
465 | * Prepare and configure the AUDIO infoframe | |
466 | * | |
467 | * AUDIO infoframe are transmitted once per frame and | |
468 | * contains information about HDMI transmission mode such as audio codec, | |
469 | * sample size, ... | |
470 | * | |
471 | * @hdmi: pointer on the hdmi internal structure | |
472 | * | |
473 | * Return negative value if error occurs | |
474 | */ | |
475 | static int hdmi_audio_infoframe_config(struct sti_hdmi *hdmi) | |
476 | { | |
2c348e50 | 477 | struct hdmi_audio_params *audio = &hdmi->audio; |
cffe1e89 | 478 | u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)]; |
2c348e50 AP |
479 | int ret, val; |
480 | ||
481 | DRM_DEBUG_DRIVER("enter %s, AIF %s\n", __func__, | |
482 | audio->enabled ? "enable" : "disable"); | |
483 | if (audio->enabled) { | |
484 | /* set audio parameters stored*/ | |
485 | ret = hdmi_audio_infoframe_pack(&audio->cea, buffer, | |
486 | sizeof(buffer)); | |
487 | if (ret < 0) { | |
488 | DRM_ERROR("failed to pack audio infoframe: %d\n", ret); | |
489 | return ret; | |
490 | } | |
491 | hdmi_infoframe_write_infopack(hdmi, buffer, ret); | |
492 | } else { | |
493 | /*disable audio info frame transmission */ | |
494 | val = hdmi_read(hdmi, HDMI_SW_DI_CFG); | |
495 | val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, | |
496 | HDMI_IFRAME_SLOT_AUDIO); | |
497 | hdmi_write(hdmi, val, HDMI_SW_DI_CFG); | |
cffe1e89 AP |
498 | } |
499 | ||
e42e7bd7 VA |
500 | return 0; |
501 | } | |
502 | ||
503 | /* | |
504 | * Prepare and configure the VS infoframe | |
505 | * | |
506 | * Vendor Specific infoframe are transmitted once per frame and | |
507 | * contains vendor specific information. | |
508 | * | |
509 | * @hdmi: pointer on the hdmi internal structure | |
510 | * | |
511 | * Return negative value if error occurs | |
512 | */ | |
513 | #define HDMI_VENDOR_INFOFRAME_MAX_SIZE 6 | |
514 | static int hdmi_vendor_infoframe_config(struct sti_hdmi *hdmi) | |
515 | { | |
516 | struct drm_display_mode *mode = &hdmi->mode; | |
517 | struct hdmi_vendor_infoframe infoframe; | |
518 | u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_VENDOR_INFOFRAME_MAX_SIZE]; | |
519 | int ret; | |
520 | ||
521 | DRM_DEBUG_DRIVER("\n"); | |
522 | ||
523 | ret = drm_hdmi_vendor_infoframe_from_display_mode(&infoframe, mode); | |
524 | if (ret < 0) { | |
525 | /* | |
526 | * Going into that statement does not means vendor infoframe | |
527 | * fails. It just informed us that vendor infoframe is not | |
528 | * needed for the selected mode. Only 4k or stereoscopic 3D | |
529 | * mode requires vendor infoframe. So just simply return 0. | |
530 | */ | |
531 | return 0; | |
532 | } | |
533 | ||
534 | ret = hdmi_vendor_infoframe_pack(&infoframe, buffer, sizeof(buffer)); | |
535 | if (ret < 0) { | |
536 | DRM_ERROR("failed to pack VS infoframe: %d\n", ret); | |
537 | return ret; | |
538 | } | |
539 | ||
540 | hdmi_infoframe_write_infopack(hdmi, buffer, ret); | |
5402626c BG |
541 | |
542 | return 0; | |
543 | } | |
544 | ||
545 | /** | |
546 | * Software reset of the hdmi subsystem | |
547 | * | |
548 | * @hdmi: pointer on the hdmi internal structure | |
549 | * | |
550 | */ | |
551 | #define HDMI_TIMEOUT_SWRESET 100 /*milliseconds */ | |
552 | static void hdmi_swreset(struct sti_hdmi *hdmi) | |
553 | { | |
554 | u32 val; | |
555 | ||
556 | DRM_DEBUG_DRIVER("\n"); | |
557 | ||
558 | /* Enable hdmi_audio clock only during hdmi reset */ | |
559 | if (clk_prepare_enable(hdmi->clk_audio)) | |
560 | DRM_INFO("Failed to prepare/enable hdmi_audio clk\n"); | |
561 | ||
562 | /* Sw reset */ | |
563 | hdmi->event_received = false; | |
564 | ||
565 | val = hdmi_read(hdmi, HDMI_CFG); | |
566 | val |= HDMI_CFG_SW_RST_EN; | |
567 | hdmi_write(hdmi, val, HDMI_CFG); | |
568 | ||
569 | /* Wait reset completed */ | |
570 | wait_event_interruptible_timeout(hdmi->wait_event, | |
7c0ca70b | 571 | hdmi->event_received, |
5402626c BG |
572 | msecs_to_jiffies |
573 | (HDMI_TIMEOUT_SWRESET)); | |
574 | ||
575 | /* | |
576 | * HDMI_STA_SW_RST bit is set to '1' when SW_RST bit in HDMI_CFG is | |
577 | * set to '1' and clk_audio is running. | |
578 | */ | |
579 | if ((hdmi_read(hdmi, HDMI_STA) & HDMI_STA_SW_RST) == 0) | |
580 | DRM_DEBUG_DRIVER("Warning: HDMI sw reset timeout occurs\n"); | |
581 | ||
582 | val = hdmi_read(hdmi, HDMI_CFG); | |
583 | val &= ~HDMI_CFG_SW_RST_EN; | |
584 | hdmi_write(hdmi, val, HDMI_CFG); | |
585 | ||
586 | /* Disable hdmi_audio clock. Not used anymore for drm purpose */ | |
587 | clk_disable_unprepare(hdmi->clk_audio); | |
588 | } | |
589 | ||
7ea6e6e4 VA |
590 | #define DBGFS_PRINT_STR(str1, str2) seq_printf(s, "%-24s %s\n", str1, str2) |
591 | #define DBGFS_PRINT_INT(str1, int2) seq_printf(s, "%-24s %d\n", str1, int2) | |
592 | #define DBGFS_DUMP(str, reg) seq_printf(s, "%s %-25s 0x%08X", str, #reg, \ | |
593 | hdmi_read(hdmi, reg)) | |
594 | #define DBGFS_DUMP_DI(reg, slot) DBGFS_DUMP("\n", reg(slot)) | |
595 | ||
596 | static void hdmi_dbg_cfg(struct seq_file *s, int val) | |
597 | { | |
598 | int tmp; | |
599 | ||
600 | seq_puts(s, "\t"); | |
601 | tmp = val & HDMI_CFG_HDMI_NOT_DVI; | |
602 | DBGFS_PRINT_STR("mode:", tmp ? "HDMI" : "DVI"); | |
603 | seq_puts(s, "\t\t\t\t\t"); | |
604 | tmp = val & HDMI_CFG_HDCP_EN; | |
605 | DBGFS_PRINT_STR("HDCP:", tmp ? "enable" : "disable"); | |
606 | seq_puts(s, "\t\t\t\t\t"); | |
607 | tmp = val & HDMI_CFG_ESS_NOT_OESS; | |
608 | DBGFS_PRINT_STR("HDCP mode:", tmp ? "ESS enable" : "OESS enable"); | |
609 | seq_puts(s, "\t\t\t\t\t"); | |
610 | tmp = val & HDMI_CFG_SINK_TERM_DET_EN; | |
611 | DBGFS_PRINT_STR("Sink term detection:", tmp ? "enable" : "disable"); | |
612 | seq_puts(s, "\t\t\t\t\t"); | |
613 | tmp = val & HDMI_CFG_H_SYNC_POL_NEG; | |
614 | DBGFS_PRINT_STR("Hsync polarity:", tmp ? "inverted" : "normal"); | |
615 | seq_puts(s, "\t\t\t\t\t"); | |
616 | tmp = val & HDMI_CFG_V_SYNC_POL_NEG; | |
617 | DBGFS_PRINT_STR("Vsync polarity:", tmp ? "inverted" : "normal"); | |
618 | seq_puts(s, "\t\t\t\t\t"); | |
619 | tmp = val & HDMI_CFG_422_EN; | |
620 | DBGFS_PRINT_STR("YUV422 format:", tmp ? "enable" : "disable"); | |
621 | } | |
622 | ||
623 | static void hdmi_dbg_sta(struct seq_file *s, int val) | |
624 | { | |
625 | int tmp; | |
626 | ||
627 | seq_puts(s, "\t"); | |
628 | tmp = (val & HDMI_STA_DLL_LCK); | |
629 | DBGFS_PRINT_STR("pll:", tmp ? "locked" : "not locked"); | |
630 | seq_puts(s, "\t\t\t\t\t"); | |
631 | tmp = (val & HDMI_STA_HOT_PLUG); | |
632 | DBGFS_PRINT_STR("hdmi cable:", tmp ? "connected" : "not connected"); | |
633 | } | |
634 | ||
635 | static void hdmi_dbg_sw_di_cfg(struct seq_file *s, int val) | |
636 | { | |
637 | int tmp; | |
638 | char *const en_di[] = {"no transmission", | |
639 | "single transmission", | |
640 | "once every field", | |
641 | "once every frame"}; | |
642 | ||
643 | seq_puts(s, "\t"); | |
644 | tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 1)); | |
645 | DBGFS_PRINT_STR("Data island 1:", en_di[tmp]); | |
646 | seq_puts(s, "\t\t\t\t\t"); | |
647 | tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 2)) >> 4; | |
648 | DBGFS_PRINT_STR("Data island 2:", en_di[tmp]); | |
649 | seq_puts(s, "\t\t\t\t\t"); | |
650 | tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 3)) >> 8; | |
651 | DBGFS_PRINT_STR("Data island 3:", en_di[tmp]); | |
652 | seq_puts(s, "\t\t\t\t\t"); | |
653 | tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 4)) >> 12; | |
654 | DBGFS_PRINT_STR("Data island 4:", en_di[tmp]); | |
655 | seq_puts(s, "\t\t\t\t\t"); | |
656 | tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 5)) >> 16; | |
657 | DBGFS_PRINT_STR("Data island 5:", en_di[tmp]); | |
658 | seq_puts(s, "\t\t\t\t\t"); | |
659 | tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 6)) >> 20; | |
660 | DBGFS_PRINT_STR("Data island 6:", en_di[tmp]); | |
661 | } | |
662 | ||
663 | static int hdmi_dbg_show(struct seq_file *s, void *data) | |
664 | { | |
665 | struct drm_info_node *node = s->private; | |
666 | struct sti_hdmi *hdmi = (struct sti_hdmi *)node->info_ent->data; | |
7ea6e6e4 VA |
667 | |
668 | seq_printf(s, "HDMI: (vaddr = 0x%p)", hdmi->regs); | |
669 | DBGFS_DUMP("\n", HDMI_CFG); | |
670 | hdmi_dbg_cfg(s, hdmi_read(hdmi, HDMI_CFG)); | |
671 | DBGFS_DUMP("", HDMI_INT_EN); | |
672 | DBGFS_DUMP("\n", HDMI_STA); | |
673 | hdmi_dbg_sta(s, hdmi_read(hdmi, HDMI_STA)); | |
674 | DBGFS_DUMP("", HDMI_ACTIVE_VID_XMIN); | |
675 | seq_puts(s, "\t"); | |
676 | DBGFS_PRINT_INT("Xmin:", hdmi_read(hdmi, HDMI_ACTIVE_VID_XMIN)); | |
677 | DBGFS_DUMP("", HDMI_ACTIVE_VID_XMAX); | |
678 | seq_puts(s, "\t"); | |
679 | DBGFS_PRINT_INT("Xmax:", hdmi_read(hdmi, HDMI_ACTIVE_VID_XMAX)); | |
680 | DBGFS_DUMP("", HDMI_ACTIVE_VID_YMIN); | |
681 | seq_puts(s, "\t"); | |
682 | DBGFS_PRINT_INT("Ymin:", hdmi_read(hdmi, HDMI_ACTIVE_VID_YMIN)); | |
683 | DBGFS_DUMP("", HDMI_ACTIVE_VID_YMAX); | |
684 | seq_puts(s, "\t"); | |
685 | DBGFS_PRINT_INT("Ymax:", hdmi_read(hdmi, HDMI_ACTIVE_VID_YMAX)); | |
686 | DBGFS_DUMP("", HDMI_SW_DI_CFG); | |
687 | hdmi_dbg_sw_di_cfg(s, hdmi_read(hdmi, HDMI_SW_DI_CFG)); | |
688 | ||
2c348e50 AP |
689 | DBGFS_DUMP("\n", HDMI_AUDIO_CFG); |
690 | DBGFS_DUMP("\n", HDMI_SPDIF_FIFO_STATUS); | |
691 | DBGFS_DUMP("\n", HDMI_AUDN); | |
692 | ||
7ea6e6e4 VA |
693 | seq_printf(s, "\n AVI Infoframe (Data Island slot N=%d):", |
694 | HDMI_IFRAME_SLOT_AVI); | |
695 | DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_AVI); | |
696 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_AVI); | |
697 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_AVI); | |
698 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_AVI); | |
699 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_AVI); | |
700 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_AVI); | |
701 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_AVI); | |
702 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_AVI); | |
703 | seq_puts(s, "\n"); | |
704 | seq_printf(s, "\n AUDIO Infoframe (Data Island slot N=%d):", | |
705 | HDMI_IFRAME_SLOT_AUDIO); | |
706 | DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_AUDIO); | |
707 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_AUDIO); | |
708 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_AUDIO); | |
709 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_AUDIO); | |
710 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_AUDIO); | |
711 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_AUDIO); | |
712 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_AUDIO); | |
713 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_AUDIO); | |
714 | seq_puts(s, "\n"); | |
715 | seq_printf(s, "\n VENDOR SPECIFIC Infoframe (Data Island slot N=%d):", | |
716 | HDMI_IFRAME_SLOT_VENDOR); | |
717 | DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_VENDOR); | |
718 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_VENDOR); | |
719 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_VENDOR); | |
720 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_VENDOR); | |
721 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_VENDOR); | |
722 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_VENDOR); | |
723 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_VENDOR); | |
724 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_VENDOR); | |
725 | seq_puts(s, "\n"); | |
726 | ||
7ea6e6e4 VA |
727 | return 0; |
728 | } | |
729 | ||
730 | static struct drm_info_list hdmi_debugfs_files[] = { | |
731 | { "hdmi", hdmi_dbg_show, 0, NULL }, | |
732 | }; | |
733 | ||
734 | static void hdmi_debugfs_exit(struct sti_hdmi *hdmi, struct drm_minor *minor) | |
735 | { | |
736 | drm_debugfs_remove_files(hdmi_debugfs_files, | |
737 | ARRAY_SIZE(hdmi_debugfs_files), | |
738 | minor); | |
739 | } | |
740 | ||
741 | static int hdmi_debugfs_init(struct sti_hdmi *hdmi, struct drm_minor *minor) | |
742 | { | |
743 | unsigned int i; | |
744 | ||
745 | for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_files); i++) | |
746 | hdmi_debugfs_files[i].data = hdmi; | |
747 | ||
748 | return drm_debugfs_create_files(hdmi_debugfs_files, | |
749 | ARRAY_SIZE(hdmi_debugfs_files), | |
750 | minor->debugfs_root, minor); | |
751 | } | |
752 | ||
5402626c BG |
753 | static void sti_hdmi_disable(struct drm_bridge *bridge) |
754 | { | |
755 | struct sti_hdmi *hdmi = bridge->driver_private; | |
756 | ||
757 | u32 val = hdmi_read(hdmi, HDMI_CFG); | |
758 | ||
759 | if (!hdmi->enabled) | |
760 | return; | |
761 | ||
762 | DRM_DEBUG_DRIVER("\n"); | |
763 | ||
764 | /* Disable HDMI */ | |
765 | val &= ~HDMI_CFG_DEVICE_EN; | |
766 | hdmi_write(hdmi, val, HDMI_CFG); | |
767 | ||
768 | hdmi_write(hdmi, 0xffffffff, HDMI_INT_CLR); | |
769 | ||
770 | /* Stop the phy */ | |
771 | hdmi->phy_ops->stop(hdmi); | |
772 | ||
181975a2 VA |
773 | /* Reset info frame transmission */ |
774 | hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_AVI); | |
775 | hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_AUDIO); | |
e42e7bd7 | 776 | hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_VENDOR); |
181975a2 | 777 | |
5402626c BG |
778 | /* Set the default channel data to be a dark red */ |
779 | hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL0_DAT); | |
780 | hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL1_DAT); | |
781 | hdmi_write(hdmi, 0x0060, HDMI_DFLT_CHL2_DAT); | |
782 | ||
783 | /* Disable/unprepare hdmi clock */ | |
784 | clk_disable_unprepare(hdmi->clk_phy); | |
785 | clk_disable_unprepare(hdmi->clk_tmds); | |
786 | clk_disable_unprepare(hdmi->clk_pix); | |
787 | ||
788 | hdmi->enabled = false; | |
789 | } | |
790 | ||
791 | static void sti_hdmi_pre_enable(struct drm_bridge *bridge) | |
792 | { | |
793 | struct sti_hdmi *hdmi = bridge->driver_private; | |
794 | ||
795 | DRM_DEBUG_DRIVER("\n"); | |
796 | ||
797 | if (hdmi->enabled) | |
798 | return; | |
799 | ||
800 | /* Prepare/enable clocks */ | |
801 | if (clk_prepare_enable(hdmi->clk_pix)) | |
802 | DRM_ERROR("Failed to prepare/enable hdmi_pix clk\n"); | |
803 | if (clk_prepare_enable(hdmi->clk_tmds)) | |
804 | DRM_ERROR("Failed to prepare/enable hdmi_tmds clk\n"); | |
805 | if (clk_prepare_enable(hdmi->clk_phy)) | |
806 | DRM_ERROR("Failed to prepare/enable hdmi_rejec_pll clk\n"); | |
807 | ||
808 | hdmi->enabled = true; | |
809 | ||
810 | /* Program hdmi serializer and start phy */ | |
811 | if (!hdmi->phy_ops->start(hdmi)) { | |
812 | DRM_ERROR("Unable to start hdmi phy\n"); | |
813 | return; | |
814 | } | |
815 | ||
816 | /* Program hdmi active area */ | |
817 | hdmi_active_area(hdmi); | |
818 | ||
819 | /* Enable working interrupts */ | |
820 | hdmi_write(hdmi, HDMI_WORKING_INT, HDMI_INT_EN); | |
821 | ||
822 | /* Program hdmi config */ | |
823 | hdmi_config(hdmi); | |
824 | ||
825 | /* Program AVI infoframe */ | |
826 | if (hdmi_avi_infoframe_config(hdmi)) | |
827 | DRM_ERROR("Unable to configure AVI infoframe\n"); | |
828 | ||
cffe1e89 AP |
829 | /* Program AUDIO infoframe */ |
830 | if (hdmi_audio_infoframe_config(hdmi)) | |
831 | DRM_ERROR("Unable to configure AUDIO infoframe\n"); | |
832 | ||
e42e7bd7 VA |
833 | /* Program VS infoframe */ |
834 | if (hdmi_vendor_infoframe_config(hdmi)) | |
835 | DRM_ERROR("Unable to configure VS infoframe\n"); | |
836 | ||
5402626c BG |
837 | /* Sw reset */ |
838 | hdmi_swreset(hdmi); | |
839 | } | |
840 | ||
841 | static void sti_hdmi_set_mode(struct drm_bridge *bridge, | |
842 | struct drm_display_mode *mode, | |
843 | struct drm_display_mode *adjusted_mode) | |
844 | { | |
845 | struct sti_hdmi *hdmi = bridge->driver_private; | |
846 | int ret; | |
847 | ||
848 | DRM_DEBUG_DRIVER("\n"); | |
849 | ||
850 | /* Copy the drm display mode in the connector local structure */ | |
851 | memcpy(&hdmi->mode, mode, sizeof(struct drm_display_mode)); | |
852 | ||
853 | /* Update clock framerate according to the selected mode */ | |
854 | ret = clk_set_rate(hdmi->clk_pix, mode->clock * 1000); | |
855 | if (ret < 0) { | |
856 | DRM_ERROR("Cannot set rate (%dHz) for hdmi_pix clk\n", | |
857 | mode->clock * 1000); | |
858 | return; | |
859 | } | |
860 | ret = clk_set_rate(hdmi->clk_phy, mode->clock * 1000); | |
861 | if (ret < 0) { | |
862 | DRM_ERROR("Cannot set rate (%dHz) for hdmi_rejection_pll clk\n", | |
863 | mode->clock * 1000); | |
864 | return; | |
865 | } | |
866 | } | |
867 | ||
868 | static void sti_hdmi_bridge_nope(struct drm_bridge *bridge) | |
869 | { | |
870 | /* do nothing */ | |
871 | } | |
872 | ||
5402626c BG |
873 | static const struct drm_bridge_funcs sti_hdmi_bridge_funcs = { |
874 | .pre_enable = sti_hdmi_pre_enable, | |
875 | .enable = sti_hdmi_bridge_nope, | |
876 | .disable = sti_hdmi_disable, | |
877 | .post_disable = sti_hdmi_bridge_nope, | |
878 | .mode_set = sti_hdmi_set_mode, | |
5402626c BG |
879 | }; |
880 | ||
881 | static int sti_hdmi_connector_get_modes(struct drm_connector *connector) | |
882 | { | |
41a14623 BG |
883 | struct sti_hdmi_connector *hdmi_connector |
884 | = to_sti_hdmi_connector(connector); | |
885 | struct sti_hdmi *hdmi = hdmi_connector->hdmi; | |
5402626c BG |
886 | struct edid *edid; |
887 | int count; | |
888 | ||
889 | DRM_DEBUG_DRIVER("\n"); | |
890 | ||
41a14623 | 891 | edid = drm_get_edid(connector, hdmi->ddc_adapt); |
5402626c BG |
892 | if (!edid) |
893 | goto fail; | |
894 | ||
895 | count = drm_add_edid_modes(connector, edid); | |
896 | drm_mode_connector_update_edid_property(connector, edid); | |
2c348e50 | 897 | drm_edid_to_eld(connector, edid); |
5402626c BG |
898 | |
899 | kfree(edid); | |
900 | return count; | |
901 | ||
902 | fail: | |
871bcdfe | 903 | DRM_ERROR("Can't read HDMI EDID\n"); |
5402626c BG |
904 | return 0; |
905 | } | |
906 | ||
907 | #define CLK_TOLERANCE_HZ 50 | |
908 | ||
909 | static int sti_hdmi_connector_mode_valid(struct drm_connector *connector, | |
910 | struct drm_display_mode *mode) | |
911 | { | |
912 | int target = mode->clock * 1000; | |
913 | int target_min = target - CLK_TOLERANCE_HZ; | |
914 | int target_max = target + CLK_TOLERANCE_HZ; | |
915 | int result; | |
916 | struct sti_hdmi_connector *hdmi_connector | |
917 | = to_sti_hdmi_connector(connector); | |
918 | struct sti_hdmi *hdmi = hdmi_connector->hdmi; | |
919 | ||
920 | ||
921 | result = clk_round_rate(hdmi->clk_pix, target); | |
922 | ||
923 | DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n", | |
924 | target, result); | |
925 | ||
926 | if ((result < target_min) || (result > target_max)) { | |
927 | DRM_DEBUG_DRIVER("hdmi pixclk=%d not supported\n", target); | |
928 | return MODE_BAD; | |
929 | } | |
930 | ||
931 | return MODE_OK; | |
932 | } | |
933 | ||
c5de4853 VS |
934 | static const |
935 | struct drm_connector_helper_funcs sti_hdmi_connector_helper_funcs = { | |
5402626c BG |
936 | .get_modes = sti_hdmi_connector_get_modes, |
937 | .mode_valid = sti_hdmi_connector_mode_valid, | |
5402626c BG |
938 | }; |
939 | ||
940 | /* get detection status of display device */ | |
941 | static enum drm_connector_status | |
942 | sti_hdmi_connector_detect(struct drm_connector *connector, bool force) | |
943 | { | |
944 | struct sti_hdmi_connector *hdmi_connector | |
945 | = to_sti_hdmi_connector(connector); | |
946 | struct sti_hdmi *hdmi = hdmi_connector->hdmi; | |
947 | ||
948 | DRM_DEBUG_DRIVER("\n"); | |
949 | ||
950 | if (hdmi->hpd) { | |
951 | DRM_DEBUG_DRIVER("hdmi cable connected\n"); | |
952 | return connector_status_connected; | |
953 | } | |
954 | ||
955 | DRM_DEBUG_DRIVER("hdmi cable disconnected\n"); | |
956 | return connector_status_disconnected; | |
957 | } | |
958 | ||
5671cefb VA |
959 | static void sti_hdmi_connector_init_property(struct drm_device *drm_dev, |
960 | struct drm_connector *connector) | |
961 | { | |
962 | struct sti_hdmi_connector *hdmi_connector | |
963 | = to_sti_hdmi_connector(connector); | |
964 | struct sti_hdmi *hdmi = hdmi_connector->hdmi; | |
965 | struct drm_property *prop; | |
966 | ||
967 | /* colorspace property */ | |
968 | hdmi->colorspace = DEFAULT_COLORSPACE_MODE; | |
969 | prop = drm_property_create_enum(drm_dev, 0, "colorspace", | |
970 | colorspace_mode_names, | |
971 | ARRAY_SIZE(colorspace_mode_names)); | |
972 | if (!prop) { | |
973 | DRM_ERROR("fails to create colorspace property\n"); | |
974 | return; | |
975 | } | |
976 | hdmi_connector->colorspace_property = prop; | |
977 | drm_object_attach_property(&connector->base, prop, hdmi->colorspace); | |
ffc4a6a1 VA |
978 | |
979 | /* hdmi_mode property */ | |
980 | hdmi->hdmi_mode = DEFAULT_HDMI_MODE; | |
981 | prop = drm_property_create_enum(drm_dev, 0, "hdmi_mode", | |
982 | hdmi_mode_names, | |
983 | ARRAY_SIZE(hdmi_mode_names)); | |
984 | if (!prop) { | |
985 | DRM_ERROR("fails to create colorspace property\n"); | |
986 | return; | |
987 | } | |
988 | hdmi_connector->hdmi_mode_property = prop; | |
989 | drm_object_attach_property(&connector->base, prop, hdmi->hdmi_mode); | |
990 | ||
5671cefb VA |
991 | } |
992 | ||
993 | static int | |
994 | sti_hdmi_connector_set_property(struct drm_connector *connector, | |
995 | struct drm_connector_state *state, | |
996 | struct drm_property *property, | |
997 | uint64_t val) | |
998 | { | |
999 | struct sti_hdmi_connector *hdmi_connector | |
1000 | = to_sti_hdmi_connector(connector); | |
1001 | struct sti_hdmi *hdmi = hdmi_connector->hdmi; | |
1002 | ||
1003 | if (property == hdmi_connector->colorspace_property) { | |
1004 | hdmi->colorspace = val; | |
1005 | return 0; | |
1006 | } | |
1007 | ||
ffc4a6a1 VA |
1008 | if (property == hdmi_connector->hdmi_mode_property) { |
1009 | hdmi->hdmi_mode = val; | |
1010 | return 0; | |
1011 | } | |
1012 | ||
5671cefb VA |
1013 | DRM_ERROR("failed to set hdmi connector property\n"); |
1014 | return -EINVAL; | |
1015 | } | |
1016 | ||
1017 | static int | |
1018 | sti_hdmi_connector_get_property(struct drm_connector *connector, | |
1019 | const struct drm_connector_state *state, | |
1020 | struct drm_property *property, | |
1021 | uint64_t *val) | |
1022 | { | |
1023 | struct sti_hdmi_connector *hdmi_connector | |
1024 | = to_sti_hdmi_connector(connector); | |
1025 | struct sti_hdmi *hdmi = hdmi_connector->hdmi; | |
1026 | ||
1027 | if (property == hdmi_connector->colorspace_property) { | |
1028 | *val = hdmi->colorspace; | |
1029 | return 0; | |
1030 | } | |
1031 | ||
ffc4a6a1 VA |
1032 | if (property == hdmi_connector->hdmi_mode_property) { |
1033 | *val = hdmi->hdmi_mode; | |
1034 | return 0; | |
1035 | } | |
1036 | ||
5671cefb VA |
1037 | DRM_ERROR("failed to get hdmi connector property\n"); |
1038 | return -EINVAL; | |
1039 | } | |
1040 | ||
83af0a48 BG |
1041 | static int sti_hdmi_late_register(struct drm_connector *connector) |
1042 | { | |
1043 | struct sti_hdmi_connector *hdmi_connector | |
1044 | = to_sti_hdmi_connector(connector); | |
1045 | struct sti_hdmi *hdmi = hdmi_connector->hdmi; | |
1046 | ||
1047 | if (hdmi_debugfs_init(hdmi, hdmi->drm_dev->primary)) { | |
1048 | DRM_ERROR("HDMI debugfs setup failed\n"); | |
1049 | return -EINVAL; | |
1050 | } | |
1051 | ||
1052 | return 0; | |
1053 | } | |
1054 | ||
c5de4853 | 1055 | static const struct drm_connector_funcs sti_hdmi_connector_funcs = { |
33030d61 | 1056 | .dpms = drm_atomic_helper_connector_dpms, |
5402626c BG |
1057 | .fill_modes = drm_helper_probe_single_connector_modes, |
1058 | .detect = sti_hdmi_connector_detect, | |
84601dbd | 1059 | .destroy = drm_connector_cleanup, |
de4b00b0 | 1060 | .reset = drm_atomic_helper_connector_reset, |
5671cefb VA |
1061 | .set_property = drm_atomic_helper_connector_set_property, |
1062 | .atomic_set_property = sti_hdmi_connector_set_property, | |
1063 | .atomic_get_property = sti_hdmi_connector_get_property, | |
de4b00b0 BG |
1064 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
1065 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, | |
83af0a48 | 1066 | .late_register = sti_hdmi_late_register, |
5402626c BG |
1067 | }; |
1068 | ||
1069 | static struct drm_encoder *sti_hdmi_find_encoder(struct drm_device *dev) | |
1070 | { | |
1071 | struct drm_encoder *encoder; | |
1072 | ||
1073 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1074 | if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) | |
1075 | return encoder; | |
1076 | } | |
1077 | ||
1078 | return NULL; | |
1079 | } | |
1080 | ||
2c348e50 AP |
1081 | /** |
1082 | * sti_hdmi_audio_get_non_coherent_n() - get N parameter for non-coherent | |
1083 | * clocks. None-coherent clocks means that audio and TMDS clocks have not the | |
1084 | * same source (drifts between clocks). In this case assumption is that CTS is | |
1085 | * automatically calculated by hardware. | |
1086 | * | |
1087 | * @audio_fs: audio frame clock frequency in Hz | |
1088 | * | |
1089 | * Values computed are based on table described in HDMI specification 1.4b | |
1090 | * | |
1091 | * Returns n value. | |
1092 | */ | |
1093 | static int sti_hdmi_audio_get_non_coherent_n(unsigned int audio_fs) | |
1094 | { | |
1095 | unsigned int n; | |
1096 | ||
1097 | switch (audio_fs) { | |
1098 | case 32000: | |
1099 | n = 4096; | |
1100 | break; | |
1101 | case 44100: | |
1102 | n = 6272; | |
1103 | break; | |
1104 | case 48000: | |
1105 | n = 6144; | |
1106 | break; | |
1107 | case 88200: | |
1108 | n = 6272 * 2; | |
1109 | break; | |
1110 | case 96000: | |
1111 | n = 6144 * 2; | |
1112 | break; | |
1113 | case 176400: | |
1114 | n = 6272 * 4; | |
1115 | break; | |
1116 | case 192000: | |
1117 | n = 6144 * 4; | |
1118 | break; | |
1119 | default: | |
1120 | /* Not pre-defined, recommended value: 128 * fs / 1000 */ | |
1121 | n = (audio_fs * 128) / 1000; | |
1122 | } | |
1123 | ||
1124 | return n; | |
1125 | } | |
1126 | ||
1127 | static int hdmi_audio_configure(struct sti_hdmi *hdmi, | |
1128 | struct hdmi_audio_params *params) | |
1129 | { | |
1130 | int audio_cfg, n; | |
1131 | struct hdmi_audio_infoframe *info = ¶ms->cea; | |
1132 | ||
1133 | DRM_DEBUG_DRIVER("\n"); | |
1134 | ||
1135 | if (!hdmi->enabled) | |
1136 | return 0; | |
1137 | ||
1138 | /* update N parameter */ | |
1139 | n = sti_hdmi_audio_get_non_coherent_n(params->sample_rate); | |
1140 | ||
1141 | DRM_DEBUG_DRIVER("Audio rate = %d Hz, TMDS clock = %d Hz, n = %d\n", | |
1142 | params->sample_rate, hdmi->mode.clock * 1000, n); | |
1143 | hdmi_write(hdmi, n, HDMI_AUDN); | |
1144 | ||
1145 | /* update HDMI registers according to configuration */ | |
1146 | audio_cfg = HDMI_AUD_CFG_SPDIF_DIV_2 | HDMI_AUD_CFG_DTS_INVALID | | |
1147 | HDMI_AUD_CFG_ONE_BIT_INVALID; | |
1148 | ||
1149 | switch (info->channels) { | |
1150 | case 8: | |
1151 | audio_cfg |= HDMI_AUD_CFG_CH78_VALID; | |
1152 | case 6: | |
1153 | audio_cfg |= HDMI_AUD_CFG_CH56_VALID; | |
1154 | case 4: | |
1155 | audio_cfg |= HDMI_AUD_CFG_CH34_VALID | HDMI_AUD_CFG_8CH; | |
1156 | case 2: | |
1157 | audio_cfg |= HDMI_AUD_CFG_CH12_VALID; | |
1158 | break; | |
1159 | default: | |
1160 | DRM_ERROR("ERROR: Unsupported number of channels (%d)!\n", | |
1161 | info->channels); | |
1162 | return -EINVAL; | |
1163 | } | |
1164 | ||
1165 | hdmi_write(hdmi, audio_cfg, HDMI_AUDIO_CFG); | |
1166 | ||
1167 | hdmi->audio = *params; | |
1168 | ||
1169 | return hdmi_audio_infoframe_config(hdmi); | |
1170 | } | |
1171 | ||
5dd0775e | 1172 | static void hdmi_audio_shutdown(struct device *dev, void *data) |
2c348e50 AP |
1173 | { |
1174 | struct sti_hdmi *hdmi = dev_get_drvdata(dev); | |
1175 | int audio_cfg; | |
1176 | ||
1177 | DRM_DEBUG_DRIVER("\n"); | |
1178 | ||
1179 | /* disable audio */ | |
1180 | audio_cfg = HDMI_AUD_CFG_SPDIF_DIV_2 | HDMI_AUD_CFG_DTS_INVALID | | |
1181 | HDMI_AUD_CFG_ONE_BIT_INVALID; | |
1182 | hdmi_write(hdmi, audio_cfg, HDMI_AUDIO_CFG); | |
1183 | ||
7c0ca70b | 1184 | hdmi->audio.enabled = false; |
2c348e50 AP |
1185 | hdmi_audio_infoframe_config(hdmi); |
1186 | } | |
1187 | ||
1188 | static int hdmi_audio_hw_params(struct device *dev, | |
5dd0775e | 1189 | void *data, |
2c348e50 AP |
1190 | struct hdmi_codec_daifmt *daifmt, |
1191 | struct hdmi_codec_params *params) | |
1192 | { | |
1193 | struct sti_hdmi *hdmi = dev_get_drvdata(dev); | |
1194 | int ret; | |
1195 | struct hdmi_audio_params audio = { | |
1196 | .sample_width = params->sample_width, | |
1197 | .sample_rate = params->sample_rate, | |
1198 | .cea = params->cea, | |
1199 | }; | |
1200 | ||
1201 | DRM_DEBUG_DRIVER("\n"); | |
1202 | ||
1203 | if (!hdmi->enabled) | |
1204 | return 0; | |
1205 | ||
1206 | if ((daifmt->fmt != HDMI_I2S) || daifmt->bit_clk_inv || | |
1207 | daifmt->frame_clk_inv || daifmt->bit_clk_master || | |
1208 | daifmt->frame_clk_master) { | |
1209 | dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__, | |
1210 | daifmt->bit_clk_inv, daifmt->frame_clk_inv, | |
1211 | daifmt->bit_clk_master, | |
1212 | daifmt->frame_clk_master); | |
1213 | return -EINVAL; | |
1214 | } | |
1215 | ||
7c0ca70b | 1216 | audio.enabled = true; |
2c348e50 AP |
1217 | |
1218 | ret = hdmi_audio_configure(hdmi, &audio); | |
1219 | if (ret < 0) | |
1220 | return ret; | |
1221 | ||
1222 | return 0; | |
1223 | } | |
1224 | ||
5dd0775e | 1225 | static int hdmi_audio_digital_mute(struct device *dev, void *data, bool enable) |
2c348e50 AP |
1226 | { |
1227 | struct sti_hdmi *hdmi = dev_get_drvdata(dev); | |
1228 | ||
1229 | DRM_DEBUG_DRIVER("%s\n", enable ? "enable" : "disable"); | |
1230 | ||
1231 | if (enable) | |
1232 | hdmi_write(hdmi, HDMI_SAMPLE_FLAT_ALL, HDMI_SAMPLE_FLAT_MASK); | |
1233 | else | |
1234 | hdmi_write(hdmi, HDMI_SAMPLE_FLAT_NO, HDMI_SAMPLE_FLAT_MASK); | |
1235 | ||
1236 | return 0; | |
1237 | } | |
1238 | ||
5dd0775e | 1239 | static int hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len) |
2c348e50 AP |
1240 | { |
1241 | struct sti_hdmi *hdmi = dev_get_drvdata(dev); | |
1242 | struct drm_connector *connector = hdmi->drm_connector; | |
1243 | ||
1244 | DRM_DEBUG_DRIVER("\n"); | |
1245 | memcpy(buf, connector->eld, min(sizeof(connector->eld), len)); | |
1246 | ||
1247 | return 0; | |
1248 | } | |
1249 | ||
1250 | static const struct hdmi_codec_ops audio_codec_ops = { | |
1251 | .hw_params = hdmi_audio_hw_params, | |
1252 | .audio_shutdown = hdmi_audio_shutdown, | |
1253 | .digital_mute = hdmi_audio_digital_mute, | |
1254 | .get_eld = hdmi_audio_get_eld, | |
1255 | }; | |
1256 | ||
1257 | static int sti_hdmi_register_audio_driver(struct device *dev, | |
1258 | struct sti_hdmi *hdmi) | |
1259 | { | |
1260 | struct hdmi_codec_pdata codec_data = { | |
1261 | .ops = &audio_codec_ops, | |
1262 | .max_i2s_channels = 8, | |
1263 | .i2s = 1, | |
1264 | }; | |
1265 | ||
1266 | DRM_DEBUG_DRIVER("\n"); | |
1267 | ||
7c0ca70b | 1268 | hdmi->audio.enabled = false; |
2c348e50 AP |
1269 | |
1270 | hdmi->audio_pdev = platform_device_register_data( | |
1271 | dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO, | |
1272 | &codec_data, sizeof(codec_data)); | |
1273 | ||
1274 | if (IS_ERR(hdmi->audio_pdev)) | |
1275 | return PTR_ERR(hdmi->audio_pdev); | |
1276 | ||
1277 | DRM_INFO("%s Driver bound %s\n", HDMI_CODEC_DRV_NAME, dev_name(dev)); | |
1278 | ||
1279 | return 0; | |
1280 | } | |
1281 | ||
5402626c BG |
1282 | static int sti_hdmi_bind(struct device *dev, struct device *master, void *data) |
1283 | { | |
1284 | struct sti_hdmi *hdmi = dev_get_drvdata(dev); | |
1285 | struct drm_device *drm_dev = data; | |
1286 | struct drm_encoder *encoder; | |
1287 | struct sti_hdmi_connector *connector; | |
1288 | struct drm_connector *drm_connector; | |
1289 | struct drm_bridge *bridge; | |
5402626c BG |
1290 | int err; |
1291 | ||
5402626c BG |
1292 | /* Set the drm device handle */ |
1293 | hdmi->drm_dev = drm_dev; | |
1294 | ||
1295 | encoder = sti_hdmi_find_encoder(drm_dev); | |
1296 | if (!encoder) | |
807642d7 | 1297 | return -EINVAL; |
5402626c BG |
1298 | |
1299 | connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL); | |
1300 | if (!connector) | |
807642d7 | 1301 | return -EINVAL; |
5402626c BG |
1302 | |
1303 | connector->hdmi = hdmi; | |
1304 | ||
1305 | bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL); | |
1306 | if (!bridge) | |
807642d7 | 1307 | return -EINVAL; |
5402626c BG |
1308 | |
1309 | bridge->driver_private = hdmi; | |
b07b90fd | 1310 | bridge->funcs = &sti_hdmi_bridge_funcs; |
3d3f8b1f | 1311 | drm_bridge_attach(drm_dev, bridge); |
5402626c BG |
1312 | |
1313 | encoder->bridge = bridge; | |
1314 | connector->encoder = encoder; | |
1315 | ||
1316 | drm_connector = (struct drm_connector *)connector; | |
1317 | ||
1318 | drm_connector->polled = DRM_CONNECTOR_POLL_HPD; | |
1319 | ||
1320 | drm_connector_init(drm_dev, drm_connector, | |
1321 | &sti_hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA); | |
1322 | drm_connector_helper_add(drm_connector, | |
1323 | &sti_hdmi_connector_helper_funcs); | |
1324 | ||
5671cefb VA |
1325 | /* initialise property */ |
1326 | sti_hdmi_connector_init_property(drm_dev, drm_connector); | |
1327 | ||
2c348e50 AP |
1328 | hdmi->drm_connector = drm_connector; |
1329 | ||
5402626c BG |
1330 | err = drm_mode_connector_attach_encoder(drm_connector, encoder); |
1331 | if (err) { | |
1332 | DRM_ERROR("Failed to attach a connector to a encoder\n"); | |
1333 | goto err_sysfs; | |
1334 | } | |
1335 | ||
2c348e50 AP |
1336 | err = sti_hdmi_register_audio_driver(dev, hdmi); |
1337 | if (err) { | |
1338 | DRM_ERROR("Failed to attach an audio codec\n"); | |
1339 | goto err_sysfs; | |
1340 | } | |
1341 | ||
1342 | /* Initialize audio infoframe */ | |
1343 | err = hdmi_audio_infoframe_init(&hdmi->audio.cea); | |
1344 | if (err) { | |
1345 | DRM_ERROR("Failed to init audio infoframe\n"); | |
1346 | goto err_sysfs; | |
1347 | } | |
1348 | ||
5402626c BG |
1349 | /* Enable default interrupts */ |
1350 | hdmi_write(hdmi, HDMI_DEFAULT_INT, HDMI_INT_EN); | |
1351 | ||
1352 | return 0; | |
1353 | ||
1354 | err_sysfs: | |
84601dbd | 1355 | drm_bridge_remove(bridge); |
2c348e50 | 1356 | hdmi->drm_connector = NULL; |
5402626c BG |
1357 | return -EINVAL; |
1358 | } | |
1359 | ||
1360 | static void sti_hdmi_unbind(struct device *dev, | |
1361 | struct device *master, void *data) | |
1362 | { | |
7ea6e6e4 VA |
1363 | struct sti_hdmi *hdmi = dev_get_drvdata(dev); |
1364 | struct drm_device *drm_dev = data; | |
1365 | ||
1366 | hdmi_debugfs_exit(hdmi, drm_dev->primary); | |
5402626c BG |
1367 | } |
1368 | ||
1369 | static const struct component_ops sti_hdmi_ops = { | |
1370 | .bind = sti_hdmi_bind, | |
1371 | .unbind = sti_hdmi_unbind, | |
1372 | }; | |
1373 | ||
8e932cf0 | 1374 | static const struct of_device_id hdmi_of_match[] = { |
5402626c | 1375 | { |
5402626c BG |
1376 | .compatible = "st,stih407-hdmi", |
1377 | .data = &tx3g4c28phy_ops, | |
1378 | }, { | |
1379 | /* end node */ | |
1380 | } | |
1381 | }; | |
1382 | MODULE_DEVICE_TABLE(of, hdmi_of_match); | |
1383 | ||
1384 | static int sti_hdmi_probe(struct platform_device *pdev) | |
1385 | { | |
1386 | struct device *dev = &pdev->dev; | |
1387 | struct sti_hdmi *hdmi; | |
1388 | struct device_node *np = dev->of_node; | |
1389 | struct resource *res; | |
53bdcf5f | 1390 | struct device_node *ddc; |
5402626c BG |
1391 | int ret; |
1392 | ||
1393 | DRM_INFO("%s\n", __func__); | |
1394 | ||
1395 | hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); | |
1396 | if (!hdmi) | |
1397 | return -ENOMEM; | |
1398 | ||
53bdcf5f BG |
1399 | ddc = of_parse_phandle(pdev->dev.of_node, "ddc", 0); |
1400 | if (ddc) { | |
4d5821a7 | 1401 | hdmi->ddc_adapt = of_get_i2c_adapter_by_node(ddc); |
53bdcf5f | 1402 | of_node_put(ddc); |
4d5821a7 VZ |
1403 | if (!hdmi->ddc_adapt) |
1404 | return -EPROBE_DEFER; | |
53bdcf5f BG |
1405 | } |
1406 | ||
5402626c BG |
1407 | hdmi->dev = pdev->dev; |
1408 | ||
1409 | /* Get resources */ | |
1410 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi-reg"); | |
1411 | if (!res) { | |
1412 | DRM_ERROR("Invalid hdmi resource\n"); | |
807642d7 VZ |
1413 | ret = -ENOMEM; |
1414 | goto release_adapter; | |
5402626c BG |
1415 | } |
1416 | hdmi->regs = devm_ioremap_nocache(dev, res->start, resource_size(res)); | |
807642d7 VZ |
1417 | if (!hdmi->regs) { |
1418 | ret = -ENOMEM; | |
1419 | goto release_adapter; | |
1420 | } | |
5402626c | 1421 | |
5402626c BG |
1422 | hdmi->phy_ops = (struct hdmi_phy_ops *) |
1423 | of_match_node(hdmi_of_match, np)->data; | |
1424 | ||
1425 | /* Get clock resources */ | |
1426 | hdmi->clk_pix = devm_clk_get(dev, "pix"); | |
1427 | if (IS_ERR(hdmi->clk_pix)) { | |
1428 | DRM_ERROR("Cannot get hdmi_pix clock\n"); | |
807642d7 VZ |
1429 | ret = PTR_ERR(hdmi->clk_pix); |
1430 | goto release_adapter; | |
5402626c BG |
1431 | } |
1432 | ||
1433 | hdmi->clk_tmds = devm_clk_get(dev, "tmds"); | |
1434 | if (IS_ERR(hdmi->clk_tmds)) { | |
1435 | DRM_ERROR("Cannot get hdmi_tmds clock\n"); | |
807642d7 VZ |
1436 | ret = PTR_ERR(hdmi->clk_tmds); |
1437 | goto release_adapter; | |
5402626c BG |
1438 | } |
1439 | ||
1440 | hdmi->clk_phy = devm_clk_get(dev, "phy"); | |
1441 | if (IS_ERR(hdmi->clk_phy)) { | |
1442 | DRM_ERROR("Cannot get hdmi_phy clock\n"); | |
807642d7 VZ |
1443 | ret = PTR_ERR(hdmi->clk_phy); |
1444 | goto release_adapter; | |
5402626c BG |
1445 | } |
1446 | ||
1447 | hdmi->clk_audio = devm_clk_get(dev, "audio"); | |
1448 | if (IS_ERR(hdmi->clk_audio)) { | |
1449 | DRM_ERROR("Cannot get hdmi_audio clock\n"); | |
807642d7 VZ |
1450 | ret = PTR_ERR(hdmi->clk_audio); |
1451 | goto release_adapter; | |
5402626c BG |
1452 | } |
1453 | ||
76569207 | 1454 | hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG; |
5402626c BG |
1455 | |
1456 | init_waitqueue_head(&hdmi->wait_event); | |
1457 | ||
1458 | hdmi->irq = platform_get_irq_byname(pdev, "irq"); | |
1459 | ||
1460 | ret = devm_request_threaded_irq(dev, hdmi->irq, hdmi_irq, | |
1461 | hdmi_irq_thread, IRQF_ONESHOT, dev_name(dev), hdmi); | |
1462 | if (ret) { | |
1463 | DRM_ERROR("Failed to register HDMI interrupt\n"); | |
807642d7 | 1464 | goto release_adapter; |
5402626c BG |
1465 | } |
1466 | ||
1467 | hdmi->reset = devm_reset_control_get(dev, "hdmi"); | |
1468 | /* Take hdmi out of reset */ | |
1469 | if (!IS_ERR(hdmi->reset)) | |
1470 | reset_control_deassert(hdmi->reset); | |
1471 | ||
1472 | platform_set_drvdata(pdev, hdmi); | |
1473 | ||
1474 | return component_add(&pdev->dev, &sti_hdmi_ops); | |
807642d7 VZ |
1475 | |
1476 | release_adapter: | |
4d5821a7 | 1477 | i2c_put_adapter(hdmi->ddc_adapt); |
807642d7 VZ |
1478 | |
1479 | return ret; | |
5402626c BG |
1480 | } |
1481 | ||
1482 | static int sti_hdmi_remove(struct platform_device *pdev) | |
1483 | { | |
41a14623 BG |
1484 | struct sti_hdmi *hdmi = dev_get_drvdata(&pdev->dev); |
1485 | ||
4d5821a7 | 1486 | i2c_put_adapter(hdmi->ddc_adapt); |
2c348e50 AP |
1487 | if (hdmi->audio_pdev) |
1488 | platform_device_unregister(hdmi->audio_pdev); | |
5402626c | 1489 | component_del(&pdev->dev, &sti_hdmi_ops); |
4d5821a7 | 1490 | |
5402626c BG |
1491 | return 0; |
1492 | } | |
1493 | ||
1494 | struct platform_driver sti_hdmi_driver = { | |
1495 | .driver = { | |
1496 | .name = "sti-hdmi", | |
1497 | .owner = THIS_MODULE, | |
1498 | .of_match_table = hdmi_of_match, | |
1499 | }, | |
1500 | .probe = sti_hdmi_probe, | |
1501 | .remove = sti_hdmi_remove, | |
1502 | }; | |
1503 | ||
5402626c BG |
1504 | MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>"); |
1505 | MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver"); | |
1506 | MODULE_LICENSE("GPL"); |