treewide: kmalloc() -> kmalloc_array()
[linux-block.git] / drivers / gpu / drm / savage / savage_bci.c
CommitLineData
282a1674
DA
1/* savage_bci.c -- BCI support for Savage
2 *
3 * Copyright 2004 Felix Kuehling
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sub license,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
20 * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
22 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
760285e7
DH
25#include <drm/drmP.h>
26#include <drm/savage_drm.h>
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27#include "savage_drv.h"
28
29/* Need a long timeout for shadow status updates can take a while
30 * and so can waiting for events when the queue is full. */
b5e89ed5
DA
31#define SAVAGE_DEFAULT_USEC_TIMEOUT 1000000 /* 1s */
32#define SAVAGE_EVENT_USEC_TIMEOUT 5000000 /* 5s */
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DA
33#define SAVAGE_FREELIST_DEBUG 0
34
eddca551 35static int savage_do_cleanup_bci(struct drm_device *dev);
ce60fe02 36
282a1674 37static int
b5e89ed5 38savage_bci_wait_fifo_shadow(drm_savage_private_t * dev_priv, unsigned int n)
282a1674
DA
39{
40 uint32_t mask = dev_priv->status_used_mask;
41 uint32_t threshold = dev_priv->bci_threshold_hi;
42 uint32_t status;
43 int i;
44
45#if SAVAGE_BCI_DEBUG
46 if (n > dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - threshold)
47 DRM_ERROR("Trying to emit %d words "
48 "(more than guaranteed space in COB)\n", n);
49#endif
50
51 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) {
85b2331b 52 mb();
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53 status = dev_priv->status_ptr[0];
54 if ((status & mask) < threshold)
55 return 0;
56 DRM_UDELAY(1);
57 }
58
59#if SAVAGE_BCI_DEBUG
60 DRM_ERROR("failed!\n");
61 DRM_INFO(" status=0x%08x, threshold=0x%08x\n", status, threshold);
62#endif
20caafa6 63 return -EBUSY;
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DA
64}
65
66static int
b5e89ed5 67savage_bci_wait_fifo_s3d(drm_savage_private_t * dev_priv, unsigned int n)
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DA
68{
69 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n;
70 uint32_t status;
71 int i;
72
73 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) {
74 status = SAVAGE_READ(SAVAGE_STATUS_WORD0);
75 if ((status & SAVAGE_FIFO_USED_MASK_S3D) <= maxUsed)
76 return 0;
77 DRM_UDELAY(1);
78 }
79
80#if SAVAGE_BCI_DEBUG
81 DRM_ERROR("failed!\n");
82 DRM_INFO(" status=0x%08x\n", status);
83#endif
20caafa6 84 return -EBUSY;
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DA
85}
86
87static int
b5e89ed5 88savage_bci_wait_fifo_s4(drm_savage_private_t * dev_priv, unsigned int n)
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DA
89{
90 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n;
91 uint32_t status;
92 int i;
93
94 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) {
95 status = SAVAGE_READ(SAVAGE_ALT_STATUS_WORD0);
96 if ((status & SAVAGE_FIFO_USED_MASK_S4) <= maxUsed)
97 return 0;
98 DRM_UDELAY(1);
99 }
100
101#if SAVAGE_BCI_DEBUG
102 DRM_ERROR("failed!\n");
103 DRM_INFO(" status=0x%08x\n", status);
104#endif
20caafa6 105 return -EBUSY;
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106}
107
108/*
109 * Waiting for events.
110 *
111 * The BIOSresets the event tag to 0 on mode changes. Therefore we
112 * never emit 0 to the event tag. If we find a 0 event tag we know the
113 * BIOS stomped on it and return success assuming that the BIOS waited
114 * for engine idle.
115 *
116 * Note: if the Xserver uses the event tag it has to follow the same
117 * rule. Otherwise there may be glitches every 2^16 events.
118 */
119static int
b5e89ed5 120savage_bci_wait_event_shadow(drm_savage_private_t * dev_priv, uint16_t e)
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121{
122 uint32_t status;
123 int i;
124
125 for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) {
85b2331b 126 mb();
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127 status = dev_priv->status_ptr[1];
128 if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff ||
129 (status & 0xffff) == 0)
130 return 0;
131 DRM_UDELAY(1);
132 }
133
134#if SAVAGE_BCI_DEBUG
135 DRM_ERROR("failed!\n");
136 DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e);
137#endif
138
20caafa6 139 return -EBUSY;
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140}
141
142static int
b5e89ed5 143savage_bci_wait_event_reg(drm_savage_private_t * dev_priv, uint16_t e)
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144{
145 uint32_t status;
146 int i;
147
148 for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) {
149 status = SAVAGE_READ(SAVAGE_STATUS_WORD1);
150 if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff ||
151 (status & 0xffff) == 0)
152 return 0;
153 DRM_UDELAY(1);
154 }
155
156#if SAVAGE_BCI_DEBUG
157 DRM_ERROR("failed!\n");
158 DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e);
159#endif
160
20caafa6 161 return -EBUSY;
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DA
162}
163
b5e89ed5 164uint16_t savage_bci_emit_event(drm_savage_private_t * dev_priv,
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165 unsigned int flags)
166{
167 uint16_t count;
168 BCI_LOCALS;
169
170 if (dev_priv->status_ptr) {
171 /* coordinate with Xserver */
172 count = dev_priv->status_ptr[1023];
173 if (count < dev_priv->event_counter)
174 dev_priv->event_wrap++;
175 } else {
176 count = dev_priv->event_counter;
177 }
178 count = (count + 1) & 0xffff;
179 if (count == 0) {
b5e89ed5 180 count++; /* See the comment above savage_wait_event_*. */
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181 dev_priv->event_wrap++;
182 }
183 dev_priv->event_counter = count;
184 if (dev_priv->status_ptr)
b5e89ed5 185 dev_priv->status_ptr[1023] = (uint32_t) count;
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186
187 if ((flags & (SAVAGE_WAIT_2D | SAVAGE_WAIT_3D))) {
188 unsigned int wait_cmd = BCI_CMD_WAIT;
189 if ((flags & SAVAGE_WAIT_2D))
190 wait_cmd |= BCI_CMD_WAIT_2D;
191 if ((flags & SAVAGE_WAIT_3D))
192 wait_cmd |= BCI_CMD_WAIT_3D;
193 BEGIN_BCI(2);
194 BCI_WRITE(wait_cmd);
195 } else {
196 BEGIN_BCI(1);
197 }
b5e89ed5 198 BCI_WRITE(BCI_CMD_UPDATE_EVENT_TAG | (uint32_t) count);
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199
200 return count;
201}
202
203/*
204 * Freelist management
205 */
eddca551 206static int savage_freelist_init(struct drm_device * dev)
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207{
208 drm_savage_private_t *dev_priv = dev->dev_private;
cdd55a29 209 struct drm_device_dma *dma = dev->dma;
056219e2 210 struct drm_buf *buf;
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211 drm_savage_buf_priv_t *entry;
212 int i;
213 DRM_DEBUG("count=%d\n", dma->buf_count);
214
215 dev_priv->head.next = &dev_priv->tail;
216 dev_priv->head.prev = NULL;
217 dev_priv->head.buf = NULL;
218
219 dev_priv->tail.next = NULL;
220 dev_priv->tail.prev = &dev_priv->head;
221 dev_priv->tail.buf = NULL;
222
223 for (i = 0; i < dma->buf_count; i++) {
224 buf = dma->buflist[i];
225 entry = buf->dev_private;
226
227 SET_AGE(&entry->age, 0, 0);
228 entry->buf = buf;
229
230 entry->next = dev_priv->head.next;
231 entry->prev = &dev_priv->head;
232 dev_priv->head.next->prev = entry;
233 dev_priv->head.next = entry;
234 }
235
236 return 0;
237}
238
056219e2 239static struct drm_buf *savage_freelist_get(struct drm_device * dev)
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240{
241 drm_savage_private_t *dev_priv = dev->dev_private;
242 drm_savage_buf_priv_t *tail = dev_priv->tail.prev;
243 uint16_t event;
244 unsigned int wrap;
245 DRM_DEBUG("\n");
246
247 UPDATE_EVENT_COUNTER();
248 if (dev_priv->status_ptr)
249 event = dev_priv->status_ptr[1] & 0xffff;
250 else
251 event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
252 wrap = dev_priv->event_wrap;
253 if (event > dev_priv->event_counter)
b5e89ed5 254 wrap--; /* hardware hasn't passed the last wrap yet */
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255
256 DRM_DEBUG(" tail=0x%04x %d\n", tail->age.event, tail->age.wrap);
257 DRM_DEBUG(" head=0x%04x %d\n", event, wrap);
258
259 if (tail->buf && (TEST_AGE(&tail->age, event, wrap) || event == 0)) {
260 drm_savage_buf_priv_t *next = tail->next;
261 drm_savage_buf_priv_t *prev = tail->prev;
262 prev->next = next;
263 next->prev = prev;
264 tail->next = tail->prev = NULL;
265 return tail->buf;
266 }
267
268 DRM_DEBUG("returning NULL, tail->buf=%p!\n", tail->buf);
269 return NULL;
270}
271
056219e2 272void savage_freelist_put(struct drm_device * dev, struct drm_buf * buf)
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DA
273{
274 drm_savage_private_t *dev_priv = dev->dev_private;
275 drm_savage_buf_priv_t *entry = buf->dev_private, *prev, *next;
276
277 DRM_DEBUG("age=0x%04x wrap=%d\n", entry->age.event, entry->age.wrap);
278
279 if (entry->next != NULL || entry->prev != NULL) {
280 DRM_ERROR("entry already on freelist.\n");
281 return;
282 }
283
284 prev = &dev_priv->head;
285 next = prev->next;
286 prev->next = entry;
287 next->prev = entry;
288 entry->prev = prev;
289 entry->next = next;
290}
291
292/*
293 * Command DMA
294 */
b5e89ed5 295static int savage_dma_init(drm_savage_private_t * dev_priv)
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296{
297 unsigned int i;
298
299 dev_priv->nr_dma_pages = dev_priv->cmd_dma->size /
b5e89ed5 300 (SAVAGE_DMA_PAGE_SIZE * 4);
6da2ec56
KC
301 dev_priv->dma_pages = kmalloc_array(dev_priv->nr_dma_pages,
302 sizeof(drm_savage_dma_page_t),
303 GFP_KERNEL);
282a1674 304 if (dev_priv->dma_pages == NULL)
20caafa6 305 return -ENOMEM;
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DA
306
307 for (i = 0; i < dev_priv->nr_dma_pages; ++i) {
308 SET_AGE(&dev_priv->dma_pages[i].age, 0, 0);
309 dev_priv->dma_pages[i].used = 0;
310 dev_priv->dma_pages[i].flushed = 0;
311 }
312 SET_AGE(&dev_priv->last_dma_age, 0, 0);
313
314 dev_priv->first_dma_page = 0;
315 dev_priv->current_dma_page = 0;
316
317 return 0;
318}
319
b5e89ed5 320void savage_dma_reset(drm_savage_private_t * dev_priv)
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DA
321{
322 uint16_t event;
323 unsigned int wrap, i;
324 event = savage_bci_emit_event(dev_priv, 0);
325 wrap = dev_priv->event_wrap;
326 for (i = 0; i < dev_priv->nr_dma_pages; ++i) {
327 SET_AGE(&dev_priv->dma_pages[i].age, event, wrap);
328 dev_priv->dma_pages[i].used = 0;
329 dev_priv->dma_pages[i].flushed = 0;
330 }
331 SET_AGE(&dev_priv->last_dma_age, event, wrap);
332 dev_priv->first_dma_page = dev_priv->current_dma_page = 0;
333}
334
b5e89ed5 335void savage_dma_wait(drm_savage_private_t * dev_priv, unsigned int page)
282a1674
DA
336{
337 uint16_t event;
338 unsigned int wrap;
339
340 /* Faked DMA buffer pages don't age. */
341 if (dev_priv->cmd_dma == &dev_priv->fake_dma)
342 return;
343
344 UPDATE_EVENT_COUNTER();
345 if (dev_priv->status_ptr)
346 event = dev_priv->status_ptr[1] & 0xffff;
347 else
348 event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
349 wrap = dev_priv->event_wrap;
350 if (event > dev_priv->event_counter)
b5e89ed5 351 wrap--; /* hardware hasn't passed the last wrap yet */
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352
353 if (dev_priv->dma_pages[page].age.wrap > wrap ||
354 (dev_priv->dma_pages[page].age.wrap == wrap &&
355 dev_priv->dma_pages[page].age.event > event)) {
356 if (dev_priv->wait_evnt(dev_priv,
357 dev_priv->dma_pages[page].age.event)
358 < 0)
359 DRM_ERROR("wait_evnt failed!\n");
360 }
361}
362
b5e89ed5 363uint32_t *savage_dma_alloc(drm_savage_private_t * dev_priv, unsigned int n)
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DA
364{
365 unsigned int cur = dev_priv->current_dma_page;
366 unsigned int rest = SAVAGE_DMA_PAGE_SIZE -
b5e89ed5
DA
367 dev_priv->dma_pages[cur].used;
368 unsigned int nr_pages = (n - rest + SAVAGE_DMA_PAGE_SIZE - 1) /
369 SAVAGE_DMA_PAGE_SIZE;
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DA
370 uint32_t *dma_ptr;
371 unsigned int i;
372
373 DRM_DEBUG("cur=%u, cur->used=%u, n=%u, rest=%u, nr_pages=%u\n",
374 cur, dev_priv->dma_pages[cur].used, n, rest, nr_pages);
375
376 if (cur + nr_pages < dev_priv->nr_dma_pages) {
b5e89ed5
DA
377 dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle +
378 cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used;
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DA
379 if (n < rest)
380 rest = n;
381 dev_priv->dma_pages[cur].used += rest;
382 n -= rest;
383 cur++;
384 } else {
385 dev_priv->dma_flush(dev_priv);
b5e89ed5
DA
386 nr_pages =
387 (n + SAVAGE_DMA_PAGE_SIZE - 1) / SAVAGE_DMA_PAGE_SIZE;
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DA
388 for (i = cur; i < dev_priv->nr_dma_pages; ++i) {
389 dev_priv->dma_pages[i].age = dev_priv->last_dma_age;
390 dev_priv->dma_pages[i].used = 0;
391 dev_priv->dma_pages[i].flushed = 0;
392 }
b5e89ed5 393 dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle;
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DA
394 dev_priv->first_dma_page = cur = 0;
395 }
396 for (i = cur; nr_pages > 0; ++i, --nr_pages) {
397#if SAVAGE_DMA_DEBUG
398 if (dev_priv->dma_pages[i].used) {
399 DRM_ERROR("unflushed page %u: used=%u\n",
400 i, dev_priv->dma_pages[i].used);
401 }
402#endif
403 if (n > SAVAGE_DMA_PAGE_SIZE)
404 dev_priv->dma_pages[i].used = SAVAGE_DMA_PAGE_SIZE;
405 else
406 dev_priv->dma_pages[i].used = n;
407 n -= SAVAGE_DMA_PAGE_SIZE;
408 }
409 dev_priv->current_dma_page = --i;
410
411 DRM_DEBUG("cur=%u, cur->used=%u, n=%u\n",
412 i, dev_priv->dma_pages[i].used, n);
413
414 savage_dma_wait(dev_priv, dev_priv->current_dma_page);
415
416 return dma_ptr;
417}
418
b5e89ed5 419static void savage_dma_flush(drm_savage_private_t * dev_priv)
282a1674
DA
420{
421 unsigned int first = dev_priv->first_dma_page;
422 unsigned int cur = dev_priv->current_dma_page;
423 uint16_t event;
424 unsigned int wrap, pad, align, len, i;
425 unsigned long phys_addr;
426 BCI_LOCALS;
427
428 if (first == cur &&
429 dev_priv->dma_pages[cur].used == dev_priv->dma_pages[cur].flushed)
430 return;
431
432 /* pad length to multiples of 2 entries
433 * align start of next DMA block to multiles of 8 entries */
434 pad = -dev_priv->dma_pages[cur].used & 1;
435 align = -(dev_priv->dma_pages[cur].used + pad) & 7;
436
437 DRM_DEBUG("first=%u, cur=%u, first->flushed=%u, cur->used=%u, "
438 "pad=%u, align=%u\n",
439 first, cur, dev_priv->dma_pages[first].flushed,
440 dev_priv->dma_pages[cur].used, pad, align);
441
442 /* pad with noops */
443 if (pad) {
b5e89ed5
DA
444 uint32_t *dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle +
445 cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used;
282a1674 446 dev_priv->dma_pages[cur].used += pad;
b5e89ed5 447 while (pad != 0) {
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DA
448 *dma_ptr++ = BCI_CMD_WAIT;
449 pad--;
450 }
451 }
452
85b2331b 453 mb();
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DA
454
455 /* do flush ... */
456 phys_addr = dev_priv->cmd_dma->offset +
b5e89ed5
DA
457 (first * SAVAGE_DMA_PAGE_SIZE +
458 dev_priv->dma_pages[first].flushed) * 4;
282a1674 459 len = (cur - first) * SAVAGE_DMA_PAGE_SIZE +
b5e89ed5 460 dev_priv->dma_pages[cur].used - dev_priv->dma_pages[first].flushed;
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DA
461
462 DRM_DEBUG("phys_addr=%lx, len=%u\n",
463 phys_addr | dev_priv->dma_type, len);
464
465 BEGIN_BCI(3);
466 BCI_SET_REGISTERS(SAVAGE_DMABUFADDR, 1);
467 BCI_WRITE(phys_addr | dev_priv->dma_type);
468 BCI_DMA(len);
469
470 /* fix alignment of the start of the next block */
471 dev_priv->dma_pages[cur].used += align;
472
473 /* age DMA pages */
474 event = savage_bci_emit_event(dev_priv, 0);
475 wrap = dev_priv->event_wrap;
476 for (i = first; i < cur; ++i) {
477 SET_AGE(&dev_priv->dma_pages[i].age, event, wrap);
478 dev_priv->dma_pages[i].used = 0;
479 dev_priv->dma_pages[i].flushed = 0;
480 }
481 /* age the current page only when it's full */
482 if (dev_priv->dma_pages[cur].used == SAVAGE_DMA_PAGE_SIZE) {
483 SET_AGE(&dev_priv->dma_pages[cur].age, event, wrap);
484 dev_priv->dma_pages[cur].used = 0;
485 dev_priv->dma_pages[cur].flushed = 0;
486 /* advance to next page */
487 cur++;
488 if (cur == dev_priv->nr_dma_pages)
489 cur = 0;
490 dev_priv->first_dma_page = dev_priv->current_dma_page = cur;
491 } else {
492 dev_priv->first_dma_page = cur;
493 dev_priv->dma_pages[cur].flushed = dev_priv->dma_pages[i].used;
494 }
495 SET_AGE(&dev_priv->last_dma_age, event, wrap);
496
497 DRM_DEBUG("first=cur=%u, cur->used=%u, cur->flushed=%u\n", cur,
498 dev_priv->dma_pages[cur].used,
499 dev_priv->dma_pages[cur].flushed);
500}
501
b5e89ed5 502static void savage_fake_dma_flush(drm_savage_private_t * dev_priv)
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DA
503{
504 unsigned int i, j;
505 BCI_LOCALS;
506
507 if (dev_priv->first_dma_page == dev_priv->current_dma_page &&
508 dev_priv->dma_pages[dev_priv->current_dma_page].used == 0)
509 return;
510
511 DRM_DEBUG("first=%u, cur=%u, cur->used=%u\n",
512 dev_priv->first_dma_page, dev_priv->current_dma_page,
513 dev_priv->dma_pages[dev_priv->current_dma_page].used);
514
515 for (i = dev_priv->first_dma_page;
516 i <= dev_priv->current_dma_page && dev_priv->dma_pages[i].used;
517 ++i) {
b5e89ed5
DA
518 uint32_t *dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle +
519 i * SAVAGE_DMA_PAGE_SIZE;
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DA
520#if SAVAGE_DMA_DEBUG
521 /* Sanity check: all pages except the last one must be full. */
522 if (i < dev_priv->current_dma_page &&
523 dev_priv->dma_pages[i].used != SAVAGE_DMA_PAGE_SIZE) {
524 DRM_ERROR("partial DMA page %u: used=%u",
525 i, dev_priv->dma_pages[i].used);
526 }
527#endif
528 BEGIN_BCI(dev_priv->dma_pages[i].used);
529 for (j = 0; j < dev_priv->dma_pages[i].used; ++j) {
530 BCI_WRITE(dma_ptr[j]);
531 }
532 dev_priv->dma_pages[i].used = 0;
533 }
534
535 /* reset to first page */
536 dev_priv->first_dma_page = dev_priv->current_dma_page = 0;
537}
538
eddca551 539int savage_driver_load(struct drm_device *dev, unsigned long chipset)
22eae947
DA
540{
541 drm_savage_private_t *dev_priv;
542
6ebc22e6 543 dev_priv = kzalloc(sizeof(drm_savage_private_t), GFP_KERNEL);
22eae947 544 if (dev_priv == NULL)
20caafa6 545 return -ENOMEM;
22eae947 546
22eae947
DA
547 dev->dev_private = (void *)dev_priv;
548
549 dev_priv->chipset = (enum savage_family)chipset;
550
df86b576
FZ
551 pci_set_master(dev->pdev);
552
22eae947
DA
553 return 0;
554}
555
556
282a1674 557/*
421f91d2 558 * Initialize mappings. On Savage4 and SavageIX the alignment
282a1674 559 * and size of the aperture is not suitable for automatic MTRR setup
9fc5cde7 560 * in drm_legacy_addmap. Therefore we add them manually before the maps are
22eae947 561 * initialized, and tear them down on last close.
282a1674 562 */
eddca551 563int savage_driver_firstopen(struct drm_device *dev)
282a1674 564{
22eae947 565 drm_savage_private_t *dev_priv = dev->dev_private;
282a1674
DA
566 unsigned long mmio_base, fb_base, fb_size, aperture_base;
567 /* fb_rsrc and aper_rsrc aren't really used currently, but still exist
568 * in case we decide we need information on the BAR for BSD in the
569 * future.
570 */
571 unsigned int fb_rsrc, aper_rsrc;
572 int ret = 0;
573
282a1674
DA
574 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
575 fb_rsrc = 0;
01d73a69 576 fb_base = pci_resource_start(dev->pdev, 0);
282a1674
DA
577 fb_size = SAVAGE_FB_SIZE_S3;
578 mmio_base = fb_base + SAVAGE_FB_SIZE_S3;
579 aper_rsrc = 0;
580 aperture_base = fb_base + SAVAGE_APERTURE_OFFSET;
581 /* this should always be true */
01d73a69 582 if (pci_resource_len(dev->pdev, 0) == 0x08000000) {
282a1674
DA
583 /* Don't make MMIO write-cobining! We need 3
584 * MTRRs. */
247d36d7
AL
585 dev_priv->mtrr_handles[0] =
586 arch_phys_wc_add(fb_base, 0x01000000);
587 dev_priv->mtrr_handles[1] =
588 arch_phys_wc_add(fb_base + 0x02000000,
589 0x02000000);
590 dev_priv->mtrr_handles[2] =
591 arch_phys_wc_add(fb_base + 0x04000000,
592 0x04000000);
282a1674 593 } else {
d883f7f1 594 DRM_ERROR("strange pci_resource_len %08llx\n",
01d73a69
JC
595 (unsigned long long)
596 pci_resource_len(dev->pdev, 0));
282a1674 597 }
22eae947
DA
598 } else if (dev_priv->chipset != S3_SUPERSAVAGE &&
599 dev_priv->chipset != S3_SAVAGE2000) {
01d73a69 600 mmio_base = pci_resource_start(dev->pdev, 0);
282a1674 601 fb_rsrc = 1;
01d73a69 602 fb_base = pci_resource_start(dev->pdev, 1);
282a1674
DA
603 fb_size = SAVAGE_FB_SIZE_S4;
604 aper_rsrc = 1;
605 aperture_base = fb_base + SAVAGE_APERTURE_OFFSET;
606 /* this should always be true */
01d73a69 607 if (pci_resource_len(dev->pdev, 1) == 0x08000000) {
282a1674
DA
608 /* Can use one MTRR to cover both fb and
609 * aperture. */
247d36d7
AL
610 dev_priv->mtrr_handles[0] =
611 arch_phys_wc_add(fb_base,
612 0x08000000);
282a1674 613 } else {
d883f7f1 614 DRM_ERROR("strange pci_resource_len %08llx\n",
01d73a69
JC
615 (unsigned long long)
616 pci_resource_len(dev->pdev, 1));
282a1674
DA
617 }
618 } else {
01d73a69 619 mmio_base = pci_resource_start(dev->pdev, 0);
282a1674 620 fb_rsrc = 1;
01d73a69
JC
621 fb_base = pci_resource_start(dev->pdev, 1);
622 fb_size = pci_resource_len(dev->pdev, 1);
282a1674 623 aper_rsrc = 2;
01d73a69 624 aperture_base = pci_resource_start(dev->pdev, 2);
282a1674
DA
625 /* Automatic MTRR setup will do the right thing. */
626 }
627
9fc5cde7
DH
628 ret = drm_legacy_addmap(dev, mmio_base, SAVAGE_MMIO_SIZE,
629 _DRM_REGISTERS, _DRM_READ_ONLY,
630 &dev_priv->mmio);
282a1674
DA
631 if (ret)
632 return ret;
633
9fc5cde7
DH
634 ret = drm_legacy_addmap(dev, fb_base, fb_size, _DRM_FRAME_BUFFER,
635 _DRM_WRITE_COMBINING, &dev_priv->fb);
282a1674
DA
636 if (ret)
637 return ret;
638
9fc5cde7
DH
639 ret = drm_legacy_addmap(dev, aperture_base, SAVAGE_APERTURE_SIZE,
640 _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING,
641 &dev_priv->aperture);
282a1674
DA
642 return ret;
643}
644
645/*
646 * Delete MTRRs and free device-private data.
647 */
eddca551 648void savage_driver_lastclose(struct drm_device *dev)
282a1674
DA
649{
650 drm_savage_private_t *dev_priv = dev->dev_private;
651 int i;
652
247d36d7
AL
653 for (i = 0; i < 3; ++i) {
654 arch_phys_wc_del(dev_priv->mtrr_handles[i]);
655 dev_priv->mtrr_handles[i] = 0;
656 }
22eae947
DA
657}
658
11b3c20b 659void savage_driver_unload(struct drm_device *dev)
22eae947
DA
660{
661 drm_savage_private_t *dev_priv = dev->dev_private;
282a1674 662
9a298b2a 663 kfree(dev_priv);
282a1674
DA
664}
665
eddca551 666static int savage_do_init_bci(struct drm_device * dev, drm_savage_init_t * init)
282a1674
DA
667{
668 drm_savage_private_t *dev_priv = dev->dev_private;
669
670 if (init->fb_bpp != 16 && init->fb_bpp != 32) {
671 DRM_ERROR("invalid frame buffer bpp %d!\n", init->fb_bpp);
20caafa6 672 return -EINVAL;
282a1674
DA
673 }
674 if (init->depth_bpp != 16 && init->depth_bpp != 32) {
675 DRM_ERROR("invalid depth buffer bpp %d!\n", init->fb_bpp);
20caafa6 676 return -EINVAL;
282a1674
DA
677 }
678 if (init->dma_type != SAVAGE_DMA_AGP &&
679 init->dma_type != SAVAGE_DMA_PCI) {
680 DRM_ERROR("invalid dma memory type %d!\n", init->dma_type);
20caafa6 681 return -EINVAL;
282a1674
DA
682 }
683
684 dev_priv->cob_size = init->cob_size;
685 dev_priv->bci_threshold_lo = init->bci_threshold_lo;
686 dev_priv->bci_threshold_hi = init->bci_threshold_hi;
687 dev_priv->dma_type = init->dma_type;
688
689 dev_priv->fb_bpp = init->fb_bpp;
690 dev_priv->front_offset = init->front_offset;
691 dev_priv->front_pitch = init->front_pitch;
692 dev_priv->back_offset = init->back_offset;
693 dev_priv->back_pitch = init->back_pitch;
694 dev_priv->depth_bpp = init->depth_bpp;
695 dev_priv->depth_offset = init->depth_offset;
696 dev_priv->depth_pitch = init->depth_pitch;
697
698 dev_priv->texture_offset = init->texture_offset;
699 dev_priv->texture_size = init->texture_size;
700
9fc5cde7 701 dev_priv->sarea = drm_legacy_getsarea(dev);
282a1674
DA
702 if (!dev_priv->sarea) {
703 DRM_ERROR("could not find sarea!\n");
704 savage_do_cleanup_bci(dev);
20caafa6 705 return -EINVAL;
282a1674
DA
706 }
707 if (init->status_offset != 0) {
86c1fbd5 708 dev_priv->status = drm_legacy_findmap(dev, init->status_offset);
282a1674
DA
709 if (!dev_priv->status) {
710 DRM_ERROR("could not find shadow status region!\n");
711 savage_do_cleanup_bci(dev);
20caafa6 712 return -EINVAL;
282a1674
DA
713 }
714 } else {
715 dev_priv->status = NULL;
716 }
717 if (dev_priv->dma_type == SAVAGE_DMA_AGP && init->buffers_offset) {
10eee0fe 718 dev->agp_buffer_token = init->buffers_offset;
86c1fbd5 719 dev->agp_buffer_map = drm_legacy_findmap(dev,
282a1674
DA
720 init->buffers_offset);
721 if (!dev->agp_buffer_map) {
722 DRM_ERROR("could not find DMA buffer region!\n");
723 savage_do_cleanup_bci(dev);
20caafa6 724 return -EINVAL;
282a1674 725 }
86c1fbd5 726 drm_legacy_ioremap(dev->agp_buffer_map, dev);
10f5ab04 727 if (!dev->agp_buffer_map->handle) {
282a1674
DA
728 DRM_ERROR("failed to ioremap DMA buffer region!\n");
729 savage_do_cleanup_bci(dev);
20caafa6 730 return -ENOMEM;
282a1674
DA
731 }
732 }
733 if (init->agp_textures_offset) {
734 dev_priv->agp_textures =
86c1fbd5 735 drm_legacy_findmap(dev, init->agp_textures_offset);
282a1674
DA
736 if (!dev_priv->agp_textures) {
737 DRM_ERROR("could not find agp texture region!\n");
738 savage_do_cleanup_bci(dev);
20caafa6 739 return -EINVAL;
282a1674
DA
740 }
741 } else {
742 dev_priv->agp_textures = NULL;
743 }
744
745 if (init->cmd_dma_offset) {
746 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
747 DRM_ERROR("command DMA not supported on "
748 "Savage3D/MX/IX.\n");
749 savage_do_cleanup_bci(dev);
20caafa6 750 return -EINVAL;
282a1674
DA
751 }
752 if (dev->dma && dev->dma->buflist) {
753 DRM_ERROR("command and vertex DMA not supported "
754 "at the same time.\n");
755 savage_do_cleanup_bci(dev);
20caafa6 756 return -EINVAL;
282a1674 757 }
86c1fbd5 758 dev_priv->cmd_dma = drm_legacy_findmap(dev, init->cmd_dma_offset);
282a1674
DA
759 if (!dev_priv->cmd_dma) {
760 DRM_ERROR("could not find command DMA region!\n");
761 savage_do_cleanup_bci(dev);
20caafa6 762 return -EINVAL;
282a1674
DA
763 }
764 if (dev_priv->dma_type == SAVAGE_DMA_AGP) {
765 if (dev_priv->cmd_dma->type != _DRM_AGP) {
766 DRM_ERROR("AGP command DMA region is not a "
767 "_DRM_AGP map!\n");
768 savage_do_cleanup_bci(dev);
20caafa6 769 return -EINVAL;
282a1674 770 }
86c1fbd5 771 drm_legacy_ioremap(dev_priv->cmd_dma, dev);
282a1674
DA
772 if (!dev_priv->cmd_dma->handle) {
773 DRM_ERROR("failed to ioremap command "
774 "DMA region!\n");
775 savage_do_cleanup_bci(dev);
20caafa6 776 return -ENOMEM;
282a1674
DA
777 }
778 } else if (dev_priv->cmd_dma->type != _DRM_CONSISTENT) {
779 DRM_ERROR("PCI command DMA region is not a "
780 "_DRM_CONSISTENT map!\n");
781 savage_do_cleanup_bci(dev);
20caafa6 782 return -EINVAL;
282a1674
DA
783 }
784 } else {
785 dev_priv->cmd_dma = NULL;
786 }
787
788 dev_priv->dma_flush = savage_dma_flush;
789 if (!dev_priv->cmd_dma) {
790 DRM_DEBUG("falling back to faked command DMA.\n");
791 dev_priv->fake_dma.offset = 0;
792 dev_priv->fake_dma.size = SAVAGE_FAKE_DMA_SIZE;
793 dev_priv->fake_dma.type = _DRM_SHM;
9a298b2a
EA
794 dev_priv->fake_dma.handle = kmalloc(SAVAGE_FAKE_DMA_SIZE,
795 GFP_KERNEL);
282a1674
DA
796 if (!dev_priv->fake_dma.handle) {
797 DRM_ERROR("could not allocate faked DMA buffer!\n");
798 savage_do_cleanup_bci(dev);
20caafa6 799 return -ENOMEM;
282a1674
DA
800 }
801 dev_priv->cmd_dma = &dev_priv->fake_dma;
802 dev_priv->dma_flush = savage_fake_dma_flush;
803 }
804
805 dev_priv->sarea_priv =
b5e89ed5
DA
806 (drm_savage_sarea_t *) ((uint8_t *) dev_priv->sarea->handle +
807 init->sarea_priv_offset);
282a1674
DA
808
809 /* setup bitmap descriptors */
810 {
811 unsigned int color_tile_format;
812 unsigned int depth_tile_format;
813 unsigned int front_stride, back_stride, depth_stride;
814 if (dev_priv->chipset <= S3_SAVAGE4) {
815 color_tile_format = dev_priv->fb_bpp == 16 ?
b5e89ed5 816 SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP;
282a1674 817 depth_tile_format = dev_priv->depth_bpp == 16 ?
b5e89ed5 818 SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP;
282a1674
DA
819 } else {
820 color_tile_format = SAVAGE_BD_TILE_DEST;
821 depth_tile_format = SAVAGE_BD_TILE_DEST;
822 }
b5e89ed5
DA
823 front_stride = dev_priv->front_pitch / (dev_priv->fb_bpp / 8);
824 back_stride = dev_priv->back_pitch / (dev_priv->fb_bpp / 8);
825 depth_stride =
826 dev_priv->depth_pitch / (dev_priv->depth_bpp / 8);
282a1674
DA
827
828 dev_priv->front_bd = front_stride | SAVAGE_BD_BW_DISABLE |
b5e89ed5
DA
829 (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) |
830 (color_tile_format << SAVAGE_BD_TILE_SHIFT);
282a1674 831
b5e89ed5
DA
832 dev_priv->back_bd = back_stride | SAVAGE_BD_BW_DISABLE |
833 (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) |
834 (color_tile_format << SAVAGE_BD_TILE_SHIFT);
282a1674
DA
835
836 dev_priv->depth_bd = depth_stride | SAVAGE_BD_BW_DISABLE |
b5e89ed5
DA
837 (dev_priv->depth_bpp << SAVAGE_BD_BPP_SHIFT) |
838 (depth_tile_format << SAVAGE_BD_TILE_SHIFT);
282a1674
DA
839 }
840
841 /* setup status and bci ptr */
842 dev_priv->event_counter = 0;
843 dev_priv->event_wrap = 0;
844 dev_priv->bci_ptr = (volatile uint32_t *)
b5e89ed5 845 ((uint8_t *) dev_priv->mmio->handle + SAVAGE_BCI_OFFSET);
282a1674
DA
846 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
847 dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S3D;
848 } else {
849 dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S4;
850 }
851 if (dev_priv->status != NULL) {
852 dev_priv->status_ptr =
b5e89ed5 853 (volatile uint32_t *)dev_priv->status->handle;
282a1674
DA
854 dev_priv->wait_fifo = savage_bci_wait_fifo_shadow;
855 dev_priv->wait_evnt = savage_bci_wait_event_shadow;
856 dev_priv->status_ptr[1023] = dev_priv->event_counter;
857 } else {
858 dev_priv->status_ptr = NULL;
859 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
860 dev_priv->wait_fifo = savage_bci_wait_fifo_s3d;
861 } else {
862 dev_priv->wait_fifo = savage_bci_wait_fifo_s4;
863 }
864 dev_priv->wait_evnt = savage_bci_wait_event_reg;
865 }
866
867 /* cliprect functions */
868 if (S3_SAVAGE3D_SERIES(dev_priv->chipset))
869 dev_priv->emit_clip_rect = savage_emit_clip_rect_s3d;
870 else
871 dev_priv->emit_clip_rect = savage_emit_clip_rect_s4;
872
873 if (savage_freelist_init(dev) < 0) {
874 DRM_ERROR("could not initialize freelist\n");
875 savage_do_cleanup_bci(dev);
20caafa6 876 return -ENOMEM;
282a1674
DA
877 }
878
b5e89ed5 879 if (savage_dma_init(dev_priv) < 0) {
282a1674
DA
880 DRM_ERROR("could not initialize command DMA\n");
881 savage_do_cleanup_bci(dev);
20caafa6 882 return -ENOMEM;
282a1674
DA
883 }
884
885 return 0;
886}
887
eddca551 888static int savage_do_cleanup_bci(struct drm_device * dev)
282a1674
DA
889{
890 drm_savage_private_t *dev_priv = dev->dev_private;
891
892 if (dev_priv->cmd_dma == &dev_priv->fake_dma) {
9a298b2a 893 kfree(dev_priv->fake_dma.handle);
282a1674
DA
894 } else if (dev_priv->cmd_dma && dev_priv->cmd_dma->handle &&
895 dev_priv->cmd_dma->type == _DRM_AGP &&
896 dev_priv->dma_type == SAVAGE_DMA_AGP)
86c1fbd5 897 drm_legacy_ioremapfree(dev_priv->cmd_dma, dev);
282a1674
DA
898
899 if (dev_priv->dma_type == SAVAGE_DMA_AGP &&
900 dev->agp_buffer_map && dev->agp_buffer_map->handle) {
86c1fbd5 901 drm_legacy_ioremapfree(dev->agp_buffer_map, dev);
282a1674
DA
902 /* make sure the next instance (which may be running
903 * in PCI mode) doesn't try to use an old
904 * agp_buffer_map. */
905 dev->agp_buffer_map = NULL;
906 }
907
9a298b2a 908 kfree(dev_priv->dma_pages);
282a1674
DA
909
910 return 0;
911}
912
c153f45f 913static int savage_bci_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
282a1674 914{
c153f45f 915 drm_savage_init_t *init = data;
282a1674 916
6c340eac 917 LOCK_TEST_WITH_RETURN(dev, file_priv);
282a1674 918
c153f45f 919 switch (init->func) {
282a1674 920 case SAVAGE_INIT_BCI:
c153f45f 921 return savage_do_init_bci(dev, init);
282a1674
DA
922 case SAVAGE_CLEANUP_BCI:
923 return savage_do_cleanup_bci(dev);
924 }
925
20caafa6 926 return -EINVAL;
282a1674
DA
927}
928
c153f45f 929static int savage_bci_event_emit(struct drm_device *dev, void *data, struct drm_file *file_priv)
282a1674 930{
282a1674 931 drm_savage_private_t *dev_priv = dev->dev_private;
c153f45f 932 drm_savage_event_emit_t *event = data;
282a1674
DA
933
934 DRM_DEBUG("\n");
935
6c340eac 936 LOCK_TEST_WITH_RETURN(dev, file_priv);
282a1674 937
c153f45f
EA
938 event->count = savage_bci_emit_event(dev_priv, event->flags);
939 event->count |= dev_priv->event_wrap << 16;
282a1674 940
282a1674
DA
941 return 0;
942}
943
c153f45f 944static int savage_bci_event_wait(struct drm_device *dev, void *data, struct drm_file *file_priv)
282a1674 945{
282a1674 946 drm_savage_private_t *dev_priv = dev->dev_private;
c153f45f 947 drm_savage_event_wait_t *event = data;
282a1674
DA
948 unsigned int event_e, hw_e;
949 unsigned int event_w, hw_w;
950
951 DRM_DEBUG("\n");
952
282a1674
DA
953 UPDATE_EVENT_COUNTER();
954 if (dev_priv->status_ptr)
955 hw_e = dev_priv->status_ptr[1] & 0xffff;
956 else
957 hw_e = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
958 hw_w = dev_priv->event_wrap;
959 if (hw_e > dev_priv->event_counter)
b5e89ed5 960 hw_w--; /* hardware hasn't passed the last wrap yet */
282a1674 961
c153f45f
EA
962 event_e = event->count & 0xffff;
963 event_w = event->count >> 16;
282a1674
DA
964
965 /* Don't need to wait if
966 * - event counter wrapped since the event was emitted or
967 * - the hardware has advanced up to or over the event to wait for.
968 */
b5e89ed5 969 if (event_w < hw_w || (event_w == hw_w && event_e <= hw_e))
282a1674
DA
970 return 0;
971 else
972 return dev_priv->wait_evnt(dev_priv, event_e);
973}
974
975/*
976 * DMA buffer management
977 */
978
6c340eac
EA
979static int savage_bci_get_buffers(struct drm_device *dev,
980 struct drm_file *file_priv,
981 struct drm_dma *d)
282a1674 982{
056219e2 983 struct drm_buf *buf;
282a1674
DA
984 int i;
985
986 for (i = d->granted_count; i < d->request_count; i++) {
987 buf = savage_freelist_get(dev);
988 if (!buf)
20caafa6 989 return -EAGAIN;
282a1674 990
6c340eac 991 buf->file_priv = file_priv;
282a1674 992
1d6ac185 993 if (copy_to_user(&d->request_indices[i],
282a1674 994 &buf->idx, sizeof(buf->idx)))
20caafa6 995 return -EFAULT;
1d6ac185 996 if (copy_to_user(&d->request_sizes[i],
282a1674 997 &buf->total, sizeof(buf->total)))
20caafa6 998 return -EFAULT;
282a1674
DA
999
1000 d->granted_count++;
1001 }
1002 return 0;
1003}
1004
c153f45f 1005int savage_bci_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
282a1674 1006{
cdd55a29 1007 struct drm_device_dma *dma = dev->dma;
c153f45f 1008 struct drm_dma *d = data;
282a1674
DA
1009 int ret = 0;
1010
6c340eac 1011 LOCK_TEST_WITH_RETURN(dev, file_priv);
282a1674 1012
282a1674
DA
1013 /* Please don't send us buffers.
1014 */
c153f45f 1015 if (d->send_count != 0) {
282a1674 1016 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
c153f45f 1017 DRM_CURRENTPID, d->send_count);
20caafa6 1018 return -EINVAL;
282a1674
DA
1019 }
1020
1021 /* We'll send you buffers.
1022 */
c153f45f 1023 if (d->request_count < 0 || d->request_count > dma->buf_count) {
282a1674 1024 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
c153f45f 1025 DRM_CURRENTPID, d->request_count, dma->buf_count);
20caafa6 1026 return -EINVAL;
282a1674
DA
1027 }
1028
c153f45f 1029 d->granted_count = 0;
282a1674 1030
c153f45f
EA
1031 if (d->request_count) {
1032 ret = savage_bci_get_buffers(dev, file_priv, d);
282a1674
DA
1033 }
1034
282a1674
DA
1035 return ret;
1036}
1037
6c340eac 1038void savage_reclaim_buffers(struct drm_device *dev, struct drm_file *file_priv)
b5e89ed5 1039{
cdd55a29 1040 struct drm_device_dma *dma = dev->dma;
282a1674 1041 drm_savage_private_t *dev_priv = dev->dev_private;
e2b3c5b6 1042 int release_idlelock = 0;
282a1674
DA
1043 int i;
1044
1045 if (!dma)
1046 return;
1047 if (!dev_priv)
1048 return;
1049 if (!dma->buflist)
1050 return;
1051
e2b3c5b6 1052 if (file_priv->master && file_priv->master->lock.hw_lock) {
bb6d822e 1053 drm_legacy_idlelock_take(&file_priv->master->lock);
e2b3c5b6
DV
1054 release_idlelock = 1;
1055 }
282a1674
DA
1056
1057 for (i = 0; i < dma->buf_count; i++) {
056219e2 1058 struct drm_buf *buf = dma->buflist[i];
282a1674
DA
1059 drm_savage_buf_priv_t *buf_priv = buf->dev_private;
1060
6c340eac 1061 if (buf->file_priv == file_priv && buf_priv &&
282a1674
DA
1062 buf_priv->next == NULL && buf_priv->prev == NULL) {
1063 uint16_t event;
1064 DRM_DEBUG("reclaimed from client\n");
1065 event = savage_bci_emit_event(dev_priv, SAVAGE_WAIT_3D);
1066 SET_AGE(&buf_priv->age, event, dev_priv->event_wrap);
1067 savage_freelist_put(dev, buf);
1068 }
1069 }
1070
e2b3c5b6 1071 if (release_idlelock)
bb6d822e 1072 drm_legacy_idlelock_release(&file_priv->master->lock);
282a1674
DA
1073}
1074
baa70943 1075const struct drm_ioctl_desc savage_ioctls[] = {
1b2f1489
DA
1076 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_INIT, savage_bci_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1077 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_CMDBUF, savage_bci_cmdbuf, DRM_AUTH),
1078 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_EVENT_EMIT, savage_bci_event_emit, DRM_AUTH),
1079 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_EVENT_WAIT, savage_bci_event_wait, DRM_AUTH),
282a1674
DA
1080};
1081
f95aeb17 1082int savage_max_ioctl = ARRAY_SIZE(savage_ioctls);