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9c92ab61 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
2048e328 MY |
2 | /* |
3 | * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd | |
4 | * Author:Mark Yao <mark.yao@rock-chips.com> | |
2048e328 MY |
5 | */ |
6 | ||
7 | #include <drm/drm.h> | |
8 | #include <drm/drmP.h> | |
63ebb9fa | 9 | #include <drm/drm_atomic.h> |
15609559 | 10 | #include <drm/drm_atomic_uapi.h> |
2048e328 | 11 | #include <drm/drm_crtc.h> |
47a7eb45 | 12 | #include <drm/drm_flip_work.h> |
63d5e06a | 13 | #include <drm/drm_gem_framebuffer_helper.h> |
2048e328 | 14 | #include <drm/drm_plane_helper.h> |
fcd70cd3 | 15 | #include <drm/drm_probe_helper.h> |
6cca3869 | 16 | #ifdef CONFIG_DRM_ANALOGIX_DP |
3190e58d | 17 | #include <drm/bridge/analogix_dp.h> |
6cca3869 | 18 | #endif |
2048e328 MY |
19 | |
20 | #include <linux/kernel.h> | |
00fe6148 | 21 | #include <linux/module.h> |
2048e328 MY |
22 | #include <linux/platform_device.h> |
23 | #include <linux/clk.h> | |
7caecdbe | 24 | #include <linux/iopoll.h> |
2048e328 MY |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
27 | #include <linux/pm_runtime.h> | |
28 | #include <linux/component.h> | |
29adeb4f | 29 | #include <linux/overflow.h> |
2048e328 MY |
30 | |
31 | #include <linux/reset.h> | |
32 | #include <linux/delay.h> | |
33 | ||
34 | #include "rockchip_drm_drv.h" | |
35 | #include "rockchip_drm_gem.h" | |
36 | #include "rockchip_drm_fb.h" | |
5182c1a5 | 37 | #include "rockchip_drm_psr.h" |
2048e328 | 38 | #include "rockchip_drm_vop.h" |
1f0f0151 | 39 | #include "rockchip_rgb.h" |
2048e328 | 40 | |
2996fb75 | 41 | #define VOP_WIN_SET(vop, win, name, v) \ |
9a61c54b | 42 | vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) |
2996fb75 | 43 | #define VOP_SCL_SET(vop, win, name, v) \ |
9a61c54b | 44 | vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) |
2996fb75 | 45 | #define VOP_SCL_SET_EXT(vop, win, name, v) \ |
9a61c54b M |
46 | vop_reg_set(vop, &win->phy->scl->ext->name, \ |
47 | win->base, ~0, v, #name) | |
ac6560df | 48 | |
2996fb75 | 49 | #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \ |
1c21aa8f DC |
50 | do { \ |
51 | if (win_yuv2yuv && win_yuv2yuv->name.mask) \ | |
52 | vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \ | |
53 | } while (0) | |
54 | ||
2996fb75 | 55 | #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \ |
1c21aa8f DC |
56 | do { \ |
57 | if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \ | |
58 | vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \ | |
59 | } while (0) | |
60 | ||
ac6560df | 61 | #define VOP_INTR_SET_MASK(vop, name, mask, v) \ |
9a61c54b M |
62 | vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) |
63 | ||
64 | #define VOP_REG_SET(vop, group, name, v) \ | |
65 | vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) | |
ac6560df | 66 | |
dbb3d944 MY |
67 | #define VOP_INTR_SET_TYPE(vop, name, type, v) \ |
68 | do { \ | |
c7647f86 | 69 | int i, reg = 0, mask = 0; \ |
dbb3d944 | 70 | for (i = 0; i < vop->data->intr->nintrs; i++) { \ |
c7647f86 | 71 | if (vop->data->intr->intrs[i] & type) { \ |
dbb3d944 | 72 | reg |= (v) << i; \ |
c7647f86 JK |
73 | mask |= 1 << i; \ |
74 | } \ | |
dbb3d944 | 75 | } \ |
ac6560df | 76 | VOP_INTR_SET_MASK(vop, name, mask, reg); \ |
dbb3d944 MY |
77 | } while (0) |
78 | #define VOP_INTR_GET_TYPE(vop, name, type) \ | |
79 | vop_get_intr_type(vop, &vop->data->intr->name, type) | |
80 | ||
2996fb75 EG |
81 | #define VOP_WIN_GET(vop, win, name) \ |
82 | vop_read_reg(vop, win->offset, win->phy->name) | |
2048e328 | 83 | |
677e8bbc DC |
84 | #define VOP_WIN_HAS_REG(win, name) \ |
85 | (!!(win->phy->name.mask)) | |
86 | ||
2048e328 MY |
87 | #define VOP_WIN_GET_YRGBADDR(vop, win) \ |
88 | vop_readl(vop, win->base + win->phy->yrgb_mst.offset) | |
89 | ||
58badaa7 KK |
90 | #define VOP_WIN_TO_INDEX(vop_win) \ |
91 | ((vop_win) - (vop_win)->vop->win) | |
92 | ||
2048e328 MY |
93 | #define to_vop(x) container_of(x, struct vop, crtc) |
94 | #define to_vop_win(x) container_of(x, struct vop_win, base) | |
95 | ||
1c21aa8f DC |
96 | /* |
97 | * The coefficients of the following matrix are all fixed points. | |
98 | * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets. | |
99 | * They are all represented in two's complement. | |
100 | */ | |
101 | static const uint32_t bt601_yuv2rgb[] = { | |
102 | 0x4A8, 0x0, 0x662, | |
103 | 0x4A8, 0x1E6F, 0x1CBF, | |
104 | 0x4A8, 0x812, 0x0, | |
105 | 0x321168, 0x0877CF, 0x2EB127 | |
106 | }; | |
107 | ||
47a7eb45 TF |
108 | enum vop_pending { |
109 | VOP_PENDING_FB_UNREF, | |
110 | }; | |
111 | ||
2048e328 MY |
112 | struct vop_win { |
113 | struct drm_plane base; | |
114 | const struct vop_win_data *data; | |
1c21aa8f | 115 | const struct vop_win_yuv2yuv_data *yuv2yuv_data; |
2048e328 | 116 | struct vop *vop; |
2048e328 MY |
117 | }; |
118 | ||
1f0f0151 | 119 | struct rockchip_rgb; |
2048e328 MY |
120 | struct vop { |
121 | struct drm_crtc crtc; | |
122 | struct device *dev; | |
123 | struct drm_device *drm_dev; | |
31e980c5 | 124 | bool is_enabled; |
2048e328 | 125 | |
1067219b | 126 | struct completion dsp_hold_completion; |
4f9d39a7 DV |
127 | |
128 | /* protected by dev->event_lock */ | |
63ebb9fa | 129 | struct drm_pending_vblank_event *event; |
2048e328 | 130 | |
47a7eb45 TF |
131 | struct drm_flip_work fb_unref_work; |
132 | unsigned long pending; | |
133 | ||
69c34e41 YY |
134 | struct completion line_flag_completion; |
135 | ||
2048e328 MY |
136 | const struct vop_data *data; |
137 | ||
138 | uint32_t *regsbak; | |
139 | void __iomem *regs; | |
140 | ||
141 | /* physical map length of vop register */ | |
142 | uint32_t len; | |
143 | ||
144 | /* one time only one process allowed to config the register */ | |
145 | spinlock_t reg_lock; | |
146 | /* lock vop irq reg */ | |
147 | spinlock_t irq_lock; | |
e334d48b | 148 | /* protects crtc enable/disable */ |
149 | struct mutex vop_lock; | |
2048e328 MY |
150 | |
151 | unsigned int irq; | |
152 | ||
153 | /* vop AHP clk */ | |
154 | struct clk *hclk; | |
155 | /* vop dclk */ | |
156 | struct clk *dclk; | |
157 | /* vop share memory frequency */ | |
158 | struct clk *aclk; | |
159 | ||
160 | /* vop dclk reset */ | |
161 | struct reset_control *dclk_rst; | |
162 | ||
1f0f0151 SH |
163 | /* optional internal rgb encoder */ |
164 | struct rockchip_rgb *rgb; | |
165 | ||
2048e328 MY |
166 | struct vop_win win[]; |
167 | }; | |
168 | ||
2048e328 MY |
169 | static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) |
170 | { | |
171 | writel(v, vop->regs + offset); | |
172 | vop->regsbak[offset >> 2] = v; | |
173 | } | |
174 | ||
175 | static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) | |
176 | { | |
177 | return readl(vop->regs + offset); | |
178 | } | |
179 | ||
180 | static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, | |
181 | const struct vop_reg *reg) | |
182 | { | |
183 | return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; | |
184 | } | |
185 | ||
9a61c54b M |
186 | static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, |
187 | uint32_t _offset, uint32_t _mask, uint32_t v, | |
188 | const char *reg_name) | |
2048e328 | 189 | { |
9a61c54b M |
190 | int offset, mask, shift; |
191 | ||
192 | if (!reg || !reg->mask) { | |
d8dd6804 | 193 | DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); |
d49463ec | 194 | return; |
9a61c54b M |
195 | } |
196 | ||
197 | offset = reg->offset + _offset; | |
198 | mask = reg->mask & _mask; | |
199 | shift = reg->shift; | |
2048e328 | 200 | |
9a61c54b | 201 | if (reg->write_mask) { |
d49463ec MY |
202 | v = ((v << shift) & 0xffff) | (mask << (shift + 16)); |
203 | } else { | |
2048e328 MY |
204 | uint32_t cached_val = vop->regsbak[offset >> 2]; |
205 | ||
d49463ec MY |
206 | v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); |
207 | vop->regsbak[offset >> 2] = v; | |
2048e328 | 208 | } |
d49463ec | 209 | |
9a61c54b | 210 | if (reg->relaxed) |
d49463ec MY |
211 | writel_relaxed(v, vop->regs + offset); |
212 | else | |
213 | writel(v, vop->regs + offset); | |
2048e328 MY |
214 | } |
215 | ||
dbb3d944 MY |
216 | static inline uint32_t vop_get_intr_type(struct vop *vop, |
217 | const struct vop_reg *reg, int type) | |
218 | { | |
219 | uint32_t i, ret = 0; | |
220 | uint32_t regs = vop_read_reg(vop, 0, reg); | |
221 | ||
222 | for (i = 0; i < vop->data->intr->nintrs; i++) { | |
223 | if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) | |
224 | ret |= vop->data->intr->intrs[i]; | |
225 | } | |
226 | ||
227 | return ret; | |
228 | } | |
229 | ||
0cf33fe3 MY |
230 | static inline void vop_cfg_done(struct vop *vop) |
231 | { | |
9a61c54b | 232 | VOP_REG_SET(vop, common, cfg_done, 1); |
0cf33fe3 MY |
233 | } |
234 | ||
85a359f2 TF |
235 | static bool has_rb_swapped(uint32_t format) |
236 | { | |
237 | switch (format) { | |
238 | case DRM_FORMAT_XBGR8888: | |
239 | case DRM_FORMAT_ABGR8888: | |
240 | case DRM_FORMAT_BGR888: | |
241 | case DRM_FORMAT_BGR565: | |
242 | return true; | |
243 | default: | |
244 | return false; | |
245 | } | |
246 | } | |
247 | ||
2048e328 MY |
248 | static enum vop_data_format vop_convert_format(uint32_t format) |
249 | { | |
250 | switch (format) { | |
251 | case DRM_FORMAT_XRGB8888: | |
252 | case DRM_FORMAT_ARGB8888: | |
85a359f2 TF |
253 | case DRM_FORMAT_XBGR8888: |
254 | case DRM_FORMAT_ABGR8888: | |
2048e328 MY |
255 | return VOP_FMT_ARGB8888; |
256 | case DRM_FORMAT_RGB888: | |
85a359f2 | 257 | case DRM_FORMAT_BGR888: |
2048e328 MY |
258 | return VOP_FMT_RGB888; |
259 | case DRM_FORMAT_RGB565: | |
85a359f2 | 260 | case DRM_FORMAT_BGR565: |
2048e328 MY |
261 | return VOP_FMT_RGB565; |
262 | case DRM_FORMAT_NV12: | |
263 | return VOP_FMT_YUV420SP; | |
264 | case DRM_FORMAT_NV16: | |
265 | return VOP_FMT_YUV422SP; | |
266 | case DRM_FORMAT_NV24: | |
267 | return VOP_FMT_YUV444SP; | |
268 | default: | |
ee4d7899 | 269 | DRM_ERROR("unsupported format[%08x]\n", format); |
2048e328 MY |
270 | return -EINVAL; |
271 | } | |
272 | } | |
273 | ||
4c156c21 MY |
274 | static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, |
275 | uint32_t dst, bool is_horizontal, | |
276 | int vsu_mode, int *vskiplines) | |
277 | { | |
278 | uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; | |
279 | ||
ce91d373 JC |
280 | if (vskiplines) |
281 | *vskiplines = 0; | |
282 | ||
4c156c21 MY |
283 | if (is_horizontal) { |
284 | if (mode == SCALE_UP) | |
285 | val = GET_SCL_FT_BIC(src, dst); | |
286 | else if (mode == SCALE_DOWN) | |
287 | val = GET_SCL_FT_BILI_DN(src, dst); | |
288 | } else { | |
289 | if (mode == SCALE_UP) { | |
290 | if (vsu_mode == SCALE_UP_BIL) | |
291 | val = GET_SCL_FT_BILI_UP(src, dst); | |
292 | else | |
293 | val = GET_SCL_FT_BIC(src, dst); | |
294 | } else if (mode == SCALE_DOWN) { | |
295 | if (vskiplines) { | |
296 | *vskiplines = scl_get_vskiplines(src, dst); | |
297 | val = scl_get_bili_dn_vskip(src, dst, | |
298 | *vskiplines); | |
299 | } else { | |
300 | val = GET_SCL_FT_BILI_DN(src, dst); | |
301 | } | |
302 | } | |
303 | } | |
304 | ||
305 | return val; | |
306 | } | |
307 | ||
308 | static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, | |
309 | uint32_t src_w, uint32_t src_h, uint32_t dst_w, | |
310 | uint32_t dst_h, uint32_t pixel_format) | |
311 | { | |
312 | uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; | |
313 | uint16_t cbcr_hor_scl_mode = SCALE_NONE; | |
314 | uint16_t cbcr_ver_scl_mode = SCALE_NONE; | |
315 | int hsub = drm_format_horz_chroma_subsampling(pixel_format); | |
316 | int vsub = drm_format_vert_chroma_subsampling(pixel_format); | |
d8bd23d9 AKH |
317 | const struct drm_format_info *info; |
318 | bool is_yuv = false; | |
4c156c21 MY |
319 | uint16_t cbcr_src_w = src_w / hsub; |
320 | uint16_t cbcr_src_h = src_h / vsub; | |
321 | uint16_t vsu_mode; | |
322 | uint16_t lb_mode; | |
323 | uint32_t val; | |
ce91d373 | 324 | int vskiplines; |
4c156c21 | 325 | |
d8bd23d9 AKH |
326 | info = drm_format_info(pixel_format); |
327 | ||
328 | if (info->is_yuv) | |
329 | is_yuv = true; | |
330 | ||
4c156c21 | 331 | if (dst_w > 3840) { |
ee4d7899 | 332 | DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); |
4c156c21 MY |
333 | return; |
334 | } | |
335 | ||
1194fffb MY |
336 | if (!win->phy->scl->ext) { |
337 | VOP_SCL_SET(vop, win, scale_yrgb_x, | |
338 | scl_cal_scale2(src_w, dst_w)); | |
339 | VOP_SCL_SET(vop, win, scale_yrgb_y, | |
340 | scl_cal_scale2(src_h, dst_h)); | |
341 | if (is_yuv) { | |
342 | VOP_SCL_SET(vop, win, scale_cbcr_x, | |
ee8662fc | 343 | scl_cal_scale2(cbcr_src_w, dst_w)); |
1194fffb | 344 | VOP_SCL_SET(vop, win, scale_cbcr_y, |
ee8662fc | 345 | scl_cal_scale2(cbcr_src_h, dst_h)); |
1194fffb MY |
346 | } |
347 | return; | |
348 | } | |
349 | ||
4c156c21 MY |
350 | yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); |
351 | yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); | |
352 | ||
353 | if (is_yuv) { | |
354 | cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); | |
355 | cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); | |
356 | if (cbcr_hor_scl_mode == SCALE_DOWN) | |
357 | lb_mode = scl_vop_cal_lb_mode(dst_w, true); | |
358 | else | |
359 | lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); | |
360 | } else { | |
361 | if (yrgb_hor_scl_mode == SCALE_DOWN) | |
362 | lb_mode = scl_vop_cal_lb_mode(dst_w, false); | |
363 | else | |
364 | lb_mode = scl_vop_cal_lb_mode(src_w, false); | |
365 | } | |
366 | ||
1194fffb | 367 | VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); |
4c156c21 MY |
368 | if (lb_mode == LB_RGB_3840X2) { |
369 | if (yrgb_ver_scl_mode != SCALE_NONE) { | |
ee4d7899 | 370 | DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); |
4c156c21 MY |
371 | return; |
372 | } | |
373 | if (cbcr_ver_scl_mode != SCALE_NONE) { | |
ee4d7899 | 374 | DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); |
4c156c21 MY |
375 | return; |
376 | } | |
377 | vsu_mode = SCALE_UP_BIL; | |
378 | } else if (lb_mode == LB_RGB_2560X4) { | |
379 | vsu_mode = SCALE_UP_BIL; | |
380 | } else { | |
381 | vsu_mode = SCALE_UP_BIC; | |
382 | } | |
383 | ||
384 | val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, | |
385 | true, 0, NULL); | |
386 | VOP_SCL_SET(vop, win, scale_yrgb_x, val); | |
387 | val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, | |
388 | false, vsu_mode, &vskiplines); | |
389 | VOP_SCL_SET(vop, win, scale_yrgb_y, val); | |
390 | ||
1194fffb MY |
391 | VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); |
392 | VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); | |
4c156c21 | 393 | |
1194fffb MY |
394 | VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); |
395 | VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); | |
396 | VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); | |
397 | VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); | |
398 | VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); | |
4c156c21 MY |
399 | if (is_yuv) { |
400 | val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, | |
401 | dst_w, true, 0, NULL); | |
402 | VOP_SCL_SET(vop, win, scale_cbcr_x, val); | |
403 | val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, | |
404 | dst_h, false, vsu_mode, &vskiplines); | |
405 | VOP_SCL_SET(vop, win, scale_cbcr_y, val); | |
406 | ||
1194fffb MY |
407 | VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); |
408 | VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); | |
409 | VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); | |
410 | VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); | |
411 | VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); | |
412 | VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); | |
413 | VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); | |
4c156c21 MY |
414 | } |
415 | } | |
416 | ||
1067219b MY |
417 | static void vop_dsp_hold_valid_irq_enable(struct vop *vop) |
418 | { | |
419 | unsigned long flags; | |
420 | ||
421 | if (WARN_ON(!vop->is_enabled)) | |
422 | return; | |
423 | ||
424 | spin_lock_irqsave(&vop->irq_lock, flags); | |
425 | ||
fa374107 | 426 | VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); |
dbb3d944 | 427 | VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); |
1067219b MY |
428 | |
429 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
430 | } | |
431 | ||
432 | static void vop_dsp_hold_valid_irq_disable(struct vop *vop) | |
433 | { | |
434 | unsigned long flags; | |
435 | ||
436 | if (WARN_ON(!vop->is_enabled)) | |
437 | return; | |
438 | ||
439 | spin_lock_irqsave(&vop->irq_lock, flags); | |
440 | ||
dbb3d944 | 441 | VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); |
1067219b MY |
442 | |
443 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
444 | } | |
445 | ||
69c34e41 YY |
446 | /* |
447 | * (1) each frame starts at the start of the Vsync pulse which is signaled by | |
448 | * the "FRAME_SYNC" interrupt. | |
449 | * (2) the active data region of each frame ends at dsp_vact_end | |
450 | * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, | |
451 | * to get "LINE_FLAG" interrupt at the end of the active on screen data. | |
452 | * | |
453 | * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end | |
454 | * Interrupts | |
455 | * LINE_FLAG -------------------------------+ | |
456 | * FRAME_SYNC ----+ | | |
457 | * | | | |
458 | * v v | |
459 | * | Vsync | Vbp | Vactive | Vfp | | |
460 | * ^ ^ ^ ^ | |
461 | * | | | | | |
462 | * | | | | | |
463 | * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END | |
464 | * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END | |
465 | * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END | |
466 | * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END | |
467 | */ | |
468 | static bool vop_line_flag_irq_is_enabled(struct vop *vop) | |
469 | { | |
470 | uint32_t line_flag_irq; | |
471 | unsigned long flags; | |
472 | ||
473 | spin_lock_irqsave(&vop->irq_lock, flags); | |
474 | ||
475 | line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); | |
476 | ||
477 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
478 | ||
479 | return !!line_flag_irq; | |
480 | } | |
481 | ||
459b086d | 482 | static void vop_line_flag_irq_enable(struct vop *vop) |
69c34e41 YY |
483 | { |
484 | unsigned long flags; | |
485 | ||
486 | if (WARN_ON(!vop->is_enabled)) | |
487 | return; | |
488 | ||
489 | spin_lock_irqsave(&vop->irq_lock, flags); | |
490 | ||
fa374107 | 491 | VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); |
69c34e41 YY |
492 | VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); |
493 | ||
494 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
495 | } | |
496 | ||
497 | static void vop_line_flag_irq_disable(struct vop *vop) | |
498 | { | |
499 | unsigned long flags; | |
500 | ||
501 | if (WARN_ON(!vop->is_enabled)) | |
502 | return; | |
503 | ||
504 | spin_lock_irqsave(&vop->irq_lock, flags); | |
505 | ||
506 | VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); | |
507 | ||
508 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
509 | } | |
510 | ||
e2810a71 HS |
511 | static int vop_core_clks_enable(struct vop *vop) |
512 | { | |
513 | int ret; | |
514 | ||
515 | ret = clk_enable(vop->hclk); | |
516 | if (ret < 0) | |
517 | return ret; | |
518 | ||
519 | ret = clk_enable(vop->aclk); | |
520 | if (ret < 0) | |
521 | goto err_disable_hclk; | |
522 | ||
523 | return 0; | |
524 | ||
525 | err_disable_hclk: | |
526 | clk_disable(vop->hclk); | |
527 | return ret; | |
528 | } | |
529 | ||
530 | static void vop_core_clks_disable(struct vop *vop) | |
531 | { | |
532 | clk_disable(vop->aclk); | |
533 | clk_disable(vop->hclk); | |
534 | } | |
535 | ||
e9abc611 JK |
536 | static void vop_win_disable(struct vop *vop, const struct vop_win_data *win) |
537 | { | |
538 | if (win->phy->scl && win->phy->scl->ext) { | |
539 | VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE); | |
540 | VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE); | |
541 | VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE); | |
542 | VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE); | |
543 | } | |
544 | ||
545 | VOP_WIN_SET(vop, win, enable, 0); | |
546 | } | |
547 | ||
39a9ad8f | 548 | static int vop_enable(struct drm_crtc *crtc) |
2048e328 MY |
549 | { |
550 | struct vop *vop = to_vop(crtc); | |
64d77564 | 551 | int ret, i; |
2048e328 | 552 | |
5d82d1a7 MY |
553 | ret = pm_runtime_get_sync(vop->dev); |
554 | if (ret < 0) { | |
d8dd6804 | 555 | DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); |
5e570373 | 556 | return ret; |
5d82d1a7 MY |
557 | } |
558 | ||
e2810a71 | 559 | ret = vop_core_clks_enable(vop); |
39a9ad8f SP |
560 | if (WARN_ON(ret < 0)) |
561 | goto err_put_pm_runtime; | |
2048e328 MY |
562 | |
563 | ret = clk_enable(vop->dclk); | |
39a9ad8f | 564 | if (WARN_ON(ret < 0)) |
e2810a71 | 565 | goto err_disable_core; |
2048e328 MY |
566 | |
567 | /* | |
568 | * Slave iommu shares power, irq and clock with vop. It was associated | |
569 | * automatically with this master device via common driver code. | |
570 | * Now that we have enabled the clock we attach it to the shared drm | |
571 | * mapping. | |
572 | */ | |
573 | ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); | |
574 | if (ret) { | |
d8dd6804 HM |
575 | DRM_DEV_ERROR(vop->dev, |
576 | "failed to attach dma mapping, %d\n", ret); | |
e2810a71 | 577 | goto err_disable_dclk; |
2048e328 MY |
578 | } |
579 | ||
76f1416e MZ |
580 | spin_lock(&vop->reg_lock); |
581 | for (i = 0; i < vop->len; i += 4) | |
582 | writel_relaxed(vop->regsbak[i / 4], vop->regs + i); | |
583 | ||
64d77564 M |
584 | /* |
585 | * We need to make sure that all windows are disabled before we | |
586 | * enable the crtc. Otherwise we might try to scan from a destroyed | |
587 | * buffer later. | |
588 | */ | |
589 | for (i = 0; i < vop->data->win_size; i++) { | |
590 | struct vop_win *vop_win = &vop->win[i]; | |
591 | const struct vop_win_data *win = vop_win->data; | |
592 | ||
e9abc611 | 593 | vop_win_disable(vop, win); |
64d77564 | 594 | } |
76f1416e | 595 | spin_unlock(&vop->reg_lock); |
64d77564 | 596 | |
17a794d7 CZ |
597 | vop_cfg_done(vop); |
598 | ||
52ab7891 MY |
599 | /* |
600 | * At here, vop clock & iommu is enable, R/W vop regs would be safe. | |
601 | */ | |
602 | vop->is_enabled = true; | |
603 | ||
2048e328 MY |
604 | spin_lock(&vop->reg_lock); |
605 | ||
9a61c54b | 606 | VOP_REG_SET(vop, common, standby, 1); |
2048e328 MY |
607 | |
608 | spin_unlock(&vop->reg_lock); | |
609 | ||
b5f7b755 | 610 | drm_crtc_vblank_on(crtc); |
2048e328 | 611 | |
39a9ad8f | 612 | return 0; |
2048e328 | 613 | |
2048e328 MY |
614 | err_disable_dclk: |
615 | clk_disable(vop->dclk); | |
e2810a71 HS |
616 | err_disable_core: |
617 | vop_core_clks_disable(vop); | |
39a9ad8f SP |
618 | err_put_pm_runtime: |
619 | pm_runtime_put_sync(vop->dev); | |
620 | return ret; | |
2048e328 MY |
621 | } |
622 | ||
64581714 LP |
623 | static void vop_crtc_atomic_disable(struct drm_crtc *crtc, |
624 | struct drm_crtc_state *old_state) | |
2048e328 MY |
625 | { |
626 | struct vop *vop = to_vop(crtc); | |
627 | ||
893b6cad DV |
628 | WARN_ON(vop->event); |
629 | ||
e334d48b | 630 | mutex_lock(&vop->vop_lock); |
b5f7b755 | 631 | drm_crtc_vblank_off(crtc); |
2048e328 | 632 | |
2048e328 | 633 | /* |
1067219b MY |
634 | * Vop standby will take effect at end of current frame, |
635 | * if dsp hold valid irq happen, it means standby complete. | |
636 | * | |
637 | * we must wait standby complete when we want to disable aclk, | |
638 | * if not, memory bus maybe dead. | |
2048e328 | 639 | */ |
1067219b MY |
640 | reinit_completion(&vop->dsp_hold_completion); |
641 | vop_dsp_hold_valid_irq_enable(vop); | |
642 | ||
2048e328 MY |
643 | spin_lock(&vop->reg_lock); |
644 | ||
9a61c54b | 645 | VOP_REG_SET(vop, common, standby, 1); |
2048e328 MY |
646 | |
647 | spin_unlock(&vop->reg_lock); | |
52ab7891 | 648 | |
1067219b MY |
649 | wait_for_completion(&vop->dsp_hold_completion); |
650 | ||
651 | vop_dsp_hold_valid_irq_disable(vop); | |
652 | ||
52ab7891 | 653 | vop->is_enabled = false; |
1067219b | 654 | |
2048e328 | 655 | /* |
1067219b | 656 | * vop standby complete, so iommu detach is safe. |
2048e328 | 657 | */ |
2048e328 MY |
658 | rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); |
659 | ||
1067219b | 660 | clk_disable(vop->dclk); |
e2810a71 | 661 | vop_core_clks_disable(vop); |
5d82d1a7 | 662 | pm_runtime_put(vop->dev); |
e334d48b | 663 | mutex_unlock(&vop->vop_lock); |
893b6cad DV |
664 | |
665 | if (crtc->state->event && !crtc->state->active) { | |
666 | spin_lock_irq(&crtc->dev->event_lock); | |
667 | drm_crtc_send_vblank_event(crtc, crtc->state->event); | |
668 | spin_unlock_irq(&crtc->dev->event_lock); | |
669 | ||
670 | crtc->state->event = NULL; | |
671 | } | |
2048e328 MY |
672 | } |
673 | ||
63ebb9fa | 674 | static void vop_plane_destroy(struct drm_plane *plane) |
2048e328 | 675 | { |
63ebb9fa | 676 | drm_plane_cleanup(plane); |
2048e328 MY |
677 | } |
678 | ||
63ebb9fa MY |
679 | static int vop_plane_atomic_check(struct drm_plane *plane, |
680 | struct drm_plane_state *state) | |
2048e328 | 681 | { |
63ebb9fa | 682 | struct drm_crtc *crtc = state->crtc; |
92915da6 | 683 | struct drm_crtc_state *crtc_state; |
63ebb9fa | 684 | struct drm_framebuffer *fb = state->fb; |
2048e328 MY |
685 | struct vop_win *vop_win = to_vop_win(plane); |
686 | const struct vop_win_data *win = vop_win->data; | |
2048e328 | 687 | int ret; |
4c156c21 MY |
688 | int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : |
689 | DRM_PLANE_HELPER_NO_SCALING; | |
690 | int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : | |
691 | DRM_PLANE_HELPER_NO_SCALING; | |
2048e328 | 692 | |
63ebb9fa | 693 | if (!crtc || !fb) |
d47a7246 | 694 | return 0; |
92915da6 JK |
695 | |
696 | crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); | |
697 | if (WARN_ON(!crtc_state)) | |
698 | return -EINVAL; | |
699 | ||
81af63a4 | 700 | ret = drm_atomic_helper_check_plane_state(state, crtc_state, |
a01cb8ba VS |
701 | min_scale, max_scale, |
702 | true, true); | |
2048e328 MY |
703 | if (ret) |
704 | return ret; | |
705 | ||
f9b96be0 | 706 | if (!state->visible) |
d47a7246 | 707 | return 0; |
2048e328 | 708 | |
438b74a5 | 709 | ret = vop_convert_format(fb->format->format); |
d47a7246 TF |
710 | if (ret < 0) |
711 | return ret; | |
84c7f8ca | 712 | |
63ebb9fa MY |
713 | /* |
714 | * Src.x1 can be odd when do clip, but yuv plane start point | |
715 | * need align with 2 pixel. | |
716 | */ | |
d8bd23d9 | 717 | if (fb->format->is_yuv && ((state->src.x1 >> 16) % 2)) { |
d415fb87 | 718 | DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n"); |
2048e328 | 719 | return -EINVAL; |
d415fb87 | 720 | } |
2048e328 | 721 | |
677e8bbc DC |
722 | if (fb->format->is_yuv && state->rotation & DRM_MODE_REFLECT_Y) { |
723 | DRM_ERROR("Invalid Source: Yuv format does not support this rotation\n"); | |
724 | return -EINVAL; | |
725 | } | |
726 | ||
63ebb9fa MY |
727 | return 0; |
728 | } | |
2048e328 | 729 | |
63ebb9fa MY |
730 | static void vop_plane_atomic_disable(struct drm_plane *plane, |
731 | struct drm_plane_state *old_state) | |
732 | { | |
63ebb9fa MY |
733 | struct vop_win *vop_win = to_vop_win(plane); |
734 | const struct vop_win_data *win = vop_win->data; | |
735 | struct vop *vop = to_vop(old_state->crtc); | |
2048e328 | 736 | |
63ebb9fa MY |
737 | if (!old_state->crtc) |
738 | return; | |
2048e328 | 739 | |
63ebb9fa | 740 | spin_lock(&vop->reg_lock); |
2048e328 | 741 | |
e9abc611 | 742 | vop_win_disable(vop, win); |
84c7f8ca | 743 | |
63ebb9fa | 744 | spin_unlock(&vop->reg_lock); |
63ebb9fa | 745 | } |
84c7f8ca | 746 | |
63ebb9fa MY |
747 | static void vop_plane_atomic_update(struct drm_plane *plane, |
748 | struct drm_plane_state *old_state) | |
749 | { | |
750 | struct drm_plane_state *state = plane->state; | |
751 | struct drm_crtc *crtc = state->crtc; | |
752 | struct vop_win *vop_win = to_vop_win(plane); | |
63ebb9fa | 753 | const struct vop_win_data *win = vop_win->data; |
1c21aa8f | 754 | const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data; |
63ebb9fa MY |
755 | struct vop *vop = to_vop(state->crtc); |
756 | struct drm_framebuffer *fb = state->fb; | |
757 | unsigned int actual_w, actual_h; | |
758 | unsigned int dsp_stx, dsp_sty; | |
759 | uint32_t act_info, dsp_info, dsp_st; | |
ac92028e VS |
760 | struct drm_rect *src = &state->src; |
761 | struct drm_rect *dest = &state->dst; | |
63ebb9fa MY |
762 | struct drm_gem_object *obj, *uv_obj; |
763 | struct rockchip_gem_object *rk_obj, *rk_uv_obj; | |
764 | unsigned long offset; | |
765 | dma_addr_t dma_addr; | |
766 | uint32_t val; | |
767 | bool rb_swap; | |
58badaa7 | 768 | int win_index = VOP_WIN_TO_INDEX(vop_win); |
d47a7246 | 769 | int format; |
1c21aa8f DC |
770 | int is_yuv = fb->format->is_yuv; |
771 | int i; | |
84c7f8ca | 772 | |
2048e328 | 773 | /* |
63ebb9fa | 774 | * can't update plane when vop is disabled. |
2048e328 | 775 | */ |
4f9d39a7 | 776 | if (WARN_ON(!crtc)) |
63ebb9fa | 777 | return; |
2048e328 | 778 | |
63ebb9fa MY |
779 | if (WARN_ON(!vop->is_enabled)) |
780 | return; | |
2048e328 | 781 | |
d47a7246 | 782 | if (!state->visible) { |
63ebb9fa MY |
783 | vop_plane_atomic_disable(plane, old_state); |
784 | return; | |
2048e328 | 785 | } |
63ebb9fa | 786 | |
957428f9 | 787 | obj = fb->obj[0]; |
63ebb9fa MY |
788 | rk_obj = to_rockchip_obj(obj); |
789 | ||
790 | actual_w = drm_rect_width(src) >> 16; | |
791 | actual_h = drm_rect_height(src) >> 16; | |
792 | act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); | |
793 | ||
794 | dsp_info = (drm_rect_height(dest) - 1) << 16; | |
795 | dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; | |
796 | ||
797 | dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; | |
798 | dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; | |
799 | dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); | |
800 | ||
353c8598 | 801 | offset = (src->x1 >> 16) * fb->format->cpp[0]; |
63ebb9fa | 802 | offset += (src->y1 >> 16) * fb->pitches[0]; |
d47a7246 TF |
803 | dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; |
804 | ||
677e8bbc DC |
805 | /* |
806 | * For y-mirroring we need to move address | |
807 | * to the beginning of the last line. | |
808 | */ | |
809 | if (state->rotation & DRM_MODE_REFLECT_Y) | |
810 | dma_addr += (actual_h - 1) * fb->pitches[0]; | |
811 | ||
438b74a5 | 812 | format = vop_convert_format(fb->format->format); |
2048e328 MY |
813 | |
814 | spin_lock(&vop->reg_lock); | |
815 | ||
d47a7246 | 816 | VOP_WIN_SET(vop, win, format, format); |
da709a7b | 817 | VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); |
d47a7246 | 818 | VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); |
1c21aa8f | 819 | VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); |
677e8bbc DC |
820 | VOP_WIN_SET(vop, win, y_mir_en, |
821 | (state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0); | |
822 | VOP_WIN_SET(vop, win, x_mir_en, | |
823 | (state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0); | |
1c21aa8f DC |
824 | |
825 | if (is_yuv) { | |
438b74a5 VS |
826 | int hsub = drm_format_horz_chroma_subsampling(fb->format->format); |
827 | int vsub = drm_format_vert_chroma_subsampling(fb->format->format); | |
353c8598 | 828 | int bpp = fb->format->cpp[1]; |
63ebb9fa | 829 | |
957428f9 | 830 | uv_obj = fb->obj[1]; |
63ebb9fa MY |
831 | rk_uv_obj = to_rockchip_obj(uv_obj); |
832 | ||
833 | offset = (src->x1 >> 16) * bpp / hsub; | |
834 | offset += (src->y1 >> 16) * fb->pitches[1] / vsub; | |
835 | ||
836 | dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; | |
da709a7b | 837 | VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); |
63ebb9fa | 838 | VOP_WIN_SET(vop, win, uv_mst, dma_addr); |
1c21aa8f DC |
839 | |
840 | for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) { | |
841 | VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, | |
842 | win_yuv2yuv, | |
843 | y2r_coefficients[i], | |
844 | bt601_yuv2rgb[i]); | |
845 | } | |
84c7f8ca | 846 | } |
4c156c21 MY |
847 | |
848 | if (win->phy->scl) | |
849 | scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, | |
63ebb9fa | 850 | drm_rect_width(dest), drm_rect_height(dest), |
438b74a5 | 851 | fb->format->format); |
4c156c21 | 852 | |
63ebb9fa MY |
853 | VOP_WIN_SET(vop, win, act_info, act_info); |
854 | VOP_WIN_SET(vop, win, dsp_info, dsp_info); | |
855 | VOP_WIN_SET(vop, win, dsp_st, dsp_st); | |
4c156c21 | 856 | |
438b74a5 | 857 | rb_swap = has_rb_swapped(fb->format->format); |
85a359f2 | 858 | VOP_WIN_SET(vop, win, rb_swap, rb_swap); |
2048e328 | 859 | |
58badaa7 KK |
860 | /* |
861 | * Blending win0 with the background color doesn't seem to work | |
862 | * correctly. We only get the background color, no matter the contents | |
863 | * of the win0 framebuffer. However, blending pre-multiplied color | |
864 | * with the default opaque black default background color is a no-op, | |
865 | * so we can just disable blending to get the correct result. | |
866 | */ | |
867 | if (fb->format->has_alpha && win_index > 0) { | |
2048e328 MY |
868 | VOP_WIN_SET(vop, win, dst_alpha_ctl, |
869 | DST_FACTOR_M0(ALPHA_SRC_INVERSE)); | |
870 | val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | | |
871 | SRC_ALPHA_M0(ALPHA_STRAIGHT) | | |
872 | SRC_BLEND_M0(ALPHA_PER_PIX) | | |
873 | SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | | |
874 | SRC_FACTOR_M0(ALPHA_ONE); | |
875 | VOP_WIN_SET(vop, win, src_alpha_ctl, val); | |
876 | } else { | |
877 | VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); | |
878 | } | |
879 | ||
880 | VOP_WIN_SET(vop, win, enable, 1); | |
2048e328 | 881 | spin_unlock(&vop->reg_lock); |
2048e328 MY |
882 | } |
883 | ||
15609559 EBS |
884 | static int vop_plane_atomic_async_check(struct drm_plane *plane, |
885 | struct drm_plane_state *state) | |
886 | { | |
887 | struct vop_win *vop_win = to_vop_win(plane); | |
888 | const struct vop_win_data *win = vop_win->data; | |
889 | int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : | |
890 | DRM_PLANE_HELPER_NO_SCALING; | |
891 | int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : | |
892 | DRM_PLANE_HELPER_NO_SCALING; | |
893 | struct drm_crtc_state *crtc_state; | |
894 | ||
895 | if (plane != state->crtc->cursor) | |
896 | return -EINVAL; | |
897 | ||
898 | if (!plane->state) | |
899 | return -EINVAL; | |
900 | ||
901 | if (!plane->state->fb) | |
902 | return -EINVAL; | |
903 | ||
904 | if (state->state) | |
905 | crtc_state = drm_atomic_get_existing_crtc_state(state->state, | |
906 | state->crtc); | |
907 | else /* Special case for asynchronous cursor updates. */ | |
908 | crtc_state = plane->crtc->state; | |
909 | ||
910 | return drm_atomic_helper_check_plane_state(plane->state, crtc_state, | |
911 | min_scale, max_scale, | |
912 | true, true); | |
913 | } | |
914 | ||
915 | static void vop_plane_atomic_async_update(struct drm_plane *plane, | |
916 | struct drm_plane_state *new_state) | |
917 | { | |
918 | struct vop *vop = to_vop(plane->state->crtc); | |
919 | struct drm_plane_state *plane_state; | |
920 | ||
921 | plane_state = plane->funcs->atomic_duplicate_state(plane); | |
922 | plane_state->crtc_x = new_state->crtc_x; | |
923 | plane_state->crtc_y = new_state->crtc_y; | |
924 | plane_state->crtc_h = new_state->crtc_h; | |
925 | plane_state->crtc_w = new_state->crtc_w; | |
926 | plane_state->src_x = new_state->src_x; | |
927 | plane_state->src_y = new_state->src_y; | |
928 | plane_state->src_h = new_state->src_h; | |
929 | plane_state->src_w = new_state->src_w; | |
930 | ||
931 | if (plane_state->fb != new_state->fb) | |
932 | drm_atomic_set_fb_for_plane(plane_state, new_state->fb); | |
933 | ||
934 | swap(plane_state, plane->state); | |
935 | ||
936 | if (plane->state->fb && plane->state->fb != new_state->fb) { | |
937 | drm_framebuffer_get(plane->state->fb); | |
938 | WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0); | |
939 | drm_flip_work_queue(&vop->fb_unref_work, plane->state->fb); | |
940 | set_bit(VOP_PENDING_FB_UNREF, &vop->pending); | |
941 | } | |
942 | ||
943 | if (vop->is_enabled) { | |
944 | rockchip_drm_psr_inhibit_get_state(new_state->state); | |
945 | vop_plane_atomic_update(plane, plane->state); | |
946 | spin_lock(&vop->reg_lock); | |
947 | vop_cfg_done(vop); | |
948 | spin_unlock(&vop->reg_lock); | |
949 | rockchip_drm_psr_inhibit_put_state(new_state->state); | |
950 | } | |
951 | ||
952 | plane->funcs->atomic_destroy_state(plane, plane_state); | |
953 | } | |
954 | ||
63ebb9fa MY |
955 | static const struct drm_plane_helper_funcs plane_helper_funcs = { |
956 | .atomic_check = vop_plane_atomic_check, | |
957 | .atomic_update = vop_plane_atomic_update, | |
958 | .atomic_disable = vop_plane_atomic_disable, | |
15609559 EBS |
959 | .atomic_async_check = vop_plane_atomic_async_check, |
960 | .atomic_async_update = vop_plane_atomic_async_update, | |
63d5e06a | 961 | .prepare_fb = drm_gem_fb_prepare_fb, |
63ebb9fa | 962 | }; |
2048e328 | 963 | |
2048e328 | 964 | static const struct drm_plane_funcs vop_plane_funcs = { |
63ebb9fa MY |
965 | .update_plane = drm_atomic_helper_update_plane, |
966 | .disable_plane = drm_atomic_helper_disable_plane, | |
2048e328 | 967 | .destroy = vop_plane_destroy, |
d47a7246 TF |
968 | .reset = drm_atomic_helper_plane_reset, |
969 | .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, | |
970 | .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, | |
2048e328 MY |
971 | }; |
972 | ||
2048e328 MY |
973 | static int vop_crtc_enable_vblank(struct drm_crtc *crtc) |
974 | { | |
975 | struct vop *vop = to_vop(crtc); | |
976 | unsigned long flags; | |
977 | ||
63ebb9fa | 978 | if (WARN_ON(!vop->is_enabled)) |
2048e328 MY |
979 | return -EPERM; |
980 | ||
981 | spin_lock_irqsave(&vop->irq_lock, flags); | |
982 | ||
fa374107 | 983 | VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); |
dbb3d944 | 984 | VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); |
2048e328 MY |
985 | |
986 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
987 | ||
988 | return 0; | |
989 | } | |
990 | ||
991 | static void vop_crtc_disable_vblank(struct drm_crtc *crtc) | |
992 | { | |
993 | struct vop *vop = to_vop(crtc); | |
994 | unsigned long flags; | |
995 | ||
63ebb9fa | 996 | if (WARN_ON(!vop->is_enabled)) |
2048e328 | 997 | return; |
31e980c5 | 998 | |
2048e328 | 999 | spin_lock_irqsave(&vop->irq_lock, flags); |
dbb3d944 MY |
1000 | |
1001 | VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); | |
1002 | ||
2048e328 MY |
1003 | spin_unlock_irqrestore(&vop->irq_lock, flags); |
1004 | } | |
1005 | ||
2048e328 MY |
1006 | static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, |
1007 | const struct drm_display_mode *mode, | |
1008 | struct drm_display_mode *adjusted_mode) | |
1009 | { | |
b59b8de3 CZ |
1010 | struct vop *vop = to_vop(crtc); |
1011 | ||
b59b8de3 CZ |
1012 | adjusted_mode->clock = |
1013 | clk_round_rate(vop->dclk, mode->clock * 1000) / 1000; | |
1014 | ||
2048e328 MY |
1015 | return true; |
1016 | } | |
1017 | ||
0b20a0f8 LP |
1018 | static void vop_crtc_atomic_enable(struct drm_crtc *crtc, |
1019 | struct drm_crtc_state *old_state) | |
2048e328 MY |
1020 | { |
1021 | struct vop *vop = to_vop(crtc); | |
efd11cc8 | 1022 | const struct vop_data *vop_data = vop->data; |
4e257d9e | 1023 | struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); |
63ebb9fa | 1024 | struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; |
2048e328 MY |
1025 | u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; |
1026 | u16 hdisplay = adjusted_mode->hdisplay; | |
1027 | u16 htotal = adjusted_mode->htotal; | |
1028 | u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; | |
1029 | u16 hact_end = hact_st + hdisplay; | |
1030 | u16 vdisplay = adjusted_mode->vdisplay; | |
1031 | u16 vtotal = adjusted_mode->vtotal; | |
1032 | u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; | |
1033 | u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; | |
1034 | u16 vact_end = vact_st + vdisplay; | |
0a63bfd0 | 1035 | uint32_t pin_pol, val; |
a5c0fa44 | 1036 | int dither_bpc = s->output_bpc ? s->output_bpc : 10; |
39a9ad8f | 1037 | int ret; |
2048e328 | 1038 | |
e334d48b | 1039 | mutex_lock(&vop->vop_lock); |
1040 | ||
893b6cad DV |
1041 | WARN_ON(vop->event); |
1042 | ||
39a9ad8f SP |
1043 | ret = vop_enable(crtc); |
1044 | if (ret) { | |
e334d48b | 1045 | mutex_unlock(&vop->vop_lock); |
39a9ad8f SP |
1046 | DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); |
1047 | return; | |
1048 | } | |
1049 | ||
1a0f7ed3 | 1050 | pin_pol = BIT(DCLK_INVERT); |
d790ad03 JK |
1051 | pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? |
1052 | BIT(HSYNC_POSITIVE) : 0; | |
1053 | pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? | |
1054 | BIT(VSYNC_POSITIVE) : 0; | |
9a61c54b | 1055 | VOP_REG_SET(vop, output, pin_pol, pin_pol); |
cf6d100d | 1056 | VOP_REG_SET(vop, output, mipi_dual_channel_en, 0); |
0a63bfd0 | 1057 | |
4e257d9e MY |
1058 | switch (s->output_type) { |
1059 | case DRM_MODE_CONNECTOR_LVDS: | |
9a61c54b M |
1060 | VOP_REG_SET(vop, output, rgb_en, 1); |
1061 | VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); | |
4e257d9e MY |
1062 | break; |
1063 | case DRM_MODE_CONNECTOR_eDP: | |
9a61c54b M |
1064 | VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); |
1065 | VOP_REG_SET(vop, output, edp_en, 1); | |
4e257d9e MY |
1066 | break; |
1067 | case DRM_MODE_CONNECTOR_HDMIA: | |
9a61c54b M |
1068 | VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); |
1069 | VOP_REG_SET(vop, output, hdmi_en, 1); | |
4e257d9e MY |
1070 | break; |
1071 | case DRM_MODE_CONNECTOR_DSI: | |
9a61c54b M |
1072 | VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); |
1073 | VOP_REG_SET(vop, output, mipi_en, 1); | |
cf6d100d HS |
1074 | VOP_REG_SET(vop, output, mipi_dual_channel_en, |
1075 | !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL)); | |
4e257d9e | 1076 | break; |
1a0f7ed3 CZ |
1077 | case DRM_MODE_CONNECTOR_DisplayPort: |
1078 | pin_pol &= ~BIT(DCLK_INVERT); | |
9a61c54b M |
1079 | VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); |
1080 | VOP_REG_SET(vop, output, dp_en, 1); | |
1a0f7ed3 | 1081 | break; |
4e257d9e | 1082 | default: |
ee4d7899 SP |
1083 | DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", |
1084 | s->output_type); | |
4e257d9e | 1085 | } |
efd11cc8 M |
1086 | |
1087 | /* | |
1088 | * if vop is not support RGB10 output, need force RGB10 to RGB888. | |
1089 | */ | |
1090 | if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && | |
1091 | !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) | |
1092 | s->output_mode = ROCKCHIP_OUT_MODE_P888; | |
6bda8112 | 1093 | |
a5c0fa44 | 1094 | if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) |
6bda8112 MY |
1095 | VOP_REG_SET(vop, common, pre_dither_down, 1); |
1096 | else | |
1097 | VOP_REG_SET(vop, common, pre_dither_down, 0); | |
1098 | ||
a5c0fa44 UR |
1099 | if (dither_bpc == 6) { |
1100 | VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO); | |
1101 | VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666); | |
1102 | VOP_REG_SET(vop, common, dither_down_en, 1); | |
1103 | } else { | |
1104 | VOP_REG_SET(vop, common, dither_down_en, 0); | |
1105 | } | |
1106 | ||
9a61c54b | 1107 | VOP_REG_SET(vop, common, out_mode, s->output_mode); |
2048e328 | 1108 | |
9a61c54b | 1109 | VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); |
2048e328 MY |
1110 | val = hact_st << 16; |
1111 | val |= hact_end; | |
9a61c54b M |
1112 | VOP_REG_SET(vop, modeset, hact_st_end, val); |
1113 | VOP_REG_SET(vop, modeset, hpost_st_end, val); | |
2048e328 | 1114 | |
9a61c54b | 1115 | VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); |
2048e328 MY |
1116 | val = vact_st << 16; |
1117 | val |= vact_end; | |
9a61c54b M |
1118 | VOP_REG_SET(vop, modeset, vact_st_end, val); |
1119 | VOP_REG_SET(vop, modeset, vpost_st_end, val); | |
2048e328 | 1120 | |
9a61c54b | 1121 | VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); |
459b086d | 1122 | |
2048e328 | 1123 | clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); |
ce3887ed | 1124 | |
9a61c54b | 1125 | VOP_REG_SET(vop, common, standby, 0); |
e334d48b | 1126 | mutex_unlock(&vop->vop_lock); |
2048e328 MY |
1127 | } |
1128 | ||
7caecdbe TF |
1129 | static bool vop_fs_irq_is_pending(struct vop *vop) |
1130 | { | |
1131 | return VOP_INTR_GET_TYPE(vop, status, FS_INTR); | |
1132 | } | |
1133 | ||
1134 | static void vop_wait_for_irq_handler(struct vop *vop) | |
1135 | { | |
1136 | bool pending; | |
1137 | int ret; | |
1138 | ||
1139 | /* | |
1140 | * Spin until frame start interrupt status bit goes low, which means | |
1141 | * that interrupt handler was invoked and cleared it. The timeout of | |
1142 | * 10 msecs is really too long, but it is just a safety measure if | |
1143 | * something goes really wrong. The wait will only happen in the very | |
1144 | * unlikely case of a vblank happening exactly at the same time and | |
1145 | * shouldn't exceed microseconds range. | |
1146 | */ | |
1147 | ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, | |
1148 | !pending, 0, 10 * 1000); | |
1149 | if (ret) | |
1150 | DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); | |
1151 | ||
1152 | synchronize_irq(vop->irq); | |
1153 | } | |
1154 | ||
63ebb9fa MY |
1155 | static void vop_crtc_atomic_flush(struct drm_crtc *crtc, |
1156 | struct drm_crtc_state *old_crtc_state) | |
2048e328 | 1157 | { |
47a7eb45 | 1158 | struct drm_atomic_state *old_state = old_crtc_state->state; |
e741f2b1 | 1159 | struct drm_plane_state *old_plane_state, *new_plane_state; |
2048e328 | 1160 | struct vop *vop = to_vop(crtc); |
47a7eb45 TF |
1161 | struct drm_plane *plane; |
1162 | int i; | |
2048e328 | 1163 | |
63ebb9fa MY |
1164 | if (WARN_ON(!vop->is_enabled)) |
1165 | return; | |
2048e328 | 1166 | |
63ebb9fa | 1167 | spin_lock(&vop->reg_lock); |
2048e328 | 1168 | |
63ebb9fa | 1169 | vop_cfg_done(vop); |
2048e328 | 1170 | |
63ebb9fa | 1171 | spin_unlock(&vop->reg_lock); |
7caecdbe TF |
1172 | |
1173 | /* | |
1174 | * There is a (rather unlikely) possiblity that a vblank interrupt | |
1175 | * fired before we set the cfg_done bit. To avoid spuriously | |
1176 | * signalling flip completion we need to wait for it to finish. | |
1177 | */ | |
1178 | vop_wait_for_irq_handler(vop); | |
47a7eb45 | 1179 | |
41ee4367 TF |
1180 | spin_lock_irq(&crtc->dev->event_lock); |
1181 | if (crtc->state->event) { | |
1182 | WARN_ON(drm_crtc_vblank_get(crtc) != 0); | |
1183 | WARN_ON(vop->event); | |
1184 | ||
1185 | vop->event = crtc->state->event; | |
1186 | crtc->state->event = NULL; | |
1187 | } | |
1188 | spin_unlock_irq(&crtc->dev->event_lock); | |
1189 | ||
e741f2b1 ML |
1190 | for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, |
1191 | new_plane_state, i) { | |
47a7eb45 TF |
1192 | if (!old_plane_state->fb) |
1193 | continue; | |
1194 | ||
e741f2b1 | 1195 | if (old_plane_state->fb == new_plane_state->fb) |
47a7eb45 TF |
1196 | continue; |
1197 | ||
adedbf03 | 1198 | drm_framebuffer_get(old_plane_state->fb); |
2d078c2d | 1199 | WARN_ON(drm_crtc_vblank_get(crtc) != 0); |
47a7eb45 TF |
1200 | drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); |
1201 | set_bit(VOP_PENDING_FB_UNREF, &vop->pending); | |
47a7eb45 | 1202 | } |
2048e328 MY |
1203 | } |
1204 | ||
63ebb9fa | 1205 | static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { |
63ebb9fa MY |
1206 | .mode_fixup = vop_crtc_mode_fixup, |
1207 | .atomic_flush = vop_crtc_atomic_flush, | |
0b20a0f8 | 1208 | .atomic_enable = vop_crtc_atomic_enable, |
64581714 | 1209 | .atomic_disable = vop_crtc_atomic_disable, |
63ebb9fa MY |
1210 | }; |
1211 | ||
2048e328 MY |
1212 | static void vop_crtc_destroy(struct drm_crtc *crtc) |
1213 | { | |
1214 | drm_crtc_cleanup(crtc); | |
1215 | } | |
1216 | ||
dc0b408f JK |
1217 | static void vop_crtc_reset(struct drm_crtc *crtc) |
1218 | { | |
1219 | if (crtc->state) | |
1220 | __drm_atomic_helper_crtc_destroy_state(crtc->state); | |
1221 | kfree(crtc->state); | |
1222 | ||
1223 | crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL); | |
1224 | if (crtc->state) | |
1225 | crtc->state->crtc = crtc; | |
1226 | } | |
1227 | ||
4e257d9e MY |
1228 | static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) |
1229 | { | |
1230 | struct rockchip_crtc_state *rockchip_state; | |
1231 | ||
1232 | rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); | |
1233 | if (!rockchip_state) | |
1234 | return NULL; | |
1235 | ||
1236 | __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); | |
1237 | return &rockchip_state->base; | |
1238 | } | |
1239 | ||
1240 | static void vop_crtc_destroy_state(struct drm_crtc *crtc, | |
1241 | struct drm_crtc_state *state) | |
1242 | { | |
1243 | struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); | |
1244 | ||
ec2dc6a0 | 1245 | __drm_atomic_helper_crtc_destroy_state(&s->base); |
4e257d9e MY |
1246 | kfree(s); |
1247 | } | |
1248 | ||
6cca3869 | 1249 | #ifdef CONFIG_DRM_ANALOGIX_DP |
3190e58d TV |
1250 | static struct drm_connector *vop_get_edp_connector(struct vop *vop) |
1251 | { | |
3190e58d | 1252 | struct drm_connector *connector; |
2cbeb64f | 1253 | struct drm_connector_list_iter conn_iter; |
3190e58d | 1254 | |
2cbeb64f GP |
1255 | drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); |
1256 | drm_for_each_connector_iter(connector, &conn_iter) { | |
3190e58d | 1257 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
2cbeb64f | 1258 | drm_connector_list_iter_end(&conn_iter); |
3190e58d TV |
1259 | return connector; |
1260 | } | |
2cbeb64f GP |
1261 | } |
1262 | drm_connector_list_iter_end(&conn_iter); | |
3190e58d TV |
1263 | |
1264 | return NULL; | |
1265 | } | |
1266 | ||
1267 | static int vop_crtc_set_crc_source(struct drm_crtc *crtc, | |
c0811a7d | 1268 | const char *source_name) |
3190e58d TV |
1269 | { |
1270 | struct vop *vop = to_vop(crtc); | |
1271 | struct drm_connector *connector; | |
1272 | int ret; | |
1273 | ||
1274 | connector = vop_get_edp_connector(vop); | |
1275 | if (!connector) | |
1276 | return -EINVAL; | |
1277 | ||
3190e58d TV |
1278 | if (source_name && strcmp(source_name, "auto") == 0) |
1279 | ret = analogix_dp_start_crc(connector); | |
1280 | else if (!source_name) | |
1281 | ret = analogix_dp_stop_crc(connector); | |
1282 | else | |
1283 | ret = -EINVAL; | |
1284 | ||
1285 | return ret; | |
1286 | } | |
b8d913c0 MK |
1287 | |
1288 | static int | |
1289 | vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, | |
1290 | size_t *values_cnt) | |
1291 | { | |
1292 | if (source_name && strcmp(source_name, "auto") != 0) | |
1293 | return -EINVAL; | |
1294 | ||
1295 | *values_cnt = 3; | |
1296 | return 0; | |
1297 | } | |
1298 | ||
6cca3869 SP |
1299 | #else |
1300 | static int vop_crtc_set_crc_source(struct drm_crtc *crtc, | |
c0811a7d | 1301 | const char *source_name) |
6cca3869 SP |
1302 | { |
1303 | return -ENODEV; | |
1304 | } | |
b8d913c0 MK |
1305 | |
1306 | static int | |
1307 | vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, | |
1308 | size_t *values_cnt) | |
1309 | { | |
1310 | return -ENODEV; | |
1311 | } | |
6cca3869 | 1312 | #endif |
3190e58d | 1313 | |
2048e328 | 1314 | static const struct drm_crtc_funcs vop_crtc_funcs = { |
63ebb9fa MY |
1315 | .set_config = drm_atomic_helper_set_config, |
1316 | .page_flip = drm_atomic_helper_page_flip, | |
2048e328 | 1317 | .destroy = vop_crtc_destroy, |
dc0b408f | 1318 | .reset = vop_crtc_reset, |
4e257d9e MY |
1319 | .atomic_duplicate_state = vop_crtc_duplicate_state, |
1320 | .atomic_destroy_state = vop_crtc_destroy_state, | |
c3605dfc SG |
1321 | .enable_vblank = vop_crtc_enable_vblank, |
1322 | .disable_vblank = vop_crtc_disable_vblank, | |
3190e58d | 1323 | .set_crc_source = vop_crtc_set_crc_source, |
b8d913c0 | 1324 | .verify_crc_source = vop_crtc_verify_crc_source, |
2048e328 MY |
1325 | }; |
1326 | ||
47a7eb45 TF |
1327 | static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) |
1328 | { | |
1329 | struct vop *vop = container_of(work, struct vop, fb_unref_work); | |
1330 | struct drm_framebuffer *fb = val; | |
1331 | ||
1332 | drm_crtc_vblank_put(&vop->crtc); | |
adedbf03 | 1333 | drm_framebuffer_put(fb); |
47a7eb45 TF |
1334 | } |
1335 | ||
63ebb9fa | 1336 | static void vop_handle_vblank(struct vop *vop) |
2048e328 | 1337 | { |
63ebb9fa MY |
1338 | struct drm_device *drm = vop->drm_dev; |
1339 | struct drm_crtc *crtc = &vop->crtc; | |
2048e328 | 1340 | |
1c85f2fa | 1341 | spin_lock(&drm->event_lock); |
63ebb9fa | 1342 | if (vop->event) { |
63ebb9fa | 1343 | drm_crtc_send_vblank_event(crtc, vop->event); |
5b680403 | 1344 | drm_crtc_vblank_put(crtc); |
646ec687 | 1345 | vop->event = NULL; |
5b680403 | 1346 | } |
1c85f2fa | 1347 | spin_unlock(&drm->event_lock); |
893b6cad | 1348 | |
47a7eb45 TF |
1349 | if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) |
1350 | drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); | |
2048e328 MY |
1351 | } |
1352 | ||
1353 | static irqreturn_t vop_isr(int irq, void *data) | |
1354 | { | |
1355 | struct vop *vop = data; | |
b5f7b755 | 1356 | struct drm_crtc *crtc = &vop->crtc; |
dbb3d944 | 1357 | uint32_t active_irqs; |
1067219b | 1358 | int ret = IRQ_NONE; |
2048e328 | 1359 | |
6456314f SH |
1360 | /* |
1361 | * The irq is shared with the iommu. If the runtime-pm state of the | |
1362 | * vop-device is disabled the irq has to be targeted at the iommu. | |
1363 | */ | |
1364 | if (!pm_runtime_get_if_in_use(vop->dev)) | |
1365 | return IRQ_NONE; | |
1366 | ||
1367 | if (vop_core_clks_enable(vop)) { | |
1368 | DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n"); | |
1369 | goto out; | |
1370 | } | |
1371 | ||
2048e328 | 1372 | /* |
dbb3d944 | 1373 | * interrupt register has interrupt status, enable and clear bits, we |
2048e328 MY |
1374 | * must hold irq_lock to avoid a race with enable/disable_vblank(). |
1375 | */ | |
1c85f2fa | 1376 | spin_lock(&vop->irq_lock); |
dbb3d944 MY |
1377 | |
1378 | active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); | |
2048e328 MY |
1379 | /* Clear all active interrupt sources */ |
1380 | if (active_irqs) | |
dbb3d944 MY |
1381 | VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); |
1382 | ||
1c85f2fa | 1383 | spin_unlock(&vop->irq_lock); |
2048e328 MY |
1384 | |
1385 | /* This is expected for vop iommu irqs, since the irq is shared */ | |
1386 | if (!active_irqs) | |
6456314f | 1387 | goto out_disable; |
2048e328 | 1388 | |
1067219b MY |
1389 | if (active_irqs & DSP_HOLD_VALID_INTR) { |
1390 | complete(&vop->dsp_hold_completion); | |
1391 | active_irqs &= ~DSP_HOLD_VALID_INTR; | |
1392 | ret = IRQ_HANDLED; | |
2048e328 MY |
1393 | } |
1394 | ||
69c34e41 YY |
1395 | if (active_irqs & LINE_FLAG_INTR) { |
1396 | complete(&vop->line_flag_completion); | |
1397 | active_irqs &= ~LINE_FLAG_INTR; | |
1398 | ret = IRQ_HANDLED; | |
1399 | } | |
1400 | ||
1067219b | 1401 | if (active_irqs & FS_INTR) { |
b5f7b755 | 1402 | drm_crtc_handle_vblank(crtc); |
63ebb9fa | 1403 | vop_handle_vblank(vop); |
1067219b | 1404 | active_irqs &= ~FS_INTR; |
63ebb9fa | 1405 | ret = IRQ_HANDLED; |
1067219b | 1406 | } |
2048e328 | 1407 | |
1067219b MY |
1408 | /* Unhandled irqs are spurious. */ |
1409 | if (active_irqs) | |
ee4d7899 SP |
1410 | DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", |
1411 | active_irqs); | |
1067219b | 1412 | |
6456314f SH |
1413 | out_disable: |
1414 | vop_core_clks_disable(vop); | |
1415 | out: | |
1416 | pm_runtime_put(vop->dev); | |
1067219b | 1417 | return ret; |
2048e328 MY |
1418 | } |
1419 | ||
677e8bbc DC |
1420 | static void vop_plane_add_properties(struct drm_plane *plane, |
1421 | const struct vop_win_data *win_data) | |
1422 | { | |
1423 | unsigned int flags = 0; | |
1424 | ||
1425 | flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0; | |
1426 | flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0; | |
1427 | if (flags) | |
1428 | drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, | |
1429 | DRM_MODE_ROTATE_0 | flags); | |
1430 | } | |
1431 | ||
2048e328 MY |
1432 | static int vop_create_crtc(struct vop *vop) |
1433 | { | |
1434 | const struct vop_data *vop_data = vop->data; | |
1435 | struct device *dev = vop->dev; | |
1436 | struct drm_device *drm_dev = vop->drm_dev; | |
328b51c0 | 1437 | struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; |
2048e328 MY |
1438 | struct drm_crtc *crtc = &vop->crtc; |
1439 | struct device_node *port; | |
1440 | int ret; | |
1441 | int i; | |
1442 | ||
1443 | /* | |
1444 | * Create drm_plane for primary and cursor planes first, since we need | |
1445 | * to pass them to drm_crtc_init_with_planes, which sets the | |
1446 | * "possible_crtcs" to the newly initialized crtc. | |
1447 | */ | |
1448 | for (i = 0; i < vop_data->win_size; i++) { | |
1449 | struct vop_win *vop_win = &vop->win[i]; | |
1450 | const struct vop_win_data *win_data = vop_win->data; | |
1451 | ||
1452 | if (win_data->type != DRM_PLANE_TYPE_PRIMARY && | |
1453 | win_data->type != DRM_PLANE_TYPE_CURSOR) | |
1454 | continue; | |
1455 | ||
1456 | ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, | |
1457 | 0, &vop_plane_funcs, | |
1458 | win_data->phy->data_formats, | |
1459 | win_data->phy->nformats, | |
e6fc3b68 | 1460 | NULL, win_data->type, NULL); |
2048e328 | 1461 | if (ret) { |
ee4d7899 SP |
1462 | DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", |
1463 | ret); | |
2048e328 MY |
1464 | goto err_cleanup_planes; |
1465 | } | |
1466 | ||
1467 | plane = &vop_win->base; | |
63ebb9fa | 1468 | drm_plane_helper_add(plane, &plane_helper_funcs); |
677e8bbc | 1469 | vop_plane_add_properties(plane, win_data); |
2048e328 MY |
1470 | if (plane->type == DRM_PLANE_TYPE_PRIMARY) |
1471 | primary = plane; | |
1472 | else if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
1473 | cursor = plane; | |
1474 | } | |
1475 | ||
1476 | ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, | |
f9882876 | 1477 | &vop_crtc_funcs, NULL); |
2048e328 | 1478 | if (ret) |
328b51c0 | 1479 | goto err_cleanup_planes; |
2048e328 MY |
1480 | |
1481 | drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); | |
1482 | ||
1483 | /* | |
1484 | * Create drm_planes for overlay windows with possible_crtcs restricted | |
1485 | * to the newly created crtc. | |
1486 | */ | |
1487 | for (i = 0; i < vop_data->win_size; i++) { | |
1488 | struct vop_win *vop_win = &vop->win[i]; | |
1489 | const struct vop_win_data *win_data = vop_win->data; | |
a3e77e16 | 1490 | unsigned long possible_crtcs = drm_crtc_mask(crtc); |
2048e328 MY |
1491 | |
1492 | if (win_data->type != DRM_PLANE_TYPE_OVERLAY) | |
1493 | continue; | |
1494 | ||
1495 | ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, | |
1496 | possible_crtcs, | |
1497 | &vop_plane_funcs, | |
1498 | win_data->phy->data_formats, | |
1499 | win_data->phy->nformats, | |
e6fc3b68 | 1500 | NULL, win_data->type, NULL); |
2048e328 | 1501 | if (ret) { |
ee4d7899 SP |
1502 | DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", |
1503 | ret); | |
2048e328 MY |
1504 | goto err_cleanup_crtc; |
1505 | } | |
63ebb9fa | 1506 | drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); |
677e8bbc | 1507 | vop_plane_add_properties(&vop_win->base, win_data); |
2048e328 MY |
1508 | } |
1509 | ||
1510 | port = of_get_child_by_name(dev->of_node, "port"); | |
1511 | if (!port) { | |
4bf99144 RH |
1512 | DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", |
1513 | dev->of_node); | |
328b51c0 | 1514 | ret = -ENOENT; |
2048e328 MY |
1515 | goto err_cleanup_crtc; |
1516 | } | |
1517 | ||
47a7eb45 TF |
1518 | drm_flip_work_init(&vop->fb_unref_work, "fb_unref", |
1519 | vop_fb_unref_worker); | |
1520 | ||
1067219b | 1521 | init_completion(&vop->dsp_hold_completion); |
69c34e41 | 1522 | init_completion(&vop->line_flag_completion); |
2048e328 | 1523 | crtc->port = port; |
2048e328 MY |
1524 | |
1525 | return 0; | |
1526 | ||
1527 | err_cleanup_crtc: | |
1528 | drm_crtc_cleanup(crtc); | |
1529 | err_cleanup_planes: | |
328b51c0 DA |
1530 | list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, |
1531 | head) | |
2048e328 MY |
1532 | drm_plane_cleanup(plane); |
1533 | return ret; | |
1534 | } | |
1535 | ||
1536 | static void vop_destroy_crtc(struct vop *vop) | |
1537 | { | |
1538 | struct drm_crtc *crtc = &vop->crtc; | |
328b51c0 DA |
1539 | struct drm_device *drm_dev = vop->drm_dev; |
1540 | struct drm_plane *plane, *tmp; | |
2048e328 | 1541 | |
2048e328 | 1542 | of_node_put(crtc->port); |
328b51c0 DA |
1543 | |
1544 | /* | |
1545 | * We need to cleanup the planes now. Why? | |
1546 | * | |
1547 | * The planes are "&vop->win[i].base". That means the memory is | |
1548 | * all part of the big "struct vop" chunk of memory. That memory | |
1549 | * was devm allocated and associated with this component. We need to | |
1550 | * free it ourselves before vop_unbind() finishes. | |
1551 | */ | |
1552 | list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, | |
1553 | head) | |
1554 | vop_plane_destroy(plane); | |
1555 | ||
1556 | /* | |
1557 | * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() | |
1558 | * references the CRTC. | |
1559 | */ | |
2048e328 | 1560 | drm_crtc_cleanup(crtc); |
47a7eb45 | 1561 | drm_flip_work_cleanup(&vop->fb_unref_work); |
2048e328 MY |
1562 | } |
1563 | ||
1564 | static int vop_initial(struct vop *vop) | |
1565 | { | |
1566 | const struct vop_data *vop_data = vop->data; | |
2048e328 MY |
1567 | struct reset_control *ahb_rst; |
1568 | int i, ret; | |
1569 | ||
1570 | vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); | |
1571 | if (IS_ERR(vop->hclk)) { | |
d8dd6804 | 1572 | DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); |
2048e328 MY |
1573 | return PTR_ERR(vop->hclk); |
1574 | } | |
1575 | vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); | |
1576 | if (IS_ERR(vop->aclk)) { | |
d8dd6804 | 1577 | DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); |
2048e328 MY |
1578 | return PTR_ERR(vop->aclk); |
1579 | } | |
1580 | vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); | |
1581 | if (IS_ERR(vop->dclk)) { | |
d8dd6804 | 1582 | DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); |
2048e328 MY |
1583 | return PTR_ERR(vop->dclk); |
1584 | } | |
1585 | ||
5e570373 JC |
1586 | ret = pm_runtime_get_sync(vop->dev); |
1587 | if (ret < 0) { | |
d8dd6804 | 1588 | DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); |
5e570373 JC |
1589 | return ret; |
1590 | } | |
1591 | ||
2048e328 MY |
1592 | ret = clk_prepare(vop->dclk); |
1593 | if (ret < 0) { | |
d8dd6804 | 1594 | DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); |
5e570373 | 1595 | goto err_put_pm_runtime; |
2048e328 MY |
1596 | } |
1597 | ||
d7b53fd9 SS |
1598 | /* Enable both the hclk and aclk to setup the vop */ |
1599 | ret = clk_prepare_enable(vop->hclk); | |
2048e328 | 1600 | if (ret < 0) { |
d8dd6804 | 1601 | DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); |
2048e328 MY |
1602 | goto err_unprepare_dclk; |
1603 | } | |
1604 | ||
d7b53fd9 | 1605 | ret = clk_prepare_enable(vop->aclk); |
2048e328 | 1606 | if (ret < 0) { |
d8dd6804 | 1607 | DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); |
d7b53fd9 | 1608 | goto err_disable_hclk; |
2048e328 | 1609 | } |
d7b53fd9 | 1610 | |
2048e328 MY |
1611 | /* |
1612 | * do hclk_reset, reset all vop registers. | |
1613 | */ | |
1614 | ahb_rst = devm_reset_control_get(vop->dev, "ahb"); | |
1615 | if (IS_ERR(ahb_rst)) { | |
d8dd6804 | 1616 | DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); |
2048e328 | 1617 | ret = PTR_ERR(ahb_rst); |
d7b53fd9 | 1618 | goto err_disable_aclk; |
2048e328 MY |
1619 | } |
1620 | reset_control_assert(ahb_rst); | |
1621 | usleep_range(10, 20); | |
1622 | reset_control_deassert(ahb_rst); | |
1623 | ||
5f9e93fe MZ |
1624 | VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1); |
1625 | VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0); | |
1626 | ||
76f1416e MZ |
1627 | for (i = 0; i < vop->len; i += sizeof(u32)) |
1628 | vop->regsbak[i / 4] = readl_relaxed(vop->regs + i); | |
2048e328 | 1629 | |
9a61c54b M |
1630 | VOP_REG_SET(vop, misc, global_regdone_en, 1); |
1631 | VOP_REG_SET(vop, common, dsp_blank, 0); | |
2048e328 MY |
1632 | |
1633 | for (i = 0; i < vop_data->win_size; i++) { | |
1634 | const struct vop_win_data *win = &vop_data->win[i]; | |
9dd2aca4 | 1635 | int channel = i * 2 + 1; |
2048e328 | 1636 | |
9dd2aca4 | 1637 | VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); |
e9abc611 | 1638 | vop_win_disable(vop, win); |
60b7ae7f | 1639 | VOP_WIN_SET(vop, win, gate, 1); |
2048e328 MY |
1640 | } |
1641 | ||
1642 | vop_cfg_done(vop); | |
1643 | ||
1644 | /* | |
1645 | * do dclk_reset, let all config take affect. | |
1646 | */ | |
1647 | vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); | |
1648 | if (IS_ERR(vop->dclk_rst)) { | |
d8dd6804 | 1649 | DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); |
2048e328 | 1650 | ret = PTR_ERR(vop->dclk_rst); |
d7b53fd9 | 1651 | goto err_disable_aclk; |
2048e328 MY |
1652 | } |
1653 | reset_control_assert(vop->dclk_rst); | |
1654 | usleep_range(10, 20); | |
1655 | reset_control_deassert(vop->dclk_rst); | |
1656 | ||
1657 | clk_disable(vop->hclk); | |
d7b53fd9 | 1658 | clk_disable(vop->aclk); |
2048e328 | 1659 | |
31e980c5 | 1660 | vop->is_enabled = false; |
2048e328 | 1661 | |
5e570373 JC |
1662 | pm_runtime_put_sync(vop->dev); |
1663 | ||
2048e328 MY |
1664 | return 0; |
1665 | ||
d7b53fd9 SS |
1666 | err_disable_aclk: |
1667 | clk_disable_unprepare(vop->aclk); | |
2048e328 | 1668 | err_disable_hclk: |
d7b53fd9 | 1669 | clk_disable_unprepare(vop->hclk); |
2048e328 MY |
1670 | err_unprepare_dclk: |
1671 | clk_unprepare(vop->dclk); | |
5e570373 JC |
1672 | err_put_pm_runtime: |
1673 | pm_runtime_put_sync(vop->dev); | |
2048e328 MY |
1674 | return ret; |
1675 | } | |
1676 | ||
1677 | /* | |
1678 | * Initialize the vop->win array elements. | |
1679 | */ | |
1680 | static void vop_win_init(struct vop *vop) | |
1681 | { | |
1682 | const struct vop_data *vop_data = vop->data; | |
1683 | unsigned int i; | |
1684 | ||
1685 | for (i = 0; i < vop_data->win_size; i++) { | |
1686 | struct vop_win *vop_win = &vop->win[i]; | |
1687 | const struct vop_win_data *win_data = &vop_data->win[i]; | |
1688 | ||
1689 | vop_win->data = win_data; | |
1690 | vop_win->vop = vop; | |
ce6912b4 HS |
1691 | |
1692 | if (vop_data->win_yuv2yuv) | |
1693 | vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i]; | |
2048e328 MY |
1694 | } |
1695 | } | |
1696 | ||
69c34e41 | 1697 | /** |
459b086d | 1698 | * rockchip_drm_wait_vact_end |
69c34e41 | 1699 | * @crtc: CRTC to enable line flag |
69c34e41 YY |
1700 | * @mstimeout: millisecond for timeout |
1701 | * | |
459b086d | 1702 | * Wait for vact_end line flag irq or timeout. |
69c34e41 YY |
1703 | * |
1704 | * Returns: | |
1705 | * Zero on success, negative errno on failure. | |
1706 | */ | |
459b086d | 1707 | int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) |
69c34e41 YY |
1708 | { |
1709 | struct vop *vop = to_vop(crtc); | |
1710 | unsigned long jiffies_left; | |
e334d48b | 1711 | int ret = 0; |
69c34e41 YY |
1712 | |
1713 | if (!crtc || !vop->is_enabled) | |
1714 | return -ENODEV; | |
1715 | ||
e334d48b | 1716 | mutex_lock(&vop->vop_lock); |
1717 | if (mstimeout <= 0) { | |
1718 | ret = -EINVAL; | |
1719 | goto out; | |
1720 | } | |
69c34e41 | 1721 | |
e334d48b | 1722 | if (vop_line_flag_irq_is_enabled(vop)) { |
1723 | ret = -EBUSY; | |
1724 | goto out; | |
1725 | } | |
69c34e41 YY |
1726 | |
1727 | reinit_completion(&vop->line_flag_completion); | |
459b086d | 1728 | vop_line_flag_irq_enable(vop); |
69c34e41 YY |
1729 | |
1730 | jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, | |
1731 | msecs_to_jiffies(mstimeout)); | |
1732 | vop_line_flag_irq_disable(vop); | |
1733 | ||
1734 | if (jiffies_left == 0) { | |
d8dd6804 | 1735 | DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); |
e334d48b | 1736 | ret = -ETIMEDOUT; |
1737 | goto out; | |
69c34e41 YY |
1738 | } |
1739 | ||
e334d48b | 1740 | out: |
1741 | mutex_unlock(&vop->vop_lock); | |
1742 | return ret; | |
69c34e41 | 1743 | } |
459b086d | 1744 | EXPORT_SYMBOL(rockchip_drm_wait_vact_end); |
69c34e41 | 1745 | |
2048e328 MY |
1746 | static int vop_bind(struct device *dev, struct device *master, void *data) |
1747 | { | |
1748 | struct platform_device *pdev = to_platform_device(dev); | |
2048e328 MY |
1749 | const struct vop_data *vop_data; |
1750 | struct drm_device *drm_dev = data; | |
1751 | struct vop *vop; | |
1752 | struct resource *res; | |
3ea68922 | 1753 | int ret, irq; |
2048e328 | 1754 | |
a67719d1 | 1755 | vop_data = of_device_get_match_data(dev); |
2048e328 MY |
1756 | if (!vop_data) |
1757 | return -ENODEV; | |
1758 | ||
1759 | /* Allocate vop struct and its vop_win array */ | |
29adeb4f GS |
1760 | vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size), |
1761 | GFP_KERNEL); | |
2048e328 MY |
1762 | if (!vop) |
1763 | return -ENOMEM; | |
1764 | ||
1765 | vop->dev = dev; | |
1766 | vop->data = vop_data; | |
1767 | vop->drm_dev = drm_dev; | |
1768 | dev_set_drvdata(dev, vop); | |
1769 | ||
1770 | vop_win_init(vop); | |
1771 | ||
1772 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1773 | vop->len = resource_size(res); | |
1774 | vop->regs = devm_ioremap_resource(dev, res); | |
1775 | if (IS_ERR(vop->regs)) | |
1776 | return PTR_ERR(vop->regs); | |
1777 | ||
1778 | vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); | |
1779 | if (!vop->regsbak) | |
1780 | return -ENOMEM; | |
1781 | ||
3ea68922 HS |
1782 | irq = platform_get_irq(pdev, 0); |
1783 | if (irq < 0) { | |
d8dd6804 | 1784 | DRM_DEV_ERROR(dev, "cannot find irq for vop\n"); |
3ea68922 | 1785 | return irq; |
2048e328 | 1786 | } |
3ea68922 | 1787 | vop->irq = (unsigned int)irq; |
2048e328 MY |
1788 | |
1789 | spin_lock_init(&vop->reg_lock); | |
1790 | spin_lock_init(&vop->irq_lock); | |
e334d48b | 1791 | mutex_init(&vop->vop_lock); |
2048e328 | 1792 | |
2048e328 MY |
1793 | ret = vop_create_crtc(vop); |
1794 | if (ret) | |
5f9e93fe | 1795 | return ret; |
2048e328 MY |
1796 | |
1797 | pm_runtime_enable(&pdev->dev); | |
5182c1a5 | 1798 | |
5e570373 JC |
1799 | ret = vop_initial(vop); |
1800 | if (ret < 0) { | |
d8dd6804 HM |
1801 | DRM_DEV_ERROR(&pdev->dev, |
1802 | "cannot initial vop dev - err %d\n", ret); | |
5e570373 JC |
1803 | goto err_disable_pm_runtime; |
1804 | } | |
1805 | ||
5f9e93fe MZ |
1806 | ret = devm_request_irq(dev, vop->irq, vop_isr, |
1807 | IRQF_SHARED, dev_name(dev), vop); | |
1808 | if (ret) | |
1809 | goto err_disable_pm_runtime; | |
1810 | ||
1f0f0151 SH |
1811 | if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) { |
1812 | vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev); | |
1813 | if (IS_ERR(vop->rgb)) { | |
1814 | ret = PTR_ERR(vop->rgb); | |
1815 | goto err_disable_pm_runtime; | |
1816 | } | |
1817 | } | |
1818 | ||
2048e328 | 1819 | return 0; |
8c763c9b | 1820 | |
5e570373 JC |
1821 | err_disable_pm_runtime: |
1822 | pm_runtime_disable(&pdev->dev); | |
1823 | vop_destroy_crtc(vop); | |
8c763c9b | 1824 | return ret; |
2048e328 MY |
1825 | } |
1826 | ||
1827 | static void vop_unbind(struct device *dev, struct device *master, void *data) | |
1828 | { | |
1829 | struct vop *vop = dev_get_drvdata(dev); | |
1830 | ||
1f0f0151 SH |
1831 | if (vop->rgb) |
1832 | rockchip_rgb_fini(vop->rgb); | |
1833 | ||
2048e328 MY |
1834 | pm_runtime_disable(dev); |
1835 | vop_destroy_crtc(vop); | |
ec6e7767 JC |
1836 | |
1837 | clk_unprepare(vop->aclk); | |
1838 | clk_unprepare(vop->hclk); | |
1839 | clk_unprepare(vop->dclk); | |
2048e328 MY |
1840 | } |
1841 | ||
a67719d1 | 1842 | const struct component_ops vop_component_ops = { |
2048e328 MY |
1843 | .bind = vop_bind, |
1844 | .unbind = vop_unbind, | |
1845 | }; | |
54255e81 | 1846 | EXPORT_SYMBOL_GPL(vop_component_ops); |