Commit | Line | Data |
---|---|---|
2048e328 MY |
1 | /* |
2 | * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd | |
3 | * Author:Mark Yao <mark.yao@rock-chips.com> | |
4 | * | |
5 | * This software is licensed under the terms of the GNU General Public | |
6 | * License version 2, as published by the Free Software Foundation, and | |
7 | * may be copied, distributed, and modified under those terms. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
15 | #include <drm/drm.h> | |
16 | #include <drm/drmP.h> | |
63ebb9fa | 17 | #include <drm/drm_atomic.h> |
2048e328 MY |
18 | #include <drm/drm_crtc.h> |
19 | #include <drm/drm_crtc_helper.h> | |
20 | #include <drm/drm_plane_helper.h> | |
21 | ||
22 | #include <linux/kernel.h> | |
00fe6148 | 23 | #include <linux/module.h> |
2048e328 MY |
24 | #include <linux/platform_device.h> |
25 | #include <linux/clk.h> | |
26 | #include <linux/of.h> | |
27 | #include <linux/of_device.h> | |
28 | #include <linux/pm_runtime.h> | |
29 | #include <linux/component.h> | |
30 | ||
31 | #include <linux/reset.h> | |
32 | #include <linux/delay.h> | |
33 | ||
34 | #include "rockchip_drm_drv.h" | |
35 | #include "rockchip_drm_gem.h" | |
36 | #include "rockchip_drm_fb.h" | |
37 | #include "rockchip_drm_vop.h" | |
38 | ||
2048e328 MY |
39 | #define __REG_SET_RELAXED(x, off, mask, shift, v) \ |
40 | vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift) | |
41 | #define __REG_SET_NORMAL(x, off, mask, shift, v) \ | |
42 | vop_mask_write(x, off, (mask) << shift, (v) << shift) | |
43 | ||
44 | #define REG_SET(x, base, reg, v, mode) \ | |
45 | __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v) | |
c7647f86 JK |
46 | #define REG_SET_MASK(x, base, reg, mask, v, mode) \ |
47 | __REG_SET_##mode(x, base + reg.offset, mask, reg.shift, v) | |
2048e328 MY |
48 | |
49 | #define VOP_WIN_SET(x, win, name, v) \ | |
50 | REG_SET(x, win->base, win->phy->name, v, RELAXED) | |
4c156c21 MY |
51 | #define VOP_SCL_SET(x, win, name, v) \ |
52 | REG_SET(x, win->base, win->phy->scl->name, v, RELAXED) | |
1194fffb MY |
53 | #define VOP_SCL_SET_EXT(x, win, name, v) \ |
54 | REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED) | |
2048e328 MY |
55 | #define VOP_CTRL_SET(x, name, v) \ |
56 | REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL) | |
57 | ||
dbb3d944 MY |
58 | #define VOP_INTR_GET(vop, name) \ |
59 | vop_read_reg(vop, 0, &vop->data->ctrl->name) | |
60 | ||
c7647f86 JK |
61 | #define VOP_INTR_SET(vop, name, mask, v) \ |
62 | REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL) | |
dbb3d944 MY |
63 | #define VOP_INTR_SET_TYPE(vop, name, type, v) \ |
64 | do { \ | |
c7647f86 | 65 | int i, reg = 0, mask = 0; \ |
dbb3d944 | 66 | for (i = 0; i < vop->data->intr->nintrs; i++) { \ |
c7647f86 | 67 | if (vop->data->intr->intrs[i] & type) { \ |
dbb3d944 | 68 | reg |= (v) << i; \ |
c7647f86 JK |
69 | mask |= 1 << i; \ |
70 | } \ | |
dbb3d944 | 71 | } \ |
c7647f86 | 72 | VOP_INTR_SET(vop, name, mask, reg); \ |
dbb3d944 MY |
73 | } while (0) |
74 | #define VOP_INTR_GET_TYPE(vop, name, type) \ | |
75 | vop_get_intr_type(vop, &vop->data->intr->name, type) | |
76 | ||
2048e328 MY |
77 | #define VOP_WIN_GET(x, win, name) \ |
78 | vop_read_reg(x, win->base, &win->phy->name) | |
79 | ||
80 | #define VOP_WIN_GET_YRGBADDR(vop, win) \ | |
81 | vop_readl(vop, win->base + win->phy->yrgb_mst.offset) | |
82 | ||
83 | #define to_vop(x) container_of(x, struct vop, crtc) | |
84 | #define to_vop_win(x) container_of(x, struct vop_win, base) | |
63ebb9fa | 85 | #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base) |
2048e328 | 86 | |
63ebb9fa MY |
87 | struct vop_plane_state { |
88 | struct drm_plane_state base; | |
89 | int format; | |
90 | struct drm_rect src; | |
91 | struct drm_rect dest; | |
2048e328 | 92 | dma_addr_t yrgb_mst; |
63ebb9fa | 93 | bool enable; |
2048e328 MY |
94 | }; |
95 | ||
96 | struct vop_win { | |
97 | struct drm_plane base; | |
98 | const struct vop_win_data *data; | |
99 | struct vop *vop; | |
100 | ||
63ebb9fa | 101 | struct vop_plane_state state; |
2048e328 MY |
102 | }; |
103 | ||
104 | struct vop { | |
105 | struct drm_crtc crtc; | |
106 | struct device *dev; | |
107 | struct drm_device *drm_dev; | |
31e980c5 | 108 | bool is_enabled; |
2048e328 | 109 | |
2048e328 MY |
110 | /* mutex vsync_ work */ |
111 | struct mutex vsync_mutex; | |
112 | bool vsync_work_pending; | |
1067219b | 113 | struct completion dsp_hold_completion; |
63ebb9fa MY |
114 | struct completion wait_update_complete; |
115 | struct drm_pending_vblank_event *event; | |
2048e328 MY |
116 | |
117 | const struct vop_data *data; | |
118 | ||
119 | uint32_t *regsbak; | |
120 | void __iomem *regs; | |
121 | ||
122 | /* physical map length of vop register */ | |
123 | uint32_t len; | |
124 | ||
125 | /* one time only one process allowed to config the register */ | |
126 | spinlock_t reg_lock; | |
127 | /* lock vop irq reg */ | |
128 | spinlock_t irq_lock; | |
129 | ||
130 | unsigned int irq; | |
131 | ||
132 | /* vop AHP clk */ | |
133 | struct clk *hclk; | |
134 | /* vop dclk */ | |
135 | struct clk *dclk; | |
136 | /* vop share memory frequency */ | |
137 | struct clk *aclk; | |
138 | ||
139 | /* vop dclk reset */ | |
140 | struct reset_control *dclk_rst; | |
141 | ||
2048e328 MY |
142 | struct vop_win win[]; |
143 | }; | |
144 | ||
2048e328 MY |
145 | static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) |
146 | { | |
147 | writel(v, vop->regs + offset); | |
148 | vop->regsbak[offset >> 2] = v; | |
149 | } | |
150 | ||
151 | static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) | |
152 | { | |
153 | return readl(vop->regs + offset); | |
154 | } | |
155 | ||
156 | static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, | |
157 | const struct vop_reg *reg) | |
158 | { | |
159 | return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; | |
160 | } | |
161 | ||
2048e328 MY |
162 | static inline void vop_mask_write(struct vop *vop, uint32_t offset, |
163 | uint32_t mask, uint32_t v) | |
164 | { | |
165 | if (mask) { | |
166 | uint32_t cached_val = vop->regsbak[offset >> 2]; | |
167 | ||
168 | cached_val = (cached_val & ~mask) | v; | |
169 | writel(cached_val, vop->regs + offset); | |
170 | vop->regsbak[offset >> 2] = cached_val; | |
171 | } | |
172 | } | |
173 | ||
174 | static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset, | |
175 | uint32_t mask, uint32_t v) | |
176 | { | |
177 | if (mask) { | |
178 | uint32_t cached_val = vop->regsbak[offset >> 2]; | |
179 | ||
180 | cached_val = (cached_val & ~mask) | v; | |
181 | writel_relaxed(cached_val, vop->regs + offset); | |
182 | vop->regsbak[offset >> 2] = cached_val; | |
183 | } | |
184 | } | |
185 | ||
dbb3d944 MY |
186 | static inline uint32_t vop_get_intr_type(struct vop *vop, |
187 | const struct vop_reg *reg, int type) | |
188 | { | |
189 | uint32_t i, ret = 0; | |
190 | uint32_t regs = vop_read_reg(vop, 0, reg); | |
191 | ||
192 | for (i = 0; i < vop->data->intr->nintrs; i++) { | |
193 | if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) | |
194 | ret |= vop->data->intr->intrs[i]; | |
195 | } | |
196 | ||
197 | return ret; | |
198 | } | |
199 | ||
0cf33fe3 MY |
200 | static inline void vop_cfg_done(struct vop *vop) |
201 | { | |
202 | VOP_CTRL_SET(vop, cfg_done, 1); | |
203 | } | |
204 | ||
85a359f2 TF |
205 | static bool has_rb_swapped(uint32_t format) |
206 | { | |
207 | switch (format) { | |
208 | case DRM_FORMAT_XBGR8888: | |
209 | case DRM_FORMAT_ABGR8888: | |
210 | case DRM_FORMAT_BGR888: | |
211 | case DRM_FORMAT_BGR565: | |
212 | return true; | |
213 | default: | |
214 | return false; | |
215 | } | |
216 | } | |
217 | ||
2048e328 MY |
218 | static enum vop_data_format vop_convert_format(uint32_t format) |
219 | { | |
220 | switch (format) { | |
221 | case DRM_FORMAT_XRGB8888: | |
222 | case DRM_FORMAT_ARGB8888: | |
85a359f2 TF |
223 | case DRM_FORMAT_XBGR8888: |
224 | case DRM_FORMAT_ABGR8888: | |
2048e328 MY |
225 | return VOP_FMT_ARGB8888; |
226 | case DRM_FORMAT_RGB888: | |
85a359f2 | 227 | case DRM_FORMAT_BGR888: |
2048e328 MY |
228 | return VOP_FMT_RGB888; |
229 | case DRM_FORMAT_RGB565: | |
85a359f2 | 230 | case DRM_FORMAT_BGR565: |
2048e328 MY |
231 | return VOP_FMT_RGB565; |
232 | case DRM_FORMAT_NV12: | |
233 | return VOP_FMT_YUV420SP; | |
234 | case DRM_FORMAT_NV16: | |
235 | return VOP_FMT_YUV422SP; | |
236 | case DRM_FORMAT_NV24: | |
237 | return VOP_FMT_YUV444SP; | |
238 | default: | |
239 | DRM_ERROR("unsupport format[%08x]\n", format); | |
240 | return -EINVAL; | |
241 | } | |
242 | } | |
243 | ||
84c7f8ca MY |
244 | static bool is_yuv_support(uint32_t format) |
245 | { | |
246 | switch (format) { | |
247 | case DRM_FORMAT_NV12: | |
248 | case DRM_FORMAT_NV16: | |
249 | case DRM_FORMAT_NV24: | |
250 | return true; | |
251 | default: | |
252 | return false; | |
253 | } | |
254 | } | |
255 | ||
2048e328 MY |
256 | static bool is_alpha_support(uint32_t format) |
257 | { | |
258 | switch (format) { | |
259 | case DRM_FORMAT_ARGB8888: | |
85a359f2 | 260 | case DRM_FORMAT_ABGR8888: |
2048e328 MY |
261 | return true; |
262 | default: | |
263 | return false; | |
264 | } | |
265 | } | |
266 | ||
4c156c21 MY |
267 | static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, |
268 | uint32_t dst, bool is_horizontal, | |
269 | int vsu_mode, int *vskiplines) | |
270 | { | |
271 | uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; | |
272 | ||
273 | if (is_horizontal) { | |
274 | if (mode == SCALE_UP) | |
275 | val = GET_SCL_FT_BIC(src, dst); | |
276 | else if (mode == SCALE_DOWN) | |
277 | val = GET_SCL_FT_BILI_DN(src, dst); | |
278 | } else { | |
279 | if (mode == SCALE_UP) { | |
280 | if (vsu_mode == SCALE_UP_BIL) | |
281 | val = GET_SCL_FT_BILI_UP(src, dst); | |
282 | else | |
283 | val = GET_SCL_FT_BIC(src, dst); | |
284 | } else if (mode == SCALE_DOWN) { | |
285 | if (vskiplines) { | |
286 | *vskiplines = scl_get_vskiplines(src, dst); | |
287 | val = scl_get_bili_dn_vskip(src, dst, | |
288 | *vskiplines); | |
289 | } else { | |
290 | val = GET_SCL_FT_BILI_DN(src, dst); | |
291 | } | |
292 | } | |
293 | } | |
294 | ||
295 | return val; | |
296 | } | |
297 | ||
298 | static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, | |
299 | uint32_t src_w, uint32_t src_h, uint32_t dst_w, | |
300 | uint32_t dst_h, uint32_t pixel_format) | |
301 | { | |
302 | uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; | |
303 | uint16_t cbcr_hor_scl_mode = SCALE_NONE; | |
304 | uint16_t cbcr_ver_scl_mode = SCALE_NONE; | |
305 | int hsub = drm_format_horz_chroma_subsampling(pixel_format); | |
306 | int vsub = drm_format_vert_chroma_subsampling(pixel_format); | |
307 | bool is_yuv = is_yuv_support(pixel_format); | |
308 | uint16_t cbcr_src_w = src_w / hsub; | |
309 | uint16_t cbcr_src_h = src_h / vsub; | |
310 | uint16_t vsu_mode; | |
311 | uint16_t lb_mode; | |
312 | uint32_t val; | |
313 | int vskiplines; | |
314 | ||
315 | if (dst_w > 3840) { | |
316 | DRM_ERROR("Maximum destination width (3840) exceeded\n"); | |
317 | return; | |
318 | } | |
319 | ||
1194fffb MY |
320 | if (!win->phy->scl->ext) { |
321 | VOP_SCL_SET(vop, win, scale_yrgb_x, | |
322 | scl_cal_scale2(src_w, dst_w)); | |
323 | VOP_SCL_SET(vop, win, scale_yrgb_y, | |
324 | scl_cal_scale2(src_h, dst_h)); | |
325 | if (is_yuv) { | |
326 | VOP_SCL_SET(vop, win, scale_cbcr_x, | |
327 | scl_cal_scale2(src_w, dst_w)); | |
328 | VOP_SCL_SET(vop, win, scale_cbcr_y, | |
329 | scl_cal_scale2(src_h, dst_h)); | |
330 | } | |
331 | return; | |
332 | } | |
333 | ||
4c156c21 MY |
334 | yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); |
335 | yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); | |
336 | ||
337 | if (is_yuv) { | |
338 | cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); | |
339 | cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); | |
340 | if (cbcr_hor_scl_mode == SCALE_DOWN) | |
341 | lb_mode = scl_vop_cal_lb_mode(dst_w, true); | |
342 | else | |
343 | lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); | |
344 | } else { | |
345 | if (yrgb_hor_scl_mode == SCALE_DOWN) | |
346 | lb_mode = scl_vop_cal_lb_mode(dst_w, false); | |
347 | else | |
348 | lb_mode = scl_vop_cal_lb_mode(src_w, false); | |
349 | } | |
350 | ||
1194fffb | 351 | VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); |
4c156c21 MY |
352 | if (lb_mode == LB_RGB_3840X2) { |
353 | if (yrgb_ver_scl_mode != SCALE_NONE) { | |
354 | DRM_ERROR("ERROR : not allow yrgb ver scale\n"); | |
355 | return; | |
356 | } | |
357 | if (cbcr_ver_scl_mode != SCALE_NONE) { | |
358 | DRM_ERROR("ERROR : not allow cbcr ver scale\n"); | |
359 | return; | |
360 | } | |
361 | vsu_mode = SCALE_UP_BIL; | |
362 | } else if (lb_mode == LB_RGB_2560X4) { | |
363 | vsu_mode = SCALE_UP_BIL; | |
364 | } else { | |
365 | vsu_mode = SCALE_UP_BIC; | |
366 | } | |
367 | ||
368 | val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, | |
369 | true, 0, NULL); | |
370 | VOP_SCL_SET(vop, win, scale_yrgb_x, val); | |
371 | val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, | |
372 | false, vsu_mode, &vskiplines); | |
373 | VOP_SCL_SET(vop, win, scale_yrgb_y, val); | |
374 | ||
1194fffb MY |
375 | VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); |
376 | VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); | |
4c156c21 | 377 | |
1194fffb MY |
378 | VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); |
379 | VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); | |
380 | VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); | |
381 | VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); | |
382 | VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); | |
4c156c21 MY |
383 | if (is_yuv) { |
384 | val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, | |
385 | dst_w, true, 0, NULL); | |
386 | VOP_SCL_SET(vop, win, scale_cbcr_x, val); | |
387 | val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, | |
388 | dst_h, false, vsu_mode, &vskiplines); | |
389 | VOP_SCL_SET(vop, win, scale_cbcr_y, val); | |
390 | ||
1194fffb MY |
391 | VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); |
392 | VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); | |
393 | VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); | |
394 | VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); | |
395 | VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); | |
396 | VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); | |
397 | VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); | |
4c156c21 MY |
398 | } |
399 | } | |
400 | ||
1067219b MY |
401 | static void vop_dsp_hold_valid_irq_enable(struct vop *vop) |
402 | { | |
403 | unsigned long flags; | |
404 | ||
405 | if (WARN_ON(!vop->is_enabled)) | |
406 | return; | |
407 | ||
408 | spin_lock_irqsave(&vop->irq_lock, flags); | |
409 | ||
dbb3d944 | 410 | VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); |
1067219b MY |
411 | |
412 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
413 | } | |
414 | ||
415 | static void vop_dsp_hold_valid_irq_disable(struct vop *vop) | |
416 | { | |
417 | unsigned long flags; | |
418 | ||
419 | if (WARN_ON(!vop->is_enabled)) | |
420 | return; | |
421 | ||
422 | spin_lock_irqsave(&vop->irq_lock, flags); | |
423 | ||
dbb3d944 | 424 | VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); |
1067219b MY |
425 | |
426 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
427 | } | |
428 | ||
63ebb9fa | 429 | static void vop_enable(struct drm_crtc *crtc) |
2048e328 MY |
430 | { |
431 | struct vop *vop = to_vop(crtc); | |
432 | int ret; | |
433 | ||
31e980c5 MY |
434 | if (vop->is_enabled) |
435 | return; | |
436 | ||
5d82d1a7 MY |
437 | ret = pm_runtime_get_sync(vop->dev); |
438 | if (ret < 0) { | |
439 | dev_err(vop->dev, "failed to get pm runtime: %d\n", ret); | |
440 | return; | |
441 | } | |
442 | ||
2048e328 MY |
443 | ret = clk_enable(vop->hclk); |
444 | if (ret < 0) { | |
445 | dev_err(vop->dev, "failed to enable hclk - %d\n", ret); | |
446 | return; | |
447 | } | |
448 | ||
449 | ret = clk_enable(vop->dclk); | |
450 | if (ret < 0) { | |
451 | dev_err(vop->dev, "failed to enable dclk - %d\n", ret); | |
452 | goto err_disable_hclk; | |
453 | } | |
454 | ||
455 | ret = clk_enable(vop->aclk); | |
456 | if (ret < 0) { | |
457 | dev_err(vop->dev, "failed to enable aclk - %d\n", ret); | |
458 | goto err_disable_dclk; | |
459 | } | |
460 | ||
461 | /* | |
462 | * Slave iommu shares power, irq and clock with vop. It was associated | |
463 | * automatically with this master device via common driver code. | |
464 | * Now that we have enabled the clock we attach it to the shared drm | |
465 | * mapping. | |
466 | */ | |
467 | ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); | |
468 | if (ret) { | |
469 | dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret); | |
470 | goto err_disable_aclk; | |
471 | } | |
472 | ||
77faa161 | 473 | memcpy(vop->regs, vop->regsbak, vop->len); |
52ab7891 MY |
474 | /* |
475 | * At here, vop clock & iommu is enable, R/W vop regs would be safe. | |
476 | */ | |
477 | vop->is_enabled = true; | |
478 | ||
2048e328 MY |
479 | spin_lock(&vop->reg_lock); |
480 | ||
481 | VOP_CTRL_SET(vop, standby, 0); | |
482 | ||
483 | spin_unlock(&vop->reg_lock); | |
484 | ||
485 | enable_irq(vop->irq); | |
486 | ||
b5f7b755 | 487 | drm_crtc_vblank_on(crtc); |
2048e328 MY |
488 | |
489 | return; | |
490 | ||
491 | err_disable_aclk: | |
492 | clk_disable(vop->aclk); | |
493 | err_disable_dclk: | |
494 | clk_disable(vop->dclk); | |
495 | err_disable_hclk: | |
496 | clk_disable(vop->hclk); | |
497 | } | |
498 | ||
0ad3675d | 499 | static void vop_crtc_disable(struct drm_crtc *crtc) |
2048e328 MY |
500 | { |
501 | struct vop *vop = to_vop(crtc); | |
3ed6c649 | 502 | int i; |
2048e328 | 503 | |
31e980c5 MY |
504 | if (!vop->is_enabled) |
505 | return; | |
506 | ||
3ed6c649 TV |
507 | /* |
508 | * We need to make sure that all windows are disabled before we | |
509 | * disable that crtc. Otherwise we might try to scan from a destroyed | |
510 | * buffer later. | |
511 | */ | |
512 | for (i = 0; i < vop->data->win_size; i++) { | |
513 | struct vop_win *vop_win = &vop->win[i]; | |
514 | const struct vop_win_data *win = vop_win->data; | |
515 | ||
516 | spin_lock(&vop->reg_lock); | |
517 | VOP_WIN_SET(vop, win, enable, 0); | |
518 | spin_unlock(&vop->reg_lock); | |
519 | } | |
520 | ||
b5f7b755 | 521 | drm_crtc_vblank_off(crtc); |
2048e328 | 522 | |
2048e328 | 523 | /* |
1067219b MY |
524 | * Vop standby will take effect at end of current frame, |
525 | * if dsp hold valid irq happen, it means standby complete. | |
526 | * | |
527 | * we must wait standby complete when we want to disable aclk, | |
528 | * if not, memory bus maybe dead. | |
2048e328 | 529 | */ |
1067219b MY |
530 | reinit_completion(&vop->dsp_hold_completion); |
531 | vop_dsp_hold_valid_irq_enable(vop); | |
532 | ||
2048e328 MY |
533 | spin_lock(&vop->reg_lock); |
534 | ||
535 | VOP_CTRL_SET(vop, standby, 1); | |
536 | ||
537 | spin_unlock(&vop->reg_lock); | |
52ab7891 | 538 | |
1067219b MY |
539 | wait_for_completion(&vop->dsp_hold_completion); |
540 | ||
541 | vop_dsp_hold_valid_irq_disable(vop); | |
542 | ||
543 | disable_irq(vop->irq); | |
544 | ||
52ab7891 | 545 | vop->is_enabled = false; |
1067219b | 546 | |
2048e328 | 547 | /* |
1067219b | 548 | * vop standby complete, so iommu detach is safe. |
2048e328 | 549 | */ |
2048e328 MY |
550 | rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); |
551 | ||
1067219b | 552 | clk_disable(vop->dclk); |
2048e328 MY |
553 | clk_disable(vop->aclk); |
554 | clk_disable(vop->hclk); | |
5d82d1a7 | 555 | pm_runtime_put(vop->dev); |
2048e328 MY |
556 | } |
557 | ||
63ebb9fa | 558 | static void vop_plane_destroy(struct drm_plane *plane) |
2048e328 | 559 | { |
63ebb9fa | 560 | drm_plane_cleanup(plane); |
2048e328 MY |
561 | } |
562 | ||
63ebb9fa MY |
563 | static int vop_plane_atomic_check(struct drm_plane *plane, |
564 | struct drm_plane_state *state) | |
2048e328 | 565 | { |
63ebb9fa | 566 | struct drm_crtc *crtc = state->crtc; |
92915da6 | 567 | struct drm_crtc_state *crtc_state; |
63ebb9fa | 568 | struct drm_framebuffer *fb = state->fb; |
2048e328 | 569 | struct vop_win *vop_win = to_vop_win(plane); |
63ebb9fa | 570 | struct vop_plane_state *vop_plane_state = to_vop_plane_state(state); |
2048e328 | 571 | const struct vop_win_data *win = vop_win->data; |
2048e328 MY |
572 | bool visible; |
573 | int ret; | |
63ebb9fa MY |
574 | struct drm_rect *dest = &vop_plane_state->dest; |
575 | struct drm_rect *src = &vop_plane_state->src; | |
576 | struct drm_rect clip; | |
4c156c21 MY |
577 | int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : |
578 | DRM_PLANE_HELPER_NO_SCALING; | |
579 | int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : | |
580 | DRM_PLANE_HELPER_NO_SCALING; | |
2048e328 | 581 | |
63ebb9fa MY |
582 | if (!crtc || !fb) |
583 | goto out_disable; | |
92915da6 JK |
584 | |
585 | crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); | |
586 | if (WARN_ON(!crtc_state)) | |
587 | return -EINVAL; | |
588 | ||
63ebb9fa MY |
589 | src->x1 = state->src_x; |
590 | src->y1 = state->src_y; | |
591 | src->x2 = state->src_x + state->src_w; | |
592 | src->y2 = state->src_y + state->src_h; | |
593 | dest->x1 = state->crtc_x; | |
594 | dest->y1 = state->crtc_y; | |
595 | dest->x2 = state->crtc_x + state->crtc_w; | |
596 | dest->y2 = state->crtc_y + state->crtc_h; | |
597 | ||
598 | clip.x1 = 0; | |
599 | clip.y1 = 0; | |
92915da6 JK |
600 | clip.x2 = crtc_state->adjusted_mode.hdisplay; |
601 | clip.y2 = crtc_state->adjusted_mode.vdisplay; | |
63ebb9fa MY |
602 | |
603 | ret = drm_plane_helper_check_update(plane, crtc, state->fb, | |
604 | src, dest, &clip, | |
4c156c21 MY |
605 | min_scale, |
606 | max_scale, | |
63ebb9fa | 607 | true, true, &visible); |
2048e328 MY |
608 | if (ret) |
609 | return ret; | |
610 | ||
611 | if (!visible) | |
63ebb9fa | 612 | goto out_disable; |
2048e328 | 613 | |
63ebb9fa MY |
614 | vop_plane_state->format = vop_convert_format(fb->pixel_format); |
615 | if (vop_plane_state->format < 0) | |
616 | return vop_plane_state->format; | |
84c7f8ca | 617 | |
63ebb9fa MY |
618 | /* |
619 | * Src.x1 can be odd when do clip, but yuv plane start point | |
620 | * need align with 2 pixel. | |
621 | */ | |
622 | if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2)) | |
2048e328 | 623 | return -EINVAL; |
2048e328 | 624 | |
63ebb9fa | 625 | vop_plane_state->enable = true; |
2048e328 | 626 | |
63ebb9fa | 627 | return 0; |
84c7f8ca | 628 | |
63ebb9fa MY |
629 | out_disable: |
630 | vop_plane_state->enable = false; | |
631 | return 0; | |
632 | } | |
2048e328 | 633 | |
63ebb9fa MY |
634 | static void vop_plane_atomic_disable(struct drm_plane *plane, |
635 | struct drm_plane_state *old_state) | |
636 | { | |
637 | struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state); | |
638 | struct vop_win *vop_win = to_vop_win(plane); | |
639 | const struct vop_win_data *win = vop_win->data; | |
640 | struct vop *vop = to_vop(old_state->crtc); | |
2048e328 | 641 | |
63ebb9fa MY |
642 | if (!old_state->crtc) |
643 | return; | |
2048e328 | 644 | |
63ebb9fa | 645 | spin_lock(&vop->reg_lock); |
2048e328 | 646 | |
63ebb9fa | 647 | VOP_WIN_SET(vop, win, enable, 0); |
84c7f8ca | 648 | |
63ebb9fa | 649 | spin_unlock(&vop->reg_lock); |
84c7f8ca | 650 | |
63ebb9fa MY |
651 | vop_plane_state->enable = false; |
652 | } | |
84c7f8ca | 653 | |
63ebb9fa MY |
654 | static void vop_plane_atomic_update(struct drm_plane *plane, |
655 | struct drm_plane_state *old_state) | |
656 | { | |
657 | struct drm_plane_state *state = plane->state; | |
658 | struct drm_crtc *crtc = state->crtc; | |
659 | struct vop_win *vop_win = to_vop_win(plane); | |
660 | struct vop_plane_state *vop_plane_state = to_vop_plane_state(state); | |
661 | const struct vop_win_data *win = vop_win->data; | |
662 | struct vop *vop = to_vop(state->crtc); | |
663 | struct drm_framebuffer *fb = state->fb; | |
664 | unsigned int actual_w, actual_h; | |
665 | unsigned int dsp_stx, dsp_sty; | |
666 | uint32_t act_info, dsp_info, dsp_st; | |
667 | struct drm_rect *src = &vop_plane_state->src; | |
668 | struct drm_rect *dest = &vop_plane_state->dest; | |
669 | struct drm_gem_object *obj, *uv_obj; | |
670 | struct rockchip_gem_object *rk_obj, *rk_uv_obj; | |
671 | unsigned long offset; | |
672 | dma_addr_t dma_addr; | |
673 | uint32_t val; | |
674 | bool rb_swap; | |
84c7f8ca | 675 | |
2048e328 | 676 | /* |
63ebb9fa | 677 | * can't update plane when vop is disabled. |
2048e328 | 678 | */ |
63ebb9fa MY |
679 | if (!crtc) |
680 | return; | |
2048e328 | 681 | |
63ebb9fa MY |
682 | if (WARN_ON(!vop->is_enabled)) |
683 | return; | |
2048e328 | 684 | |
63ebb9fa MY |
685 | if (!vop_plane_state->enable) { |
686 | vop_plane_atomic_disable(plane, old_state); | |
687 | return; | |
2048e328 | 688 | } |
63ebb9fa MY |
689 | |
690 | obj = rockchip_fb_get_gem_obj(fb, 0); | |
691 | rk_obj = to_rockchip_obj(obj); | |
692 | ||
693 | actual_w = drm_rect_width(src) >> 16; | |
694 | actual_h = drm_rect_height(src) >> 16; | |
695 | act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); | |
696 | ||
697 | dsp_info = (drm_rect_height(dest) - 1) << 16; | |
698 | dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; | |
699 | ||
700 | dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; | |
701 | dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; | |
702 | dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); | |
703 | ||
704 | offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0); | |
705 | offset += (src->y1 >> 16) * fb->pitches[0]; | |
706 | vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0]; | |
2048e328 MY |
707 | |
708 | spin_lock(&vop->reg_lock); | |
709 | ||
63ebb9fa MY |
710 | VOP_WIN_SET(vop, win, format, vop_plane_state->format); |
711 | VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2); | |
712 | VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst); | |
713 | if (is_yuv_support(fb->pixel_format)) { | |
714 | int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format); | |
715 | int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format); | |
716 | int bpp = drm_format_plane_cpp(fb->pixel_format, 1); | |
717 | ||
718 | uv_obj = rockchip_fb_get_gem_obj(fb, 1); | |
719 | rk_uv_obj = to_rockchip_obj(uv_obj); | |
720 | ||
721 | offset = (src->x1 >> 16) * bpp / hsub; | |
722 | offset += (src->y1 >> 16) * fb->pitches[1] / vsub; | |
723 | ||
724 | dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; | |
725 | VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2); | |
726 | VOP_WIN_SET(vop, win, uv_mst, dma_addr); | |
84c7f8ca | 727 | } |
4c156c21 MY |
728 | |
729 | if (win->phy->scl) | |
730 | scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, | |
63ebb9fa | 731 | drm_rect_width(dest), drm_rect_height(dest), |
4c156c21 MY |
732 | fb->pixel_format); |
733 | ||
63ebb9fa MY |
734 | VOP_WIN_SET(vop, win, act_info, act_info); |
735 | VOP_WIN_SET(vop, win, dsp_info, dsp_info); | |
736 | VOP_WIN_SET(vop, win, dsp_st, dsp_st); | |
4c156c21 | 737 | |
63ebb9fa | 738 | rb_swap = has_rb_swapped(fb->pixel_format); |
85a359f2 | 739 | VOP_WIN_SET(vop, win, rb_swap, rb_swap); |
2048e328 | 740 | |
63ebb9fa | 741 | if (is_alpha_support(fb->pixel_format)) { |
2048e328 MY |
742 | VOP_WIN_SET(vop, win, dst_alpha_ctl, |
743 | DST_FACTOR_M0(ALPHA_SRC_INVERSE)); | |
744 | val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | | |
745 | SRC_ALPHA_M0(ALPHA_STRAIGHT) | | |
746 | SRC_BLEND_M0(ALPHA_PER_PIX) | | |
747 | SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | | |
748 | SRC_FACTOR_M0(ALPHA_ONE); | |
749 | VOP_WIN_SET(vop, win, src_alpha_ctl, val); | |
750 | } else { | |
751 | VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); | |
752 | } | |
753 | ||
754 | VOP_WIN_SET(vop, win, enable, 1); | |
2048e328 | 755 | spin_unlock(&vop->reg_lock); |
2048e328 MY |
756 | } |
757 | ||
63ebb9fa MY |
758 | static const struct drm_plane_helper_funcs plane_helper_funcs = { |
759 | .atomic_check = vop_plane_atomic_check, | |
760 | .atomic_update = vop_plane_atomic_update, | |
761 | .atomic_disable = vop_plane_atomic_disable, | |
762 | }; | |
2048e328 | 763 | |
63ebb9fa | 764 | void vop_atomic_plane_reset(struct drm_plane *plane) |
2048e328 | 765 | { |
63ebb9fa MY |
766 | struct vop_plane_state *vop_plane_state = |
767 | to_vop_plane_state(plane->state); | |
2048e328 | 768 | |
63ebb9fa MY |
769 | if (plane->state && plane->state->fb) |
770 | drm_framebuffer_unreference(plane->state->fb); | |
771 | ||
772 | kfree(vop_plane_state); | |
773 | vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL); | |
774 | if (!vop_plane_state) | |
775 | return; | |
2048e328 | 776 | |
63ebb9fa MY |
777 | plane->state = &vop_plane_state->base; |
778 | plane->state->plane = plane; | |
2048e328 MY |
779 | } |
780 | ||
63ebb9fa MY |
781 | struct drm_plane_state * |
782 | vop_atomic_plane_duplicate_state(struct drm_plane *plane) | |
2048e328 | 783 | { |
63ebb9fa MY |
784 | struct vop_plane_state *old_vop_plane_state; |
785 | struct vop_plane_state *vop_plane_state; | |
2048e328 | 786 | |
63ebb9fa MY |
787 | if (WARN_ON(!plane->state)) |
788 | return NULL; | |
2048e328 | 789 | |
63ebb9fa MY |
790 | old_vop_plane_state = to_vop_plane_state(plane->state); |
791 | vop_plane_state = kmemdup(old_vop_plane_state, | |
792 | sizeof(*vop_plane_state), GFP_KERNEL); | |
793 | if (!vop_plane_state) | |
794 | return NULL; | |
2048e328 | 795 | |
63ebb9fa MY |
796 | __drm_atomic_helper_plane_duplicate_state(plane, |
797 | &vop_plane_state->base); | |
2048e328 | 798 | |
63ebb9fa | 799 | return &vop_plane_state->base; |
2048e328 MY |
800 | } |
801 | ||
63ebb9fa MY |
802 | static void vop_atomic_plane_destroy_state(struct drm_plane *plane, |
803 | struct drm_plane_state *state) | |
2048e328 | 804 | { |
63ebb9fa MY |
805 | struct vop_plane_state *vop_state = to_vop_plane_state(state); |
806 | ||
807 | __drm_atomic_helper_plane_destroy_state(plane, state); | |
808 | ||
809 | kfree(vop_state); | |
2048e328 MY |
810 | } |
811 | ||
812 | static const struct drm_plane_funcs vop_plane_funcs = { | |
63ebb9fa MY |
813 | .update_plane = drm_atomic_helper_update_plane, |
814 | .disable_plane = drm_atomic_helper_disable_plane, | |
2048e328 | 815 | .destroy = vop_plane_destroy, |
63ebb9fa MY |
816 | .reset = vop_atomic_plane_reset, |
817 | .atomic_duplicate_state = vop_atomic_plane_duplicate_state, | |
818 | .atomic_destroy_state = vop_atomic_plane_destroy_state, | |
2048e328 MY |
819 | }; |
820 | ||
821 | int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, | |
822 | int connector_type, | |
823 | int out_mode) | |
824 | { | |
825 | struct vop *vop = to_vop(crtc); | |
826 | ||
d0e20d0e MY |
827 | if (WARN_ON(!vop->is_enabled)) |
828 | return -EINVAL; | |
829 | ||
830 | switch (connector_type) { | |
831 | case DRM_MODE_CONNECTOR_LVDS: | |
832 | VOP_CTRL_SET(vop, rgb_en, 1); | |
833 | break; | |
834 | case DRM_MODE_CONNECTOR_eDP: | |
835 | VOP_CTRL_SET(vop, edp_en, 1); | |
836 | break; | |
837 | case DRM_MODE_CONNECTOR_HDMIA: | |
838 | VOP_CTRL_SET(vop, hdmi_en, 1); | |
839 | break; | |
84e05408 CZ |
840 | case DRM_MODE_CONNECTOR_DSI: |
841 | VOP_CTRL_SET(vop, mipi_en, 1); | |
842 | break; | |
d0e20d0e MY |
843 | default: |
844 | DRM_ERROR("unsupport connector_type[%d]\n", connector_type); | |
845 | return -EINVAL; | |
846 | }; | |
847 | VOP_CTRL_SET(vop, out_mode, out_mode); | |
2048e328 MY |
848 | |
849 | return 0; | |
850 | } | |
f66a1627 | 851 | EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config); |
2048e328 MY |
852 | |
853 | static int vop_crtc_enable_vblank(struct drm_crtc *crtc) | |
854 | { | |
855 | struct vop *vop = to_vop(crtc); | |
856 | unsigned long flags; | |
857 | ||
63ebb9fa | 858 | if (WARN_ON(!vop->is_enabled)) |
2048e328 MY |
859 | return -EPERM; |
860 | ||
861 | spin_lock_irqsave(&vop->irq_lock, flags); | |
862 | ||
dbb3d944 | 863 | VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); |
2048e328 MY |
864 | |
865 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
866 | ||
867 | return 0; | |
868 | } | |
869 | ||
870 | static void vop_crtc_disable_vblank(struct drm_crtc *crtc) | |
871 | { | |
872 | struct vop *vop = to_vop(crtc); | |
873 | unsigned long flags; | |
874 | ||
63ebb9fa | 875 | if (WARN_ON(!vop->is_enabled)) |
2048e328 | 876 | return; |
31e980c5 | 877 | |
2048e328 | 878 | spin_lock_irqsave(&vop->irq_lock, flags); |
dbb3d944 MY |
879 | |
880 | VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); | |
881 | ||
2048e328 MY |
882 | spin_unlock_irqrestore(&vop->irq_lock, flags); |
883 | } | |
884 | ||
63ebb9fa MY |
885 | static void vop_crtc_wait_for_update(struct drm_crtc *crtc) |
886 | { | |
887 | struct vop *vop = to_vop(crtc); | |
888 | ||
889 | reinit_completion(&vop->wait_update_complete); | |
890 | WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100)); | |
891 | } | |
892 | ||
f135046e JK |
893 | static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc, |
894 | struct drm_file *file_priv) | |
895 | { | |
896 | struct drm_device *drm = crtc->dev; | |
897 | struct vop *vop = to_vop(crtc); | |
898 | struct drm_pending_vblank_event *e; | |
899 | unsigned long flags; | |
900 | ||
901 | spin_lock_irqsave(&drm->event_lock, flags); | |
902 | e = vop->event; | |
903 | if (e && e->base.file_priv == file_priv) { | |
904 | vop->event = NULL; | |
905 | ||
906 | e->base.destroy(&e->base); | |
907 | file_priv->event_space += sizeof(e->event); | |
908 | } | |
909 | spin_unlock_irqrestore(&drm->event_lock, flags); | |
910 | } | |
911 | ||
2048e328 MY |
912 | static const struct rockchip_crtc_funcs private_crtc_funcs = { |
913 | .enable_vblank = vop_crtc_enable_vblank, | |
914 | .disable_vblank = vop_crtc_disable_vblank, | |
63ebb9fa | 915 | .wait_for_update = vop_crtc_wait_for_update, |
f135046e | 916 | .cancel_pending_vblank = vop_crtc_cancel_pending_vblank, |
2048e328 MY |
917 | }; |
918 | ||
2048e328 MY |
919 | static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, |
920 | const struct drm_display_mode *mode, | |
921 | struct drm_display_mode *adjusted_mode) | |
922 | { | |
b59b8de3 CZ |
923 | struct vop *vop = to_vop(crtc); |
924 | ||
b59b8de3 CZ |
925 | adjusted_mode->clock = |
926 | clk_round_rate(vop->dclk, mode->clock * 1000) / 1000; | |
927 | ||
2048e328 MY |
928 | return true; |
929 | } | |
930 | ||
63ebb9fa | 931 | static void vop_crtc_enable(struct drm_crtc *crtc) |
2048e328 MY |
932 | { |
933 | struct vop *vop = to_vop(crtc); | |
63ebb9fa | 934 | struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; |
2048e328 MY |
935 | u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; |
936 | u16 hdisplay = adjusted_mode->hdisplay; | |
937 | u16 htotal = adjusted_mode->htotal; | |
938 | u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; | |
939 | u16 hact_end = hact_st + hdisplay; | |
940 | u16 vdisplay = adjusted_mode->vdisplay; | |
941 | u16 vtotal = adjusted_mode->vtotal; | |
942 | u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; | |
943 | u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; | |
944 | u16 vact_end = vact_st + vdisplay; | |
2048e328 MY |
945 | uint32_t val; |
946 | ||
63ebb9fa | 947 | vop_enable(crtc); |
2048e328 | 948 | /* |
ce3887ed MY |
949 | * If dclk rate is zero, mean that scanout is stop, |
950 | * we don't need wait any more. | |
2048e328 | 951 | */ |
ce3887ed MY |
952 | if (clk_get_rate(vop->dclk)) { |
953 | /* | |
954 | * Rk3288 vop timing register is immediately, when configure | |
955 | * display timing on display time, may cause tearing. | |
956 | * | |
957 | * Vop standby will take effect at end of current frame, | |
958 | * if dsp hold valid irq happen, it means standby complete. | |
959 | * | |
960 | * mode set: | |
961 | * standby and wait complete --> |---- | |
962 | * | display time | |
963 | * |---- | |
964 | * |---> dsp hold irq | |
965 | * configure display timing --> | | |
966 | * standby exit | | |
967 | * | new frame start. | |
968 | */ | |
969 | ||
970 | reinit_completion(&vop->dsp_hold_completion); | |
971 | vop_dsp_hold_valid_irq_enable(vop); | |
972 | ||
973 | spin_lock(&vop->reg_lock); | |
974 | ||
975 | VOP_CTRL_SET(vop, standby, 1); | |
976 | ||
977 | spin_unlock(&vop->reg_lock); | |
978 | ||
979 | wait_for_completion(&vop->dsp_hold_completion); | |
980 | ||
981 | vop_dsp_hold_valid_irq_disable(vop); | |
982 | } | |
2048e328 | 983 | |
2048e328 | 984 | val = 0x8; |
44ddb7ef MY |
985 | val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; |
986 | val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); | |
2048e328 MY |
987 | VOP_CTRL_SET(vop, pin_pol, val); |
988 | ||
989 | VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); | |
990 | val = hact_st << 16; | |
991 | val |= hact_end; | |
992 | VOP_CTRL_SET(vop, hact_st_end, val); | |
993 | VOP_CTRL_SET(vop, hpost_st_end, val); | |
994 | ||
995 | VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); | |
996 | val = vact_st << 16; | |
997 | val |= vact_end; | |
998 | VOP_CTRL_SET(vop, vact_st_end, val); | |
999 | VOP_CTRL_SET(vop, vpost_st_end, val); | |
1000 | ||
2048e328 | 1001 | clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); |
ce3887ed MY |
1002 | |
1003 | VOP_CTRL_SET(vop, standby, 0); | |
2048e328 MY |
1004 | } |
1005 | ||
63ebb9fa MY |
1006 | static void vop_crtc_atomic_flush(struct drm_crtc *crtc, |
1007 | struct drm_crtc_state *old_crtc_state) | |
2048e328 MY |
1008 | { |
1009 | struct vop *vop = to_vop(crtc); | |
2048e328 | 1010 | |
63ebb9fa MY |
1011 | if (WARN_ON(!vop->is_enabled)) |
1012 | return; | |
2048e328 | 1013 | |
63ebb9fa | 1014 | spin_lock(&vop->reg_lock); |
2048e328 | 1015 | |
63ebb9fa | 1016 | vop_cfg_done(vop); |
2048e328 | 1017 | |
63ebb9fa | 1018 | spin_unlock(&vop->reg_lock); |
2048e328 MY |
1019 | } |
1020 | ||
63ebb9fa MY |
1021 | static void vop_crtc_atomic_begin(struct drm_crtc *crtc, |
1022 | struct drm_crtc_state *old_crtc_state) | |
2048e328 | 1023 | { |
63ebb9fa | 1024 | struct vop *vop = to_vop(crtc); |
2048e328 | 1025 | |
63ebb9fa MY |
1026 | if (crtc->state->event) { |
1027 | WARN_ON(drm_crtc_vblank_get(crtc) != 0); | |
2048e328 | 1028 | |
63ebb9fa MY |
1029 | vop->event = crtc->state->event; |
1030 | crtc->state->event = NULL; | |
1031 | } | |
2048e328 MY |
1032 | } |
1033 | ||
63ebb9fa MY |
1034 | static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { |
1035 | .enable = vop_crtc_enable, | |
1036 | .disable = vop_crtc_disable, | |
1037 | .mode_fixup = vop_crtc_mode_fixup, | |
1038 | .atomic_flush = vop_crtc_atomic_flush, | |
1039 | .atomic_begin = vop_crtc_atomic_begin, | |
1040 | }; | |
1041 | ||
2048e328 MY |
1042 | static void vop_crtc_destroy(struct drm_crtc *crtc) |
1043 | { | |
1044 | drm_crtc_cleanup(crtc); | |
1045 | } | |
1046 | ||
1047 | static const struct drm_crtc_funcs vop_crtc_funcs = { | |
63ebb9fa MY |
1048 | .set_config = drm_atomic_helper_set_config, |
1049 | .page_flip = drm_atomic_helper_page_flip, | |
2048e328 | 1050 | .destroy = vop_crtc_destroy, |
63ebb9fa MY |
1051 | .reset = drm_atomic_helper_crtc_reset, |
1052 | .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, | |
1053 | .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, | |
2048e328 MY |
1054 | }; |
1055 | ||
63ebb9fa | 1056 | static bool vop_win_pending_is_complete(struct vop_win *vop_win) |
2048e328 | 1057 | { |
63ebb9fa MY |
1058 | struct drm_plane *plane = &vop_win->base; |
1059 | struct vop_plane_state *state = to_vop_plane_state(plane->state); | |
1060 | dma_addr_t yrgb_mst; | |
2048e328 | 1061 | |
63ebb9fa MY |
1062 | if (!state->enable) |
1063 | return VOP_WIN_GET(vop_win->vop, vop_win->data, enable) == 0; | |
2048e328 | 1064 | |
63ebb9fa | 1065 | yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data); |
2048e328 | 1066 | |
63ebb9fa | 1067 | return yrgb_mst == state->yrgb_mst; |
2048e328 MY |
1068 | } |
1069 | ||
63ebb9fa | 1070 | static void vop_handle_vblank(struct vop *vop) |
2048e328 | 1071 | { |
63ebb9fa MY |
1072 | struct drm_device *drm = vop->drm_dev; |
1073 | struct drm_crtc *crtc = &vop->crtc; | |
1074 | unsigned long flags; | |
1075 | int i; | |
2048e328 | 1076 | |
63ebb9fa MY |
1077 | for (i = 0; i < vop->data->win_size; i++) { |
1078 | if (!vop_win_pending_is_complete(&vop->win[i])) | |
1079 | return; | |
2048e328 MY |
1080 | } |
1081 | ||
63ebb9fa MY |
1082 | if (vop->event) { |
1083 | spin_lock_irqsave(&drm->event_lock, flags); | |
2048e328 | 1084 | |
63ebb9fa MY |
1085 | drm_crtc_send_vblank_event(crtc, vop->event); |
1086 | drm_crtc_vblank_put(crtc); | |
1087 | vop->event = NULL; | |
2048e328 | 1088 | |
63ebb9fa | 1089 | spin_unlock_irqrestore(&drm->event_lock, flags); |
2048e328 | 1090 | } |
63ebb9fa MY |
1091 | if (!completion_done(&vop->wait_update_complete)) |
1092 | complete(&vop->wait_update_complete); | |
2048e328 MY |
1093 | } |
1094 | ||
1095 | static irqreturn_t vop_isr(int irq, void *data) | |
1096 | { | |
1097 | struct vop *vop = data; | |
b5f7b755 | 1098 | struct drm_crtc *crtc = &vop->crtc; |
dbb3d944 | 1099 | uint32_t active_irqs; |
2048e328 | 1100 | unsigned long flags; |
1067219b | 1101 | int ret = IRQ_NONE; |
2048e328 MY |
1102 | |
1103 | /* | |
dbb3d944 | 1104 | * interrupt register has interrupt status, enable and clear bits, we |
2048e328 MY |
1105 | * must hold irq_lock to avoid a race with enable/disable_vblank(). |
1106 | */ | |
1107 | spin_lock_irqsave(&vop->irq_lock, flags); | |
dbb3d944 MY |
1108 | |
1109 | active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); | |
2048e328 MY |
1110 | /* Clear all active interrupt sources */ |
1111 | if (active_irqs) | |
dbb3d944 MY |
1112 | VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); |
1113 | ||
2048e328 MY |
1114 | spin_unlock_irqrestore(&vop->irq_lock, flags); |
1115 | ||
1116 | /* This is expected for vop iommu irqs, since the irq is shared */ | |
1117 | if (!active_irqs) | |
1118 | return IRQ_NONE; | |
1119 | ||
1067219b MY |
1120 | if (active_irqs & DSP_HOLD_VALID_INTR) { |
1121 | complete(&vop->dsp_hold_completion); | |
1122 | active_irqs &= ~DSP_HOLD_VALID_INTR; | |
1123 | ret = IRQ_HANDLED; | |
2048e328 MY |
1124 | } |
1125 | ||
1067219b | 1126 | if (active_irqs & FS_INTR) { |
b5f7b755 | 1127 | drm_crtc_handle_vblank(crtc); |
63ebb9fa | 1128 | vop_handle_vblank(vop); |
1067219b | 1129 | active_irqs &= ~FS_INTR; |
63ebb9fa | 1130 | ret = IRQ_HANDLED; |
1067219b | 1131 | } |
2048e328 | 1132 | |
1067219b MY |
1133 | /* Unhandled irqs are spurious. */ |
1134 | if (active_irqs) | |
1135 | DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs); | |
1136 | ||
1137 | return ret; | |
2048e328 MY |
1138 | } |
1139 | ||
1140 | static int vop_create_crtc(struct vop *vop) | |
1141 | { | |
1142 | const struct vop_data *vop_data = vop->data; | |
1143 | struct device *dev = vop->dev; | |
1144 | struct drm_device *drm_dev = vop->drm_dev; | |
1145 | struct drm_plane *primary = NULL, *cursor = NULL, *plane; | |
1146 | struct drm_crtc *crtc = &vop->crtc; | |
1147 | struct device_node *port; | |
1148 | int ret; | |
1149 | int i; | |
1150 | ||
1151 | /* | |
1152 | * Create drm_plane for primary and cursor planes first, since we need | |
1153 | * to pass them to drm_crtc_init_with_planes, which sets the | |
1154 | * "possible_crtcs" to the newly initialized crtc. | |
1155 | */ | |
1156 | for (i = 0; i < vop_data->win_size; i++) { | |
1157 | struct vop_win *vop_win = &vop->win[i]; | |
1158 | const struct vop_win_data *win_data = vop_win->data; | |
1159 | ||
1160 | if (win_data->type != DRM_PLANE_TYPE_PRIMARY && | |
1161 | win_data->type != DRM_PLANE_TYPE_CURSOR) | |
1162 | continue; | |
1163 | ||
1164 | ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, | |
1165 | 0, &vop_plane_funcs, | |
1166 | win_data->phy->data_formats, | |
1167 | win_data->phy->nformats, | |
b0b3b795 | 1168 | win_data->type, NULL); |
2048e328 MY |
1169 | if (ret) { |
1170 | DRM_ERROR("failed to initialize plane\n"); | |
1171 | goto err_cleanup_planes; | |
1172 | } | |
1173 | ||
1174 | plane = &vop_win->base; | |
63ebb9fa | 1175 | drm_plane_helper_add(plane, &plane_helper_funcs); |
2048e328 MY |
1176 | if (plane->type == DRM_PLANE_TYPE_PRIMARY) |
1177 | primary = plane; | |
1178 | else if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
1179 | cursor = plane; | |
1180 | } | |
1181 | ||
1182 | ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, | |
f9882876 | 1183 | &vop_crtc_funcs, NULL); |
2048e328 MY |
1184 | if (ret) |
1185 | return ret; | |
1186 | ||
1187 | drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); | |
1188 | ||
1189 | /* | |
1190 | * Create drm_planes for overlay windows with possible_crtcs restricted | |
1191 | * to the newly created crtc. | |
1192 | */ | |
1193 | for (i = 0; i < vop_data->win_size; i++) { | |
1194 | struct vop_win *vop_win = &vop->win[i]; | |
1195 | const struct vop_win_data *win_data = vop_win->data; | |
1196 | unsigned long possible_crtcs = 1 << drm_crtc_index(crtc); | |
1197 | ||
1198 | if (win_data->type != DRM_PLANE_TYPE_OVERLAY) | |
1199 | continue; | |
1200 | ||
1201 | ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, | |
1202 | possible_crtcs, | |
1203 | &vop_plane_funcs, | |
1204 | win_data->phy->data_formats, | |
1205 | win_data->phy->nformats, | |
b0b3b795 | 1206 | win_data->type, NULL); |
2048e328 MY |
1207 | if (ret) { |
1208 | DRM_ERROR("failed to initialize overlay plane\n"); | |
1209 | goto err_cleanup_crtc; | |
1210 | } | |
63ebb9fa | 1211 | drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); |
2048e328 MY |
1212 | } |
1213 | ||
1214 | port = of_get_child_by_name(dev->of_node, "port"); | |
1215 | if (!port) { | |
1216 | DRM_ERROR("no port node found in %s\n", | |
1217 | dev->of_node->full_name); | |
1218 | goto err_cleanup_crtc; | |
1219 | } | |
1220 | ||
1067219b | 1221 | init_completion(&vop->dsp_hold_completion); |
63ebb9fa | 1222 | init_completion(&vop->wait_update_complete); |
2048e328 | 1223 | crtc->port = port; |
b5f7b755 | 1224 | rockchip_register_crtc_funcs(crtc, &private_crtc_funcs); |
2048e328 MY |
1225 | |
1226 | return 0; | |
1227 | ||
1228 | err_cleanup_crtc: | |
1229 | drm_crtc_cleanup(crtc); | |
1230 | err_cleanup_planes: | |
1231 | list_for_each_entry(plane, &drm_dev->mode_config.plane_list, head) | |
1232 | drm_plane_cleanup(plane); | |
1233 | return ret; | |
1234 | } | |
1235 | ||
1236 | static void vop_destroy_crtc(struct vop *vop) | |
1237 | { | |
1238 | struct drm_crtc *crtc = &vop->crtc; | |
1239 | ||
b5f7b755 | 1240 | rockchip_unregister_crtc_funcs(crtc); |
2048e328 MY |
1241 | of_node_put(crtc->port); |
1242 | drm_crtc_cleanup(crtc); | |
1243 | } | |
1244 | ||
1245 | static int vop_initial(struct vop *vop) | |
1246 | { | |
1247 | const struct vop_data *vop_data = vop->data; | |
1248 | const struct vop_reg_data *init_table = vop_data->init_table; | |
1249 | struct reset_control *ahb_rst; | |
1250 | int i, ret; | |
1251 | ||
1252 | vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); | |
1253 | if (IS_ERR(vop->hclk)) { | |
1254 | dev_err(vop->dev, "failed to get hclk source\n"); | |
1255 | return PTR_ERR(vop->hclk); | |
1256 | } | |
1257 | vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); | |
1258 | if (IS_ERR(vop->aclk)) { | |
1259 | dev_err(vop->dev, "failed to get aclk source\n"); | |
1260 | return PTR_ERR(vop->aclk); | |
1261 | } | |
1262 | vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); | |
1263 | if (IS_ERR(vop->dclk)) { | |
1264 | dev_err(vop->dev, "failed to get dclk source\n"); | |
1265 | return PTR_ERR(vop->dclk); | |
1266 | } | |
1267 | ||
2048e328 MY |
1268 | ret = clk_prepare(vop->dclk); |
1269 | if (ret < 0) { | |
1270 | dev_err(vop->dev, "failed to prepare dclk\n"); | |
d7b53fd9 | 1271 | return ret; |
2048e328 MY |
1272 | } |
1273 | ||
d7b53fd9 SS |
1274 | /* Enable both the hclk and aclk to setup the vop */ |
1275 | ret = clk_prepare_enable(vop->hclk); | |
2048e328 | 1276 | if (ret < 0) { |
d7b53fd9 | 1277 | dev_err(vop->dev, "failed to prepare/enable hclk\n"); |
2048e328 MY |
1278 | goto err_unprepare_dclk; |
1279 | } | |
1280 | ||
d7b53fd9 | 1281 | ret = clk_prepare_enable(vop->aclk); |
2048e328 | 1282 | if (ret < 0) { |
d7b53fd9 SS |
1283 | dev_err(vop->dev, "failed to prepare/enable aclk\n"); |
1284 | goto err_disable_hclk; | |
2048e328 | 1285 | } |
d7b53fd9 | 1286 | |
2048e328 MY |
1287 | /* |
1288 | * do hclk_reset, reset all vop registers. | |
1289 | */ | |
1290 | ahb_rst = devm_reset_control_get(vop->dev, "ahb"); | |
1291 | if (IS_ERR(ahb_rst)) { | |
1292 | dev_err(vop->dev, "failed to get ahb reset\n"); | |
1293 | ret = PTR_ERR(ahb_rst); | |
d7b53fd9 | 1294 | goto err_disable_aclk; |
2048e328 MY |
1295 | } |
1296 | reset_control_assert(ahb_rst); | |
1297 | usleep_range(10, 20); | |
1298 | reset_control_deassert(ahb_rst); | |
1299 | ||
1300 | memcpy(vop->regsbak, vop->regs, vop->len); | |
1301 | ||
1302 | for (i = 0; i < vop_data->table_size; i++) | |
1303 | vop_writel(vop, init_table[i].offset, init_table[i].value); | |
1304 | ||
1305 | for (i = 0; i < vop_data->win_size; i++) { | |
1306 | const struct vop_win_data *win = &vop_data->win[i]; | |
1307 | ||
1308 | VOP_WIN_SET(vop, win, enable, 0); | |
1309 | } | |
1310 | ||
1311 | vop_cfg_done(vop); | |
1312 | ||
1313 | /* | |
1314 | * do dclk_reset, let all config take affect. | |
1315 | */ | |
1316 | vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); | |
1317 | if (IS_ERR(vop->dclk_rst)) { | |
1318 | dev_err(vop->dev, "failed to get dclk reset\n"); | |
1319 | ret = PTR_ERR(vop->dclk_rst); | |
d7b53fd9 | 1320 | goto err_disable_aclk; |
2048e328 MY |
1321 | } |
1322 | reset_control_assert(vop->dclk_rst); | |
1323 | usleep_range(10, 20); | |
1324 | reset_control_deassert(vop->dclk_rst); | |
1325 | ||
1326 | clk_disable(vop->hclk); | |
d7b53fd9 | 1327 | clk_disable(vop->aclk); |
2048e328 | 1328 | |
31e980c5 | 1329 | vop->is_enabled = false; |
2048e328 MY |
1330 | |
1331 | return 0; | |
1332 | ||
d7b53fd9 SS |
1333 | err_disable_aclk: |
1334 | clk_disable_unprepare(vop->aclk); | |
2048e328 | 1335 | err_disable_hclk: |
d7b53fd9 | 1336 | clk_disable_unprepare(vop->hclk); |
2048e328 MY |
1337 | err_unprepare_dclk: |
1338 | clk_unprepare(vop->dclk); | |
2048e328 MY |
1339 | return ret; |
1340 | } | |
1341 | ||
1342 | /* | |
1343 | * Initialize the vop->win array elements. | |
1344 | */ | |
1345 | static void vop_win_init(struct vop *vop) | |
1346 | { | |
1347 | const struct vop_data *vop_data = vop->data; | |
1348 | unsigned int i; | |
1349 | ||
1350 | for (i = 0; i < vop_data->win_size; i++) { | |
1351 | struct vop_win *vop_win = &vop->win[i]; | |
1352 | const struct vop_win_data *win_data = &vop_data->win[i]; | |
1353 | ||
1354 | vop_win->data = win_data; | |
1355 | vop_win->vop = vop; | |
2048e328 MY |
1356 | } |
1357 | } | |
1358 | ||
1359 | static int vop_bind(struct device *dev, struct device *master, void *data) | |
1360 | { | |
1361 | struct platform_device *pdev = to_platform_device(dev); | |
2048e328 MY |
1362 | const struct vop_data *vop_data; |
1363 | struct drm_device *drm_dev = data; | |
1364 | struct vop *vop; | |
1365 | struct resource *res; | |
1366 | size_t alloc_size; | |
3ea68922 | 1367 | int ret, irq; |
2048e328 | 1368 | |
a67719d1 | 1369 | vop_data = of_device_get_match_data(dev); |
2048e328 MY |
1370 | if (!vop_data) |
1371 | return -ENODEV; | |
1372 | ||
1373 | /* Allocate vop struct and its vop_win array */ | |
1374 | alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size; | |
1375 | vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL); | |
1376 | if (!vop) | |
1377 | return -ENOMEM; | |
1378 | ||
1379 | vop->dev = dev; | |
1380 | vop->data = vop_data; | |
1381 | vop->drm_dev = drm_dev; | |
1382 | dev_set_drvdata(dev, vop); | |
1383 | ||
1384 | vop_win_init(vop); | |
1385 | ||
1386 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1387 | vop->len = resource_size(res); | |
1388 | vop->regs = devm_ioremap_resource(dev, res); | |
1389 | if (IS_ERR(vop->regs)) | |
1390 | return PTR_ERR(vop->regs); | |
1391 | ||
1392 | vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); | |
1393 | if (!vop->regsbak) | |
1394 | return -ENOMEM; | |
1395 | ||
1396 | ret = vop_initial(vop); | |
1397 | if (ret < 0) { | |
1398 | dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret); | |
1399 | return ret; | |
1400 | } | |
1401 | ||
3ea68922 HS |
1402 | irq = platform_get_irq(pdev, 0); |
1403 | if (irq < 0) { | |
2048e328 | 1404 | dev_err(dev, "cannot find irq for vop\n"); |
3ea68922 | 1405 | return irq; |
2048e328 | 1406 | } |
3ea68922 | 1407 | vop->irq = (unsigned int)irq; |
2048e328 MY |
1408 | |
1409 | spin_lock_init(&vop->reg_lock); | |
1410 | spin_lock_init(&vop->irq_lock); | |
1411 | ||
1412 | mutex_init(&vop->vsync_mutex); | |
1413 | ||
63ebb9fa MY |
1414 | ret = devm_request_irq(dev, vop->irq, vop_isr, |
1415 | IRQF_SHARED, dev_name(dev), vop); | |
2048e328 MY |
1416 | if (ret) |
1417 | return ret; | |
1418 | ||
1419 | /* IRQ is initially disabled; it gets enabled in power_on */ | |
1420 | disable_irq(vop->irq); | |
1421 | ||
1422 | ret = vop_create_crtc(vop); | |
1423 | if (ret) | |
1424 | return ret; | |
1425 | ||
1426 | pm_runtime_enable(&pdev->dev); | |
1427 | return 0; | |
1428 | } | |
1429 | ||
1430 | static void vop_unbind(struct device *dev, struct device *master, void *data) | |
1431 | { | |
1432 | struct vop *vop = dev_get_drvdata(dev); | |
1433 | ||
1434 | pm_runtime_disable(dev); | |
1435 | vop_destroy_crtc(vop); | |
1436 | } | |
1437 | ||
a67719d1 | 1438 | const struct component_ops vop_component_ops = { |
2048e328 MY |
1439 | .bind = vop_bind, |
1440 | .unbind = vop_unbind, | |
1441 | }; | |
54255e81 | 1442 | EXPORT_SYMBOL_GPL(vop_component_ops); |