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Merge branch 'drm-etnaviv-next' of git://git.pengutronix.de/git/lst/linux into drm...
[linux-2.6-block.git] / drivers / gpu / drm / rockchip / rockchip_drm_vop.c
CommitLineData
2048e328
MY		 1/*
2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <drm/drm.h>
16#include <drm/drmP.h>
63ebb9fa 17#include <drm/drm_atomic.h>
2048e328
MY		 18#include <drm/drm_crtc.h>
19#include <drm/drm_crtc_helper.h>
47a7eb45 20#include <drm/drm_flip_work.h>
2048e328
MY		 21#include <drm/drm_plane_helper.h>
22
23#include <linux/kernel.h>
00fe6148 24#include <linux/module.h>
2048e328
MY		 25#include <linux/platform_device.h>
26#include <linux/clk.h>
7caecdbe 27#include <linux/iopoll.h>
2048e328
MY		 28#include <linux/of.h>
29#include <linux/of_device.h>
30#include <linux/pm_runtime.h>
31#include <linux/component.h>
32
33#include <linux/reset.h>
34#include <linux/delay.h>
35
36#include "rockchip_drm_drv.h"
37#include "rockchip_drm_gem.h"
38#include "rockchip_drm_fb.h"
5182c1a5 39#include "rockchip_drm_psr.h"
2048e328
MY		 40#include "rockchip_drm_vop.h"
41
d49463ec
MY		 42#define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \
43 vop_mask_write(x, off, mask, shift, v, write_mask, true)
44
45#define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \
46 vop_mask_write(x, off, mask, shift, v, write_mask, false)
2048e328
MY		 47
48#define REG_SET(x, base, reg, v, mode) \
d49463ec
MY		 49 __REG_SET_##mode(x, base + reg.offset, \
50 reg.mask, reg.shift, v, reg.write_mask)
c7647f86 51#define REG_SET_MASK(x, base, reg, mask, v, mode) \
d49463ec
MY		 52 __REG_SET_##mode(x, base + reg.offset, \
53 mask, reg.shift, v, reg.write_mask)
2048e328
MY		 54
55#define VOP_WIN_SET(x, win, name, v) \
56 REG_SET(x, win->base, win->phy->name, v, RELAXED)
4c156c21
MY		 57#define VOP_SCL_SET(x, win, name, v) \
58 REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
1194fffb
MY		 59#define VOP_SCL_SET_EXT(x, win, name, v) \
60 REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED)
2048e328
MY		 61#define VOP_CTRL_SET(x, name, v) \
62 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
63
dbb3d944
MY		 64#define VOP_INTR_GET(vop, name) \
65 vop_read_reg(vop, 0, &vop->data->ctrl->name)
66
c7647f86
JK		 67#define VOP_INTR_SET(vop, name, mask, v) \
68 REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
dbb3d944
MY		 69#define VOP_INTR_SET_TYPE(vop, name, type, v) \
70 do { \
c7647f86 71 int i, reg = 0, mask = 0; \
dbb3d944 72 for (i = 0; i < vop->data->intr->nintrs; i++) { \
c7647f86 73 if (vop->data->intr->intrs[i] & type) { \
dbb3d944 74 reg |= (v) << i; \
c7647f86
JK		 75 mask |= 1 << i; \
76 } \
dbb3d944 77 } \
c7647f86 78 VOP_INTR_SET(vop, name, mask, reg); \
dbb3d944
MY		 79 } while (0)
80#define VOP_INTR_GET_TYPE(vop, name, type) \
81 vop_get_intr_type(vop, &vop->data->intr->name, type)
82
2048e328
MY		 83#define VOP_WIN_GET(x, win, name) \
84 vop_read_reg(x, win->base, &win->phy->name)
85
86#define VOP_WIN_GET_YRGBADDR(vop, win) \
87 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
88
89#define to_vop(x) container_of(x, struct vop, crtc)
90#define to_vop_win(x) container_of(x, struct vop_win, base)
91
47a7eb45
TF		 92enum vop_pending {
93 VOP_PENDING_FB_UNREF,
94};
95
2048e328
MY		 96struct vop_win {
97 struct drm_plane base;
98 const struct vop_win_data *data;
99 struct vop *vop;
2048e328
MY		 100};
101
102struct vop {
103 struct drm_crtc crtc;
104 struct device *dev;
105 struct drm_device *drm_dev;
31e980c5 106 bool is_enabled;
2048e328 107
2048e328
MY		 108 /* mutex vsync_ work */
109 struct mutex vsync_mutex;
110 bool vsync_work_pending;
1067219b 111 struct completion dsp_hold_completion;
4f9d39a7
DV		 112
113 /* protected by dev->event_lock */
63ebb9fa 114 struct drm_pending_vblank_event *event;
2048e328 115
47a7eb45
TF		 116 struct drm_flip_work fb_unref_work;
117 unsigned long pending;
118
69c34e41
YY		 119 struct completion line_flag_completion;
120
2048e328
MY		 121 const struct vop_data *data;
122
123 uint32_t *regsbak;
124 void __iomem *regs;
125
126 /* physical map length of vop register */
127 uint32_t len;
128
129 /* one time only one process allowed to config the register */
130 spinlock_t reg_lock;
131 /* lock vop irq reg */
132 spinlock_t irq_lock;
133
134 unsigned int irq;
135
136 /* vop AHP clk */
137 struct clk *hclk;
138 /* vop dclk */
139 struct clk *dclk;
140 /* vop share memory frequency */
141 struct clk *aclk;
142
143 /* vop dclk reset */
144 struct reset_control *dclk_rst;
145
2048e328
MY		 146 struct vop_win win[];
147};
148
2048e328
MY		 149static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
150{
151 writel(v, vop->regs + offset);
152 vop->regsbak[offset >> 2] = v;
153}
154
155static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
156{
157 return readl(vop->regs + offset);
158}
159
160static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
161 const struct vop_reg *reg)
162{
163 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
164}
165
2048e328 166static inline void vop_mask_write(struct vop *vop, uint32_t offset,
d49463ec
MY		 167 uint32_t mask, uint32_t shift, uint32_t v,
168 bool write_mask, bool relaxed)
2048e328 169{
d49463ec
MY		 170 if (!mask)
171 return;
2048e328 172
d49463ec
MY		 173 if (write_mask) {
174 v = ((v << shift) & 0xffff) | (mask << (shift + 16));
175 } else {
2048e328
MY		 176 uint32_t cached_val = vop->regsbak[offset >> 2];
177
d49463ec
MY		 178 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
179 vop->regsbak[offset >> 2] = v;
2048e328 180 }
d49463ec
MY		 181
182 if (relaxed)
183 writel_relaxed(v, vop->regs + offset);
184 else
185 writel(v, vop->regs + offset);
2048e328
MY		 186}
187
dbb3d944
MY		 188static inline uint32_t vop_get_intr_type(struct vop *vop,
189 const struct vop_reg *reg, int type)
190{
191 uint32_t i, ret = 0;
192 uint32_t regs = vop_read_reg(vop, 0, reg);
193
194 for (i = 0; i < vop->data->intr->nintrs; i++) {
195 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
196 ret |= vop->data->intr->intrs[i];
197 }
198
199 return ret;
200}
201
0cf33fe3
MY		 202static inline void vop_cfg_done(struct vop *vop)
203{
204 VOP_CTRL_SET(vop, cfg_done, 1);
205}
206
85a359f2
TF		 207static bool has_rb_swapped(uint32_t format)
208{
209 switch (format) {
210 case DRM_FORMAT_XBGR8888:
211 case DRM_FORMAT_ABGR8888:
212 case DRM_FORMAT_BGR888:
213 case DRM_FORMAT_BGR565:
214 return true;
215 default:
216 return false;
217 }
218}
219
2048e328
MY		 220static enum vop_data_format vop_convert_format(uint32_t format)
221{
222 switch (format) {
223 case DRM_FORMAT_XRGB8888:
224 case DRM_FORMAT_ARGB8888:
85a359f2
TF		 225 case DRM_FORMAT_XBGR8888:
226 case DRM_FORMAT_ABGR8888:
2048e328
MY		 227 return VOP_FMT_ARGB8888;
228 case DRM_FORMAT_RGB888:
85a359f2 229 case DRM_FORMAT_BGR888:
2048e328
MY		 230 return VOP_FMT_RGB888;
231 case DRM_FORMAT_RGB565:
85a359f2 232 case DRM_FORMAT_BGR565:
2048e328
MY		 233 return VOP_FMT_RGB565;
234 case DRM_FORMAT_NV12:
235 return VOP_FMT_YUV420SP;
236 case DRM_FORMAT_NV16:
237 return VOP_FMT_YUV422SP;
238 case DRM_FORMAT_NV24:
239 return VOP_FMT_YUV444SP;
240 default:
ee4d7899 241 DRM_ERROR("unsupported format[%08x]\n", format);
2048e328
MY		 242 return -EINVAL;
243 }
244}
245
84c7f8ca
MY		 246static bool is_yuv_support(uint32_t format)
247{
248 switch (format) {
249 case DRM_FORMAT_NV12:
250 case DRM_FORMAT_NV16:
251 case DRM_FORMAT_NV24:
252 return true;
253 default:
254 return false;
255 }
256}
257
2048e328
MY		 258static bool is_alpha_support(uint32_t format)
259{
260 switch (format) {
261 case DRM_FORMAT_ARGB8888:
85a359f2 262 case DRM_FORMAT_ABGR8888:
2048e328
MY		 263 return true;
264 default:
265 return false;
266 }
267}
268
4c156c21
MY		 269static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
270 uint32_t dst, bool is_horizontal,
271 int vsu_mode, int *vskiplines)
272{
273 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
274
275 if (is_horizontal) {
276 if (mode == SCALE_UP)
277 val = GET_SCL_FT_BIC(src, dst);
278 else if (mode == SCALE_DOWN)
279 val = GET_SCL_FT_BILI_DN(src, dst);
280 } else {
281 if (mode == SCALE_UP) {
282 if (vsu_mode == SCALE_UP_BIL)
283 val = GET_SCL_FT_BILI_UP(src, dst);
284 else
285 val = GET_SCL_FT_BIC(src, dst);
286 } else if (mode == SCALE_DOWN) {
287 if (vskiplines) {
288 *vskiplines = scl_get_vskiplines(src, dst);
289 val = scl_get_bili_dn_vskip(src, dst,
290 *vskiplines);
291 } else {
292 val = GET_SCL_FT_BILI_DN(src, dst);
293 }
294 }
295 }
296
297 return val;
298}
299
300static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
301 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
302 uint32_t dst_h, uint32_t pixel_format)
303{
304 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
305 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
306 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
307 int hsub = drm_format_horz_chroma_subsampling(pixel_format);
308 int vsub = drm_format_vert_chroma_subsampling(pixel_format);
309 bool is_yuv = is_yuv_support(pixel_format);
310 uint16_t cbcr_src_w = src_w / hsub;
311 uint16_t cbcr_src_h = src_h / vsub;
312 uint16_t vsu_mode;
313 uint16_t lb_mode;
314 uint32_t val;
2db00cf5 315 int vskiplines = 0;
4c156c21
MY		 316
317 if (dst_w > 3840) {
ee4d7899 318 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
4c156c21
MY		 319 return;
320 }
321
1194fffb
MY		 322 if (!win->phy->scl->ext) {
323 VOP_SCL_SET(vop, win, scale_yrgb_x,
324 scl_cal_scale2(src_w, dst_w));
325 VOP_SCL_SET(vop, win, scale_yrgb_y,
326 scl_cal_scale2(src_h, dst_h));
327 if (is_yuv) {
328 VOP_SCL_SET(vop, win, scale_cbcr_x,
ee8662fc 329 scl_cal_scale2(cbcr_src_w, dst_w));
1194fffb 330 VOP_SCL_SET(vop, win, scale_cbcr_y,
ee8662fc 331 scl_cal_scale2(cbcr_src_h, dst_h));
1194fffb
MY		 332 }
333 return;
334 }
335
4c156c21
MY		 336 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
337 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
338
339 if (is_yuv) {
340 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
341 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
342 if (cbcr_hor_scl_mode == SCALE_DOWN)
343 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
344 else
345 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
346 } else {
347 if (yrgb_hor_scl_mode == SCALE_DOWN)
348 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
349 else
350 lb_mode = scl_vop_cal_lb_mode(src_w, false);
351 }
352
1194fffb 353 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
4c156c21
MY		 354 if (lb_mode == LB_RGB_3840X2) {
355 if (yrgb_ver_scl_mode != SCALE_NONE) {
ee4d7899 356 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");
4c156c21
MY		 357 return;
358 }
359 if (cbcr_ver_scl_mode != SCALE_NONE) {
ee4d7899 360 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");
4c156c21
MY		 361 return;
362 }
363 vsu_mode = SCALE_UP_BIL;
364 } else if (lb_mode == LB_RGB_2560X4) {
365 vsu_mode = SCALE_UP_BIL;
366 } else {
367 vsu_mode = SCALE_UP_BIC;
368 }
369
370 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
371 true, 0, NULL);
372 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
373 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
374 false, vsu_mode, &vskiplines);
375 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
376
1194fffb
MY		 377 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
378 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
4c156c21 379
1194fffb
MY		 380 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
381 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
382 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
383 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
384 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
4c156c21
MY		 385 if (is_yuv) {
386 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
387 dst_w, true, 0, NULL);
388 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
389 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
390 dst_h, false, vsu_mode, &vskiplines);
391 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
392
1194fffb
MY		 393 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
394 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
395 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
396 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
397 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
398 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
399 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
4c156c21
MY		 400 }
401}
402
1067219b
MY		 403static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
404{
405 unsigned long flags;
406
407 if (WARN_ON(!vop->is_enabled))
408 return;
409
410 spin_lock_irqsave(&vop->irq_lock, flags);
411
fa374107 412 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
dbb3d944 413 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
1067219b
MY		 414
415 spin_unlock_irqrestore(&vop->irq_lock, flags);
416}
417
418static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
419{
420 unsigned long flags;
421
422 if (WARN_ON(!vop->is_enabled))
423 return;
424
425 spin_lock_irqsave(&vop->irq_lock, flags);
426
dbb3d944 427 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
1067219b
MY		 428
429 spin_unlock_irqrestore(&vop->irq_lock, flags);
430}
431
69c34e41
YY		 432/*
433 * (1) each frame starts at the start of the Vsync pulse which is signaled by
434 * the "FRAME_SYNC" interrupt.
435 * (2) the active data region of each frame ends at dsp_vact_end
436 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
437 * to get "LINE_FLAG" interrupt at the end of the active on screen data.
438 *
439 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
440 * Interrupts
441 * LINE_FLAG -------------------------------+
442 * FRAME_SYNC ----+ |
443 * | |
444 * v v
445 * | Vsync | Vbp | Vactive | Vfp |
446 * ^ ^ ^ ^
447 * | | | |
448 * | | | |
449 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END
450 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END
451 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END
452 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END
453 */
454static bool vop_line_flag_irq_is_enabled(struct vop *vop)
455{
456 uint32_t line_flag_irq;
457 unsigned long flags;
458
459 spin_lock_irqsave(&vop->irq_lock, flags);
460
461 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
462
463 spin_unlock_irqrestore(&vop->irq_lock, flags);
464
465 return !!line_flag_irq;
466}
467
468static void vop_line_flag_irq_enable(struct vop *vop, int line_num)
469{
470 unsigned long flags;
471
472 if (WARN_ON(!vop->is_enabled))
473 return;
474
475 spin_lock_irqsave(&vop->irq_lock, flags);
476
477 VOP_CTRL_SET(vop, line_flag_num[0], line_num);
fa374107 478 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
69c34e41
YY		 479 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
480
481 spin_unlock_irqrestore(&vop->irq_lock, flags);
482}
483
484static void vop_line_flag_irq_disable(struct vop *vop)
485{
486 unsigned long flags;
487
488 if (WARN_ON(!vop->is_enabled))
489 return;
490
491 spin_lock_irqsave(&vop->irq_lock, flags);
492
493 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
494
495 spin_unlock_irqrestore(&vop->irq_lock, flags);
496}
497
39a9ad8f 498static int vop_enable(struct drm_crtc *crtc)
2048e328
MY		 499{
500 struct vop *vop = to_vop(crtc);
501 int ret;
502
5d82d1a7
MY		 503 ret = pm_runtime_get_sync(vop->dev);
504 if (ret < 0) {
505 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
39a9ad8f 506 goto err_put_pm_runtime;
5d82d1a7
MY		 507 }
508
2048e328 509 ret = clk_enable(vop->hclk);
39a9ad8f
SP		 510 if (WARN_ON(ret < 0))
511 goto err_put_pm_runtime;
2048e328
MY		 512
513 ret = clk_enable(vop->dclk);
39a9ad8f 514 if (WARN_ON(ret < 0))
2048e328 515 goto err_disable_hclk;
2048e328
MY		 516
517 ret = clk_enable(vop->aclk);
39a9ad8f 518 if (WARN_ON(ret < 0))
2048e328 519 goto err_disable_dclk;
2048e328
MY		 520
521 /*
522 * Slave iommu shares power, irq and clock with vop. It was associated
523 * automatically with this master device via common driver code.
524 * Now that we have enabled the clock we attach it to the shared drm
525 * mapping.
526 */
527 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
528 if (ret) {
529 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
530 goto err_disable_aclk;
531 }
532
77faa161 533 memcpy(vop->regs, vop->regsbak, vop->len);
52ab7891
MY		 534 /*
535 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
536 */
537 vop->is_enabled = true;
538
2048e328
MY		 539 spin_lock(&vop->reg_lock);
540
541 VOP_CTRL_SET(vop, standby, 0);
542
543 spin_unlock(&vop->reg_lock);
544
545 enable_irq(vop->irq);
546
b5f7b755 547 drm_crtc_vblank_on(crtc);
2048e328 548
39a9ad8f 549 return 0;
2048e328
MY		 550
551err_disable_aclk:
552 clk_disable(vop->aclk);
553err_disable_dclk:
554 clk_disable(vop->dclk);
555err_disable_hclk:
556 clk_disable(vop->hclk);
39a9ad8f
SP		 557err_put_pm_runtime:
558 pm_runtime_put_sync(vop->dev);
559 return ret;
2048e328
MY		 560}
561
0ad3675d 562static void vop_crtc_disable(struct drm_crtc *crtc)
2048e328
MY		 563{
564 struct vop *vop = to_vop(crtc);
3ed6c649 565 int i;
2048e328 566
893b6cad
DV		 567 WARN_ON(vop->event);
568
b883c9ba
SP		 569 rockchip_drm_psr_deactivate(&vop->crtc);
570
3ed6c649
TV		 571 /*
572 * We need to make sure that all windows are disabled before we
573 * disable that crtc. Otherwise we might try to scan from a destroyed
574 * buffer later.
575 */
576 for (i = 0; i < vop->data->win_size; i++) {
577 struct vop_win *vop_win = &vop->win[i];
578 const struct vop_win_data *win = vop_win->data;
579
580 spin_lock(&vop->reg_lock);
581 VOP_WIN_SET(vop, win, enable, 0);
582 spin_unlock(&vop->reg_lock);
583 }
584
b5f7b755 585 drm_crtc_vblank_off(crtc);
2048e328 586
2048e328 587 /*
1067219b
MY		 588 * Vop standby will take effect at end of current frame,
589 * if dsp hold valid irq happen, it means standby complete.
590 *
591 * we must wait standby complete when we want to disable aclk,
592 * if not, memory bus maybe dead.
2048e328 593 */
1067219b
MY		 594 reinit_completion(&vop->dsp_hold_completion);
595 vop_dsp_hold_valid_irq_enable(vop);
596
2048e328
MY		 597 spin_lock(&vop->reg_lock);
598
599 VOP_CTRL_SET(vop, standby, 1);
600
601 spin_unlock(&vop->reg_lock);
52ab7891 602
1067219b
MY		 603 wait_for_completion(&vop->dsp_hold_completion);
604
605 vop_dsp_hold_valid_irq_disable(vop);
606
607 disable_irq(vop->irq);
608
52ab7891 609 vop->is_enabled = false;
1067219b 610
2048e328 611 /*
1067219b 612 * vop standby complete, so iommu detach is safe.
2048e328 613 */
2048e328
MY		 614 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
615
1067219b 616 clk_disable(vop->dclk);
2048e328
MY		 617 clk_disable(vop->aclk);
618 clk_disable(vop->hclk);
5d82d1a7 619 pm_runtime_put(vop->dev);
893b6cad
DV		 620
621 if (crtc->state->event && !crtc->state->active) {
622 spin_lock_irq(&crtc->dev->event_lock);
623 drm_crtc_send_vblank_event(crtc, crtc->state->event);
624 spin_unlock_irq(&crtc->dev->event_lock);
625
626 crtc->state->event = NULL;
627 }
2048e328
MY		 628}
629
63ebb9fa 630static void vop_plane_destroy(struct drm_plane *plane)
2048e328 631{
63ebb9fa 632 drm_plane_cleanup(plane);
2048e328
MY		 633}
634
63ebb9fa
MY		 635static int vop_plane_atomic_check(struct drm_plane *plane,
636 struct drm_plane_state *state)
2048e328 637{
63ebb9fa 638 struct drm_crtc *crtc = state->crtc;
92915da6 639 struct drm_crtc_state *crtc_state;
63ebb9fa 640 struct drm_framebuffer *fb = state->fb;
2048e328
MY		 641 struct vop_win *vop_win = to_vop_win(plane);
642 const struct vop_win_data *win = vop_win->data;
2048e328 643 int ret;
63ebb9fa 644 struct drm_rect clip;
4c156c21
MY		 645 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
646 DRM_PLANE_HELPER_NO_SCALING;
647 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
648 DRM_PLANE_HELPER_NO_SCALING;
2048e328 649
63ebb9fa 650 if (!crtc || !fb)
d47a7246 651 return 0;
92915da6
JK		 652
653 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
654 if (WARN_ON(!crtc_state))
655 return -EINVAL;
656
63ebb9fa
MY		 657 clip.x1 = 0;
658 clip.y1 = 0;
92915da6
JK		 659 clip.x2 = crtc_state->adjusted_mode.hdisplay;
660 clip.y2 = crtc_state->adjusted_mode.vdisplay;
63ebb9fa 661
f9b96be0
VS		 662 ret = drm_plane_helper_check_state(state, &clip,
663 min_scale, max_scale,
664 true, true);
2048e328
MY		 665 if (ret)
666 return ret;
667
f9b96be0 668 if (!state->visible)
d47a7246 669 return 0;
2048e328 670
d47a7246
TF		 671 ret = vop_convert_format(fb->pixel_format);
672 if (ret < 0)
673 return ret;
84c7f8ca 674
63ebb9fa
MY		 675 /*
676 * Src.x1 can be odd when do clip, but yuv plane start point
677 * need align with 2 pixel.
678 */
f9b96be0 679 if (is_yuv_support(fb->pixel_format) && ((state->src.x1 >> 16) % 2))
2048e328 680 return -EINVAL;
2048e328 681
63ebb9fa
MY		 682 return 0;
683}
2048e328 684
63ebb9fa
MY		 685static void vop_plane_atomic_disable(struct drm_plane *plane,
686 struct drm_plane_state *old_state)
687{
63ebb9fa
MY		 688 struct vop_win *vop_win = to_vop_win(plane);
689 const struct vop_win_data *win = vop_win->data;
690 struct vop *vop = to_vop(old_state->crtc);
2048e328 691
63ebb9fa
MY		 692 if (!old_state->crtc)
693 return;
2048e328 694
63ebb9fa 695 spin_lock(&vop->reg_lock);
2048e328 696
63ebb9fa 697 VOP_WIN_SET(vop, win, enable, 0);
84c7f8ca 698
63ebb9fa 699 spin_unlock(&vop->reg_lock);
63ebb9fa 700}
84c7f8ca 701
63ebb9fa
MY		 702static void vop_plane_atomic_update(struct drm_plane *plane,
703 struct drm_plane_state *old_state)
704{
705 struct drm_plane_state *state = plane->state;
706 struct drm_crtc *crtc = state->crtc;
707 struct vop_win *vop_win = to_vop_win(plane);
63ebb9fa
MY		 708 const struct vop_win_data *win = vop_win->data;
709 struct vop *vop = to_vop(state->crtc);
710 struct drm_framebuffer *fb = state->fb;
711 unsigned int actual_w, actual_h;
712 unsigned int dsp_stx, dsp_sty;
713 uint32_t act_info, dsp_info, dsp_st;
ac92028e
VS		 714 struct drm_rect *src = &state->src;
715 struct drm_rect *dest = &state->dst;
63ebb9fa
MY		 716 struct drm_gem_object *obj, *uv_obj;
717 struct rockchip_gem_object *rk_obj, *rk_uv_obj;
718 unsigned long offset;
719 dma_addr_t dma_addr;
720 uint32_t val;
721 bool rb_swap;
d47a7246 722 int format;
84c7f8ca 723
2048e328 724 /*
63ebb9fa 725 * can't update plane when vop is disabled.
2048e328 726 */
4f9d39a7 727 if (WARN_ON(!crtc))
63ebb9fa 728 return;
2048e328 729
63ebb9fa
MY		 730 if (WARN_ON(!vop->is_enabled))
731 return;
2048e328 732
d47a7246 733 if (!state->visible) {
63ebb9fa
MY		 734 vop_plane_atomic_disable(plane, old_state);
735 return;
2048e328 736 }
63ebb9fa
MY		 737
738 obj = rockchip_fb_get_gem_obj(fb, 0);
739 rk_obj = to_rockchip_obj(obj);
740
741 actual_w = drm_rect_width(src) >> 16;
742 actual_h = drm_rect_height(src) >> 16;
743 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
744
745 dsp_info = (drm_rect_height(dest) - 1) << 16;
746 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
747
748 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
749 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
750 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
751
752 offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
753 offset += (src->y1 >> 16) * fb->pitches[0];
d47a7246
TF		 754 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
755
756 format = vop_convert_format(fb->pixel_format);
2048e328
MY		 757
758 spin_lock(&vop->reg_lock);
759
d47a7246 760 VOP_WIN_SET(vop, win, format, format);
63ebb9fa 761 VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
d47a7246 762 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
63ebb9fa
MY		 763 if (is_yuv_support(fb->pixel_format)) {
764 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
765 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
766 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
767
768 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
769 rk_uv_obj = to_rockchip_obj(uv_obj);
770
771 offset = (src->x1 >> 16) * bpp / hsub;
772 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
773
774 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
775 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
776 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
84c7f8ca 777 }
4c156c21
MY		 778
779 if (win->phy->scl)
780 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
63ebb9fa 781 drm_rect_width(dest), drm_rect_height(dest),
4c156c21
MY		 782 fb->pixel_format);
783
63ebb9fa
MY		 784 VOP_WIN_SET(vop, win, act_info, act_info);
785 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
786 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
4c156c21 787
63ebb9fa 788 rb_swap = has_rb_swapped(fb->pixel_format);
85a359f2 789 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
2048e328 790
63ebb9fa 791 if (is_alpha_support(fb->pixel_format)) {
2048e328
MY		 792 VOP_WIN_SET(vop, win, dst_alpha_ctl,
793 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
794 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
795 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
796 SRC_BLEND_M0(ALPHA_PER_PIX) |
797 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
798 SRC_FACTOR_M0(ALPHA_ONE);
799 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
800 } else {
801 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
802 }
803
804 VOP_WIN_SET(vop, win, enable, 1);
2048e328 805 spin_unlock(&vop->reg_lock);
2048e328
MY		 806}
807
63ebb9fa
MY		 808static const struct drm_plane_helper_funcs plane_helper_funcs = {
809 .atomic_check = vop_plane_atomic_check,
810 .atomic_update = vop_plane_atomic_update,
811 .atomic_disable = vop_plane_atomic_disable,
812};
2048e328 813
2048e328 814static const struct drm_plane_funcs vop_plane_funcs = {
63ebb9fa
MY		 815 .update_plane = drm_atomic_helper_update_plane,
816 .disable_plane = drm_atomic_helper_disable_plane,
2048e328 817 .destroy = vop_plane_destroy,
d47a7246
TF		 818 .reset = drm_atomic_helper_plane_reset,
819 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
820 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
2048e328
MY		 821};
822
2048e328
MY		 823static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
824{
825 struct vop *vop = to_vop(crtc);
826 unsigned long flags;
827
63ebb9fa 828 if (WARN_ON(!vop->is_enabled))
2048e328
MY		 829 return -EPERM;
830
831 spin_lock_irqsave(&vop->irq_lock, flags);
832
fa374107 833 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
dbb3d944 834 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
2048e328
MY		 835
836 spin_unlock_irqrestore(&vop->irq_lock, flags);
837
838 return 0;
839}
840
841static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
842{
843 struct vop *vop = to_vop(crtc);
844 unsigned long flags;
845
63ebb9fa 846 if (WARN_ON(!vop->is_enabled))
2048e328 847 return;
31e980c5 848
2048e328 849 spin_lock_irqsave(&vop->irq_lock, flags);
dbb3d944
MY		 850
851 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
852
2048e328
MY		 853 spin_unlock_irqrestore(&vop->irq_lock, flags);
854}
855
856static const struct rockchip_crtc_funcs private_crtc_funcs = {
857 .enable_vblank = vop_crtc_enable_vblank,
858 .disable_vblank = vop_crtc_disable_vblank,
859};
860
2048e328
MY		 861static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
862 const struct drm_display_mode *mode,
863 struct drm_display_mode *adjusted_mode)
864{
b59b8de3
CZ		 865 struct vop *vop = to_vop(crtc);
866
b59b8de3
CZ		 867 adjusted_mode->clock =
868 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
869
2048e328
MY		 870 return true;
871}
872
63ebb9fa 873static void vop_crtc_enable(struct drm_crtc *crtc)
2048e328
MY		 874{
875 struct vop *vop = to_vop(crtc);
4e257d9e 876 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
63ebb9fa 877 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
2048e328
MY		 878 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
879 u16 hdisplay = adjusted_mode->hdisplay;
880 u16 htotal = adjusted_mode->htotal;
881 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
882 u16 hact_end = hact_st + hdisplay;
883 u16 vdisplay = adjusted_mode->vdisplay;
884 u16 vtotal = adjusted_mode->vtotal;
885 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
886 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
887 u16 vact_end = vact_st + vdisplay;
0a63bfd0 888 uint32_t pin_pol, val;
39a9ad8f 889 int ret;
2048e328 890
893b6cad
DV		 891 WARN_ON(vop->event);
892
39a9ad8f
SP		 893 ret = vop_enable(crtc);
894 if (ret) {
895 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
896 return;
897 }
898
2048e328 899 /*
ce3887ed
MY		 900 * If dclk rate is zero, mean that scanout is stop,
901 * we don't need wait any more.
2048e328 902 */
ce3887ed
MY		 903 if (clk_get_rate(vop->dclk)) {
904 /*
905 * Rk3288 vop timing register is immediately, when configure
906 * display timing on display time, may cause tearing.
907 *
908 * Vop standby will take effect at end of current frame,
909 * if dsp hold valid irq happen, it means standby complete.
910 *
911 * mode set:
912 * standby and wait complete --> |----
913 * | display time
914 * |----
915 * |---> dsp hold irq
916 * configure display timing --> |
917 * standby exit |
918 * | new frame start.
919 */
920
921 reinit_completion(&vop->dsp_hold_completion);
922 vop_dsp_hold_valid_irq_enable(vop);
923
924 spin_lock(&vop->reg_lock);
925
926 VOP_CTRL_SET(vop, standby, 1);
927
928 spin_unlock(&vop->reg_lock);
929
930 wait_for_completion(&vop->dsp_hold_completion);
931
932 vop_dsp_hold_valid_irq_disable(vop);
933 }
2048e328 934
0a63bfd0
MY		 935 pin_pol = 0x8;
936 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
937 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
938 VOP_CTRL_SET(vop, pin_pol, pin_pol);
939
4e257d9e
MY		 940 switch (s->output_type) {
941 case DRM_MODE_CONNECTOR_LVDS:
942 VOP_CTRL_SET(vop, rgb_en, 1);
0a63bfd0 943 VOP_CTRL_SET(vop, rgb_pin_pol, pin_pol);
4e257d9e
MY		 944 break;
945 case DRM_MODE_CONNECTOR_eDP:
0a63bfd0 946 VOP_CTRL_SET(vop, edp_pin_pol, pin_pol);
4e257d9e
MY		 947 VOP_CTRL_SET(vop, edp_en, 1);
948 break;
949 case DRM_MODE_CONNECTOR_HDMIA:
0a63bfd0 950 VOP_CTRL_SET(vop, hdmi_pin_pol, pin_pol);
4e257d9e
MY		 951 VOP_CTRL_SET(vop, hdmi_en, 1);
952 break;
953 case DRM_MODE_CONNECTOR_DSI:
0a63bfd0 954 VOP_CTRL_SET(vop, mipi_pin_pol, pin_pol);
4e257d9e
MY		 955 VOP_CTRL_SET(vop, mipi_en, 1);
956 break;
957 default:
ee4d7899
SP		 958 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
959 s->output_type);
4e257d9e
MY		 960 }
961 VOP_CTRL_SET(vop, out_mode, s->output_mode);
2048e328
MY		 962
963 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
964 val = hact_st << 16;
965 val |= hact_end;
966 VOP_CTRL_SET(vop, hact_st_end, val);
967 VOP_CTRL_SET(vop, hpost_st_end, val);
968
969 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
970 val = vact_st << 16;
971 val |= vact_end;
972 VOP_CTRL_SET(vop, vact_st_end, val);
973 VOP_CTRL_SET(vop, vpost_st_end, val);
974
2048e328 975 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
ce3887ed
MY		 976
977 VOP_CTRL_SET(vop, standby, 0);
b883c9ba
SP		 978
979 rockchip_drm_psr_activate(&vop->crtc);
2048e328
MY		 980}
981
7caecdbe
TF		 982static bool vop_fs_irq_is_pending(struct vop *vop)
983{
984 return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
985}
986
987static void vop_wait_for_irq_handler(struct vop *vop)
988{
989 bool pending;
990 int ret;
991
992 /*
993 * Spin until frame start interrupt status bit goes low, which means
994 * that interrupt handler was invoked and cleared it. The timeout of
995 * 10 msecs is really too long, but it is just a safety measure if
996 * something goes really wrong. The wait will only happen in the very
997 * unlikely case of a vblank happening exactly at the same time and
998 * shouldn't exceed microseconds range.
999 */
1000 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
1001 !pending, 0, 10 * 1000);
1002 if (ret)
1003 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
1004
1005 synchronize_irq(vop->irq);
1006}
1007
63ebb9fa
MY		 1008static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1009 struct drm_crtc_state *old_crtc_state)
2048e328 1010{
47a7eb45
TF		 1011 struct drm_atomic_state *old_state = old_crtc_state->state;
1012 struct drm_plane_state *old_plane_state;
2048e328 1013 struct vop *vop = to_vop(crtc);
47a7eb45
TF		 1014 struct drm_plane *plane;
1015 int i;
2048e328 1016
63ebb9fa
MY		 1017 if (WARN_ON(!vop->is_enabled))
1018 return;
2048e328 1019
63ebb9fa 1020 spin_lock(&vop->reg_lock);
2048e328 1021
63ebb9fa 1022 vop_cfg_done(vop);
2048e328 1023
63ebb9fa 1024 spin_unlock(&vop->reg_lock);
7caecdbe
TF		 1025
1026 /*
1027 * There is a (rather unlikely) possiblity that a vblank interrupt
1028 * fired before we set the cfg_done bit. To avoid spuriously
1029 * signalling flip completion we need to wait for it to finish.
1030 */
1031 vop_wait_for_irq_handler(vop);
47a7eb45 1032
41ee4367
TF		 1033 spin_lock_irq(&crtc->dev->event_lock);
1034 if (crtc->state->event) {
1035 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1036 WARN_ON(vop->event);
1037
1038 vop->event = crtc->state->event;
1039 crtc->state->event = NULL;
1040 }
1041 spin_unlock_irq(&crtc->dev->event_lock);
1042
47a7eb45
TF		 1043 for_each_plane_in_state(old_state, plane, old_plane_state, i) {
1044 if (!old_plane_state->fb)
1045 continue;
1046
1047 if (old_plane_state->fb == plane->state->fb)
1048 continue;
1049
1050 drm_framebuffer_reference(old_plane_state->fb);
1051 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
1052 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1053 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1054 }
2048e328
MY		 1055}
1056
63ebb9fa
MY		 1057static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1058 struct drm_crtc_state *old_crtc_state)
2048e328 1059{
b883c9ba 1060 rockchip_drm_psr_flush(crtc);
2048e328
MY		 1061}
1062
63ebb9fa
MY		 1063static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1064 .enable = vop_crtc_enable,
1065 .disable = vop_crtc_disable,
1066 .mode_fixup = vop_crtc_mode_fixup,
1067 .atomic_flush = vop_crtc_atomic_flush,
1068 .atomic_begin = vop_crtc_atomic_begin,
1069};
1070
2048e328
MY		 1071static void vop_crtc_destroy(struct drm_crtc *crtc)
1072{
1073 drm_crtc_cleanup(crtc);
1074}
1075
dc0b408f
JK		 1076static void vop_crtc_reset(struct drm_crtc *crtc)
1077{
1078 if (crtc->state)
1079 __drm_atomic_helper_crtc_destroy_state(crtc->state);
1080 kfree(crtc->state);
1081
1082 crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
1083 if (crtc->state)
1084 crtc->state->crtc = crtc;
1085}
1086
4e257d9e
MY		 1087static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1088{
1089 struct rockchip_crtc_state *rockchip_state;
1090
1091 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1092 if (!rockchip_state)
1093 return NULL;
1094
1095 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1096 return &rockchip_state->base;
1097}
1098
1099static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1100 struct drm_crtc_state *state)
1101{
1102 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1103
ec2dc6a0 1104 __drm_atomic_helper_crtc_destroy_state(&s->base);
4e257d9e
MY		 1105 kfree(s);
1106}
1107
2048e328 1108static const struct drm_crtc_funcs vop_crtc_funcs = {
63ebb9fa
MY		 1109 .set_config = drm_atomic_helper_set_config,
1110 .page_flip = drm_atomic_helper_page_flip,
2048e328 1111 .destroy = vop_crtc_destroy,
dc0b408f 1112 .reset = vop_crtc_reset,
4e257d9e
MY		 1113 .atomic_duplicate_state = vop_crtc_duplicate_state,
1114 .atomic_destroy_state = vop_crtc_destroy_state,
2048e328
MY		 1115};
1116
47a7eb45
TF		 1117static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
1118{
1119 struct vop *vop = container_of(work, struct vop, fb_unref_work);
1120 struct drm_framebuffer *fb = val;
1121
1122 drm_crtc_vblank_put(&vop->crtc);
1123 drm_framebuffer_unreference(fb);
1124}
1125
63ebb9fa 1126static void vop_handle_vblank(struct vop *vop)
2048e328 1127{
63ebb9fa
MY		 1128 struct drm_device *drm = vop->drm_dev;
1129 struct drm_crtc *crtc = &vop->crtc;
1130 unsigned long flags;
2048e328 1131
893b6cad 1132 spin_lock_irqsave(&drm->event_lock, flags);
63ebb9fa 1133 if (vop->event) {
63ebb9fa 1134 drm_crtc_send_vblank_event(crtc, vop->event);
5b680403 1135 drm_crtc_vblank_put(crtc);
646ec687 1136 vop->event = NULL;
5b680403 1137 }
893b6cad
DV		 1138 spin_unlock_irqrestore(&drm->event_lock, flags);
1139
47a7eb45
TF		 1140 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
1141 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
2048e328
MY		 1142}
1143
1144static irqreturn_t vop_isr(int irq, void *data)
1145{
1146 struct vop *vop = data;
b5f7b755 1147 struct drm_crtc *crtc = &vop->crtc;
dbb3d944 1148 uint32_t active_irqs;
2048e328 1149 unsigned long flags;
1067219b 1150 int ret = IRQ_NONE;
2048e328
MY		 1151
1152 /*
dbb3d944 1153 * interrupt register has interrupt status, enable and clear bits, we
2048e328
MY		 1154 * must hold irq_lock to avoid a race with enable/disable_vblank().
1155 */
1156 spin_lock_irqsave(&vop->irq_lock, flags);
dbb3d944
MY		 1157
1158 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
2048e328
MY		 1159 /* Clear all active interrupt sources */
1160 if (active_irqs)
dbb3d944
MY		 1161 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1162
2048e328
MY		 1163 spin_unlock_irqrestore(&vop->irq_lock, flags);
1164
1165 /* This is expected for vop iommu irqs, since the irq is shared */
1166 if (!active_irqs)
1167 return IRQ_NONE;
1168
1067219b
MY		 1169 if (active_irqs & DSP_HOLD_VALID_INTR) {
1170 complete(&vop->dsp_hold_completion);
1171 active_irqs &= ~DSP_HOLD_VALID_INTR;
1172 ret = IRQ_HANDLED;
2048e328
MY		 1173 }
1174
69c34e41
YY		 1175 if (active_irqs & LINE_FLAG_INTR) {
1176 complete(&vop->line_flag_completion);
1177 active_irqs &= ~LINE_FLAG_INTR;
1178 ret = IRQ_HANDLED;
1179 }
1180
1067219b 1181 if (active_irqs & FS_INTR) {
b5f7b755 1182 drm_crtc_handle_vblank(crtc);
63ebb9fa 1183 vop_handle_vblank(vop);
1067219b 1184 active_irqs &= ~FS_INTR;
63ebb9fa 1185 ret = IRQ_HANDLED;
1067219b 1186 }
2048e328 1187
1067219b
MY		 1188 /* Unhandled irqs are spurious. */
1189 if (active_irqs)
ee4d7899
SP		 1190 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",
1191 active_irqs);
1067219b
MY		 1192
1193 return ret;
2048e328
MY		 1194}
1195
1196static int vop_create_crtc(struct vop *vop)
1197{
1198 const struct vop_data *vop_data = vop->data;
1199 struct device *dev = vop->dev;
1200 struct drm_device *drm_dev = vop->drm_dev;
328b51c0 1201 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
2048e328
MY		 1202 struct drm_crtc *crtc = &vop->crtc;
1203 struct device_node *port;
1204 int ret;
1205 int i;
1206
1207 /*
1208 * Create drm_plane for primary and cursor planes first, since we need
1209 * to pass them to drm_crtc_init_with_planes, which sets the
1210 * "possible_crtcs" to the newly initialized crtc.
1211 */
1212 for (i = 0; i < vop_data->win_size; i++) {
1213 struct vop_win *vop_win = &vop->win[i];
1214 const struct vop_win_data *win_data = vop_win->data;
1215
1216 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1217 win_data->type != DRM_PLANE_TYPE_CURSOR)
1218 continue;
1219
1220 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1221 0, &vop_plane_funcs,
1222 win_data->phy->data_formats,
1223 win_data->phy->nformats,
b0b3b795 1224 win_data->type, NULL);
2048e328 1225 if (ret) {
ee4d7899
SP		 1226 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",
1227 ret);
2048e328
MY		 1228 goto err_cleanup_planes;
1229 }
1230
1231 plane = &vop_win->base;
63ebb9fa 1232 drm_plane_helper_add(plane, &plane_helper_funcs);
2048e328
MY		 1233 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1234 primary = plane;
1235 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1236 cursor = plane;
1237 }
1238
1239 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
f9882876 1240 &vop_crtc_funcs, NULL);
2048e328 1241 if (ret)
328b51c0 1242 goto err_cleanup_planes;
2048e328
MY		 1243
1244 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1245
1246 /*
1247 * Create drm_planes for overlay windows with possible_crtcs restricted
1248 * to the newly created crtc.
1249 */
1250 for (i = 0; i < vop_data->win_size; i++) {
1251 struct vop_win *vop_win = &vop->win[i];
1252 const struct vop_win_data *win_data = vop_win->data;
1253 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1254
1255 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1256 continue;
1257
1258 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1259 possible_crtcs,
1260 &vop_plane_funcs,
1261 win_data->phy->data_formats,
1262 win_data->phy->nformats,
b0b3b795 1263 win_data->type, NULL);
2048e328 1264 if (ret) {
ee4d7899
SP		 1265 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
1266 ret);
2048e328
MY		 1267 goto err_cleanup_crtc;
1268 }
63ebb9fa 1269 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
2048e328
MY		 1270 }
1271
1272 port = of_get_child_by_name(dev->of_node, "port");
1273 if (!port) {
ee4d7899
SP		 1274 DRM_DEV_ERROR(vop->dev, "no port node found in %s\n",
1275 dev->of_node->full_name);
328b51c0 1276 ret = -ENOENT;
2048e328
MY		 1277 goto err_cleanup_crtc;
1278 }
1279
47a7eb45
TF		 1280 drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
1281 vop_fb_unref_worker);
1282
1067219b 1283 init_completion(&vop->dsp_hold_completion);
69c34e41 1284 init_completion(&vop->line_flag_completion);
2048e328 1285 crtc->port = port;
b5f7b755 1286 rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
2048e328
MY		 1287
1288 return 0;
1289
1290err_cleanup_crtc:
1291 drm_crtc_cleanup(crtc);
1292err_cleanup_planes:
328b51c0
DA		 1293 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1294 head)
2048e328
MY		 1295 drm_plane_cleanup(plane);
1296 return ret;
1297}
1298
1299static void vop_destroy_crtc(struct vop *vop)
1300{
1301 struct drm_crtc *crtc = &vop->crtc;
328b51c0
DA		 1302 struct drm_device *drm_dev = vop->drm_dev;
1303 struct drm_plane *plane, *tmp;
2048e328 1304
b5f7b755 1305 rockchip_unregister_crtc_funcs(crtc);
2048e328 1306 of_node_put(crtc->port);
328b51c0
DA		 1307
1308 /*
1309 * We need to cleanup the planes now. Why?
1310 *
1311 * The planes are "&vop->win[i].base". That means the memory is
1312 * all part of the big "struct vop" chunk of memory. That memory
1313 * was devm allocated and associated with this component. We need to
1314 * free it ourselves before vop_unbind() finishes.
1315 */
1316 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1317 head)
1318 vop_plane_destroy(plane);
1319
1320 /*
1321 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1322 * references the CRTC.
1323 */
2048e328 1324 drm_crtc_cleanup(crtc);
47a7eb45 1325 drm_flip_work_cleanup(&vop->fb_unref_work);
2048e328
MY		 1326}
1327
1328static int vop_initial(struct vop *vop)
1329{
1330 const struct vop_data *vop_data = vop->data;
1331 const struct vop_reg_data *init_table = vop_data->init_table;
1332 struct reset_control *ahb_rst;
1333 int i, ret;
1334
1335 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1336 if (IS_ERR(vop->hclk)) {
1337 dev_err(vop->dev, "failed to get hclk source\n");
1338 return PTR_ERR(vop->hclk);
1339 }
1340 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1341 if (IS_ERR(vop->aclk)) {
1342 dev_err(vop->dev, "failed to get aclk source\n");
1343 return PTR_ERR(vop->aclk);
1344 }
1345 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1346 if (IS_ERR(vop->dclk)) {
1347 dev_err(vop->dev, "failed to get dclk source\n");
1348 return PTR_ERR(vop->dclk);
1349 }
1350
2048e328
MY		 1351 ret = clk_prepare(vop->dclk);
1352 if (ret < 0) {
1353 dev_err(vop->dev, "failed to prepare dclk\n");
d7b53fd9 1354 return ret;
2048e328
MY		 1355 }
1356
d7b53fd9
SS		 1357 /* Enable both the hclk and aclk to setup the vop */
1358 ret = clk_prepare_enable(vop->hclk);
2048e328 1359 if (ret < 0) {
d7b53fd9 1360 dev_err(vop->dev, "failed to prepare/enable hclk\n");
2048e328
MY		 1361 goto err_unprepare_dclk;
1362 }
1363
d7b53fd9 1364 ret = clk_prepare_enable(vop->aclk);
2048e328 1365 if (ret < 0) {
d7b53fd9
SS		 1366 dev_err(vop->dev, "failed to prepare/enable aclk\n");
1367 goto err_disable_hclk;
2048e328 1368 }
d7b53fd9 1369
2048e328
MY		 1370 /*
1371 * do hclk_reset, reset all vop registers.
1372 */
1373 ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1374 if (IS_ERR(ahb_rst)) {
1375 dev_err(vop->dev, "failed to get ahb reset\n");
1376 ret = PTR_ERR(ahb_rst);
d7b53fd9 1377 goto err_disable_aclk;
2048e328
MY		 1378 }
1379 reset_control_assert(ahb_rst);
1380 usleep_range(10, 20);
1381 reset_control_deassert(ahb_rst);
1382
1383 memcpy(vop->regsbak, vop->regs, vop->len);
1384
1385 for (i = 0; i < vop_data->table_size; i++)
1386 vop_writel(vop, init_table[i].offset, init_table[i].value);
1387
1388 for (i = 0; i < vop_data->win_size; i++) {
1389 const struct vop_win_data *win = &vop_data->win[i];
1390
1391 VOP_WIN_SET(vop, win, enable, 0);
1392 }
1393
1394 vop_cfg_done(vop);
1395
1396 /*
1397 * do dclk_reset, let all config take affect.
1398 */
1399 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1400 if (IS_ERR(vop->dclk_rst)) {
1401 dev_err(vop->dev, "failed to get dclk reset\n");
1402 ret = PTR_ERR(vop->dclk_rst);
d7b53fd9 1403 goto err_disable_aclk;
2048e328
MY		 1404 }
1405 reset_control_assert(vop->dclk_rst);
1406 usleep_range(10, 20);
1407 reset_control_deassert(vop->dclk_rst);
1408
1409 clk_disable(vop->hclk);
d7b53fd9 1410 clk_disable(vop->aclk);
2048e328 1411
31e980c5 1412 vop->is_enabled = false;
2048e328
MY		 1413
1414 return 0;
1415
d7b53fd9
SS		 1416err_disable_aclk:
1417 clk_disable_unprepare(vop->aclk);
2048e328 1418err_disable_hclk:
d7b53fd9 1419 clk_disable_unprepare(vop->hclk);
2048e328
MY		 1420err_unprepare_dclk:
1421 clk_unprepare(vop->dclk);
2048e328
MY		 1422 return ret;
1423}
1424
1425/*
1426 * Initialize the vop->win array elements.
1427 */
1428static void vop_win_init(struct vop *vop)
1429{
1430 const struct vop_data *vop_data = vop->data;
1431 unsigned int i;
1432
1433 for (i = 0; i < vop_data->win_size; i++) {
1434 struct vop_win *vop_win = &vop->win[i];
1435 const struct vop_win_data *win_data = &vop_data->win[i];
1436
1437 vop_win->data = win_data;
1438 vop_win->vop = vop;
2048e328
MY		 1439 }
1440}
1441
69c34e41
YY		 1442/**
1443 * rockchip_drm_wait_line_flag - acqiure the give line flag event
1444 * @crtc: CRTC to enable line flag
1445 * @line_num: interested line number
1446 * @mstimeout: millisecond for timeout
1447 *
1448 * Driver would hold here until the interested line flag interrupt have
1449 * happened or timeout to wait.
1450 *
1451 * Returns:
1452 * Zero on success, negative errno on failure.
1453 */
1454int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num,
1455 unsigned int mstimeout)
1456{
1457 struct vop *vop = to_vop(crtc);
1458 unsigned long jiffies_left;
1459
1460 if (!crtc || !vop->is_enabled)
1461 return -ENODEV;
1462
1463 if (line_num > crtc->mode.vtotal || mstimeout <= 0)
1464 return -EINVAL;
1465
1466 if (vop_line_flag_irq_is_enabled(vop))
1467 return -EBUSY;
1468
1469 reinit_completion(&vop->line_flag_completion);
1470 vop_line_flag_irq_enable(vop, line_num);
1471
1472 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
1473 msecs_to_jiffies(mstimeout));
1474 vop_line_flag_irq_disable(vop);
1475
1476 if (jiffies_left == 0) {
1477 dev_err(vop->dev, "Timeout waiting for IRQ\n");
1478 return -ETIMEDOUT;
1479 }
1480
1481 return 0;
1482}
1483EXPORT_SYMBOL(rockchip_drm_wait_line_flag);
1484
2048e328
MY		 1485static int vop_bind(struct device *dev, struct device *master, void *data)
1486{
1487 struct platform_device *pdev = to_platform_device(dev);
2048e328
MY		 1488 const struct vop_data *vop_data;
1489 struct drm_device *drm_dev = data;
1490 struct vop *vop;
1491 struct resource *res;
1492 size_t alloc_size;
3ea68922 1493 int ret, irq;
2048e328 1494
a67719d1 1495 vop_data = of_device_get_match_data(dev);
2048e328
MY		 1496 if (!vop_data)
1497 return -ENODEV;
1498
1499 /* Allocate vop struct and its vop_win array */
1500 alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
1501 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1502 if (!vop)
1503 return -ENOMEM;
1504
1505 vop->dev = dev;
1506 vop->data = vop_data;
1507 vop->drm_dev = drm_dev;
1508 dev_set_drvdata(dev, vop);
1509
1510 vop_win_init(vop);
1511
1512 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1513 vop->len = resource_size(res);
1514 vop->regs = devm_ioremap_resource(dev, res);
1515 if (IS_ERR(vop->regs))
1516 return PTR_ERR(vop->regs);
1517
1518 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1519 if (!vop->regsbak)
1520 return -ENOMEM;
1521
1522 ret = vop_initial(vop);
1523 if (ret < 0) {
1524 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1525 return ret;
1526 }
1527
3ea68922
HS		 1528 irq = platform_get_irq(pdev, 0);
1529 if (irq < 0) {
2048e328 1530 dev_err(dev, "cannot find irq for vop\n");
3ea68922 1531 return irq;
2048e328 1532 }
3ea68922 1533 vop->irq = (unsigned int)irq;
2048e328
MY		 1534
1535 spin_lock_init(&vop->reg_lock);
1536 spin_lock_init(&vop->irq_lock);
1537
1538 mutex_init(&vop->vsync_mutex);
1539
63ebb9fa
MY		 1540 ret = devm_request_irq(dev, vop->irq, vop_isr,
1541 IRQF_SHARED, dev_name(dev), vop);
2048e328
MY		 1542 if (ret)
1543 return ret;
1544
1545 /* IRQ is initially disabled; it gets enabled in power_on */
1546 disable_irq(vop->irq);
1547
1548 ret = vop_create_crtc(vop);
1549 if (ret)
8c763c9b 1550 goto err_enable_irq;
2048e328
MY		 1551
1552 pm_runtime_enable(&pdev->dev);
5182c1a5 1553
2048e328 1554 return 0;
8c763c9b
SP		 1555
1556err_enable_irq:
1557 enable_irq(vop->irq); /* To balance out the disable_irq above */
1558 return ret;
2048e328
MY		 1559}
1560
1561static void vop_unbind(struct device *dev, struct device *master, void *data)
1562{
1563 struct vop *vop = dev_get_drvdata(dev);
1564
1565 pm_runtime_disable(dev);
1566 vop_destroy_crtc(vop);
1567}
1568
a67719d1 1569const struct component_ops vop_component_ops = {
2048e328
MY		 1570 .bind = vop_bind,
1571 .unbind = vop_unbind,
1572};
54255e81 1573EXPORT_SYMBOL_GPL(vop_component_ops);
Linux 6.x block layer and io_uring tree(s)