Commit | Line | Data |
---|---|---|
2048e328 MY |
1 | /* |
2 | * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd | |
3 | * Author:Mark Yao <mark.yao@rock-chips.com> | |
4 | * | |
5 | * This software is licensed under the terms of the GNU General Public | |
6 | * License version 2, as published by the Free Software Foundation, and | |
7 | * may be copied, distributed, and modified under those terms. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
15 | #include <drm/drm.h> | |
16 | #include <drm/drmP.h> | |
63ebb9fa | 17 | #include <drm/drm_atomic.h> |
2048e328 MY |
18 | #include <drm/drm_crtc.h> |
19 | #include <drm/drm_crtc_helper.h> | |
47a7eb45 | 20 | #include <drm/drm_flip_work.h> |
2048e328 MY |
21 | #include <drm/drm_plane_helper.h> |
22 | ||
23 | #include <linux/kernel.h> | |
00fe6148 | 24 | #include <linux/module.h> |
2048e328 MY |
25 | #include <linux/platform_device.h> |
26 | #include <linux/clk.h> | |
7caecdbe | 27 | #include <linux/iopoll.h> |
2048e328 MY |
28 | #include <linux/of.h> |
29 | #include <linux/of_device.h> | |
30 | #include <linux/pm_runtime.h> | |
31 | #include <linux/component.h> | |
32 | ||
33 | #include <linux/reset.h> | |
34 | #include <linux/delay.h> | |
35 | ||
36 | #include "rockchip_drm_drv.h" | |
37 | #include "rockchip_drm_gem.h" | |
38 | #include "rockchip_drm_fb.h" | |
5182c1a5 | 39 | #include "rockchip_drm_psr.h" |
2048e328 MY |
40 | #include "rockchip_drm_vop.h" |
41 | ||
d49463ec MY |
42 | #define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \ |
43 | vop_mask_write(x, off, mask, shift, v, write_mask, true) | |
44 | ||
45 | #define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \ | |
46 | vop_mask_write(x, off, mask, shift, v, write_mask, false) | |
2048e328 MY |
47 | |
48 | #define REG_SET(x, base, reg, v, mode) \ | |
d49463ec MY |
49 | __REG_SET_##mode(x, base + reg.offset, \ |
50 | reg.mask, reg.shift, v, reg.write_mask) | |
c7647f86 | 51 | #define REG_SET_MASK(x, base, reg, mask, v, mode) \ |
d49463ec MY |
52 | __REG_SET_##mode(x, base + reg.offset, \ |
53 | mask, reg.shift, v, reg.write_mask) | |
2048e328 MY |
54 | |
55 | #define VOP_WIN_SET(x, win, name, v) \ | |
56 | REG_SET(x, win->base, win->phy->name, v, RELAXED) | |
4c156c21 MY |
57 | #define VOP_SCL_SET(x, win, name, v) \ |
58 | REG_SET(x, win->base, win->phy->scl->name, v, RELAXED) | |
1194fffb MY |
59 | #define VOP_SCL_SET_EXT(x, win, name, v) \ |
60 | REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED) | |
2048e328 MY |
61 | #define VOP_CTRL_SET(x, name, v) \ |
62 | REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL) | |
63 | ||
dbb3d944 MY |
64 | #define VOP_INTR_GET(vop, name) \ |
65 | vop_read_reg(vop, 0, &vop->data->ctrl->name) | |
66 | ||
c7647f86 JK |
67 | #define VOP_INTR_SET(vop, name, mask, v) \ |
68 | REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL) | |
dbb3d944 MY |
69 | #define VOP_INTR_SET_TYPE(vop, name, type, v) \ |
70 | do { \ | |
c7647f86 | 71 | int i, reg = 0, mask = 0; \ |
dbb3d944 | 72 | for (i = 0; i < vop->data->intr->nintrs; i++) { \ |
c7647f86 | 73 | if (vop->data->intr->intrs[i] & type) { \ |
dbb3d944 | 74 | reg |= (v) << i; \ |
c7647f86 JK |
75 | mask |= 1 << i; \ |
76 | } \ | |
dbb3d944 | 77 | } \ |
c7647f86 | 78 | VOP_INTR_SET(vop, name, mask, reg); \ |
dbb3d944 MY |
79 | } while (0) |
80 | #define VOP_INTR_GET_TYPE(vop, name, type) \ | |
81 | vop_get_intr_type(vop, &vop->data->intr->name, type) | |
82 | ||
2048e328 MY |
83 | #define VOP_WIN_GET(x, win, name) \ |
84 | vop_read_reg(x, win->base, &win->phy->name) | |
85 | ||
86 | #define VOP_WIN_GET_YRGBADDR(vop, win) \ | |
87 | vop_readl(vop, win->base + win->phy->yrgb_mst.offset) | |
88 | ||
89 | #define to_vop(x) container_of(x, struct vop, crtc) | |
90 | #define to_vop_win(x) container_of(x, struct vop_win, base) | |
91 | ||
47a7eb45 TF |
92 | enum vop_pending { |
93 | VOP_PENDING_FB_UNREF, | |
94 | }; | |
95 | ||
2048e328 MY |
96 | struct vop_win { |
97 | struct drm_plane base; | |
98 | const struct vop_win_data *data; | |
99 | struct vop *vop; | |
2048e328 MY |
100 | }; |
101 | ||
102 | struct vop { | |
103 | struct drm_crtc crtc; | |
104 | struct device *dev; | |
105 | struct drm_device *drm_dev; | |
31e980c5 | 106 | bool is_enabled; |
2048e328 | 107 | |
2048e328 MY |
108 | /* mutex vsync_ work */ |
109 | struct mutex vsync_mutex; | |
110 | bool vsync_work_pending; | |
1067219b | 111 | struct completion dsp_hold_completion; |
4f9d39a7 DV |
112 | |
113 | /* protected by dev->event_lock */ | |
63ebb9fa | 114 | struct drm_pending_vblank_event *event; |
2048e328 | 115 | |
47a7eb45 TF |
116 | struct drm_flip_work fb_unref_work; |
117 | unsigned long pending; | |
118 | ||
69c34e41 YY |
119 | struct completion line_flag_completion; |
120 | ||
2048e328 MY |
121 | const struct vop_data *data; |
122 | ||
123 | uint32_t *regsbak; | |
124 | void __iomem *regs; | |
125 | ||
126 | /* physical map length of vop register */ | |
127 | uint32_t len; | |
128 | ||
129 | /* one time only one process allowed to config the register */ | |
130 | spinlock_t reg_lock; | |
131 | /* lock vop irq reg */ | |
132 | spinlock_t irq_lock; | |
133 | ||
134 | unsigned int irq; | |
135 | ||
136 | /* vop AHP clk */ | |
137 | struct clk *hclk; | |
138 | /* vop dclk */ | |
139 | struct clk *dclk; | |
140 | /* vop share memory frequency */ | |
141 | struct clk *aclk; | |
142 | ||
143 | /* vop dclk reset */ | |
144 | struct reset_control *dclk_rst; | |
145 | ||
2048e328 MY |
146 | struct vop_win win[]; |
147 | }; | |
148 | ||
2048e328 MY |
149 | static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) |
150 | { | |
151 | writel(v, vop->regs + offset); | |
152 | vop->regsbak[offset >> 2] = v; | |
153 | } | |
154 | ||
155 | static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) | |
156 | { | |
157 | return readl(vop->regs + offset); | |
158 | } | |
159 | ||
160 | static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, | |
161 | const struct vop_reg *reg) | |
162 | { | |
163 | return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; | |
164 | } | |
165 | ||
2048e328 | 166 | static inline void vop_mask_write(struct vop *vop, uint32_t offset, |
d49463ec MY |
167 | uint32_t mask, uint32_t shift, uint32_t v, |
168 | bool write_mask, bool relaxed) | |
2048e328 | 169 | { |
d49463ec MY |
170 | if (!mask) |
171 | return; | |
2048e328 | 172 | |
d49463ec MY |
173 | if (write_mask) { |
174 | v = ((v << shift) & 0xffff) | (mask << (shift + 16)); | |
175 | } else { | |
2048e328 MY |
176 | uint32_t cached_val = vop->regsbak[offset >> 2]; |
177 | ||
d49463ec MY |
178 | v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); |
179 | vop->regsbak[offset >> 2] = v; | |
2048e328 | 180 | } |
d49463ec MY |
181 | |
182 | if (relaxed) | |
183 | writel_relaxed(v, vop->regs + offset); | |
184 | else | |
185 | writel(v, vop->regs + offset); | |
2048e328 MY |
186 | } |
187 | ||
dbb3d944 MY |
188 | static inline uint32_t vop_get_intr_type(struct vop *vop, |
189 | const struct vop_reg *reg, int type) | |
190 | { | |
191 | uint32_t i, ret = 0; | |
192 | uint32_t regs = vop_read_reg(vop, 0, reg); | |
193 | ||
194 | for (i = 0; i < vop->data->intr->nintrs; i++) { | |
195 | if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) | |
196 | ret |= vop->data->intr->intrs[i]; | |
197 | } | |
198 | ||
199 | return ret; | |
200 | } | |
201 | ||
0cf33fe3 MY |
202 | static inline void vop_cfg_done(struct vop *vop) |
203 | { | |
204 | VOP_CTRL_SET(vop, cfg_done, 1); | |
205 | } | |
206 | ||
85a359f2 TF |
207 | static bool has_rb_swapped(uint32_t format) |
208 | { | |
209 | switch (format) { | |
210 | case DRM_FORMAT_XBGR8888: | |
211 | case DRM_FORMAT_ABGR8888: | |
212 | case DRM_FORMAT_BGR888: | |
213 | case DRM_FORMAT_BGR565: | |
214 | return true; | |
215 | default: | |
216 | return false; | |
217 | } | |
218 | } | |
219 | ||
2048e328 MY |
220 | static enum vop_data_format vop_convert_format(uint32_t format) |
221 | { | |
222 | switch (format) { | |
223 | case DRM_FORMAT_XRGB8888: | |
224 | case DRM_FORMAT_ARGB8888: | |
85a359f2 TF |
225 | case DRM_FORMAT_XBGR8888: |
226 | case DRM_FORMAT_ABGR8888: | |
2048e328 MY |
227 | return VOP_FMT_ARGB8888; |
228 | case DRM_FORMAT_RGB888: | |
85a359f2 | 229 | case DRM_FORMAT_BGR888: |
2048e328 MY |
230 | return VOP_FMT_RGB888; |
231 | case DRM_FORMAT_RGB565: | |
85a359f2 | 232 | case DRM_FORMAT_BGR565: |
2048e328 MY |
233 | return VOP_FMT_RGB565; |
234 | case DRM_FORMAT_NV12: | |
235 | return VOP_FMT_YUV420SP; | |
236 | case DRM_FORMAT_NV16: | |
237 | return VOP_FMT_YUV422SP; | |
238 | case DRM_FORMAT_NV24: | |
239 | return VOP_FMT_YUV444SP; | |
240 | default: | |
ee4d7899 | 241 | DRM_ERROR("unsupported format[%08x]\n", format); |
2048e328 MY |
242 | return -EINVAL; |
243 | } | |
244 | } | |
245 | ||
84c7f8ca MY |
246 | static bool is_yuv_support(uint32_t format) |
247 | { | |
248 | switch (format) { | |
249 | case DRM_FORMAT_NV12: | |
250 | case DRM_FORMAT_NV16: | |
251 | case DRM_FORMAT_NV24: | |
252 | return true; | |
253 | default: | |
254 | return false; | |
255 | } | |
256 | } | |
257 | ||
2048e328 MY |
258 | static bool is_alpha_support(uint32_t format) |
259 | { | |
260 | switch (format) { | |
261 | case DRM_FORMAT_ARGB8888: | |
85a359f2 | 262 | case DRM_FORMAT_ABGR8888: |
2048e328 MY |
263 | return true; |
264 | default: | |
265 | return false; | |
266 | } | |
267 | } | |
268 | ||
4c156c21 MY |
269 | static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, |
270 | uint32_t dst, bool is_horizontal, | |
271 | int vsu_mode, int *vskiplines) | |
272 | { | |
273 | uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; | |
274 | ||
275 | if (is_horizontal) { | |
276 | if (mode == SCALE_UP) | |
277 | val = GET_SCL_FT_BIC(src, dst); | |
278 | else if (mode == SCALE_DOWN) | |
279 | val = GET_SCL_FT_BILI_DN(src, dst); | |
280 | } else { | |
281 | if (mode == SCALE_UP) { | |
282 | if (vsu_mode == SCALE_UP_BIL) | |
283 | val = GET_SCL_FT_BILI_UP(src, dst); | |
284 | else | |
285 | val = GET_SCL_FT_BIC(src, dst); | |
286 | } else if (mode == SCALE_DOWN) { | |
287 | if (vskiplines) { | |
288 | *vskiplines = scl_get_vskiplines(src, dst); | |
289 | val = scl_get_bili_dn_vskip(src, dst, | |
290 | *vskiplines); | |
291 | } else { | |
292 | val = GET_SCL_FT_BILI_DN(src, dst); | |
293 | } | |
294 | } | |
295 | } | |
296 | ||
297 | return val; | |
298 | } | |
299 | ||
300 | static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, | |
301 | uint32_t src_w, uint32_t src_h, uint32_t dst_w, | |
302 | uint32_t dst_h, uint32_t pixel_format) | |
303 | { | |
304 | uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; | |
305 | uint16_t cbcr_hor_scl_mode = SCALE_NONE; | |
306 | uint16_t cbcr_ver_scl_mode = SCALE_NONE; | |
307 | int hsub = drm_format_horz_chroma_subsampling(pixel_format); | |
308 | int vsub = drm_format_vert_chroma_subsampling(pixel_format); | |
309 | bool is_yuv = is_yuv_support(pixel_format); | |
310 | uint16_t cbcr_src_w = src_w / hsub; | |
311 | uint16_t cbcr_src_h = src_h / vsub; | |
312 | uint16_t vsu_mode; | |
313 | uint16_t lb_mode; | |
314 | uint32_t val; | |
2db00cf5 | 315 | int vskiplines = 0; |
4c156c21 MY |
316 | |
317 | if (dst_w > 3840) { | |
ee4d7899 | 318 | DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); |
4c156c21 MY |
319 | return; |
320 | } | |
321 | ||
1194fffb MY |
322 | if (!win->phy->scl->ext) { |
323 | VOP_SCL_SET(vop, win, scale_yrgb_x, | |
324 | scl_cal_scale2(src_w, dst_w)); | |
325 | VOP_SCL_SET(vop, win, scale_yrgb_y, | |
326 | scl_cal_scale2(src_h, dst_h)); | |
327 | if (is_yuv) { | |
328 | VOP_SCL_SET(vop, win, scale_cbcr_x, | |
ee8662fc | 329 | scl_cal_scale2(cbcr_src_w, dst_w)); |
1194fffb | 330 | VOP_SCL_SET(vop, win, scale_cbcr_y, |
ee8662fc | 331 | scl_cal_scale2(cbcr_src_h, dst_h)); |
1194fffb MY |
332 | } |
333 | return; | |
334 | } | |
335 | ||
4c156c21 MY |
336 | yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); |
337 | yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); | |
338 | ||
339 | if (is_yuv) { | |
340 | cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); | |
341 | cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); | |
342 | if (cbcr_hor_scl_mode == SCALE_DOWN) | |
343 | lb_mode = scl_vop_cal_lb_mode(dst_w, true); | |
344 | else | |
345 | lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); | |
346 | } else { | |
347 | if (yrgb_hor_scl_mode == SCALE_DOWN) | |
348 | lb_mode = scl_vop_cal_lb_mode(dst_w, false); | |
349 | else | |
350 | lb_mode = scl_vop_cal_lb_mode(src_w, false); | |
351 | } | |
352 | ||
1194fffb | 353 | VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); |
4c156c21 MY |
354 | if (lb_mode == LB_RGB_3840X2) { |
355 | if (yrgb_ver_scl_mode != SCALE_NONE) { | |
ee4d7899 | 356 | DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); |
4c156c21 MY |
357 | return; |
358 | } | |
359 | if (cbcr_ver_scl_mode != SCALE_NONE) { | |
ee4d7899 | 360 | DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); |
4c156c21 MY |
361 | return; |
362 | } | |
363 | vsu_mode = SCALE_UP_BIL; | |
364 | } else if (lb_mode == LB_RGB_2560X4) { | |
365 | vsu_mode = SCALE_UP_BIL; | |
366 | } else { | |
367 | vsu_mode = SCALE_UP_BIC; | |
368 | } | |
369 | ||
370 | val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, | |
371 | true, 0, NULL); | |
372 | VOP_SCL_SET(vop, win, scale_yrgb_x, val); | |
373 | val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, | |
374 | false, vsu_mode, &vskiplines); | |
375 | VOP_SCL_SET(vop, win, scale_yrgb_y, val); | |
376 | ||
1194fffb MY |
377 | VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); |
378 | VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); | |
4c156c21 | 379 | |
1194fffb MY |
380 | VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); |
381 | VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); | |
382 | VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); | |
383 | VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); | |
384 | VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); | |
4c156c21 MY |
385 | if (is_yuv) { |
386 | val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, | |
387 | dst_w, true, 0, NULL); | |
388 | VOP_SCL_SET(vop, win, scale_cbcr_x, val); | |
389 | val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, | |
390 | dst_h, false, vsu_mode, &vskiplines); | |
391 | VOP_SCL_SET(vop, win, scale_cbcr_y, val); | |
392 | ||
1194fffb MY |
393 | VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); |
394 | VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); | |
395 | VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); | |
396 | VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); | |
397 | VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); | |
398 | VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); | |
399 | VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); | |
4c156c21 MY |
400 | } |
401 | } | |
402 | ||
1067219b MY |
403 | static void vop_dsp_hold_valid_irq_enable(struct vop *vop) |
404 | { | |
405 | unsigned long flags; | |
406 | ||
407 | if (WARN_ON(!vop->is_enabled)) | |
408 | return; | |
409 | ||
410 | spin_lock_irqsave(&vop->irq_lock, flags); | |
411 | ||
fa374107 | 412 | VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); |
dbb3d944 | 413 | VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); |
1067219b MY |
414 | |
415 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
416 | } | |
417 | ||
418 | static void vop_dsp_hold_valid_irq_disable(struct vop *vop) | |
419 | { | |
420 | unsigned long flags; | |
421 | ||
422 | if (WARN_ON(!vop->is_enabled)) | |
423 | return; | |
424 | ||
425 | spin_lock_irqsave(&vop->irq_lock, flags); | |
426 | ||
dbb3d944 | 427 | VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); |
1067219b MY |
428 | |
429 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
430 | } | |
431 | ||
69c34e41 YY |
432 | /* |
433 | * (1) each frame starts at the start of the Vsync pulse which is signaled by | |
434 | * the "FRAME_SYNC" interrupt. | |
435 | * (2) the active data region of each frame ends at dsp_vact_end | |
436 | * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, | |
437 | * to get "LINE_FLAG" interrupt at the end of the active on screen data. | |
438 | * | |
439 | * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end | |
440 | * Interrupts | |
441 | * LINE_FLAG -------------------------------+ | |
442 | * FRAME_SYNC ----+ | | |
443 | * | | | |
444 | * v v | |
445 | * | Vsync | Vbp | Vactive | Vfp | | |
446 | * ^ ^ ^ ^ | |
447 | * | | | | | |
448 | * | | | | | |
449 | * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END | |
450 | * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END | |
451 | * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END | |
452 | * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END | |
453 | */ | |
454 | static bool vop_line_flag_irq_is_enabled(struct vop *vop) | |
455 | { | |
456 | uint32_t line_flag_irq; | |
457 | unsigned long flags; | |
458 | ||
459 | spin_lock_irqsave(&vop->irq_lock, flags); | |
460 | ||
461 | line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); | |
462 | ||
463 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
464 | ||
465 | return !!line_flag_irq; | |
466 | } | |
467 | ||
468 | static void vop_line_flag_irq_enable(struct vop *vop, int line_num) | |
469 | { | |
470 | unsigned long flags; | |
471 | ||
472 | if (WARN_ON(!vop->is_enabled)) | |
473 | return; | |
474 | ||
475 | spin_lock_irqsave(&vop->irq_lock, flags); | |
476 | ||
477 | VOP_CTRL_SET(vop, line_flag_num[0], line_num); | |
fa374107 | 478 | VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); |
69c34e41 YY |
479 | VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); |
480 | ||
481 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
482 | } | |
483 | ||
484 | static void vop_line_flag_irq_disable(struct vop *vop) | |
485 | { | |
486 | unsigned long flags; | |
487 | ||
488 | if (WARN_ON(!vop->is_enabled)) | |
489 | return; | |
490 | ||
491 | spin_lock_irqsave(&vop->irq_lock, flags); | |
492 | ||
493 | VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); | |
494 | ||
495 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
496 | } | |
497 | ||
39a9ad8f | 498 | static int vop_enable(struct drm_crtc *crtc) |
2048e328 MY |
499 | { |
500 | struct vop *vop = to_vop(crtc); | |
501 | int ret; | |
502 | ||
5d82d1a7 MY |
503 | ret = pm_runtime_get_sync(vop->dev); |
504 | if (ret < 0) { | |
505 | dev_err(vop->dev, "failed to get pm runtime: %d\n", ret); | |
39a9ad8f | 506 | goto err_put_pm_runtime; |
5d82d1a7 MY |
507 | } |
508 | ||
2048e328 | 509 | ret = clk_enable(vop->hclk); |
39a9ad8f SP |
510 | if (WARN_ON(ret < 0)) |
511 | goto err_put_pm_runtime; | |
2048e328 MY |
512 | |
513 | ret = clk_enable(vop->dclk); | |
39a9ad8f | 514 | if (WARN_ON(ret < 0)) |
2048e328 | 515 | goto err_disable_hclk; |
2048e328 MY |
516 | |
517 | ret = clk_enable(vop->aclk); | |
39a9ad8f | 518 | if (WARN_ON(ret < 0)) |
2048e328 | 519 | goto err_disable_dclk; |
2048e328 MY |
520 | |
521 | /* | |
522 | * Slave iommu shares power, irq and clock with vop. It was associated | |
523 | * automatically with this master device via common driver code. | |
524 | * Now that we have enabled the clock we attach it to the shared drm | |
525 | * mapping. | |
526 | */ | |
527 | ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); | |
528 | if (ret) { | |
529 | dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret); | |
530 | goto err_disable_aclk; | |
531 | } | |
532 | ||
77faa161 | 533 | memcpy(vop->regs, vop->regsbak, vop->len); |
17a794d7 CZ |
534 | vop_cfg_done(vop); |
535 | ||
52ab7891 MY |
536 | /* |
537 | * At here, vop clock & iommu is enable, R/W vop regs would be safe. | |
538 | */ | |
539 | vop->is_enabled = true; | |
540 | ||
2048e328 MY |
541 | spin_lock(&vop->reg_lock); |
542 | ||
543 | VOP_CTRL_SET(vop, standby, 0); | |
544 | ||
545 | spin_unlock(&vop->reg_lock); | |
546 | ||
547 | enable_irq(vop->irq); | |
548 | ||
b5f7b755 | 549 | drm_crtc_vblank_on(crtc); |
2048e328 | 550 | |
39a9ad8f | 551 | return 0; |
2048e328 MY |
552 | |
553 | err_disable_aclk: | |
554 | clk_disable(vop->aclk); | |
555 | err_disable_dclk: | |
556 | clk_disable(vop->dclk); | |
557 | err_disable_hclk: | |
558 | clk_disable(vop->hclk); | |
39a9ad8f SP |
559 | err_put_pm_runtime: |
560 | pm_runtime_put_sync(vop->dev); | |
561 | return ret; | |
2048e328 MY |
562 | } |
563 | ||
0ad3675d | 564 | static void vop_crtc_disable(struct drm_crtc *crtc) |
2048e328 MY |
565 | { |
566 | struct vop *vop = to_vop(crtc); | |
3ed6c649 | 567 | int i; |
2048e328 | 568 | |
893b6cad DV |
569 | WARN_ON(vop->event); |
570 | ||
b883c9ba SP |
571 | rockchip_drm_psr_deactivate(&vop->crtc); |
572 | ||
3ed6c649 TV |
573 | /* |
574 | * We need to make sure that all windows are disabled before we | |
575 | * disable that crtc. Otherwise we might try to scan from a destroyed | |
576 | * buffer later. | |
577 | */ | |
578 | for (i = 0; i < vop->data->win_size; i++) { | |
579 | struct vop_win *vop_win = &vop->win[i]; | |
580 | const struct vop_win_data *win = vop_win->data; | |
581 | ||
582 | spin_lock(&vop->reg_lock); | |
583 | VOP_WIN_SET(vop, win, enable, 0); | |
584 | spin_unlock(&vop->reg_lock); | |
585 | } | |
586 | ||
17a794d7 CZ |
587 | vop_cfg_done(vop); |
588 | ||
b5f7b755 | 589 | drm_crtc_vblank_off(crtc); |
2048e328 | 590 | |
2048e328 | 591 | /* |
1067219b MY |
592 | * Vop standby will take effect at end of current frame, |
593 | * if dsp hold valid irq happen, it means standby complete. | |
594 | * | |
595 | * we must wait standby complete when we want to disable aclk, | |
596 | * if not, memory bus maybe dead. | |
2048e328 | 597 | */ |
1067219b MY |
598 | reinit_completion(&vop->dsp_hold_completion); |
599 | vop_dsp_hold_valid_irq_enable(vop); | |
600 | ||
2048e328 MY |
601 | spin_lock(&vop->reg_lock); |
602 | ||
603 | VOP_CTRL_SET(vop, standby, 1); | |
604 | ||
605 | spin_unlock(&vop->reg_lock); | |
52ab7891 | 606 | |
1067219b MY |
607 | wait_for_completion(&vop->dsp_hold_completion); |
608 | ||
609 | vop_dsp_hold_valid_irq_disable(vop); | |
610 | ||
611 | disable_irq(vop->irq); | |
612 | ||
52ab7891 | 613 | vop->is_enabled = false; |
1067219b | 614 | |
2048e328 | 615 | /* |
1067219b | 616 | * vop standby complete, so iommu detach is safe. |
2048e328 | 617 | */ |
2048e328 MY |
618 | rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); |
619 | ||
1067219b | 620 | clk_disable(vop->dclk); |
2048e328 MY |
621 | clk_disable(vop->aclk); |
622 | clk_disable(vop->hclk); | |
5d82d1a7 | 623 | pm_runtime_put(vop->dev); |
893b6cad DV |
624 | |
625 | if (crtc->state->event && !crtc->state->active) { | |
626 | spin_lock_irq(&crtc->dev->event_lock); | |
627 | drm_crtc_send_vblank_event(crtc, crtc->state->event); | |
628 | spin_unlock_irq(&crtc->dev->event_lock); | |
629 | ||
630 | crtc->state->event = NULL; | |
631 | } | |
2048e328 MY |
632 | } |
633 | ||
63ebb9fa | 634 | static void vop_plane_destroy(struct drm_plane *plane) |
2048e328 | 635 | { |
63ebb9fa | 636 | drm_plane_cleanup(plane); |
2048e328 MY |
637 | } |
638 | ||
63ebb9fa MY |
639 | static int vop_plane_atomic_check(struct drm_plane *plane, |
640 | struct drm_plane_state *state) | |
2048e328 | 641 | { |
63ebb9fa | 642 | struct drm_crtc *crtc = state->crtc; |
92915da6 | 643 | struct drm_crtc_state *crtc_state; |
63ebb9fa | 644 | struct drm_framebuffer *fb = state->fb; |
2048e328 MY |
645 | struct vop_win *vop_win = to_vop_win(plane); |
646 | const struct vop_win_data *win = vop_win->data; | |
2048e328 | 647 | int ret; |
63ebb9fa | 648 | struct drm_rect clip; |
4c156c21 MY |
649 | int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : |
650 | DRM_PLANE_HELPER_NO_SCALING; | |
651 | int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : | |
652 | DRM_PLANE_HELPER_NO_SCALING; | |
2048e328 | 653 | |
63ebb9fa | 654 | if (!crtc || !fb) |
d47a7246 | 655 | return 0; |
92915da6 JK |
656 | |
657 | crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); | |
658 | if (WARN_ON(!crtc_state)) | |
659 | return -EINVAL; | |
660 | ||
63ebb9fa MY |
661 | clip.x1 = 0; |
662 | clip.y1 = 0; | |
92915da6 JK |
663 | clip.x2 = crtc_state->adjusted_mode.hdisplay; |
664 | clip.y2 = crtc_state->adjusted_mode.vdisplay; | |
63ebb9fa | 665 | |
f9b96be0 VS |
666 | ret = drm_plane_helper_check_state(state, &clip, |
667 | min_scale, max_scale, | |
668 | true, true); | |
2048e328 MY |
669 | if (ret) |
670 | return ret; | |
671 | ||
f9b96be0 | 672 | if (!state->visible) |
d47a7246 | 673 | return 0; |
2048e328 | 674 | |
438b74a5 | 675 | ret = vop_convert_format(fb->format->format); |
d47a7246 TF |
676 | if (ret < 0) |
677 | return ret; | |
84c7f8ca | 678 | |
63ebb9fa MY |
679 | /* |
680 | * Src.x1 can be odd when do clip, but yuv plane start point | |
681 | * need align with 2 pixel. | |
682 | */ | |
438b74a5 | 683 | if (is_yuv_support(fb->format->format) && ((state->src.x1 >> 16) % 2)) |
2048e328 | 684 | return -EINVAL; |
2048e328 | 685 | |
63ebb9fa MY |
686 | return 0; |
687 | } | |
2048e328 | 688 | |
63ebb9fa MY |
689 | static void vop_plane_atomic_disable(struct drm_plane *plane, |
690 | struct drm_plane_state *old_state) | |
691 | { | |
63ebb9fa MY |
692 | struct vop_win *vop_win = to_vop_win(plane); |
693 | const struct vop_win_data *win = vop_win->data; | |
694 | struct vop *vop = to_vop(old_state->crtc); | |
2048e328 | 695 | |
63ebb9fa MY |
696 | if (!old_state->crtc) |
697 | return; | |
2048e328 | 698 | |
63ebb9fa | 699 | spin_lock(&vop->reg_lock); |
2048e328 | 700 | |
63ebb9fa | 701 | VOP_WIN_SET(vop, win, enable, 0); |
84c7f8ca | 702 | |
63ebb9fa | 703 | spin_unlock(&vop->reg_lock); |
63ebb9fa | 704 | } |
84c7f8ca | 705 | |
63ebb9fa MY |
706 | static void vop_plane_atomic_update(struct drm_plane *plane, |
707 | struct drm_plane_state *old_state) | |
708 | { | |
709 | struct drm_plane_state *state = plane->state; | |
710 | struct drm_crtc *crtc = state->crtc; | |
711 | struct vop_win *vop_win = to_vop_win(plane); | |
63ebb9fa MY |
712 | const struct vop_win_data *win = vop_win->data; |
713 | struct vop *vop = to_vop(state->crtc); | |
714 | struct drm_framebuffer *fb = state->fb; | |
715 | unsigned int actual_w, actual_h; | |
716 | unsigned int dsp_stx, dsp_sty; | |
717 | uint32_t act_info, dsp_info, dsp_st; | |
ac92028e VS |
718 | struct drm_rect *src = &state->src; |
719 | struct drm_rect *dest = &state->dst; | |
63ebb9fa MY |
720 | struct drm_gem_object *obj, *uv_obj; |
721 | struct rockchip_gem_object *rk_obj, *rk_uv_obj; | |
722 | unsigned long offset; | |
723 | dma_addr_t dma_addr; | |
724 | uint32_t val; | |
725 | bool rb_swap; | |
d47a7246 | 726 | int format; |
84c7f8ca | 727 | |
2048e328 | 728 | /* |
63ebb9fa | 729 | * can't update plane when vop is disabled. |
2048e328 | 730 | */ |
4f9d39a7 | 731 | if (WARN_ON(!crtc)) |
63ebb9fa | 732 | return; |
2048e328 | 733 | |
63ebb9fa MY |
734 | if (WARN_ON(!vop->is_enabled)) |
735 | return; | |
2048e328 | 736 | |
d47a7246 | 737 | if (!state->visible) { |
63ebb9fa MY |
738 | vop_plane_atomic_disable(plane, old_state); |
739 | return; | |
2048e328 | 740 | } |
63ebb9fa MY |
741 | |
742 | obj = rockchip_fb_get_gem_obj(fb, 0); | |
743 | rk_obj = to_rockchip_obj(obj); | |
744 | ||
745 | actual_w = drm_rect_width(src) >> 16; | |
746 | actual_h = drm_rect_height(src) >> 16; | |
747 | act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); | |
748 | ||
749 | dsp_info = (drm_rect_height(dest) - 1) << 16; | |
750 | dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; | |
751 | ||
752 | dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; | |
753 | dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; | |
754 | dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); | |
755 | ||
353c8598 | 756 | offset = (src->x1 >> 16) * fb->format->cpp[0]; |
63ebb9fa | 757 | offset += (src->y1 >> 16) * fb->pitches[0]; |
d47a7246 TF |
758 | dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; |
759 | ||
438b74a5 | 760 | format = vop_convert_format(fb->format->format); |
2048e328 MY |
761 | |
762 | spin_lock(&vop->reg_lock); | |
763 | ||
d47a7246 | 764 | VOP_WIN_SET(vop, win, format, format); |
63ebb9fa | 765 | VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2); |
d47a7246 | 766 | VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); |
438b74a5 VS |
767 | if (is_yuv_support(fb->format->format)) { |
768 | int hsub = drm_format_horz_chroma_subsampling(fb->format->format); | |
769 | int vsub = drm_format_vert_chroma_subsampling(fb->format->format); | |
353c8598 | 770 | int bpp = fb->format->cpp[1]; |
63ebb9fa MY |
771 | |
772 | uv_obj = rockchip_fb_get_gem_obj(fb, 1); | |
773 | rk_uv_obj = to_rockchip_obj(uv_obj); | |
774 | ||
775 | offset = (src->x1 >> 16) * bpp / hsub; | |
776 | offset += (src->y1 >> 16) * fb->pitches[1] / vsub; | |
777 | ||
778 | dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; | |
779 | VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2); | |
780 | VOP_WIN_SET(vop, win, uv_mst, dma_addr); | |
84c7f8ca | 781 | } |
4c156c21 MY |
782 | |
783 | if (win->phy->scl) | |
784 | scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, | |
63ebb9fa | 785 | drm_rect_width(dest), drm_rect_height(dest), |
438b74a5 | 786 | fb->format->format); |
4c156c21 | 787 | |
63ebb9fa MY |
788 | VOP_WIN_SET(vop, win, act_info, act_info); |
789 | VOP_WIN_SET(vop, win, dsp_info, dsp_info); | |
790 | VOP_WIN_SET(vop, win, dsp_st, dsp_st); | |
4c156c21 | 791 | |
438b74a5 | 792 | rb_swap = has_rb_swapped(fb->format->format); |
85a359f2 | 793 | VOP_WIN_SET(vop, win, rb_swap, rb_swap); |
2048e328 | 794 | |
438b74a5 | 795 | if (is_alpha_support(fb->format->format)) { |
2048e328 MY |
796 | VOP_WIN_SET(vop, win, dst_alpha_ctl, |
797 | DST_FACTOR_M0(ALPHA_SRC_INVERSE)); | |
798 | val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | | |
799 | SRC_ALPHA_M0(ALPHA_STRAIGHT) | | |
800 | SRC_BLEND_M0(ALPHA_PER_PIX) | | |
801 | SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | | |
802 | SRC_FACTOR_M0(ALPHA_ONE); | |
803 | VOP_WIN_SET(vop, win, src_alpha_ctl, val); | |
804 | } else { | |
805 | VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); | |
806 | } | |
807 | ||
808 | VOP_WIN_SET(vop, win, enable, 1); | |
2048e328 | 809 | spin_unlock(&vop->reg_lock); |
2048e328 MY |
810 | } |
811 | ||
63ebb9fa MY |
812 | static const struct drm_plane_helper_funcs plane_helper_funcs = { |
813 | .atomic_check = vop_plane_atomic_check, | |
814 | .atomic_update = vop_plane_atomic_update, | |
815 | .atomic_disable = vop_plane_atomic_disable, | |
816 | }; | |
2048e328 | 817 | |
2048e328 | 818 | static const struct drm_plane_funcs vop_plane_funcs = { |
63ebb9fa MY |
819 | .update_plane = drm_atomic_helper_update_plane, |
820 | .disable_plane = drm_atomic_helper_disable_plane, | |
2048e328 | 821 | .destroy = vop_plane_destroy, |
d47a7246 TF |
822 | .reset = drm_atomic_helper_plane_reset, |
823 | .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, | |
824 | .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, | |
2048e328 MY |
825 | }; |
826 | ||
2048e328 MY |
827 | static int vop_crtc_enable_vblank(struct drm_crtc *crtc) |
828 | { | |
829 | struct vop *vop = to_vop(crtc); | |
830 | unsigned long flags; | |
831 | ||
63ebb9fa | 832 | if (WARN_ON(!vop->is_enabled)) |
2048e328 MY |
833 | return -EPERM; |
834 | ||
835 | spin_lock_irqsave(&vop->irq_lock, flags); | |
836 | ||
fa374107 | 837 | VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); |
dbb3d944 | 838 | VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); |
2048e328 MY |
839 | |
840 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
841 | ||
842 | return 0; | |
843 | } | |
844 | ||
845 | static void vop_crtc_disable_vblank(struct drm_crtc *crtc) | |
846 | { | |
847 | struct vop *vop = to_vop(crtc); | |
848 | unsigned long flags; | |
849 | ||
63ebb9fa | 850 | if (WARN_ON(!vop->is_enabled)) |
2048e328 | 851 | return; |
31e980c5 | 852 | |
2048e328 | 853 | spin_lock_irqsave(&vop->irq_lock, flags); |
dbb3d944 MY |
854 | |
855 | VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); | |
856 | ||
2048e328 MY |
857 | spin_unlock_irqrestore(&vop->irq_lock, flags); |
858 | } | |
859 | ||
2048e328 MY |
860 | static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, |
861 | const struct drm_display_mode *mode, | |
862 | struct drm_display_mode *adjusted_mode) | |
863 | { | |
b59b8de3 CZ |
864 | struct vop *vop = to_vop(crtc); |
865 | ||
b59b8de3 CZ |
866 | adjusted_mode->clock = |
867 | clk_round_rate(vop->dclk, mode->clock * 1000) / 1000; | |
868 | ||
2048e328 MY |
869 | return true; |
870 | } | |
871 | ||
63ebb9fa | 872 | static void vop_crtc_enable(struct drm_crtc *crtc) |
2048e328 MY |
873 | { |
874 | struct vop *vop = to_vop(crtc); | |
4e257d9e | 875 | struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); |
63ebb9fa | 876 | struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; |
2048e328 MY |
877 | u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; |
878 | u16 hdisplay = adjusted_mode->hdisplay; | |
879 | u16 htotal = adjusted_mode->htotal; | |
880 | u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; | |
881 | u16 hact_end = hact_st + hdisplay; | |
882 | u16 vdisplay = adjusted_mode->vdisplay; | |
883 | u16 vtotal = adjusted_mode->vtotal; | |
884 | u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; | |
885 | u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; | |
886 | u16 vact_end = vact_st + vdisplay; | |
0a63bfd0 | 887 | uint32_t pin_pol, val; |
39a9ad8f | 888 | int ret; |
2048e328 | 889 | |
893b6cad DV |
890 | WARN_ON(vop->event); |
891 | ||
39a9ad8f SP |
892 | ret = vop_enable(crtc); |
893 | if (ret) { | |
894 | DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); | |
895 | return; | |
896 | } | |
897 | ||
2048e328 | 898 | /* |
ce3887ed MY |
899 | * If dclk rate is zero, mean that scanout is stop, |
900 | * we don't need wait any more. | |
2048e328 | 901 | */ |
ce3887ed MY |
902 | if (clk_get_rate(vop->dclk)) { |
903 | /* | |
904 | * Rk3288 vop timing register is immediately, when configure | |
905 | * display timing on display time, may cause tearing. | |
906 | * | |
907 | * Vop standby will take effect at end of current frame, | |
908 | * if dsp hold valid irq happen, it means standby complete. | |
909 | * | |
910 | * mode set: | |
911 | * standby and wait complete --> |---- | |
912 | * | display time | |
913 | * |---- | |
914 | * |---> dsp hold irq | |
915 | * configure display timing --> | | |
916 | * standby exit | | |
917 | * | new frame start. | |
918 | */ | |
919 | ||
920 | reinit_completion(&vop->dsp_hold_completion); | |
921 | vop_dsp_hold_valid_irq_enable(vop); | |
922 | ||
923 | spin_lock(&vop->reg_lock); | |
924 | ||
925 | VOP_CTRL_SET(vop, standby, 1); | |
926 | ||
927 | spin_unlock(&vop->reg_lock); | |
928 | ||
929 | wait_for_completion(&vop->dsp_hold_completion); | |
930 | ||
931 | vop_dsp_hold_valid_irq_disable(vop); | |
932 | } | |
2048e328 | 933 | |
1a0f7ed3 CZ |
934 | pin_pol = BIT(DCLK_INVERT); |
935 | pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? | |
936 | 0 : BIT(HSYNC_POSITIVE); | |
937 | pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? | |
938 | 0 : BIT(VSYNC_POSITIVE); | |
0a63bfd0 MY |
939 | VOP_CTRL_SET(vop, pin_pol, pin_pol); |
940 | ||
4e257d9e MY |
941 | switch (s->output_type) { |
942 | case DRM_MODE_CONNECTOR_LVDS: | |
943 | VOP_CTRL_SET(vop, rgb_en, 1); | |
0a63bfd0 | 944 | VOP_CTRL_SET(vop, rgb_pin_pol, pin_pol); |
4e257d9e MY |
945 | break; |
946 | case DRM_MODE_CONNECTOR_eDP: | |
0a63bfd0 | 947 | VOP_CTRL_SET(vop, edp_pin_pol, pin_pol); |
4e257d9e MY |
948 | VOP_CTRL_SET(vop, edp_en, 1); |
949 | break; | |
950 | case DRM_MODE_CONNECTOR_HDMIA: | |
0a63bfd0 | 951 | VOP_CTRL_SET(vop, hdmi_pin_pol, pin_pol); |
4e257d9e MY |
952 | VOP_CTRL_SET(vop, hdmi_en, 1); |
953 | break; | |
954 | case DRM_MODE_CONNECTOR_DSI: | |
0a63bfd0 | 955 | VOP_CTRL_SET(vop, mipi_pin_pol, pin_pol); |
4e257d9e MY |
956 | VOP_CTRL_SET(vop, mipi_en, 1); |
957 | break; | |
1a0f7ed3 CZ |
958 | case DRM_MODE_CONNECTOR_DisplayPort: |
959 | pin_pol &= ~BIT(DCLK_INVERT); | |
960 | VOP_CTRL_SET(vop, dp_pin_pol, pin_pol); | |
961 | VOP_CTRL_SET(vop, dp_en, 1); | |
962 | break; | |
4e257d9e | 963 | default: |
ee4d7899 SP |
964 | DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", |
965 | s->output_type); | |
4e257d9e MY |
966 | } |
967 | VOP_CTRL_SET(vop, out_mode, s->output_mode); | |
2048e328 MY |
968 | |
969 | VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); | |
970 | val = hact_st << 16; | |
971 | val |= hact_end; | |
972 | VOP_CTRL_SET(vop, hact_st_end, val); | |
973 | VOP_CTRL_SET(vop, hpost_st_end, val); | |
974 | ||
975 | VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); | |
976 | val = vact_st << 16; | |
977 | val |= vact_end; | |
978 | VOP_CTRL_SET(vop, vact_st_end, val); | |
979 | VOP_CTRL_SET(vop, vpost_st_end, val); | |
980 | ||
2048e328 | 981 | clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); |
ce3887ed MY |
982 | |
983 | VOP_CTRL_SET(vop, standby, 0); | |
b883c9ba SP |
984 | |
985 | rockchip_drm_psr_activate(&vop->crtc); | |
2048e328 MY |
986 | } |
987 | ||
7caecdbe TF |
988 | static bool vop_fs_irq_is_pending(struct vop *vop) |
989 | { | |
990 | return VOP_INTR_GET_TYPE(vop, status, FS_INTR); | |
991 | } | |
992 | ||
993 | static void vop_wait_for_irq_handler(struct vop *vop) | |
994 | { | |
995 | bool pending; | |
996 | int ret; | |
997 | ||
998 | /* | |
999 | * Spin until frame start interrupt status bit goes low, which means | |
1000 | * that interrupt handler was invoked and cleared it. The timeout of | |
1001 | * 10 msecs is really too long, but it is just a safety measure if | |
1002 | * something goes really wrong. The wait will only happen in the very | |
1003 | * unlikely case of a vblank happening exactly at the same time and | |
1004 | * shouldn't exceed microseconds range. | |
1005 | */ | |
1006 | ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, | |
1007 | !pending, 0, 10 * 1000); | |
1008 | if (ret) | |
1009 | DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); | |
1010 | ||
1011 | synchronize_irq(vop->irq); | |
1012 | } | |
1013 | ||
63ebb9fa MY |
1014 | static void vop_crtc_atomic_flush(struct drm_crtc *crtc, |
1015 | struct drm_crtc_state *old_crtc_state) | |
2048e328 | 1016 | { |
47a7eb45 TF |
1017 | struct drm_atomic_state *old_state = old_crtc_state->state; |
1018 | struct drm_plane_state *old_plane_state; | |
2048e328 | 1019 | struct vop *vop = to_vop(crtc); |
47a7eb45 TF |
1020 | struct drm_plane *plane; |
1021 | int i; | |
2048e328 | 1022 | |
63ebb9fa MY |
1023 | if (WARN_ON(!vop->is_enabled)) |
1024 | return; | |
2048e328 | 1025 | |
63ebb9fa | 1026 | spin_lock(&vop->reg_lock); |
2048e328 | 1027 | |
63ebb9fa | 1028 | vop_cfg_done(vop); |
2048e328 | 1029 | |
63ebb9fa | 1030 | spin_unlock(&vop->reg_lock); |
7caecdbe TF |
1031 | |
1032 | /* | |
1033 | * There is a (rather unlikely) possiblity that a vblank interrupt | |
1034 | * fired before we set the cfg_done bit. To avoid spuriously | |
1035 | * signalling flip completion we need to wait for it to finish. | |
1036 | */ | |
1037 | vop_wait_for_irq_handler(vop); | |
47a7eb45 | 1038 | |
41ee4367 TF |
1039 | spin_lock_irq(&crtc->dev->event_lock); |
1040 | if (crtc->state->event) { | |
1041 | WARN_ON(drm_crtc_vblank_get(crtc) != 0); | |
1042 | WARN_ON(vop->event); | |
1043 | ||
1044 | vop->event = crtc->state->event; | |
1045 | crtc->state->event = NULL; | |
1046 | } | |
1047 | spin_unlock_irq(&crtc->dev->event_lock); | |
1048 | ||
47a7eb45 TF |
1049 | for_each_plane_in_state(old_state, plane, old_plane_state, i) { |
1050 | if (!old_plane_state->fb) | |
1051 | continue; | |
1052 | ||
1053 | if (old_plane_state->fb == plane->state->fb) | |
1054 | continue; | |
1055 | ||
1056 | drm_framebuffer_reference(old_plane_state->fb); | |
1057 | drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); | |
1058 | set_bit(VOP_PENDING_FB_UNREF, &vop->pending); | |
1059 | WARN_ON(drm_crtc_vblank_get(crtc) != 0); | |
1060 | } | |
2048e328 MY |
1061 | } |
1062 | ||
63ebb9fa MY |
1063 | static void vop_crtc_atomic_begin(struct drm_crtc *crtc, |
1064 | struct drm_crtc_state *old_crtc_state) | |
2048e328 | 1065 | { |
b883c9ba | 1066 | rockchip_drm_psr_flush(crtc); |
2048e328 MY |
1067 | } |
1068 | ||
63ebb9fa MY |
1069 | static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { |
1070 | .enable = vop_crtc_enable, | |
1071 | .disable = vop_crtc_disable, | |
1072 | .mode_fixup = vop_crtc_mode_fixup, | |
1073 | .atomic_flush = vop_crtc_atomic_flush, | |
1074 | .atomic_begin = vop_crtc_atomic_begin, | |
1075 | }; | |
1076 | ||
2048e328 MY |
1077 | static void vop_crtc_destroy(struct drm_crtc *crtc) |
1078 | { | |
1079 | drm_crtc_cleanup(crtc); | |
1080 | } | |
1081 | ||
dc0b408f JK |
1082 | static void vop_crtc_reset(struct drm_crtc *crtc) |
1083 | { | |
1084 | if (crtc->state) | |
1085 | __drm_atomic_helper_crtc_destroy_state(crtc->state); | |
1086 | kfree(crtc->state); | |
1087 | ||
1088 | crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL); | |
1089 | if (crtc->state) | |
1090 | crtc->state->crtc = crtc; | |
1091 | } | |
1092 | ||
4e257d9e MY |
1093 | static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) |
1094 | { | |
1095 | struct rockchip_crtc_state *rockchip_state; | |
1096 | ||
1097 | rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); | |
1098 | if (!rockchip_state) | |
1099 | return NULL; | |
1100 | ||
1101 | __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); | |
1102 | return &rockchip_state->base; | |
1103 | } | |
1104 | ||
1105 | static void vop_crtc_destroy_state(struct drm_crtc *crtc, | |
1106 | struct drm_crtc_state *state) | |
1107 | { | |
1108 | struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); | |
1109 | ||
ec2dc6a0 | 1110 | __drm_atomic_helper_crtc_destroy_state(&s->base); |
4e257d9e MY |
1111 | kfree(s); |
1112 | } | |
1113 | ||
2048e328 | 1114 | static const struct drm_crtc_funcs vop_crtc_funcs = { |
63ebb9fa MY |
1115 | .set_config = drm_atomic_helper_set_config, |
1116 | .page_flip = drm_atomic_helper_page_flip, | |
2048e328 | 1117 | .destroy = vop_crtc_destroy, |
dc0b408f | 1118 | .reset = vop_crtc_reset, |
4e257d9e MY |
1119 | .atomic_duplicate_state = vop_crtc_duplicate_state, |
1120 | .atomic_destroy_state = vop_crtc_destroy_state, | |
c3605dfc SG |
1121 | .enable_vblank = vop_crtc_enable_vblank, |
1122 | .disable_vblank = vop_crtc_disable_vblank, | |
2048e328 MY |
1123 | }; |
1124 | ||
47a7eb45 TF |
1125 | static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) |
1126 | { | |
1127 | struct vop *vop = container_of(work, struct vop, fb_unref_work); | |
1128 | struct drm_framebuffer *fb = val; | |
1129 | ||
1130 | drm_crtc_vblank_put(&vop->crtc); | |
1131 | drm_framebuffer_unreference(fb); | |
1132 | } | |
1133 | ||
63ebb9fa | 1134 | static void vop_handle_vblank(struct vop *vop) |
2048e328 | 1135 | { |
63ebb9fa MY |
1136 | struct drm_device *drm = vop->drm_dev; |
1137 | struct drm_crtc *crtc = &vop->crtc; | |
1138 | unsigned long flags; | |
2048e328 | 1139 | |
893b6cad | 1140 | spin_lock_irqsave(&drm->event_lock, flags); |
63ebb9fa | 1141 | if (vop->event) { |
63ebb9fa | 1142 | drm_crtc_send_vblank_event(crtc, vop->event); |
5b680403 | 1143 | drm_crtc_vblank_put(crtc); |
646ec687 | 1144 | vop->event = NULL; |
5b680403 | 1145 | } |
893b6cad DV |
1146 | spin_unlock_irqrestore(&drm->event_lock, flags); |
1147 | ||
47a7eb45 TF |
1148 | if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) |
1149 | drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); | |
2048e328 MY |
1150 | } |
1151 | ||
1152 | static irqreturn_t vop_isr(int irq, void *data) | |
1153 | { | |
1154 | struct vop *vop = data; | |
b5f7b755 | 1155 | struct drm_crtc *crtc = &vop->crtc; |
dbb3d944 | 1156 | uint32_t active_irqs; |
2048e328 | 1157 | unsigned long flags; |
1067219b | 1158 | int ret = IRQ_NONE; |
2048e328 MY |
1159 | |
1160 | /* | |
dbb3d944 | 1161 | * interrupt register has interrupt status, enable and clear bits, we |
2048e328 MY |
1162 | * must hold irq_lock to avoid a race with enable/disable_vblank(). |
1163 | */ | |
1164 | spin_lock_irqsave(&vop->irq_lock, flags); | |
dbb3d944 MY |
1165 | |
1166 | active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); | |
2048e328 MY |
1167 | /* Clear all active interrupt sources */ |
1168 | if (active_irqs) | |
dbb3d944 MY |
1169 | VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); |
1170 | ||
2048e328 MY |
1171 | spin_unlock_irqrestore(&vop->irq_lock, flags); |
1172 | ||
1173 | /* This is expected for vop iommu irqs, since the irq is shared */ | |
1174 | if (!active_irqs) | |
1175 | return IRQ_NONE; | |
1176 | ||
1067219b MY |
1177 | if (active_irqs & DSP_HOLD_VALID_INTR) { |
1178 | complete(&vop->dsp_hold_completion); | |
1179 | active_irqs &= ~DSP_HOLD_VALID_INTR; | |
1180 | ret = IRQ_HANDLED; | |
2048e328 MY |
1181 | } |
1182 | ||
69c34e41 YY |
1183 | if (active_irqs & LINE_FLAG_INTR) { |
1184 | complete(&vop->line_flag_completion); | |
1185 | active_irqs &= ~LINE_FLAG_INTR; | |
1186 | ret = IRQ_HANDLED; | |
1187 | } | |
1188 | ||
1067219b | 1189 | if (active_irqs & FS_INTR) { |
b5f7b755 | 1190 | drm_crtc_handle_vblank(crtc); |
63ebb9fa | 1191 | vop_handle_vblank(vop); |
1067219b | 1192 | active_irqs &= ~FS_INTR; |
63ebb9fa | 1193 | ret = IRQ_HANDLED; |
1067219b | 1194 | } |
2048e328 | 1195 | |
1067219b MY |
1196 | /* Unhandled irqs are spurious. */ |
1197 | if (active_irqs) | |
ee4d7899 SP |
1198 | DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", |
1199 | active_irqs); | |
1067219b MY |
1200 | |
1201 | return ret; | |
2048e328 MY |
1202 | } |
1203 | ||
1204 | static int vop_create_crtc(struct vop *vop) | |
1205 | { | |
1206 | const struct vop_data *vop_data = vop->data; | |
1207 | struct device *dev = vop->dev; | |
1208 | struct drm_device *drm_dev = vop->drm_dev; | |
328b51c0 | 1209 | struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; |
2048e328 MY |
1210 | struct drm_crtc *crtc = &vop->crtc; |
1211 | struct device_node *port; | |
1212 | int ret; | |
1213 | int i; | |
1214 | ||
1215 | /* | |
1216 | * Create drm_plane for primary and cursor planes first, since we need | |
1217 | * to pass them to drm_crtc_init_with_planes, which sets the | |
1218 | * "possible_crtcs" to the newly initialized crtc. | |
1219 | */ | |
1220 | for (i = 0; i < vop_data->win_size; i++) { | |
1221 | struct vop_win *vop_win = &vop->win[i]; | |
1222 | const struct vop_win_data *win_data = vop_win->data; | |
1223 | ||
1224 | if (win_data->type != DRM_PLANE_TYPE_PRIMARY && | |
1225 | win_data->type != DRM_PLANE_TYPE_CURSOR) | |
1226 | continue; | |
1227 | ||
1228 | ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, | |
1229 | 0, &vop_plane_funcs, | |
1230 | win_data->phy->data_formats, | |
1231 | win_data->phy->nformats, | |
b0b3b795 | 1232 | win_data->type, NULL); |
2048e328 | 1233 | if (ret) { |
ee4d7899 SP |
1234 | DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", |
1235 | ret); | |
2048e328 MY |
1236 | goto err_cleanup_planes; |
1237 | } | |
1238 | ||
1239 | plane = &vop_win->base; | |
63ebb9fa | 1240 | drm_plane_helper_add(plane, &plane_helper_funcs); |
2048e328 MY |
1241 | if (plane->type == DRM_PLANE_TYPE_PRIMARY) |
1242 | primary = plane; | |
1243 | else if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
1244 | cursor = plane; | |
1245 | } | |
1246 | ||
1247 | ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, | |
f9882876 | 1248 | &vop_crtc_funcs, NULL); |
2048e328 | 1249 | if (ret) |
328b51c0 | 1250 | goto err_cleanup_planes; |
2048e328 MY |
1251 | |
1252 | drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); | |
1253 | ||
1254 | /* | |
1255 | * Create drm_planes for overlay windows with possible_crtcs restricted | |
1256 | * to the newly created crtc. | |
1257 | */ | |
1258 | for (i = 0; i < vop_data->win_size; i++) { | |
1259 | struct vop_win *vop_win = &vop->win[i]; | |
1260 | const struct vop_win_data *win_data = vop_win->data; | |
1261 | unsigned long possible_crtcs = 1 << drm_crtc_index(crtc); | |
1262 | ||
1263 | if (win_data->type != DRM_PLANE_TYPE_OVERLAY) | |
1264 | continue; | |
1265 | ||
1266 | ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, | |
1267 | possible_crtcs, | |
1268 | &vop_plane_funcs, | |
1269 | win_data->phy->data_formats, | |
1270 | win_data->phy->nformats, | |
b0b3b795 | 1271 | win_data->type, NULL); |
2048e328 | 1272 | if (ret) { |
ee4d7899 SP |
1273 | DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", |
1274 | ret); | |
2048e328 MY |
1275 | goto err_cleanup_crtc; |
1276 | } | |
63ebb9fa | 1277 | drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); |
2048e328 MY |
1278 | } |
1279 | ||
1280 | port = of_get_child_by_name(dev->of_node, "port"); | |
1281 | if (!port) { | |
ee4d7899 SP |
1282 | DRM_DEV_ERROR(vop->dev, "no port node found in %s\n", |
1283 | dev->of_node->full_name); | |
328b51c0 | 1284 | ret = -ENOENT; |
2048e328 MY |
1285 | goto err_cleanup_crtc; |
1286 | } | |
1287 | ||
47a7eb45 TF |
1288 | drm_flip_work_init(&vop->fb_unref_work, "fb_unref", |
1289 | vop_fb_unref_worker); | |
1290 | ||
1067219b | 1291 | init_completion(&vop->dsp_hold_completion); |
69c34e41 | 1292 | init_completion(&vop->line_flag_completion); |
2048e328 | 1293 | crtc->port = port; |
2048e328 MY |
1294 | |
1295 | return 0; | |
1296 | ||
1297 | err_cleanup_crtc: | |
1298 | drm_crtc_cleanup(crtc); | |
1299 | err_cleanup_planes: | |
328b51c0 DA |
1300 | list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, |
1301 | head) | |
2048e328 MY |
1302 | drm_plane_cleanup(plane); |
1303 | return ret; | |
1304 | } | |
1305 | ||
1306 | static void vop_destroy_crtc(struct vop *vop) | |
1307 | { | |
1308 | struct drm_crtc *crtc = &vop->crtc; | |
328b51c0 DA |
1309 | struct drm_device *drm_dev = vop->drm_dev; |
1310 | struct drm_plane *plane, *tmp; | |
2048e328 | 1311 | |
2048e328 | 1312 | of_node_put(crtc->port); |
328b51c0 DA |
1313 | |
1314 | /* | |
1315 | * We need to cleanup the planes now. Why? | |
1316 | * | |
1317 | * The planes are "&vop->win[i].base". That means the memory is | |
1318 | * all part of the big "struct vop" chunk of memory. That memory | |
1319 | * was devm allocated and associated with this component. We need to | |
1320 | * free it ourselves before vop_unbind() finishes. | |
1321 | */ | |
1322 | list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, | |
1323 | head) | |
1324 | vop_plane_destroy(plane); | |
1325 | ||
1326 | /* | |
1327 | * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() | |
1328 | * references the CRTC. | |
1329 | */ | |
2048e328 | 1330 | drm_crtc_cleanup(crtc); |
47a7eb45 | 1331 | drm_flip_work_cleanup(&vop->fb_unref_work); |
2048e328 MY |
1332 | } |
1333 | ||
1334 | static int vop_initial(struct vop *vop) | |
1335 | { | |
1336 | const struct vop_data *vop_data = vop->data; | |
1337 | const struct vop_reg_data *init_table = vop_data->init_table; | |
1338 | struct reset_control *ahb_rst; | |
1339 | int i, ret; | |
1340 | ||
1341 | vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); | |
1342 | if (IS_ERR(vop->hclk)) { | |
1343 | dev_err(vop->dev, "failed to get hclk source\n"); | |
1344 | return PTR_ERR(vop->hclk); | |
1345 | } | |
1346 | vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); | |
1347 | if (IS_ERR(vop->aclk)) { | |
1348 | dev_err(vop->dev, "failed to get aclk source\n"); | |
1349 | return PTR_ERR(vop->aclk); | |
1350 | } | |
1351 | vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); | |
1352 | if (IS_ERR(vop->dclk)) { | |
1353 | dev_err(vop->dev, "failed to get dclk source\n"); | |
1354 | return PTR_ERR(vop->dclk); | |
1355 | } | |
1356 | ||
2048e328 MY |
1357 | ret = clk_prepare(vop->dclk); |
1358 | if (ret < 0) { | |
1359 | dev_err(vop->dev, "failed to prepare dclk\n"); | |
d7b53fd9 | 1360 | return ret; |
2048e328 MY |
1361 | } |
1362 | ||
d7b53fd9 SS |
1363 | /* Enable both the hclk and aclk to setup the vop */ |
1364 | ret = clk_prepare_enable(vop->hclk); | |
2048e328 | 1365 | if (ret < 0) { |
d7b53fd9 | 1366 | dev_err(vop->dev, "failed to prepare/enable hclk\n"); |
2048e328 MY |
1367 | goto err_unprepare_dclk; |
1368 | } | |
1369 | ||
d7b53fd9 | 1370 | ret = clk_prepare_enable(vop->aclk); |
2048e328 | 1371 | if (ret < 0) { |
d7b53fd9 SS |
1372 | dev_err(vop->dev, "failed to prepare/enable aclk\n"); |
1373 | goto err_disable_hclk; | |
2048e328 | 1374 | } |
d7b53fd9 | 1375 | |
2048e328 MY |
1376 | /* |
1377 | * do hclk_reset, reset all vop registers. | |
1378 | */ | |
1379 | ahb_rst = devm_reset_control_get(vop->dev, "ahb"); | |
1380 | if (IS_ERR(ahb_rst)) { | |
1381 | dev_err(vop->dev, "failed to get ahb reset\n"); | |
1382 | ret = PTR_ERR(ahb_rst); | |
d7b53fd9 | 1383 | goto err_disable_aclk; |
2048e328 MY |
1384 | } |
1385 | reset_control_assert(ahb_rst); | |
1386 | usleep_range(10, 20); | |
1387 | reset_control_deassert(ahb_rst); | |
1388 | ||
1389 | memcpy(vop->regsbak, vop->regs, vop->len); | |
1390 | ||
1391 | for (i = 0; i < vop_data->table_size; i++) | |
1392 | vop_writel(vop, init_table[i].offset, init_table[i].value); | |
1393 | ||
1394 | for (i = 0; i < vop_data->win_size; i++) { | |
1395 | const struct vop_win_data *win = &vop_data->win[i]; | |
1396 | ||
1397 | VOP_WIN_SET(vop, win, enable, 0); | |
1398 | } | |
1399 | ||
1400 | vop_cfg_done(vop); | |
1401 | ||
1402 | /* | |
1403 | * do dclk_reset, let all config take affect. | |
1404 | */ | |
1405 | vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); | |
1406 | if (IS_ERR(vop->dclk_rst)) { | |
1407 | dev_err(vop->dev, "failed to get dclk reset\n"); | |
1408 | ret = PTR_ERR(vop->dclk_rst); | |
d7b53fd9 | 1409 | goto err_disable_aclk; |
2048e328 MY |
1410 | } |
1411 | reset_control_assert(vop->dclk_rst); | |
1412 | usleep_range(10, 20); | |
1413 | reset_control_deassert(vop->dclk_rst); | |
1414 | ||
1415 | clk_disable(vop->hclk); | |
d7b53fd9 | 1416 | clk_disable(vop->aclk); |
2048e328 | 1417 | |
31e980c5 | 1418 | vop->is_enabled = false; |
2048e328 MY |
1419 | |
1420 | return 0; | |
1421 | ||
d7b53fd9 SS |
1422 | err_disable_aclk: |
1423 | clk_disable_unprepare(vop->aclk); | |
2048e328 | 1424 | err_disable_hclk: |
d7b53fd9 | 1425 | clk_disable_unprepare(vop->hclk); |
2048e328 MY |
1426 | err_unprepare_dclk: |
1427 | clk_unprepare(vop->dclk); | |
2048e328 MY |
1428 | return ret; |
1429 | } | |
1430 | ||
1431 | /* | |
1432 | * Initialize the vop->win array elements. | |
1433 | */ | |
1434 | static void vop_win_init(struct vop *vop) | |
1435 | { | |
1436 | const struct vop_data *vop_data = vop->data; | |
1437 | unsigned int i; | |
1438 | ||
1439 | for (i = 0; i < vop_data->win_size; i++) { | |
1440 | struct vop_win *vop_win = &vop->win[i]; | |
1441 | const struct vop_win_data *win_data = &vop_data->win[i]; | |
1442 | ||
1443 | vop_win->data = win_data; | |
1444 | vop_win->vop = vop; | |
2048e328 MY |
1445 | } |
1446 | } | |
1447 | ||
69c34e41 YY |
1448 | /** |
1449 | * rockchip_drm_wait_line_flag - acqiure the give line flag event | |
1450 | * @crtc: CRTC to enable line flag | |
1451 | * @line_num: interested line number | |
1452 | * @mstimeout: millisecond for timeout | |
1453 | * | |
1454 | * Driver would hold here until the interested line flag interrupt have | |
1455 | * happened or timeout to wait. | |
1456 | * | |
1457 | * Returns: | |
1458 | * Zero on success, negative errno on failure. | |
1459 | */ | |
1460 | int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num, | |
1461 | unsigned int mstimeout) | |
1462 | { | |
1463 | struct vop *vop = to_vop(crtc); | |
1464 | unsigned long jiffies_left; | |
1465 | ||
1466 | if (!crtc || !vop->is_enabled) | |
1467 | return -ENODEV; | |
1468 | ||
1469 | if (line_num > crtc->mode.vtotal || mstimeout <= 0) | |
1470 | return -EINVAL; | |
1471 | ||
1472 | if (vop_line_flag_irq_is_enabled(vop)) | |
1473 | return -EBUSY; | |
1474 | ||
1475 | reinit_completion(&vop->line_flag_completion); | |
1476 | vop_line_flag_irq_enable(vop, line_num); | |
1477 | ||
1478 | jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, | |
1479 | msecs_to_jiffies(mstimeout)); | |
1480 | vop_line_flag_irq_disable(vop); | |
1481 | ||
1482 | if (jiffies_left == 0) { | |
1483 | dev_err(vop->dev, "Timeout waiting for IRQ\n"); | |
1484 | return -ETIMEDOUT; | |
1485 | } | |
1486 | ||
1487 | return 0; | |
1488 | } | |
1489 | EXPORT_SYMBOL(rockchip_drm_wait_line_flag); | |
1490 | ||
2048e328 MY |
1491 | static int vop_bind(struct device *dev, struct device *master, void *data) |
1492 | { | |
1493 | struct platform_device *pdev = to_platform_device(dev); | |
2048e328 MY |
1494 | const struct vop_data *vop_data; |
1495 | struct drm_device *drm_dev = data; | |
1496 | struct vop *vop; | |
1497 | struct resource *res; | |
1498 | size_t alloc_size; | |
3ea68922 | 1499 | int ret, irq; |
2048e328 | 1500 | |
a67719d1 | 1501 | vop_data = of_device_get_match_data(dev); |
2048e328 MY |
1502 | if (!vop_data) |
1503 | return -ENODEV; | |
1504 | ||
1505 | /* Allocate vop struct and its vop_win array */ | |
1506 | alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size; | |
1507 | vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL); | |
1508 | if (!vop) | |
1509 | return -ENOMEM; | |
1510 | ||
1511 | vop->dev = dev; | |
1512 | vop->data = vop_data; | |
1513 | vop->drm_dev = drm_dev; | |
1514 | dev_set_drvdata(dev, vop); | |
1515 | ||
1516 | vop_win_init(vop); | |
1517 | ||
1518 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1519 | vop->len = resource_size(res); | |
1520 | vop->regs = devm_ioremap_resource(dev, res); | |
1521 | if (IS_ERR(vop->regs)) | |
1522 | return PTR_ERR(vop->regs); | |
1523 | ||
1524 | vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); | |
1525 | if (!vop->regsbak) | |
1526 | return -ENOMEM; | |
1527 | ||
1528 | ret = vop_initial(vop); | |
1529 | if (ret < 0) { | |
1530 | dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret); | |
1531 | return ret; | |
1532 | } | |
1533 | ||
3ea68922 HS |
1534 | irq = platform_get_irq(pdev, 0); |
1535 | if (irq < 0) { | |
2048e328 | 1536 | dev_err(dev, "cannot find irq for vop\n"); |
3ea68922 | 1537 | return irq; |
2048e328 | 1538 | } |
3ea68922 | 1539 | vop->irq = (unsigned int)irq; |
2048e328 MY |
1540 | |
1541 | spin_lock_init(&vop->reg_lock); | |
1542 | spin_lock_init(&vop->irq_lock); | |
1543 | ||
1544 | mutex_init(&vop->vsync_mutex); | |
1545 | ||
63ebb9fa MY |
1546 | ret = devm_request_irq(dev, vop->irq, vop_isr, |
1547 | IRQF_SHARED, dev_name(dev), vop); | |
2048e328 MY |
1548 | if (ret) |
1549 | return ret; | |
1550 | ||
1551 | /* IRQ is initially disabled; it gets enabled in power_on */ | |
1552 | disable_irq(vop->irq); | |
1553 | ||
1554 | ret = vop_create_crtc(vop); | |
1555 | if (ret) | |
8c763c9b | 1556 | goto err_enable_irq; |
2048e328 MY |
1557 | |
1558 | pm_runtime_enable(&pdev->dev); | |
5182c1a5 | 1559 | |
2048e328 | 1560 | return 0; |
8c763c9b SP |
1561 | |
1562 | err_enable_irq: | |
1563 | enable_irq(vop->irq); /* To balance out the disable_irq above */ | |
1564 | return ret; | |
2048e328 MY |
1565 | } |
1566 | ||
1567 | static void vop_unbind(struct device *dev, struct device *master, void *data) | |
1568 | { | |
1569 | struct vop *vop = dev_get_drvdata(dev); | |
1570 | ||
1571 | pm_runtime_disable(dev); | |
1572 | vop_destroy_crtc(vop); | |
1573 | } | |
1574 | ||
a67719d1 | 1575 | const struct component_ops vop_component_ops = { |
2048e328 MY |
1576 | .bind = vop_bind, |
1577 | .unbind = vop_unbind, | |
1578 | }; | |
54255e81 | 1579 | EXPORT_SYMBOL_GPL(vop_component_ops); |