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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 281
[linux-2.6-block.git] / drivers / gpu / drm / rockchip / rockchip_drm_vop.c
CommitLineData
2048e328
MY		 1/*
2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <drm/drm.h>
16#include <drm/drmP.h>
63ebb9fa 17#include <drm/drm_atomic.h>
15609559 18#include <drm/drm_atomic_uapi.h>
2048e328 19#include <drm/drm_crtc.h>
47a7eb45 20#include <drm/drm_flip_work.h>
63d5e06a 21#include <drm/drm_gem_framebuffer_helper.h>
2048e328 22#include <drm/drm_plane_helper.h>
fcd70cd3 23#include <drm/drm_probe_helper.h>
6cca3869 24#ifdef CONFIG_DRM_ANALOGIX_DP
3190e58d 25#include <drm/bridge/analogix_dp.h>
6cca3869 26#endif
2048e328
MY		 27
28#include <linux/kernel.h>
00fe6148 29#include <linux/module.h>
2048e328
MY		 30#include <linux/platform_device.h>
31#include <linux/clk.h>
7caecdbe 32#include <linux/iopoll.h>
2048e328
MY		 33#include <linux/of.h>
34#include <linux/of_device.h>
35#include <linux/pm_runtime.h>
36#include <linux/component.h>
29adeb4f 37#include <linux/overflow.h>
2048e328
MY		 38
39#include <linux/reset.h>
40#include <linux/delay.h>
41
42#include "rockchip_drm_drv.h"
43#include "rockchip_drm_gem.h"
44#include "rockchip_drm_fb.h"
5182c1a5 45#include "rockchip_drm_psr.h"
2048e328 46#include "rockchip_drm_vop.h"
1f0f0151 47#include "rockchip_rgb.h"
2048e328 48
2996fb75 49#define VOP_WIN_SET(vop, win, name, v) \
9a61c54b 50 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)
2996fb75 51#define VOP_SCL_SET(vop, win, name, v) \
9a61c54b 52 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name)
2996fb75 53#define VOP_SCL_SET_EXT(vop, win, name, v) \
9a61c54b
M		 54 vop_reg_set(vop, &win->phy->scl->ext->name, \
55 win->base, ~0, v, #name)
ac6560df 56
2996fb75 57#define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \
1c21aa8f
DC		 58 do { \
59 if (win_yuv2yuv && win_yuv2yuv->name.mask) \
60 vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \
61 } while (0)
62
2996fb75 63#define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \
1c21aa8f
DC		 64 do { \
65 if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \
66 vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \
67 } while (0)
68
ac6560df 69#define VOP_INTR_SET_MASK(vop, name, mask, v) \
9a61c54b
M		 70 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name)
71
72#define VOP_REG_SET(vop, group, name, v) \
73 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
ac6560df 74
dbb3d944
MY		 75#define VOP_INTR_SET_TYPE(vop, name, type, v) \
76 do { \
c7647f86 77 int i, reg = 0, mask = 0; \
dbb3d944 78 for (i = 0; i < vop->data->intr->nintrs; i++) { \
c7647f86 79 if (vop->data->intr->intrs[i] & type) { \
dbb3d944 80 reg |= (v) << i; \
c7647f86
JK		 81 mask |= 1 << i; \
82 } \
dbb3d944 83 } \
ac6560df 84 VOP_INTR_SET_MASK(vop, name, mask, reg); \
dbb3d944
MY		 85 } while (0)
86#define VOP_INTR_GET_TYPE(vop, name, type) \
87 vop_get_intr_type(vop, &vop->data->intr->name, type)
88
2996fb75
EG		 89#define VOP_WIN_GET(vop, win, name) \
90 vop_read_reg(vop, win->offset, win->phy->name)
2048e328 91
677e8bbc
DC		 92#define VOP_WIN_HAS_REG(win, name) \
93 (!!(win->phy->name.mask))
94
2048e328
MY		 95#define VOP_WIN_GET_YRGBADDR(vop, win) \
96 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
97
58badaa7
KK		 98#define VOP_WIN_TO_INDEX(vop_win) \
99 ((vop_win) - (vop_win)->vop->win)
100
2048e328
MY		 101#define to_vop(x) container_of(x, struct vop, crtc)
102#define to_vop_win(x) container_of(x, struct vop_win, base)
103
1c21aa8f
DC		 104/*
105 * The coefficients of the following matrix are all fixed points.
106 * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets.
107 * They are all represented in two's complement.
108 */
109static const uint32_t bt601_yuv2rgb[] = {
110 0x4A8, 0x0, 0x662,
111 0x4A8, 0x1E6F, 0x1CBF,
112 0x4A8, 0x812, 0x0,
113 0x321168, 0x0877CF, 0x2EB127
114};
115
47a7eb45
TF		 116enum vop_pending {
117 VOP_PENDING_FB_UNREF,
118};
119
2048e328
MY		 120struct vop_win {
121 struct drm_plane base;
122 const struct vop_win_data *data;
1c21aa8f 123 const struct vop_win_yuv2yuv_data *yuv2yuv_data;
2048e328 124 struct vop *vop;
2048e328
MY		 125};
126
1f0f0151 127struct rockchip_rgb;
2048e328
MY		 128struct vop {
129 struct drm_crtc crtc;
130 struct device *dev;
131 struct drm_device *drm_dev;
31e980c5 132 bool is_enabled;
2048e328 133
1067219b 134 struct completion dsp_hold_completion;
4f9d39a7
DV		 135
136 /* protected by dev->event_lock */
63ebb9fa 137 struct drm_pending_vblank_event *event;
2048e328 138
47a7eb45
TF		 139 struct drm_flip_work fb_unref_work;
140 unsigned long pending;
141
69c34e41
YY		 142 struct completion line_flag_completion;
143
2048e328
MY		 144 const struct vop_data *data;
145
146 uint32_t *regsbak;
147 void __iomem *regs;
148
149 /* physical map length of vop register */
150 uint32_t len;
151
152 /* one time only one process allowed to config the register */
153 spinlock_t reg_lock;
154 /* lock vop irq reg */
155 spinlock_t irq_lock;
e334d48b 156 /* protects crtc enable/disable */
157 struct mutex vop_lock;
2048e328
MY		 158
159 unsigned int irq;
160
161 /* vop AHP clk */
162 struct clk *hclk;
163 /* vop dclk */
164 struct clk *dclk;
165 /* vop share memory frequency */
166 struct clk *aclk;
167
168 /* vop dclk reset */
169 struct reset_control *dclk_rst;
170
1f0f0151
SH		 171 /* optional internal rgb encoder */
172 struct rockchip_rgb *rgb;
173
2048e328
MY		 174 struct vop_win win[];
175};
176
2048e328
MY		 177static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
178{
179 writel(v, vop->regs + offset);
180 vop->regsbak[offset >> 2] = v;
181}
182
183static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
184{
185 return readl(vop->regs + offset);
186}
187
188static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
189 const struct vop_reg *reg)
190{
191 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
192}
193
9a61c54b
M		 194static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
195 uint32_t _offset, uint32_t _mask, uint32_t v,
196 const char *reg_name)
2048e328 197{
9a61c54b
M		 198 int offset, mask, shift;
199
200 if (!reg || !reg->mask) {
d8dd6804 201 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name);
d49463ec 202 return;
9a61c54b
M		 203 }
204
205 offset = reg->offset + _offset;
206 mask = reg->mask & _mask;
207 shift = reg->shift;
2048e328 208
9a61c54b 209 if (reg->write_mask) {
d49463ec
MY		 210 v = ((v << shift) & 0xffff) | (mask << (shift + 16));
211 } else {
2048e328
MY		 212 uint32_t cached_val = vop->regsbak[offset >> 2];
213
d49463ec
MY		 214 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
215 vop->regsbak[offset >> 2] = v;
2048e328 216 }
d49463ec 217
9a61c54b 218 if (reg->relaxed)
d49463ec
MY		 219 writel_relaxed(v, vop->regs + offset);
220 else
221 writel(v, vop->regs + offset);
2048e328
MY		 222}
223
dbb3d944
MY		 224static inline uint32_t vop_get_intr_type(struct vop *vop,
225 const struct vop_reg *reg, int type)
226{
227 uint32_t i, ret = 0;
228 uint32_t regs = vop_read_reg(vop, 0, reg);
229
230 for (i = 0; i < vop->data->intr->nintrs; i++) {
231 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
232 ret |= vop->data->intr->intrs[i];
233 }
234
235 return ret;
236}
237
0cf33fe3
MY		 238static inline void vop_cfg_done(struct vop *vop)
239{
9a61c54b 240 VOP_REG_SET(vop, common, cfg_done, 1);
0cf33fe3
MY		 241}
242
85a359f2
TF		 243static bool has_rb_swapped(uint32_t format)
244{
245 switch (format) {
246 case DRM_FORMAT_XBGR8888:
247 case DRM_FORMAT_ABGR8888:
248 case DRM_FORMAT_BGR888:
249 case DRM_FORMAT_BGR565:
250 return true;
251 default:
252 return false;
253 }
254}
255
2048e328
MY		 256static enum vop_data_format vop_convert_format(uint32_t format)
257{
258 switch (format) {
259 case DRM_FORMAT_XRGB8888:
260 case DRM_FORMAT_ARGB8888:
85a359f2
TF		 261 case DRM_FORMAT_XBGR8888:
262 case DRM_FORMAT_ABGR8888:
2048e328
MY		 263 return VOP_FMT_ARGB8888;
264 case DRM_FORMAT_RGB888:
85a359f2 265 case DRM_FORMAT_BGR888:
2048e328
MY		 266 return VOP_FMT_RGB888;
267 case DRM_FORMAT_RGB565:
85a359f2 268 case DRM_FORMAT_BGR565:
2048e328
MY		 269 return VOP_FMT_RGB565;
270 case DRM_FORMAT_NV12:
271 return VOP_FMT_YUV420SP;
272 case DRM_FORMAT_NV16:
273 return VOP_FMT_YUV422SP;
274 case DRM_FORMAT_NV24:
275 return VOP_FMT_YUV444SP;
276 default:
ee4d7899 277 DRM_ERROR("unsupported format[%08x]\n", format);
2048e328
MY		 278 return -EINVAL;
279 }
280}
281
4c156c21
MY		 282static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
283 uint32_t dst, bool is_horizontal,
284 int vsu_mode, int *vskiplines)
285{
286 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
287
ce91d373
JC		 288 if (vskiplines)
289 *vskiplines = 0;
290
4c156c21
MY		 291 if (is_horizontal) {
292 if (mode == SCALE_UP)
293 val = GET_SCL_FT_BIC(src, dst);
294 else if (mode == SCALE_DOWN)
295 val = GET_SCL_FT_BILI_DN(src, dst);
296 } else {
297 if (mode == SCALE_UP) {
298 if (vsu_mode == SCALE_UP_BIL)
299 val = GET_SCL_FT_BILI_UP(src, dst);
300 else
301 val = GET_SCL_FT_BIC(src, dst);
302 } else if (mode == SCALE_DOWN) {
303 if (vskiplines) {
304 *vskiplines = scl_get_vskiplines(src, dst);
305 val = scl_get_bili_dn_vskip(src, dst,
306 *vskiplines);
307 } else {
308 val = GET_SCL_FT_BILI_DN(src, dst);
309 }
310 }
311 }
312
313 return val;
314}
315
316static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
317 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
318 uint32_t dst_h, uint32_t pixel_format)
319{
320 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
321 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
322 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
323 int hsub = drm_format_horz_chroma_subsampling(pixel_format);
324 int vsub = drm_format_vert_chroma_subsampling(pixel_format);
d8bd23d9
AKH		 325 const struct drm_format_info *info;
326 bool is_yuv = false;
4c156c21
MY		 327 uint16_t cbcr_src_w = src_w / hsub;
328 uint16_t cbcr_src_h = src_h / vsub;
329 uint16_t vsu_mode;
330 uint16_t lb_mode;
331 uint32_t val;
ce91d373 332 int vskiplines;
4c156c21 333
d8bd23d9
AKH		 334 info = drm_format_info(pixel_format);
335
336 if (info->is_yuv)
337 is_yuv = true;
338
4c156c21 339 if (dst_w > 3840) {
ee4d7899 340 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
4c156c21
MY		 341 return;
342 }
343
1194fffb
MY		 344 if (!win->phy->scl->ext) {
345 VOP_SCL_SET(vop, win, scale_yrgb_x,
346 scl_cal_scale2(src_w, dst_w));
347 VOP_SCL_SET(vop, win, scale_yrgb_y,
348 scl_cal_scale2(src_h, dst_h));
349 if (is_yuv) {
350 VOP_SCL_SET(vop, win, scale_cbcr_x,
ee8662fc 351 scl_cal_scale2(cbcr_src_w, dst_w));
1194fffb 352 VOP_SCL_SET(vop, win, scale_cbcr_y,
ee8662fc 353 scl_cal_scale2(cbcr_src_h, dst_h));
1194fffb
MY		 354 }
355 return;
356 }
357
4c156c21
MY		 358 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
359 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
360
361 if (is_yuv) {
362 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
363 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
364 if (cbcr_hor_scl_mode == SCALE_DOWN)
365 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
366 else
367 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
368 } else {
369 if (yrgb_hor_scl_mode == SCALE_DOWN)
370 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
371 else
372 lb_mode = scl_vop_cal_lb_mode(src_w, false);
373 }
374
1194fffb 375 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
4c156c21
MY		 376 if (lb_mode == LB_RGB_3840X2) {
377 if (yrgb_ver_scl_mode != SCALE_NONE) {
ee4d7899 378 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");
4c156c21
MY		 379 return;
380 }
381 if (cbcr_ver_scl_mode != SCALE_NONE) {
ee4d7899 382 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");
4c156c21
MY		 383 return;
384 }
385 vsu_mode = SCALE_UP_BIL;
386 } else if (lb_mode == LB_RGB_2560X4) {
387 vsu_mode = SCALE_UP_BIL;
388 } else {
389 vsu_mode = SCALE_UP_BIC;
390 }
391
392 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
393 true, 0, NULL);
394 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
395 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
396 false, vsu_mode, &vskiplines);
397 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
398
1194fffb
MY		 399 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
400 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
4c156c21 401
1194fffb
MY		 402 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
403 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
404 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
405 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
406 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
4c156c21
MY		 407 if (is_yuv) {
408 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
409 dst_w, true, 0, NULL);
410 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
411 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
412 dst_h, false, vsu_mode, &vskiplines);
413 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
414
1194fffb
MY		 415 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
416 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
417 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
418 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
419 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
420 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
421 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
4c156c21
MY		 422 }
423}
424
1067219b
MY		 425static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
426{
427 unsigned long flags;
428
429 if (WARN_ON(!vop->is_enabled))
430 return;
431
432 spin_lock_irqsave(&vop->irq_lock, flags);
433
fa374107 434 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
dbb3d944 435 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
1067219b
MY		 436
437 spin_unlock_irqrestore(&vop->irq_lock, flags);
438}
439
440static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
441{
442 unsigned long flags;
443
444 if (WARN_ON(!vop->is_enabled))
445 return;
446
447 spin_lock_irqsave(&vop->irq_lock, flags);
448
dbb3d944 449 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
1067219b
MY		 450
451 spin_unlock_irqrestore(&vop->irq_lock, flags);
452}
453
69c34e41
YY		 454/*
455 * (1) each frame starts at the start of the Vsync pulse which is signaled by
456 * the "FRAME_SYNC" interrupt.
457 * (2) the active data region of each frame ends at dsp_vact_end
458 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
459 * to get "LINE_FLAG" interrupt at the end of the active on screen data.
460 *
461 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
462 * Interrupts
463 * LINE_FLAG -------------------------------+
464 * FRAME_SYNC ----+ |
465 * | |
466 * v v
467 * | Vsync | Vbp | Vactive | Vfp |
468 * ^ ^ ^ ^
469 * | | | |
470 * | | | |
471 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END
472 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END
473 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END
474 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END
475 */
476static bool vop_line_flag_irq_is_enabled(struct vop *vop)
477{
478 uint32_t line_flag_irq;
479 unsigned long flags;
480
481 spin_lock_irqsave(&vop->irq_lock, flags);
482
483 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
484
485 spin_unlock_irqrestore(&vop->irq_lock, flags);
486
487 return !!line_flag_irq;
488}
489
459b086d 490static void vop_line_flag_irq_enable(struct vop *vop)
69c34e41
YY		 491{
492 unsigned long flags;
493
494 if (WARN_ON(!vop->is_enabled))
495 return;
496
497 spin_lock_irqsave(&vop->irq_lock, flags);
498
fa374107 499 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
69c34e41
YY		 500 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
501
502 spin_unlock_irqrestore(&vop->irq_lock, flags);
503}
504
505static void vop_line_flag_irq_disable(struct vop *vop)
506{
507 unsigned long flags;
508
509 if (WARN_ON(!vop->is_enabled))
510 return;
511
512 spin_lock_irqsave(&vop->irq_lock, flags);
513
514 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
515
516 spin_unlock_irqrestore(&vop->irq_lock, flags);
517}
518
e2810a71
HS		 519static int vop_core_clks_enable(struct vop *vop)
520{
521 int ret;
522
523 ret = clk_enable(vop->hclk);
524 if (ret < 0)
525 return ret;
526
527 ret = clk_enable(vop->aclk);
528 if (ret < 0)
529 goto err_disable_hclk;
530
531 return 0;
532
533err_disable_hclk:
534 clk_disable(vop->hclk);
535 return ret;
536}
537
538static void vop_core_clks_disable(struct vop *vop)
539{
540 clk_disable(vop->aclk);
541 clk_disable(vop->hclk);
542}
543
e9abc611
JK		 544static void vop_win_disable(struct vop *vop, const struct vop_win_data *win)
545{
546 if (win->phy->scl && win->phy->scl->ext) {
547 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
548 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
549 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
550 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
551 }
552
553 VOP_WIN_SET(vop, win, enable, 0);
554}
555
39a9ad8f 556static int vop_enable(struct drm_crtc *crtc)
2048e328
MY		 557{
558 struct vop *vop = to_vop(crtc);
64d77564 559 int ret, i;
2048e328 560
5d82d1a7
MY		 561 ret = pm_runtime_get_sync(vop->dev);
562 if (ret < 0) {
d8dd6804 563 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
5e570373 564 return ret;
5d82d1a7
MY		 565 }
566
e2810a71 567 ret = vop_core_clks_enable(vop);
39a9ad8f
SP		 568 if (WARN_ON(ret < 0))
569 goto err_put_pm_runtime;
2048e328
MY		 570
571 ret = clk_enable(vop->dclk);
39a9ad8f 572 if (WARN_ON(ret < 0))
e2810a71 573 goto err_disable_core;
2048e328
MY		 574
575 /*
576 * Slave iommu shares power, irq and clock with vop. It was associated
577 * automatically with this master device via common driver code.
578 * Now that we have enabled the clock we attach it to the shared drm
579 * mapping.
580 */
581 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
582 if (ret) {
d8dd6804
HM		 583 DRM_DEV_ERROR(vop->dev,
584 "failed to attach dma mapping, %d\n", ret);
e2810a71 585 goto err_disable_dclk;
2048e328
MY		 586 }
587
76f1416e
MZ		 588 spin_lock(&vop->reg_lock);
589 for (i = 0; i < vop->len; i += 4)
590 writel_relaxed(vop->regsbak[i / 4], vop->regs + i);
591
64d77564
M		 592 /*
593 * We need to make sure that all windows are disabled before we
594 * enable the crtc. Otherwise we might try to scan from a destroyed
595 * buffer later.
596 */
597 for (i = 0; i < vop->data->win_size; i++) {
598 struct vop_win *vop_win = &vop->win[i];
599 const struct vop_win_data *win = vop_win->data;
600
e9abc611 601 vop_win_disable(vop, win);
64d77564 602 }
76f1416e 603 spin_unlock(&vop->reg_lock);
64d77564 604
17a794d7
CZ		 605 vop_cfg_done(vop);
606
52ab7891
MY		 607 /*
608 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
609 */
610 vop->is_enabled = true;
611
2048e328
MY		 612 spin_lock(&vop->reg_lock);
613
9a61c54b 614 VOP_REG_SET(vop, common, standby, 1);
2048e328
MY		 615
616 spin_unlock(&vop->reg_lock);
617
b5f7b755 618 drm_crtc_vblank_on(crtc);
2048e328 619
39a9ad8f 620 return 0;
2048e328 621
2048e328
MY		 622err_disable_dclk:
623 clk_disable(vop->dclk);
e2810a71
HS		 624err_disable_core:
625 vop_core_clks_disable(vop);
39a9ad8f
SP		 626err_put_pm_runtime:
627 pm_runtime_put_sync(vop->dev);
628 return ret;
2048e328
MY		 629}
630
64581714
LP		 631static void vop_crtc_atomic_disable(struct drm_crtc *crtc,
632 struct drm_crtc_state *old_state)
2048e328
MY		 633{
634 struct vop *vop = to_vop(crtc);
635
893b6cad
DV		 636 WARN_ON(vop->event);
637
e334d48b 638 mutex_lock(&vop->vop_lock);
b5f7b755 639 drm_crtc_vblank_off(crtc);
2048e328 640
2048e328 641 /*
1067219b
MY		 642 * Vop standby will take effect at end of current frame,
643 * if dsp hold valid irq happen, it means standby complete.
644 *
645 * we must wait standby complete when we want to disable aclk,
646 * if not, memory bus maybe dead.
2048e328 647 */
1067219b
MY		 648 reinit_completion(&vop->dsp_hold_completion);
649 vop_dsp_hold_valid_irq_enable(vop);
650
2048e328
MY		 651 spin_lock(&vop->reg_lock);
652
9a61c54b 653 VOP_REG_SET(vop, common, standby, 1);
2048e328
MY		 654
655 spin_unlock(&vop->reg_lock);
52ab7891 656
1067219b
MY		 657 wait_for_completion(&vop->dsp_hold_completion);
658
659 vop_dsp_hold_valid_irq_disable(vop);
660
52ab7891 661 vop->is_enabled = false;
1067219b 662
2048e328 663 /*
1067219b 664 * vop standby complete, so iommu detach is safe.
2048e328 665 */
2048e328
MY		 666 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
667
1067219b 668 clk_disable(vop->dclk);
e2810a71 669 vop_core_clks_disable(vop);
5d82d1a7 670 pm_runtime_put(vop->dev);
e334d48b 671 mutex_unlock(&vop->vop_lock);
893b6cad
DV		 672
673 if (crtc->state->event && !crtc->state->active) {
674 spin_lock_irq(&crtc->dev->event_lock);
675 drm_crtc_send_vblank_event(crtc, crtc->state->event);
676 spin_unlock_irq(&crtc->dev->event_lock);
677
678 crtc->state->event = NULL;
679 }
2048e328
MY		 680}
681
63ebb9fa 682static void vop_plane_destroy(struct drm_plane *plane)
2048e328 683{
63ebb9fa 684 drm_plane_cleanup(plane);
2048e328
MY		 685}
686
63ebb9fa
MY		 687static int vop_plane_atomic_check(struct drm_plane *plane,
688 struct drm_plane_state *state)
2048e328 689{
63ebb9fa 690 struct drm_crtc *crtc = state->crtc;
92915da6 691 struct drm_crtc_state *crtc_state;
63ebb9fa 692 struct drm_framebuffer *fb = state->fb;
2048e328
MY		 693 struct vop_win *vop_win = to_vop_win(plane);
694 const struct vop_win_data *win = vop_win->data;
2048e328 695 int ret;
4c156c21
MY		 696 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
697 DRM_PLANE_HELPER_NO_SCALING;
698 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
699 DRM_PLANE_HELPER_NO_SCALING;
2048e328 700
63ebb9fa 701 if (!crtc || !fb)
d47a7246 702 return 0;
92915da6
JK		 703
704 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
705 if (WARN_ON(!crtc_state))
706 return -EINVAL;
707
81af63a4 708 ret = drm_atomic_helper_check_plane_state(state, crtc_state,
a01cb8ba
VS		 709 min_scale, max_scale,
710 true, true);
2048e328
MY		 711 if (ret)
712 return ret;
713
f9b96be0 714 if (!state->visible)
d47a7246 715 return 0;
2048e328 716
438b74a5 717 ret = vop_convert_format(fb->format->format);
d47a7246
TF		 718 if (ret < 0)
719 return ret;
84c7f8ca 720
63ebb9fa
MY		 721 /*
722 * Src.x1 can be odd when do clip, but yuv plane start point
723 * need align with 2 pixel.
724 */
d8bd23d9 725 if (fb->format->is_yuv && ((state->src.x1 >> 16) % 2)) {
d415fb87 726 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n");
2048e328 727 return -EINVAL;
d415fb87 728 }
2048e328 729
677e8bbc
DC		 730 if (fb->format->is_yuv && state->rotation & DRM_MODE_REFLECT_Y) {
731 DRM_ERROR("Invalid Source: Yuv format does not support this rotation\n");
732 return -EINVAL;
733 }
734
63ebb9fa
MY		 735 return 0;
736}
2048e328 737
63ebb9fa
MY		 738static void vop_plane_atomic_disable(struct drm_plane *plane,
739 struct drm_plane_state *old_state)
740{
63ebb9fa
MY		 741 struct vop_win *vop_win = to_vop_win(plane);
742 const struct vop_win_data *win = vop_win->data;
743 struct vop *vop = to_vop(old_state->crtc);
2048e328 744
63ebb9fa
MY		 745 if (!old_state->crtc)
746 return;
2048e328 747
63ebb9fa 748 spin_lock(&vop->reg_lock);
2048e328 749
e9abc611 750 vop_win_disable(vop, win);
84c7f8ca 751
63ebb9fa 752 spin_unlock(&vop->reg_lock);
63ebb9fa 753}
84c7f8ca 754
63ebb9fa
MY		 755static void vop_plane_atomic_update(struct drm_plane *plane,
756 struct drm_plane_state *old_state)
757{
758 struct drm_plane_state *state = plane->state;
759 struct drm_crtc *crtc = state->crtc;
760 struct vop_win *vop_win = to_vop_win(plane);
63ebb9fa 761 const struct vop_win_data *win = vop_win->data;
1c21aa8f 762 const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data;
63ebb9fa
MY		 763 struct vop *vop = to_vop(state->crtc);
764 struct drm_framebuffer *fb = state->fb;
765 unsigned int actual_w, actual_h;
766 unsigned int dsp_stx, dsp_sty;
767 uint32_t act_info, dsp_info, dsp_st;
ac92028e
VS		 768 struct drm_rect *src = &state->src;
769 struct drm_rect *dest = &state->dst;
63ebb9fa
MY		 770 struct drm_gem_object *obj, *uv_obj;
771 struct rockchip_gem_object *rk_obj, *rk_uv_obj;
772 unsigned long offset;
773 dma_addr_t dma_addr;
774 uint32_t val;
775 bool rb_swap;
58badaa7 776 int win_index = VOP_WIN_TO_INDEX(vop_win);
d47a7246 777 int format;
1c21aa8f
DC		 778 int is_yuv = fb->format->is_yuv;
779 int i;
84c7f8ca 780
2048e328 781 /*
63ebb9fa 782 * can't update plane when vop is disabled.
2048e328 783 */
4f9d39a7 784 if (WARN_ON(!crtc))
63ebb9fa 785 return;
2048e328 786
63ebb9fa
MY		 787 if (WARN_ON(!vop->is_enabled))
788 return;
2048e328 789
d47a7246 790 if (!state->visible) {
63ebb9fa
MY		 791 vop_plane_atomic_disable(plane, old_state);
792 return;
2048e328 793 }
63ebb9fa 794
957428f9 795 obj = fb->obj[0];
63ebb9fa
MY		 796 rk_obj = to_rockchip_obj(obj);
797
798 actual_w = drm_rect_width(src) >> 16;
799 actual_h = drm_rect_height(src) >> 16;
800 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
801
802 dsp_info = (drm_rect_height(dest) - 1) << 16;
803 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
804
805 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
806 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
807 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
808
353c8598 809 offset = (src->x1 >> 16) * fb->format->cpp[0];
63ebb9fa 810 offset += (src->y1 >> 16) * fb->pitches[0];
d47a7246
TF		 811 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
812
677e8bbc
DC		 813 /*
814 * For y-mirroring we need to move address
815 * to the beginning of the last line.
816 */
817 if (state->rotation & DRM_MODE_REFLECT_Y)
818 dma_addr += (actual_h - 1) * fb->pitches[0];
819
438b74a5 820 format = vop_convert_format(fb->format->format);
2048e328
MY		 821
822 spin_lock(&vop->reg_lock);
823
d47a7246 824 VOP_WIN_SET(vop, win, format, format);
da709a7b 825 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
d47a7246 826 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
1c21aa8f 827 VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
677e8bbc
DC		 828 VOP_WIN_SET(vop, win, y_mir_en,
829 (state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0);
830 VOP_WIN_SET(vop, win, x_mir_en,
831 (state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0);
1c21aa8f
DC		 832
833 if (is_yuv) {
438b74a5
VS		 834 int hsub = drm_format_horz_chroma_subsampling(fb->format->format);
835 int vsub = drm_format_vert_chroma_subsampling(fb->format->format);
353c8598 836 int bpp = fb->format->cpp[1];
63ebb9fa 837
957428f9 838 uv_obj = fb->obj[1];
63ebb9fa
MY		 839 rk_uv_obj = to_rockchip_obj(uv_obj);
840
841 offset = (src->x1 >> 16) * bpp / hsub;
842 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
843
844 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
da709a7b 845 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
63ebb9fa 846 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
1c21aa8f
DC		 847
848 for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) {
849 VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop,
850 win_yuv2yuv,
851 y2r_coefficients[i],
852 bt601_yuv2rgb[i]);
853 }
84c7f8ca 854 }
4c156c21
MY		 855
856 if (win->phy->scl)
857 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
63ebb9fa 858 drm_rect_width(dest), drm_rect_height(dest),
438b74a5 859 fb->format->format);
4c156c21 860
63ebb9fa
MY		 861 VOP_WIN_SET(vop, win, act_info, act_info);
862 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
863 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
4c156c21 864
438b74a5 865 rb_swap = has_rb_swapped(fb->format->format);
85a359f2 866 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
2048e328 867
58badaa7
KK		 868 /*
869 * Blending win0 with the background color doesn't seem to work
870 * correctly. We only get the background color, no matter the contents
871 * of the win0 framebuffer. However, blending pre-multiplied color
872 * with the default opaque black default background color is a no-op,
873 * so we can just disable blending to get the correct result.
874 */
875 if (fb->format->has_alpha && win_index > 0) {
2048e328
MY		 876 VOP_WIN_SET(vop, win, dst_alpha_ctl,
877 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
878 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
879 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
880 SRC_BLEND_M0(ALPHA_PER_PIX) |
881 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
882 SRC_FACTOR_M0(ALPHA_ONE);
883 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
884 } else {
885 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
886 }
887
888 VOP_WIN_SET(vop, win, enable, 1);
2048e328 889 spin_unlock(&vop->reg_lock);
2048e328
MY		 890}
891
15609559
EBS		 892static int vop_plane_atomic_async_check(struct drm_plane *plane,
893 struct drm_plane_state *state)
894{
895 struct vop_win *vop_win = to_vop_win(plane);
896 const struct vop_win_data *win = vop_win->data;
897 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
898 DRM_PLANE_HELPER_NO_SCALING;
899 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
900 DRM_PLANE_HELPER_NO_SCALING;
901 struct drm_crtc_state *crtc_state;
902
903 if (plane != state->crtc->cursor)
904 return -EINVAL;
905
906 if (!plane->state)
907 return -EINVAL;
908
909 if (!plane->state->fb)
910 return -EINVAL;
911
912 if (state->state)
913 crtc_state = drm_atomic_get_existing_crtc_state(state->state,
914 state->crtc);
915 else /* Special case for asynchronous cursor updates. */
916 crtc_state = plane->crtc->state;
917
918 return drm_atomic_helper_check_plane_state(plane->state, crtc_state,
919 min_scale, max_scale,
920 true, true);
921}
922
923static void vop_plane_atomic_async_update(struct drm_plane *plane,
924 struct drm_plane_state *new_state)
925{
926 struct vop *vop = to_vop(plane->state->crtc);
927 struct drm_plane_state *plane_state;
928
929 plane_state = plane->funcs->atomic_duplicate_state(plane);
930 plane_state->crtc_x = new_state->crtc_x;
931 plane_state->crtc_y = new_state->crtc_y;
932 plane_state->crtc_h = new_state->crtc_h;
933 plane_state->crtc_w = new_state->crtc_w;
934 plane_state->src_x = new_state->src_x;
935 plane_state->src_y = new_state->src_y;
936 plane_state->src_h = new_state->src_h;
937 plane_state->src_w = new_state->src_w;
938
939 if (plane_state->fb != new_state->fb)
940 drm_atomic_set_fb_for_plane(plane_state, new_state->fb);
941
942 swap(plane_state, plane->state);
943
944 if (plane->state->fb && plane->state->fb != new_state->fb) {
945 drm_framebuffer_get(plane->state->fb);
946 WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0);
947 drm_flip_work_queue(&vop->fb_unref_work, plane->state->fb);
948 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
949 }
950
951 if (vop->is_enabled) {
952 rockchip_drm_psr_inhibit_get_state(new_state->state);
953 vop_plane_atomic_update(plane, plane->state);
954 spin_lock(&vop->reg_lock);
955 vop_cfg_done(vop);
956 spin_unlock(&vop->reg_lock);
957 rockchip_drm_psr_inhibit_put_state(new_state->state);
958 }
959
960 plane->funcs->atomic_destroy_state(plane, plane_state);
961}
962
63ebb9fa
MY		 963static const struct drm_plane_helper_funcs plane_helper_funcs = {
964 .atomic_check = vop_plane_atomic_check,
965 .atomic_update = vop_plane_atomic_update,
966 .atomic_disable = vop_plane_atomic_disable,
15609559
EBS		 967 .atomic_async_check = vop_plane_atomic_async_check,
968 .atomic_async_update = vop_plane_atomic_async_update,
63d5e06a 969 .prepare_fb = drm_gem_fb_prepare_fb,
63ebb9fa 970};
2048e328 971
2048e328 972static const struct drm_plane_funcs vop_plane_funcs = {
63ebb9fa
MY		 973 .update_plane = drm_atomic_helper_update_plane,
974 .disable_plane = drm_atomic_helper_disable_plane,
2048e328 975 .destroy = vop_plane_destroy,
d47a7246
TF		 976 .reset = drm_atomic_helper_plane_reset,
977 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
978 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
2048e328
MY		 979};
980
2048e328
MY		 981static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
982{
983 struct vop *vop = to_vop(crtc);
984 unsigned long flags;
985
63ebb9fa 986 if (WARN_ON(!vop->is_enabled))
2048e328
MY		 987 return -EPERM;
988
989 spin_lock_irqsave(&vop->irq_lock, flags);
990
fa374107 991 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
dbb3d944 992 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
2048e328
MY		 993
994 spin_unlock_irqrestore(&vop->irq_lock, flags);
995
996 return 0;
997}
998
999static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1000{
1001 struct vop *vop = to_vop(crtc);
1002 unsigned long flags;
1003
63ebb9fa 1004 if (WARN_ON(!vop->is_enabled))
2048e328 1005 return;
31e980c5 1006
2048e328 1007 spin_lock_irqsave(&vop->irq_lock, flags);
dbb3d944
MY		 1008
1009 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1010
2048e328
MY		 1011 spin_unlock_irqrestore(&vop->irq_lock, flags);
1012}
1013
2048e328
MY		 1014static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1015 const struct drm_display_mode *mode,
1016 struct drm_display_mode *adjusted_mode)
1017{
b59b8de3
CZ		 1018 struct vop *vop = to_vop(crtc);
1019
b59b8de3
CZ		 1020 adjusted_mode->clock =
1021 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
1022
2048e328
MY		 1023 return true;
1024}
1025
0b20a0f8
LP		 1026static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
1027 struct drm_crtc_state *old_state)
2048e328
MY		 1028{
1029 struct vop *vop = to_vop(crtc);
efd11cc8 1030 const struct vop_data *vop_data = vop->data;
4e257d9e 1031 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
63ebb9fa 1032 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
2048e328
MY		 1033 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1034 u16 hdisplay = adjusted_mode->hdisplay;
1035 u16 htotal = adjusted_mode->htotal;
1036 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1037 u16 hact_end = hact_st + hdisplay;
1038 u16 vdisplay = adjusted_mode->vdisplay;
1039 u16 vtotal = adjusted_mode->vtotal;
1040 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1041 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1042 u16 vact_end = vact_st + vdisplay;
0a63bfd0 1043 uint32_t pin_pol, val;
a5c0fa44 1044 int dither_bpc = s->output_bpc ? s->output_bpc : 10;
39a9ad8f 1045 int ret;
2048e328 1046
e334d48b 1047 mutex_lock(&vop->vop_lock);
1048
893b6cad
DV		 1049 WARN_ON(vop->event);
1050
39a9ad8f
SP		 1051 ret = vop_enable(crtc);
1052 if (ret) {
e334d48b 1053 mutex_unlock(&vop->vop_lock);
39a9ad8f
SP		 1054 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
1055 return;
1056 }
1057
1a0f7ed3 1058 pin_pol = BIT(DCLK_INVERT);
d790ad03
JK		 1059 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
1060 BIT(HSYNC_POSITIVE) : 0;
1061 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ?
1062 BIT(VSYNC_POSITIVE) : 0;
9a61c54b 1063 VOP_REG_SET(vop, output, pin_pol, pin_pol);
cf6d100d 1064 VOP_REG_SET(vop, output, mipi_dual_channel_en, 0);
0a63bfd0 1065
4e257d9e
MY		 1066 switch (s->output_type) {
1067 case DRM_MODE_CONNECTOR_LVDS:
9a61c54b
M		 1068 VOP_REG_SET(vop, output, rgb_en, 1);
1069 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol);
4e257d9e
MY		 1070 break;
1071 case DRM_MODE_CONNECTOR_eDP:
9a61c54b
M		 1072 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol);
1073 VOP_REG_SET(vop, output, edp_en, 1);
4e257d9e
MY		 1074 break;
1075 case DRM_MODE_CONNECTOR_HDMIA:
9a61c54b
M		 1076 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol);
1077 VOP_REG_SET(vop, output, hdmi_en, 1);
4e257d9e
MY		 1078 break;
1079 case DRM_MODE_CONNECTOR_DSI:
9a61c54b
M		 1080 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol);
1081 VOP_REG_SET(vop, output, mipi_en, 1);
cf6d100d
HS		 1082 VOP_REG_SET(vop, output, mipi_dual_channel_en,
1083 !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL));
4e257d9e 1084 break;
1a0f7ed3
CZ		 1085 case DRM_MODE_CONNECTOR_DisplayPort:
1086 pin_pol &= ~BIT(DCLK_INVERT);
9a61c54b
M		 1087 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol);
1088 VOP_REG_SET(vop, output, dp_en, 1);
1a0f7ed3 1089 break;
4e257d9e 1090 default:
ee4d7899
SP		 1091 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
1092 s->output_type);
4e257d9e 1093 }
efd11cc8
M		 1094
1095 /*
1096 * if vop is not support RGB10 output, need force RGB10 to RGB888.
1097 */
1098 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1099 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
1100 s->output_mode = ROCKCHIP_OUT_MODE_P888;
6bda8112 1101
a5c0fa44 1102 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8)
6bda8112
MY		 1103 VOP_REG_SET(vop, common, pre_dither_down, 1);
1104 else
1105 VOP_REG_SET(vop, common, pre_dither_down, 0);
1106
a5c0fa44
UR		 1107 if (dither_bpc == 6) {
1108 VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO);
1109 VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666);
1110 VOP_REG_SET(vop, common, dither_down_en, 1);
1111 } else {
1112 VOP_REG_SET(vop, common, dither_down_en, 0);
1113 }
1114
9a61c54b 1115 VOP_REG_SET(vop, common, out_mode, s->output_mode);
2048e328 1116
9a61c54b 1117 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len);
2048e328
MY		 1118 val = hact_st << 16;
1119 val |= hact_end;
9a61c54b
M		 1120 VOP_REG_SET(vop, modeset, hact_st_end, val);
1121 VOP_REG_SET(vop, modeset, hpost_st_end, val);
2048e328 1122
9a61c54b 1123 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len);
2048e328
MY		 1124 val = vact_st << 16;
1125 val |= vact_end;
9a61c54b
M		 1126 VOP_REG_SET(vop, modeset, vact_st_end, val);
1127 VOP_REG_SET(vop, modeset, vpost_st_end, val);
2048e328 1128
9a61c54b 1129 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end);
459b086d 1130
2048e328 1131 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
ce3887ed 1132
9a61c54b 1133 VOP_REG_SET(vop, common, standby, 0);
e334d48b 1134 mutex_unlock(&vop->vop_lock);
2048e328
MY		 1135}
1136
7caecdbe
TF		 1137static bool vop_fs_irq_is_pending(struct vop *vop)
1138{
1139 return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
1140}
1141
1142static void vop_wait_for_irq_handler(struct vop *vop)
1143{
1144 bool pending;
1145 int ret;
1146
1147 /*
1148 * Spin until frame start interrupt status bit goes low, which means
1149 * that interrupt handler was invoked and cleared it. The timeout of
1150 * 10 msecs is really too long, but it is just a safety measure if
1151 * something goes really wrong. The wait will only happen in the very
1152 * unlikely case of a vblank happening exactly at the same time and
1153 * shouldn't exceed microseconds range.
1154 */
1155 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
1156 !pending, 0, 10 * 1000);
1157 if (ret)
1158 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
1159
1160 synchronize_irq(vop->irq);
1161}
1162
63ebb9fa
MY		 1163static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1164 struct drm_crtc_state *old_crtc_state)
2048e328 1165{
47a7eb45 1166 struct drm_atomic_state *old_state = old_crtc_state->state;
e741f2b1 1167 struct drm_plane_state *old_plane_state, *new_plane_state;
2048e328 1168 struct vop *vop = to_vop(crtc);
47a7eb45
TF		 1169 struct drm_plane *plane;
1170 int i;
2048e328 1171
63ebb9fa
MY		 1172 if (WARN_ON(!vop->is_enabled))
1173 return;
2048e328 1174
63ebb9fa 1175 spin_lock(&vop->reg_lock);
2048e328 1176
63ebb9fa 1177 vop_cfg_done(vop);
2048e328 1178
63ebb9fa 1179 spin_unlock(&vop->reg_lock);
7caecdbe
TF		 1180
1181 /*
1182 * There is a (rather unlikely) possiblity that a vblank interrupt
1183 * fired before we set the cfg_done bit. To avoid spuriously
1184 * signalling flip completion we need to wait for it to finish.
1185 */
1186 vop_wait_for_irq_handler(vop);
47a7eb45 1187
41ee4367
TF		 1188 spin_lock_irq(&crtc->dev->event_lock);
1189 if (crtc->state->event) {
1190 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1191 WARN_ON(vop->event);
1192
1193 vop->event = crtc->state->event;
1194 crtc->state->event = NULL;
1195 }
1196 spin_unlock_irq(&crtc->dev->event_lock);
1197
e741f2b1
ML		 1198 for_each_oldnew_plane_in_state(old_state, plane, old_plane_state,
1199 new_plane_state, i) {
47a7eb45
TF		 1200 if (!old_plane_state->fb)
1201 continue;
1202
e741f2b1 1203 if (old_plane_state->fb == new_plane_state->fb)
47a7eb45
TF		 1204 continue;
1205
adedbf03 1206 drm_framebuffer_get(old_plane_state->fb);
2d078c2d 1207 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
47a7eb45
TF		 1208 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
1209 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
47a7eb45 1210 }
2048e328
MY		 1211}
1212
63ebb9fa 1213static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
63ebb9fa
MY		 1214 .mode_fixup = vop_crtc_mode_fixup,
1215 .atomic_flush = vop_crtc_atomic_flush,
0b20a0f8 1216 .atomic_enable = vop_crtc_atomic_enable,
64581714 1217 .atomic_disable = vop_crtc_atomic_disable,
63ebb9fa
MY		 1218};
1219
2048e328
MY		 1220static void vop_crtc_destroy(struct drm_crtc *crtc)
1221{
1222 drm_crtc_cleanup(crtc);
1223}
1224
dc0b408f
JK		 1225static void vop_crtc_reset(struct drm_crtc *crtc)
1226{
1227 if (crtc->state)
1228 __drm_atomic_helper_crtc_destroy_state(crtc->state);
1229 kfree(crtc->state);
1230
1231 crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
1232 if (crtc->state)
1233 crtc->state->crtc = crtc;
1234}
1235
4e257d9e
MY		 1236static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1237{
1238 struct rockchip_crtc_state *rockchip_state;
1239
1240 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1241 if (!rockchip_state)
1242 return NULL;
1243
1244 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1245 return &rockchip_state->base;
1246}
1247
1248static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1249 struct drm_crtc_state *state)
1250{
1251 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1252
ec2dc6a0 1253 __drm_atomic_helper_crtc_destroy_state(&s->base);
4e257d9e
MY		 1254 kfree(s);
1255}
1256
6cca3869 1257#ifdef CONFIG_DRM_ANALOGIX_DP
3190e58d
TV		 1258static struct drm_connector *vop_get_edp_connector(struct vop *vop)
1259{
3190e58d 1260 struct drm_connector *connector;
2cbeb64f 1261 struct drm_connector_list_iter conn_iter;
3190e58d 1262
2cbeb64f
GP		 1263 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter);
1264 drm_for_each_connector_iter(connector, &conn_iter) {
3190e58d 1265 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
2cbeb64f 1266 drm_connector_list_iter_end(&conn_iter);
3190e58d
TV		 1267 return connector;
1268 }
2cbeb64f
GP		 1269 }
1270 drm_connector_list_iter_end(&conn_iter);
3190e58d
TV		 1271
1272 return NULL;
1273}
1274
1275static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
c0811a7d 1276 const char *source_name)
3190e58d
TV		 1277{
1278 struct vop *vop = to_vop(crtc);
1279 struct drm_connector *connector;
1280 int ret;
1281
1282 connector = vop_get_edp_connector(vop);
1283 if (!connector)
1284 return -EINVAL;
1285
3190e58d
TV		 1286 if (source_name && strcmp(source_name, "auto") == 0)
1287 ret = analogix_dp_start_crc(connector);
1288 else if (!source_name)
1289 ret = analogix_dp_stop_crc(connector);
1290 else
1291 ret = -EINVAL;
1292
1293 return ret;
1294}
b8d913c0
MK		 1295
1296static int
1297vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1298 size_t *values_cnt)
1299{
1300 if (source_name && strcmp(source_name, "auto") != 0)
1301 return -EINVAL;
1302
1303 *values_cnt = 3;
1304 return 0;
1305}
1306
6cca3869
SP		 1307#else
1308static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
c0811a7d 1309 const char *source_name)
6cca3869
SP		 1310{
1311 return -ENODEV;
1312}
b8d913c0
MK		 1313
1314static int
1315vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1316 size_t *values_cnt)
1317{
1318 return -ENODEV;
1319}
6cca3869 1320#endif
3190e58d 1321
2048e328 1322static const struct drm_crtc_funcs vop_crtc_funcs = {
63ebb9fa
MY		 1323 .set_config = drm_atomic_helper_set_config,
1324 .page_flip = drm_atomic_helper_page_flip,
2048e328 1325 .destroy = vop_crtc_destroy,
dc0b408f 1326 .reset = vop_crtc_reset,
4e257d9e
MY		 1327 .atomic_duplicate_state = vop_crtc_duplicate_state,
1328 .atomic_destroy_state = vop_crtc_destroy_state,
c3605dfc
SG		 1329 .enable_vblank = vop_crtc_enable_vblank,
1330 .disable_vblank = vop_crtc_disable_vblank,
3190e58d 1331 .set_crc_source = vop_crtc_set_crc_source,
b8d913c0 1332 .verify_crc_source = vop_crtc_verify_crc_source,
2048e328
MY		 1333};
1334
47a7eb45
TF		 1335static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
1336{
1337 struct vop *vop = container_of(work, struct vop, fb_unref_work);
1338 struct drm_framebuffer *fb = val;
1339
1340 drm_crtc_vblank_put(&vop->crtc);
adedbf03 1341 drm_framebuffer_put(fb);
47a7eb45
TF		 1342}
1343
63ebb9fa 1344static void vop_handle_vblank(struct vop *vop)
2048e328 1345{
63ebb9fa
MY		 1346 struct drm_device *drm = vop->drm_dev;
1347 struct drm_crtc *crtc = &vop->crtc;
2048e328 1348
1c85f2fa 1349 spin_lock(&drm->event_lock);
63ebb9fa 1350 if (vop->event) {
63ebb9fa 1351 drm_crtc_send_vblank_event(crtc, vop->event);
5b680403 1352 drm_crtc_vblank_put(crtc);
646ec687 1353 vop->event = NULL;
5b680403 1354 }
1c85f2fa 1355 spin_unlock(&drm->event_lock);
893b6cad 1356
47a7eb45
TF		 1357 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
1358 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
2048e328
MY		 1359}
1360
1361static irqreturn_t vop_isr(int irq, void *data)
1362{
1363 struct vop *vop = data;
b5f7b755 1364 struct drm_crtc *crtc = &vop->crtc;
dbb3d944 1365 uint32_t active_irqs;
1067219b 1366 int ret = IRQ_NONE;
2048e328 1367
6456314f
SH		 1368 /*
1369 * The irq is shared with the iommu. If the runtime-pm state of the
1370 * vop-device is disabled the irq has to be targeted at the iommu.
1371 */
1372 if (!pm_runtime_get_if_in_use(vop->dev))
1373 return IRQ_NONE;
1374
1375 if (vop_core_clks_enable(vop)) {
1376 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n");
1377 goto out;
1378 }
1379
2048e328 1380 /*
dbb3d944 1381 * interrupt register has interrupt status, enable and clear bits, we
2048e328
MY		 1382 * must hold irq_lock to avoid a race with enable/disable_vblank().
1383 */
1c85f2fa 1384 spin_lock(&vop->irq_lock);
dbb3d944
MY		 1385
1386 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
2048e328
MY		 1387 /* Clear all active interrupt sources */
1388 if (active_irqs)
dbb3d944
MY		 1389 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1390
1c85f2fa 1391 spin_unlock(&vop->irq_lock);
2048e328
MY		 1392
1393 /* This is expected for vop iommu irqs, since the irq is shared */
1394 if (!active_irqs)
6456314f 1395 goto out_disable;
2048e328 1396
1067219b
MY		 1397 if (active_irqs & DSP_HOLD_VALID_INTR) {
1398 complete(&vop->dsp_hold_completion);
1399 active_irqs &= ~DSP_HOLD_VALID_INTR;
1400 ret = IRQ_HANDLED;
2048e328
MY		 1401 }
1402
69c34e41
YY		 1403 if (active_irqs & LINE_FLAG_INTR) {
1404 complete(&vop->line_flag_completion);
1405 active_irqs &= ~LINE_FLAG_INTR;
1406 ret = IRQ_HANDLED;
1407 }
1408
1067219b 1409 if (active_irqs & FS_INTR) {
b5f7b755 1410 drm_crtc_handle_vblank(crtc);
63ebb9fa 1411 vop_handle_vblank(vop);
1067219b 1412 active_irqs &= ~FS_INTR;
63ebb9fa 1413 ret = IRQ_HANDLED;
1067219b 1414 }
2048e328 1415
1067219b
MY		 1416 /* Unhandled irqs are spurious. */
1417 if (active_irqs)
ee4d7899
SP		 1418 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",
1419 active_irqs);
1067219b 1420
6456314f
SH		 1421out_disable:
1422 vop_core_clks_disable(vop);
1423out:
1424 pm_runtime_put(vop->dev);
1067219b 1425 return ret;
2048e328
MY		 1426}
1427
677e8bbc
DC		 1428static void vop_plane_add_properties(struct drm_plane *plane,
1429 const struct vop_win_data *win_data)
1430{
1431 unsigned int flags = 0;
1432
1433 flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0;
1434 flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0;
1435 if (flags)
1436 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
1437 DRM_MODE_ROTATE_0 | flags);
1438}
1439
2048e328
MY		 1440static int vop_create_crtc(struct vop *vop)
1441{
1442 const struct vop_data *vop_data = vop->data;
1443 struct device *dev = vop->dev;
1444 struct drm_device *drm_dev = vop->drm_dev;
328b51c0 1445 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
2048e328
MY		 1446 struct drm_crtc *crtc = &vop->crtc;
1447 struct device_node *port;
1448 int ret;
1449 int i;
1450
1451 /*
1452 * Create drm_plane for primary and cursor planes first, since we need
1453 * to pass them to drm_crtc_init_with_planes, which sets the
1454 * "possible_crtcs" to the newly initialized crtc.
1455 */
1456 for (i = 0; i < vop_data->win_size; i++) {
1457 struct vop_win *vop_win = &vop->win[i];
1458 const struct vop_win_data *win_data = vop_win->data;
1459
1460 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1461 win_data->type != DRM_PLANE_TYPE_CURSOR)
1462 continue;
1463
1464 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1465 0, &vop_plane_funcs,
1466 win_data->phy->data_formats,
1467 win_data->phy->nformats,
e6fc3b68 1468 NULL, win_data->type, NULL);
2048e328 1469 if (ret) {
ee4d7899
SP		 1470 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",
1471 ret);
2048e328
MY		 1472 goto err_cleanup_planes;
1473 }
1474
1475 plane = &vop_win->base;
63ebb9fa 1476 drm_plane_helper_add(plane, &plane_helper_funcs);
677e8bbc 1477 vop_plane_add_properties(plane, win_data);
2048e328
MY		 1478 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1479 primary = plane;
1480 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1481 cursor = plane;
1482 }
1483
1484 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
f9882876 1485 &vop_crtc_funcs, NULL);
2048e328 1486 if (ret)
328b51c0 1487 goto err_cleanup_planes;
2048e328
MY		 1488
1489 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1490
1491 /*
1492 * Create drm_planes for overlay windows with possible_crtcs restricted
1493 * to the newly created crtc.
1494 */
1495 for (i = 0; i < vop_data->win_size; i++) {
1496 struct vop_win *vop_win = &vop->win[i];
1497 const struct vop_win_data *win_data = vop_win->data;
a3e77e16 1498 unsigned long possible_crtcs = drm_crtc_mask(crtc);
2048e328
MY		 1499
1500 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1501 continue;
1502
1503 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1504 possible_crtcs,
1505 &vop_plane_funcs,
1506 win_data->phy->data_formats,
1507 win_data->phy->nformats,
e6fc3b68 1508 NULL, win_data->type, NULL);
2048e328 1509 if (ret) {
ee4d7899
SP		 1510 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
1511 ret);
2048e328
MY		 1512 goto err_cleanup_crtc;
1513 }
63ebb9fa 1514 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
677e8bbc 1515 vop_plane_add_properties(&vop_win->base, win_data);
2048e328
MY		 1516 }
1517
1518 port = of_get_child_by_name(dev->of_node, "port");
1519 if (!port) {
4bf99144
RH		 1520 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n",
1521 dev->of_node);
328b51c0 1522 ret = -ENOENT;
2048e328
MY		 1523 goto err_cleanup_crtc;
1524 }
1525
47a7eb45
TF		 1526 drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
1527 vop_fb_unref_worker);
1528
1067219b 1529 init_completion(&vop->dsp_hold_completion);
69c34e41 1530 init_completion(&vop->line_flag_completion);
2048e328 1531 crtc->port = port;
2048e328
MY		 1532
1533 return 0;
1534
1535err_cleanup_crtc:
1536 drm_crtc_cleanup(crtc);
1537err_cleanup_planes:
328b51c0
DA		 1538 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1539 head)
2048e328
MY		 1540 drm_plane_cleanup(plane);
1541 return ret;
1542}
1543
1544static void vop_destroy_crtc(struct vop *vop)
1545{
1546 struct drm_crtc *crtc = &vop->crtc;
328b51c0
DA		 1547 struct drm_device *drm_dev = vop->drm_dev;
1548 struct drm_plane *plane, *tmp;
2048e328 1549
2048e328 1550 of_node_put(crtc->port);
328b51c0
DA		 1551
1552 /*
1553 * We need to cleanup the planes now. Why?
1554 *
1555 * The planes are "&vop->win[i].base". That means the memory is
1556 * all part of the big "struct vop" chunk of memory. That memory
1557 * was devm allocated and associated with this component. We need to
1558 * free it ourselves before vop_unbind() finishes.
1559 */
1560 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1561 head)
1562 vop_plane_destroy(plane);
1563
1564 /*
1565 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1566 * references the CRTC.
1567 */
2048e328 1568 drm_crtc_cleanup(crtc);
47a7eb45 1569 drm_flip_work_cleanup(&vop->fb_unref_work);
2048e328
MY		 1570}
1571
1572static int vop_initial(struct vop *vop)
1573{
1574 const struct vop_data *vop_data = vop->data;
2048e328
MY		 1575 struct reset_control *ahb_rst;
1576 int i, ret;
1577
1578 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1579 if (IS_ERR(vop->hclk)) {
d8dd6804 1580 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n");
2048e328
MY		 1581 return PTR_ERR(vop->hclk);
1582 }
1583 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1584 if (IS_ERR(vop->aclk)) {
d8dd6804 1585 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n");
2048e328
MY		 1586 return PTR_ERR(vop->aclk);
1587 }
1588 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1589 if (IS_ERR(vop->dclk)) {
d8dd6804 1590 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n");
2048e328
MY		 1591 return PTR_ERR(vop->dclk);
1592 }
1593
5e570373
JC		 1594 ret = pm_runtime_get_sync(vop->dev);
1595 if (ret < 0) {
d8dd6804 1596 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
5e570373
JC		 1597 return ret;
1598 }
1599
2048e328
MY		 1600 ret = clk_prepare(vop->dclk);
1601 if (ret < 0) {
d8dd6804 1602 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n");
5e570373 1603 goto err_put_pm_runtime;
2048e328
MY		 1604 }
1605
d7b53fd9
SS		 1606 /* Enable both the hclk and aclk to setup the vop */
1607 ret = clk_prepare_enable(vop->hclk);
2048e328 1608 if (ret < 0) {
d8dd6804 1609 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n");
2048e328
MY		 1610 goto err_unprepare_dclk;
1611 }
1612
d7b53fd9 1613 ret = clk_prepare_enable(vop->aclk);
2048e328 1614 if (ret < 0) {
d8dd6804 1615 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n");
d7b53fd9 1616 goto err_disable_hclk;
2048e328 1617 }
d7b53fd9 1618
2048e328
MY		 1619 /*
1620 * do hclk_reset, reset all vop registers.
1621 */
1622 ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1623 if (IS_ERR(ahb_rst)) {
d8dd6804 1624 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n");
2048e328 1625 ret = PTR_ERR(ahb_rst);
d7b53fd9 1626 goto err_disable_aclk;
2048e328
MY		 1627 }
1628 reset_control_assert(ahb_rst);
1629 usleep_range(10, 20);
1630 reset_control_deassert(ahb_rst);
1631
5f9e93fe
MZ		 1632 VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1);
1633 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0);
1634
76f1416e
MZ		 1635 for (i = 0; i < vop->len; i += sizeof(u32))
1636 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i);
2048e328 1637
9a61c54b
M		 1638 VOP_REG_SET(vop, misc, global_regdone_en, 1);
1639 VOP_REG_SET(vop, common, dsp_blank, 0);
2048e328
MY		 1640
1641 for (i = 0; i < vop_data->win_size; i++) {
1642 const struct vop_win_data *win = &vop_data->win[i];
9dd2aca4 1643 int channel = i * 2 + 1;
2048e328 1644
9dd2aca4 1645 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
e9abc611 1646 vop_win_disable(vop, win);
60b7ae7f 1647 VOP_WIN_SET(vop, win, gate, 1);
2048e328
MY		 1648 }
1649
1650 vop_cfg_done(vop);
1651
1652 /*
1653 * do dclk_reset, let all config take affect.
1654 */
1655 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1656 if (IS_ERR(vop->dclk_rst)) {
d8dd6804 1657 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n");
2048e328 1658 ret = PTR_ERR(vop->dclk_rst);
d7b53fd9 1659 goto err_disable_aclk;
2048e328
MY		 1660 }
1661 reset_control_assert(vop->dclk_rst);
1662 usleep_range(10, 20);
1663 reset_control_deassert(vop->dclk_rst);
1664
1665 clk_disable(vop->hclk);
d7b53fd9 1666 clk_disable(vop->aclk);
2048e328 1667
31e980c5 1668 vop->is_enabled = false;
2048e328 1669
5e570373
JC		 1670 pm_runtime_put_sync(vop->dev);
1671
2048e328
MY		 1672 return 0;
1673
d7b53fd9
SS		 1674err_disable_aclk:
1675 clk_disable_unprepare(vop->aclk);
2048e328 1676err_disable_hclk:
d7b53fd9 1677 clk_disable_unprepare(vop->hclk);
2048e328
MY		 1678err_unprepare_dclk:
1679 clk_unprepare(vop->dclk);
5e570373
JC		 1680err_put_pm_runtime:
1681 pm_runtime_put_sync(vop->dev);
2048e328
MY		 1682 return ret;
1683}
1684
1685/*
1686 * Initialize the vop->win array elements.
1687 */
1688static void vop_win_init(struct vop *vop)
1689{
1690 const struct vop_data *vop_data = vop->data;
1691 unsigned int i;
1692
1693 for (i = 0; i < vop_data->win_size; i++) {
1694 struct vop_win *vop_win = &vop->win[i];
1695 const struct vop_win_data *win_data = &vop_data->win[i];
1696
1697 vop_win->data = win_data;
1698 vop_win->vop = vop;
ce6912b4
HS		 1699
1700 if (vop_data->win_yuv2yuv)
1701 vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i];
2048e328
MY		 1702 }
1703}
1704
69c34e41 1705/**
459b086d 1706 * rockchip_drm_wait_vact_end
69c34e41 1707 * @crtc: CRTC to enable line flag
69c34e41
YY		 1708 * @mstimeout: millisecond for timeout
1709 *
459b086d 1710 * Wait for vact_end line flag irq or timeout.
69c34e41
YY		 1711 *
1712 * Returns:
1713 * Zero on success, negative errno on failure.
1714 */
459b086d 1715int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
69c34e41
YY		 1716{
1717 struct vop *vop = to_vop(crtc);
1718 unsigned long jiffies_left;
e334d48b 1719 int ret = 0;
69c34e41
YY		 1720
1721 if (!crtc || !vop->is_enabled)
1722 return -ENODEV;
1723
e334d48b 1724 mutex_lock(&vop->vop_lock);
1725 if (mstimeout <= 0) {
1726 ret = -EINVAL;
1727 goto out;
1728 }
69c34e41 1729
e334d48b 1730 if (vop_line_flag_irq_is_enabled(vop)) {
1731 ret = -EBUSY;
1732 goto out;
1733 }
69c34e41
YY		 1734
1735 reinit_completion(&vop->line_flag_completion);
459b086d 1736 vop_line_flag_irq_enable(vop);
69c34e41
YY		 1737
1738 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
1739 msecs_to_jiffies(mstimeout));
1740 vop_line_flag_irq_disable(vop);
1741
1742 if (jiffies_left == 0) {
d8dd6804 1743 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n");
e334d48b 1744 ret = -ETIMEDOUT;
1745 goto out;
69c34e41
YY		 1746 }
1747
e334d48b 1748out:
1749 mutex_unlock(&vop->vop_lock);
1750 return ret;
69c34e41 1751}
459b086d 1752EXPORT_SYMBOL(rockchip_drm_wait_vact_end);
69c34e41 1753
2048e328
MY		 1754static int vop_bind(struct device *dev, struct device *master, void *data)
1755{
1756 struct platform_device *pdev = to_platform_device(dev);
2048e328
MY		 1757 const struct vop_data *vop_data;
1758 struct drm_device *drm_dev = data;
1759 struct vop *vop;
1760 struct resource *res;
3ea68922 1761 int ret, irq;
2048e328 1762
a67719d1 1763 vop_data = of_device_get_match_data(dev);
2048e328
MY		 1764 if (!vop_data)
1765 return -ENODEV;
1766
1767 /* Allocate vop struct and its vop_win array */
29adeb4f
GS		 1768 vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size),
1769 GFP_KERNEL);
2048e328
MY		 1770 if (!vop)
1771 return -ENOMEM;
1772
1773 vop->dev = dev;
1774 vop->data = vop_data;
1775 vop->drm_dev = drm_dev;
1776 dev_set_drvdata(dev, vop);
1777
1778 vop_win_init(vop);
1779
1780 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1781 vop->len = resource_size(res);
1782 vop->regs = devm_ioremap_resource(dev, res);
1783 if (IS_ERR(vop->regs))
1784 return PTR_ERR(vop->regs);
1785
1786 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1787 if (!vop->regsbak)
1788 return -ENOMEM;
1789
3ea68922
HS		 1790 irq = platform_get_irq(pdev, 0);
1791 if (irq < 0) {
d8dd6804 1792 DRM_DEV_ERROR(dev, "cannot find irq for vop\n");
3ea68922 1793 return irq;
2048e328 1794 }
3ea68922 1795 vop->irq = (unsigned int)irq;
2048e328
MY		 1796
1797 spin_lock_init(&vop->reg_lock);
1798 spin_lock_init(&vop->irq_lock);
e334d48b 1799 mutex_init(&vop->vop_lock);
2048e328 1800
2048e328
MY		 1801 ret = vop_create_crtc(vop);
1802 if (ret)
5f9e93fe 1803 return ret;
2048e328
MY		 1804
1805 pm_runtime_enable(&pdev->dev);
5182c1a5 1806
5e570373
JC		 1807 ret = vop_initial(vop);
1808 if (ret < 0) {
d8dd6804
HM		 1809 DRM_DEV_ERROR(&pdev->dev,
1810 "cannot initial vop dev - err %d\n", ret);
5e570373
JC		 1811 goto err_disable_pm_runtime;
1812 }
1813
5f9e93fe
MZ		 1814 ret = devm_request_irq(dev, vop->irq, vop_isr,
1815 IRQF_SHARED, dev_name(dev), vop);
1816 if (ret)
1817 goto err_disable_pm_runtime;
1818
1f0f0151
SH		 1819 if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) {
1820 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev);
1821 if (IS_ERR(vop->rgb)) {
1822 ret = PTR_ERR(vop->rgb);
1823 goto err_disable_pm_runtime;
1824 }
1825 }
1826
2048e328 1827 return 0;
8c763c9b 1828
5e570373
JC		 1829err_disable_pm_runtime:
1830 pm_runtime_disable(&pdev->dev);
1831 vop_destroy_crtc(vop);
8c763c9b 1832 return ret;
2048e328
MY		 1833}
1834
1835static void vop_unbind(struct device *dev, struct device *master, void *data)
1836{
1837 struct vop *vop = dev_get_drvdata(dev);
1838
1f0f0151
SH		 1839 if (vop->rgb)
1840 rockchip_rgb_fini(vop->rgb);
1841
2048e328
MY		 1842 pm_runtime_disable(dev);
1843 vop_destroy_crtc(vop);
ec6e7767
JC		 1844
1845 clk_unprepare(vop->aclk);
1846 clk_unprepare(vop->hclk);
1847 clk_unprepare(vop->dclk);
2048e328
MY		 1848}
1849
a67719d1 1850const struct component_ops vop_component_ops = {
2048e328
MY		 1851 .bind = vop_bind,
1852 .unbind = vop_unbind,
1853};
54255e81 1854EXPORT_SYMBOL_GPL(vop_component_ops);
Linux 6.x block layer and io_uring tree(s)