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Merge tag 'tty-5.3-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
[linux-2.6-block.git] / drivers / gpu / drm / rockchip / rockchip_drm_vop.c
CommitLineData
9c92ab61 1// SPDX-License-Identifier: GPL-2.0-only
2048e328
MY		 2/*
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author:Mark Yao <mark.yao@rock-chips.com>
2048e328
MY		 5 */
6
7#include <drm/drm.h>
8#include <drm/drmP.h>
63ebb9fa 9#include <drm/drm_atomic.h>
15609559 10#include <drm/drm_atomic_uapi.h>
2048e328 11#include <drm/drm_crtc.h>
47a7eb45 12#include <drm/drm_flip_work.h>
63d5e06a 13#include <drm/drm_gem_framebuffer_helper.h>
2048e328 14#include <drm/drm_plane_helper.h>
fcd70cd3 15#include <drm/drm_probe_helper.h>
6cca3869 16#ifdef CONFIG_DRM_ANALOGIX_DP
3190e58d 17#include <drm/bridge/analogix_dp.h>
6cca3869 18#endif
2048e328
MY		 19
20#include <linux/kernel.h>
00fe6148 21#include <linux/module.h>
2048e328
MY		 22#include <linux/platform_device.h>
23#include <linux/clk.h>
7caecdbe 24#include <linux/iopoll.h>
2048e328
MY		 25#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/pm_runtime.h>
28#include <linux/component.h>
29adeb4f 29#include <linux/overflow.h>
2048e328
MY		 30
31#include <linux/reset.h>
32#include <linux/delay.h>
33
34#include "rockchip_drm_drv.h"
35#include "rockchip_drm_gem.h"
36#include "rockchip_drm_fb.h"
5182c1a5 37#include "rockchip_drm_psr.h"
2048e328 38#include "rockchip_drm_vop.h"
1f0f0151 39#include "rockchip_rgb.h"
2048e328 40
2996fb75 41#define VOP_WIN_SET(vop, win, name, v) \
9a61c54b 42 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)
2996fb75 43#define VOP_SCL_SET(vop, win, name, v) \
9a61c54b 44 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name)
2996fb75 45#define VOP_SCL_SET_EXT(vop, win, name, v) \
9a61c54b
M		 46 vop_reg_set(vop, &win->phy->scl->ext->name, \
47 win->base, ~0, v, #name)
ac6560df 48
2996fb75 49#define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \
1c21aa8f
DC		 50 do { \
51 if (win_yuv2yuv && win_yuv2yuv->name.mask) \
52 vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \
53 } while (0)
54
2996fb75 55#define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \
1c21aa8f
DC		 56 do { \
57 if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \
58 vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \
59 } while (0)
60
ac6560df 61#define VOP_INTR_SET_MASK(vop, name, mask, v) \
9a61c54b
M		 62 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name)
63
64#define VOP_REG_SET(vop, group, name, v) \
65 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
ac6560df 66
dbb3d944
MY		 67#define VOP_INTR_SET_TYPE(vop, name, type, v) \
68 do { \
c7647f86 69 int i, reg = 0, mask = 0; \
dbb3d944 70 for (i = 0; i < vop->data->intr->nintrs; i++) { \
c7647f86 71 if (vop->data->intr->intrs[i] & type) { \
dbb3d944 72 reg |= (v) << i; \
c7647f86
JK		 73 mask |= 1 << i; \
74 } \
dbb3d944 75 } \
ac6560df 76 VOP_INTR_SET_MASK(vop, name, mask, reg); \
dbb3d944
MY		 77 } while (0)
78#define VOP_INTR_GET_TYPE(vop, name, type) \
79 vop_get_intr_type(vop, &vop->data->intr->name, type)
80
2996fb75
EG		 81#define VOP_WIN_GET(vop, win, name) \
82 vop_read_reg(vop, win->offset, win->phy->name)
2048e328 83
677e8bbc
DC		 84#define VOP_WIN_HAS_REG(win, name) \
85 (!!(win->phy->name.mask))
86
2048e328
MY		 87#define VOP_WIN_GET_YRGBADDR(vop, win) \
88 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
89
58badaa7
KK		 90#define VOP_WIN_TO_INDEX(vop_win) \
91 ((vop_win) - (vop_win)->vop->win)
92
2048e328
MY		 93#define to_vop(x) container_of(x, struct vop, crtc)
94#define to_vop_win(x) container_of(x, struct vop_win, base)
95
1c21aa8f
DC		 96/*
97 * The coefficients of the following matrix are all fixed points.
98 * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets.
99 * They are all represented in two's complement.
100 */
101static const uint32_t bt601_yuv2rgb[] = {
102 0x4A8, 0x0, 0x662,
103 0x4A8, 0x1E6F, 0x1CBF,
104 0x4A8, 0x812, 0x0,
105 0x321168, 0x0877CF, 0x2EB127
106};
107
47a7eb45
TF		 108enum vop_pending {
109 VOP_PENDING_FB_UNREF,
110};
111
2048e328
MY		 112struct vop_win {
113 struct drm_plane base;
114 const struct vop_win_data *data;
1c21aa8f 115 const struct vop_win_yuv2yuv_data *yuv2yuv_data;
2048e328 116 struct vop *vop;
2048e328
MY		 117};
118
1f0f0151 119struct rockchip_rgb;
2048e328
MY		 120struct vop {
121 struct drm_crtc crtc;
122 struct device *dev;
123 struct drm_device *drm_dev;
31e980c5 124 bool is_enabled;
2048e328 125
1067219b 126 struct completion dsp_hold_completion;
4f9d39a7
DV		 127
128 /* protected by dev->event_lock */
63ebb9fa 129 struct drm_pending_vblank_event *event;
2048e328 130
47a7eb45
TF		 131 struct drm_flip_work fb_unref_work;
132 unsigned long pending;
133
69c34e41
YY		 134 struct completion line_flag_completion;
135
2048e328
MY		 136 const struct vop_data *data;
137
138 uint32_t *regsbak;
139 void __iomem *regs;
140
141 /* physical map length of vop register */
142 uint32_t len;
143
144 /* one time only one process allowed to config the register */
145 spinlock_t reg_lock;
146 /* lock vop irq reg */
147 spinlock_t irq_lock;
e334d48b 148 /* protects crtc enable/disable */
149 struct mutex vop_lock;
2048e328
MY		 150
151 unsigned int irq;
152
153 /* vop AHP clk */
154 struct clk *hclk;
155 /* vop dclk */
156 struct clk *dclk;
157 /* vop share memory frequency */
158 struct clk *aclk;
159
160 /* vop dclk reset */
161 struct reset_control *dclk_rst;
162
1f0f0151
SH		 163 /* optional internal rgb encoder */
164 struct rockchip_rgb *rgb;
165
2048e328
MY		 166 struct vop_win win[];
167};
168
2048e328
MY		 169static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
170{
171 writel(v, vop->regs + offset);
172 vop->regsbak[offset >> 2] = v;
173}
174
175static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
176{
177 return readl(vop->regs + offset);
178}
179
180static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
181 const struct vop_reg *reg)
182{
183 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
184}
185
9a61c54b
M		 186static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
187 uint32_t _offset, uint32_t _mask, uint32_t v,
188 const char *reg_name)
2048e328 189{
9a61c54b
M		 190 int offset, mask, shift;
191
192 if (!reg || !reg->mask) {
d8dd6804 193 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name);
d49463ec 194 return;
9a61c54b
M		 195 }
196
197 offset = reg->offset + _offset;
198 mask = reg->mask & _mask;
199 shift = reg->shift;
2048e328 200
9a61c54b 201 if (reg->write_mask) {
d49463ec
MY		 202 v = ((v << shift) & 0xffff) | (mask << (shift + 16));
203 } else {
2048e328
MY		 204 uint32_t cached_val = vop->regsbak[offset >> 2];
205
d49463ec
MY		 206 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
207 vop->regsbak[offset >> 2] = v;
2048e328 208 }
d49463ec 209
9a61c54b 210 if (reg->relaxed)
d49463ec
MY		 211 writel_relaxed(v, vop->regs + offset);
212 else
213 writel(v, vop->regs + offset);
2048e328
MY		 214}
215
dbb3d944
MY		 216static inline uint32_t vop_get_intr_type(struct vop *vop,
217 const struct vop_reg *reg, int type)
218{
219 uint32_t i, ret = 0;
220 uint32_t regs = vop_read_reg(vop, 0, reg);
221
222 for (i = 0; i < vop->data->intr->nintrs; i++) {
223 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
224 ret |= vop->data->intr->intrs[i];
225 }
226
227 return ret;
228}
229
0cf33fe3
MY		 230static inline void vop_cfg_done(struct vop *vop)
231{
9a61c54b 232 VOP_REG_SET(vop, common, cfg_done, 1);
0cf33fe3
MY		 233}
234
85a359f2
TF		 235static bool has_rb_swapped(uint32_t format)
236{
237 switch (format) {
238 case DRM_FORMAT_XBGR8888:
239 case DRM_FORMAT_ABGR8888:
240 case DRM_FORMAT_BGR888:
241 case DRM_FORMAT_BGR565:
242 return true;
243 default:
244 return false;
245 }
246}
247
2048e328
MY		 248static enum vop_data_format vop_convert_format(uint32_t format)
249{
250 switch (format) {
251 case DRM_FORMAT_XRGB8888:
252 case DRM_FORMAT_ARGB8888:
85a359f2
TF		 253 case DRM_FORMAT_XBGR8888:
254 case DRM_FORMAT_ABGR8888:
2048e328
MY		 255 return VOP_FMT_ARGB8888;
256 case DRM_FORMAT_RGB888:
85a359f2 257 case DRM_FORMAT_BGR888:
2048e328
MY		 258 return VOP_FMT_RGB888;
259 case DRM_FORMAT_RGB565:
85a359f2 260 case DRM_FORMAT_BGR565:
2048e328
MY		 261 return VOP_FMT_RGB565;
262 case DRM_FORMAT_NV12:
263 return VOP_FMT_YUV420SP;
264 case DRM_FORMAT_NV16:
265 return VOP_FMT_YUV422SP;
266 case DRM_FORMAT_NV24:
267 return VOP_FMT_YUV444SP;
268 default:
ee4d7899 269 DRM_ERROR("unsupported format[%08x]\n", format);
2048e328
MY		 270 return -EINVAL;
271 }
272}
273
4c156c21
MY		 274static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
275 uint32_t dst, bool is_horizontal,
276 int vsu_mode, int *vskiplines)
277{
278 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
279
ce91d373
JC		 280 if (vskiplines)
281 *vskiplines = 0;
282
4c156c21
MY		 283 if (is_horizontal) {
284 if (mode == SCALE_UP)
285 val = GET_SCL_FT_BIC(src, dst);
286 else if (mode == SCALE_DOWN)
287 val = GET_SCL_FT_BILI_DN(src, dst);
288 } else {
289 if (mode == SCALE_UP) {
290 if (vsu_mode == SCALE_UP_BIL)
291 val = GET_SCL_FT_BILI_UP(src, dst);
292 else
293 val = GET_SCL_FT_BIC(src, dst);
294 } else if (mode == SCALE_DOWN) {
295 if (vskiplines) {
296 *vskiplines = scl_get_vskiplines(src, dst);
297 val = scl_get_bili_dn_vskip(src, dst,
298 *vskiplines);
299 } else {
300 val = GET_SCL_FT_BILI_DN(src, dst);
301 }
302 }
303 }
304
305 return val;
306}
307
308static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
309 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
45babef0 310 uint32_t dst_h, const struct drm_format_info *info)
4c156c21
MY		 311{
312 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
313 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
314 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
d8bd23d9 315 bool is_yuv = false;
f3e9632c
MR		 316 uint16_t cbcr_src_w = src_w / info->hsub;
317 uint16_t cbcr_src_h = src_h / info->vsub;
4c156c21
MY		 318 uint16_t vsu_mode;
319 uint16_t lb_mode;
320 uint32_t val;
ce91d373 321 int vskiplines;
4c156c21 322
d8bd23d9
AKH		 323 if (info->is_yuv)
324 is_yuv = true;
325
4c156c21 326 if (dst_w > 3840) {
ee4d7899 327 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
4c156c21
MY		 328 return;
329 }
330
1194fffb
MY		 331 if (!win->phy->scl->ext) {
332 VOP_SCL_SET(vop, win, scale_yrgb_x,
333 scl_cal_scale2(src_w, dst_w));
334 VOP_SCL_SET(vop, win, scale_yrgb_y,
335 scl_cal_scale2(src_h, dst_h));
336 if (is_yuv) {
337 VOP_SCL_SET(vop, win, scale_cbcr_x,
ee8662fc 338 scl_cal_scale2(cbcr_src_w, dst_w));
1194fffb 339 VOP_SCL_SET(vop, win, scale_cbcr_y,
ee8662fc 340 scl_cal_scale2(cbcr_src_h, dst_h));
1194fffb
MY		 341 }
342 return;
343 }
344
4c156c21
MY		 345 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
346 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
347
348 if (is_yuv) {
349 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
350 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
351 if (cbcr_hor_scl_mode == SCALE_DOWN)
352 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
353 else
354 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
355 } else {
356 if (yrgb_hor_scl_mode == SCALE_DOWN)
357 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
358 else
359 lb_mode = scl_vop_cal_lb_mode(src_w, false);
360 }
361
1194fffb 362 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
4c156c21
MY		 363 if (lb_mode == LB_RGB_3840X2) {
364 if (yrgb_ver_scl_mode != SCALE_NONE) {
ee4d7899 365 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");
4c156c21
MY		 366 return;
367 }
368 if (cbcr_ver_scl_mode != SCALE_NONE) {
ee4d7899 369 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");
4c156c21
MY		 370 return;
371 }
372 vsu_mode = SCALE_UP_BIL;
373 } else if (lb_mode == LB_RGB_2560X4) {
374 vsu_mode = SCALE_UP_BIL;
375 } else {
376 vsu_mode = SCALE_UP_BIC;
377 }
378
379 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
380 true, 0, NULL);
381 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
382 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
383 false, vsu_mode, &vskiplines);
384 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
385
1194fffb
MY		 386 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
387 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
4c156c21 388
1194fffb
MY		 389 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
390 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
391 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
392 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
393 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
4c156c21
MY		 394 if (is_yuv) {
395 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
396 dst_w, true, 0, NULL);
397 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
398 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
399 dst_h, false, vsu_mode, &vskiplines);
400 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
401
1194fffb
MY		 402 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
403 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
404 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
405 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
406 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
407 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
408 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
4c156c21
MY		 409 }
410}
411
1067219b
MY		 412static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
413{
414 unsigned long flags;
415
416 if (WARN_ON(!vop->is_enabled))
417 return;
418
419 spin_lock_irqsave(&vop->irq_lock, flags);
420
fa374107 421 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
dbb3d944 422 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
1067219b
MY		 423
424 spin_unlock_irqrestore(&vop->irq_lock, flags);
425}
426
427static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
428{
429 unsigned long flags;
430
431 if (WARN_ON(!vop->is_enabled))
432 return;
433
434 spin_lock_irqsave(&vop->irq_lock, flags);
435
dbb3d944 436 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
1067219b
MY		 437
438 spin_unlock_irqrestore(&vop->irq_lock, flags);
439}
440
69c34e41
YY		 441/*
442 * (1) each frame starts at the start of the Vsync pulse which is signaled by
443 * the "FRAME_SYNC" interrupt.
444 * (2) the active data region of each frame ends at dsp_vact_end
445 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
446 * to get "LINE_FLAG" interrupt at the end of the active on screen data.
447 *
448 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
449 * Interrupts
450 * LINE_FLAG -------------------------------+
451 * FRAME_SYNC ----+ |
452 * | |
453 * v v
454 * | Vsync | Vbp | Vactive | Vfp |
455 * ^ ^ ^ ^
456 * | | | |
457 * | | | |
458 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END
459 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END
460 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END
461 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END
462 */
463static bool vop_line_flag_irq_is_enabled(struct vop *vop)
464{
465 uint32_t line_flag_irq;
466 unsigned long flags;
467
468 spin_lock_irqsave(&vop->irq_lock, flags);
469
470 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
471
472 spin_unlock_irqrestore(&vop->irq_lock, flags);
473
474 return !!line_flag_irq;
475}
476
459b086d 477static void vop_line_flag_irq_enable(struct vop *vop)
69c34e41
YY		 478{
479 unsigned long flags;
480
481 if (WARN_ON(!vop->is_enabled))
482 return;
483
484 spin_lock_irqsave(&vop->irq_lock, flags);
485
fa374107 486 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
69c34e41
YY		 487 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
488
489 spin_unlock_irqrestore(&vop->irq_lock, flags);
490}
491
492static void vop_line_flag_irq_disable(struct vop *vop)
493{
494 unsigned long flags;
495
496 if (WARN_ON(!vop->is_enabled))
497 return;
498
499 spin_lock_irqsave(&vop->irq_lock, flags);
500
501 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
502
503 spin_unlock_irqrestore(&vop->irq_lock, flags);
504}
505
e2810a71
HS		 506static int vop_core_clks_enable(struct vop *vop)
507{
508 int ret;
509
510 ret = clk_enable(vop->hclk);
511 if (ret < 0)
512 return ret;
513
514 ret = clk_enable(vop->aclk);
515 if (ret < 0)
516 goto err_disable_hclk;
517
518 return 0;
519
520err_disable_hclk:
521 clk_disable(vop->hclk);
522 return ret;
523}
524
525static void vop_core_clks_disable(struct vop *vop)
526{
527 clk_disable(vop->aclk);
528 clk_disable(vop->hclk);
529}
530
e9abc611
JK		 531static void vop_win_disable(struct vop *vop, const struct vop_win_data *win)
532{
533 if (win->phy->scl && win->phy->scl->ext) {
534 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
535 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
536 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
537 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
538 }
539
540 VOP_WIN_SET(vop, win, enable, 0);
541}
542
39a9ad8f 543static int vop_enable(struct drm_crtc *crtc)
2048e328
MY		 544{
545 struct vop *vop = to_vop(crtc);
64d77564 546 int ret, i;
2048e328 547
5d82d1a7
MY		 548 ret = pm_runtime_get_sync(vop->dev);
549 if (ret < 0) {
d8dd6804 550 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
5e570373 551 return ret;
5d82d1a7
MY		 552 }
553
e2810a71 554 ret = vop_core_clks_enable(vop);
39a9ad8f
SP		 555 if (WARN_ON(ret < 0))
556 goto err_put_pm_runtime;
2048e328
MY		 557
558 ret = clk_enable(vop->dclk);
39a9ad8f 559 if (WARN_ON(ret < 0))
e2810a71 560 goto err_disable_core;
2048e328
MY		 561
562 /*
563 * Slave iommu shares power, irq and clock with vop. It was associated
564 * automatically with this master device via common driver code.
565 * Now that we have enabled the clock we attach it to the shared drm
566 * mapping.
567 */
568 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
569 if (ret) {
d8dd6804
HM		 570 DRM_DEV_ERROR(vop->dev,
571 "failed to attach dma mapping, %d\n", ret);
e2810a71 572 goto err_disable_dclk;
2048e328
MY		 573 }
574
76f1416e
MZ		 575 spin_lock(&vop->reg_lock);
576 for (i = 0; i < vop->len; i += 4)
577 writel_relaxed(vop->regsbak[i / 4], vop->regs + i);
578
64d77564
M		 579 /*
580 * We need to make sure that all windows are disabled before we
581 * enable the crtc. Otherwise we might try to scan from a destroyed
582 * buffer later.
583 */
584 for (i = 0; i < vop->data->win_size; i++) {
585 struct vop_win *vop_win = &vop->win[i];
586 const struct vop_win_data *win = vop_win->data;
587
e9abc611 588 vop_win_disable(vop, win);
64d77564 589 }
76f1416e 590 spin_unlock(&vop->reg_lock);
64d77564 591
17a794d7
CZ		 592 vop_cfg_done(vop);
593
52ab7891
MY		 594 /*
595 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
596 */
597 vop->is_enabled = true;
598
2048e328
MY		 599 spin_lock(&vop->reg_lock);
600
9a61c54b 601 VOP_REG_SET(vop, common, standby, 1);
2048e328
MY		 602
603 spin_unlock(&vop->reg_lock);
604
b5f7b755 605 drm_crtc_vblank_on(crtc);
2048e328 606
39a9ad8f 607 return 0;
2048e328 608
2048e328
MY		 609err_disable_dclk:
610 clk_disable(vop->dclk);
e2810a71
HS		 611err_disable_core:
612 vop_core_clks_disable(vop);
39a9ad8f
SP		 613err_put_pm_runtime:
614 pm_runtime_put_sync(vop->dev);
615 return ret;
2048e328
MY		 616}
617
64581714
LP		 618static void vop_crtc_atomic_disable(struct drm_crtc *crtc,
619 struct drm_crtc_state *old_state)
2048e328
MY		 620{
621 struct vop *vop = to_vop(crtc);
622
893b6cad
DV		 623 WARN_ON(vop->event);
624
e334d48b 625 mutex_lock(&vop->vop_lock);
b5f7b755 626 drm_crtc_vblank_off(crtc);
2048e328 627
2048e328 628 /*
1067219b
MY		 629 * Vop standby will take effect at end of current frame,
630 * if dsp hold valid irq happen, it means standby complete.
631 *
632 * we must wait standby complete when we want to disable aclk,
633 * if not, memory bus maybe dead.
2048e328 634 */
1067219b
MY		 635 reinit_completion(&vop->dsp_hold_completion);
636 vop_dsp_hold_valid_irq_enable(vop);
637
2048e328
MY		 638 spin_lock(&vop->reg_lock);
639
9a61c54b 640 VOP_REG_SET(vop, common, standby, 1);
2048e328
MY		 641
642 spin_unlock(&vop->reg_lock);
52ab7891 643
1067219b
MY		 644 wait_for_completion(&vop->dsp_hold_completion);
645
646 vop_dsp_hold_valid_irq_disable(vop);
647
52ab7891 648 vop->is_enabled = false;
1067219b 649
2048e328 650 /*
1067219b 651 * vop standby complete, so iommu detach is safe.
2048e328 652 */
2048e328
MY		 653 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
654
1067219b 655 clk_disable(vop->dclk);
e2810a71 656 vop_core_clks_disable(vop);
5d82d1a7 657 pm_runtime_put(vop->dev);
e334d48b 658 mutex_unlock(&vop->vop_lock);
893b6cad
DV		 659
660 if (crtc->state->event && !crtc->state->active) {
661 spin_lock_irq(&crtc->dev->event_lock);
662 drm_crtc_send_vblank_event(crtc, crtc->state->event);
663 spin_unlock_irq(&crtc->dev->event_lock);
664
665 crtc->state->event = NULL;
666 }
2048e328
MY		 667}
668
63ebb9fa 669static void vop_plane_destroy(struct drm_plane *plane)
2048e328 670{
63ebb9fa 671 drm_plane_cleanup(plane);
2048e328
MY		 672}
673
63ebb9fa
MY		 674static int vop_plane_atomic_check(struct drm_plane *plane,
675 struct drm_plane_state *state)
2048e328 676{
63ebb9fa 677 struct drm_crtc *crtc = state->crtc;
92915da6 678 struct drm_crtc_state *crtc_state;
63ebb9fa 679 struct drm_framebuffer *fb = state->fb;
2048e328
MY		 680 struct vop_win *vop_win = to_vop_win(plane);
681 const struct vop_win_data *win = vop_win->data;
2048e328 682 int ret;
4c156c21
MY		 683 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
684 DRM_PLANE_HELPER_NO_SCALING;
685 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
686 DRM_PLANE_HELPER_NO_SCALING;
2048e328 687
63ebb9fa 688 if (!crtc || !fb)
d47a7246 689 return 0;
92915da6
JK		 690
691 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
692 if (WARN_ON(!crtc_state))
693 return -EINVAL;
694
81af63a4 695 ret = drm_atomic_helper_check_plane_state(state, crtc_state,
a01cb8ba
VS		 696 min_scale, max_scale,
697 true, true);
2048e328
MY		 698 if (ret)
699 return ret;
700
f9b96be0 701 if (!state->visible)
d47a7246 702 return 0;
2048e328 703
438b74a5 704 ret = vop_convert_format(fb->format->format);
d47a7246
TF		 705 if (ret < 0)
706 return ret;
84c7f8ca 707
63ebb9fa
MY		 708 /*
709 * Src.x1 can be odd when do clip, but yuv plane start point
710 * need align with 2 pixel.
711 */
d8bd23d9 712 if (fb->format->is_yuv && ((state->src.x1 >> 16) % 2)) {
d415fb87 713 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n");
2048e328 714 return -EINVAL;
d415fb87 715 }
2048e328 716
677e8bbc
DC		 717 if (fb->format->is_yuv && state->rotation & DRM_MODE_REFLECT_Y) {
718 DRM_ERROR("Invalid Source: Yuv format does not support this rotation\n");
719 return -EINVAL;
720 }
721
63ebb9fa
MY		 722 return 0;
723}
2048e328 724
63ebb9fa
MY		 725static void vop_plane_atomic_disable(struct drm_plane *plane,
726 struct drm_plane_state *old_state)
727{
63ebb9fa
MY		 728 struct vop_win *vop_win = to_vop_win(plane);
729 const struct vop_win_data *win = vop_win->data;
730 struct vop *vop = to_vop(old_state->crtc);
2048e328 731
63ebb9fa
MY		 732 if (!old_state->crtc)
733 return;
2048e328 734
63ebb9fa 735 spin_lock(&vop->reg_lock);
2048e328 736
e9abc611 737 vop_win_disable(vop, win);
84c7f8ca 738
63ebb9fa 739 spin_unlock(&vop->reg_lock);
63ebb9fa 740}
84c7f8ca 741
63ebb9fa
MY		 742static void vop_plane_atomic_update(struct drm_plane *plane,
743 struct drm_plane_state *old_state)
744{
745 struct drm_plane_state *state = plane->state;
746 struct drm_crtc *crtc = state->crtc;
747 struct vop_win *vop_win = to_vop_win(plane);
63ebb9fa 748 const struct vop_win_data *win = vop_win->data;
1c21aa8f 749 const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data;
63ebb9fa
MY		 750 struct vop *vop = to_vop(state->crtc);
751 struct drm_framebuffer *fb = state->fb;
752 unsigned int actual_w, actual_h;
753 unsigned int dsp_stx, dsp_sty;
754 uint32_t act_info, dsp_info, dsp_st;
ac92028e
VS		 755 struct drm_rect *src = &state->src;
756 struct drm_rect *dest = &state->dst;
63ebb9fa
MY		 757 struct drm_gem_object *obj, *uv_obj;
758 struct rockchip_gem_object *rk_obj, *rk_uv_obj;
759 unsigned long offset;
760 dma_addr_t dma_addr;
761 uint32_t val;
762 bool rb_swap;
58badaa7 763 int win_index = VOP_WIN_TO_INDEX(vop_win);
d47a7246 764 int format;
1c21aa8f
DC		 765 int is_yuv = fb->format->is_yuv;
766 int i;
84c7f8ca 767
2048e328 768 /*
63ebb9fa 769 * can't update plane when vop is disabled.
2048e328 770 */
4f9d39a7 771 if (WARN_ON(!crtc))
63ebb9fa 772 return;
2048e328 773
63ebb9fa
MY		 774 if (WARN_ON(!vop->is_enabled))
775 return;
2048e328 776
d47a7246 777 if (!state->visible) {
63ebb9fa
MY		 778 vop_plane_atomic_disable(plane, old_state);
779 return;
2048e328 780 }
63ebb9fa 781
957428f9 782 obj = fb->obj[0];
63ebb9fa
MY		 783 rk_obj = to_rockchip_obj(obj);
784
785 actual_w = drm_rect_width(src) >> 16;
786 actual_h = drm_rect_height(src) >> 16;
787 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
788
789 dsp_info = (drm_rect_height(dest) - 1) << 16;
790 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
791
792 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
793 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
794 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
795
353c8598 796 offset = (src->x1 >> 16) * fb->format->cpp[0];
63ebb9fa 797 offset += (src->y1 >> 16) * fb->pitches[0];
d47a7246
TF		 798 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
799
677e8bbc
DC		 800 /*
801 * For y-mirroring we need to move address
802 * to the beginning of the last line.
803 */
804 if (state->rotation & DRM_MODE_REFLECT_Y)
805 dma_addr += (actual_h - 1) * fb->pitches[0];
806
438b74a5 807 format = vop_convert_format(fb->format->format);
2048e328
MY		 808
809 spin_lock(&vop->reg_lock);
810
d47a7246 811 VOP_WIN_SET(vop, win, format, format);
da709a7b 812 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
d47a7246 813 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
1c21aa8f 814 VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
677e8bbc
DC		 815 VOP_WIN_SET(vop, win, y_mir_en,
816 (state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0);
817 VOP_WIN_SET(vop, win, x_mir_en,
818 (state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0);
1c21aa8f
DC		 819
820 if (is_yuv) {
f3e9632c
MR		 821 int hsub = fb->format->hsub;
822 int vsub = fb->format->vsub;
353c8598 823 int bpp = fb->format->cpp[1];
63ebb9fa 824
957428f9 825 uv_obj = fb->obj[1];
63ebb9fa
MY		 826 rk_uv_obj = to_rockchip_obj(uv_obj);
827
828 offset = (src->x1 >> 16) * bpp / hsub;
829 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
830
831 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
da709a7b 832 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
63ebb9fa 833 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
1c21aa8f
DC		 834
835 for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) {
836 VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop,
837 win_yuv2yuv,
838 y2r_coefficients[i],
839 bt601_yuv2rgb[i]);
840 }
84c7f8ca 841 }
4c156c21
MY		 842
843 if (win->phy->scl)
844 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
63ebb9fa 845 drm_rect_width(dest), drm_rect_height(dest),
45babef0 846 fb->format);
4c156c21 847
63ebb9fa
MY		 848 VOP_WIN_SET(vop, win, act_info, act_info);
849 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
850 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
4c156c21 851
438b74a5 852 rb_swap = has_rb_swapped(fb->format->format);
85a359f2 853 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
2048e328 854
58badaa7
KK		 855 /*
856 * Blending win0 with the background color doesn't seem to work
857 * correctly. We only get the background color, no matter the contents
858 * of the win0 framebuffer. However, blending pre-multiplied color
859 * with the default opaque black default background color is a no-op,
860 * so we can just disable blending to get the correct result.
861 */
862 if (fb->format->has_alpha && win_index > 0) {
2048e328
MY		 863 VOP_WIN_SET(vop, win, dst_alpha_ctl,
864 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
865 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
866 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
867 SRC_BLEND_M0(ALPHA_PER_PIX) |
868 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
869 SRC_FACTOR_M0(ALPHA_ONE);
870 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
871 } else {
872 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
873 }
874
875 VOP_WIN_SET(vop, win, enable, 1);
2048e328 876 spin_unlock(&vop->reg_lock);
2048e328
MY		 877}
878
15609559
EBS		 879static int vop_plane_atomic_async_check(struct drm_plane *plane,
880 struct drm_plane_state *state)
881{
882 struct vop_win *vop_win = to_vop_win(plane);
883 const struct vop_win_data *win = vop_win->data;
884 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
885 DRM_PLANE_HELPER_NO_SCALING;
886 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
887 DRM_PLANE_HELPER_NO_SCALING;
888 struct drm_crtc_state *crtc_state;
889
890 if (plane != state->crtc->cursor)
891 return -EINVAL;
892
893 if (!plane->state)
894 return -EINVAL;
895
896 if (!plane->state->fb)
897 return -EINVAL;
898
899 if (state->state)
900 crtc_state = drm_atomic_get_existing_crtc_state(state->state,
901 state->crtc);
902 else /* Special case for asynchronous cursor updates. */
903 crtc_state = plane->crtc->state;
904
905 return drm_atomic_helper_check_plane_state(plane->state, crtc_state,
906 min_scale, max_scale,
907 true, true);
908}
909
910static void vop_plane_atomic_async_update(struct drm_plane *plane,
911 struct drm_plane_state *new_state)
912{
913 struct vop *vop = to_vop(plane->state->crtc);
d985a353
HK		 914 struct drm_framebuffer *old_fb = plane->state->fb;
915
916 plane->state->crtc_x = new_state->crtc_x;
917 plane->state->crtc_y = new_state->crtc_y;
918 plane->state->crtc_h = new_state->crtc_h;
919 plane->state->crtc_w = new_state->crtc_w;
920 plane->state->src_x = new_state->src_x;
921 plane->state->src_y = new_state->src_y;
922 plane->state->src_h = new_state->src_h;
923 plane->state->src_w = new_state->src_w;
924 swap(plane->state->fb, new_state->fb);
15609559
EBS		 925
926 if (vop->is_enabled) {
927 rockchip_drm_psr_inhibit_get_state(new_state->state);
928 vop_plane_atomic_update(plane, plane->state);
929 spin_lock(&vop->reg_lock);
930 vop_cfg_done(vop);
931 spin_unlock(&vop->reg_lock);
932 rockchip_drm_psr_inhibit_put_state(new_state->state);
15609559 933
d985a353
HK		 934 /*
935 * A scanout can still be occurring, so we can't drop the
936 * reference to the old framebuffer. To solve this we get a
937 * reference to old_fb and set a worker to release it later.
938 * FIXME: if we perform 500 async_update calls before the
939 * vblank, then we can have 500 different framebuffers waiting
940 * to be released.
941 */
942 if (old_fb && plane->state->fb != old_fb) {
943 drm_framebuffer_get(old_fb);
944 WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0);
945 drm_flip_work_queue(&vop->fb_unref_work, old_fb);
946 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
947 }
948 }
15609559
EBS		 949}
950
63ebb9fa
MY		 951static const struct drm_plane_helper_funcs plane_helper_funcs = {
952 .atomic_check = vop_plane_atomic_check,
953 .atomic_update = vop_plane_atomic_update,
954 .atomic_disable = vop_plane_atomic_disable,
15609559
EBS		 955 .atomic_async_check = vop_plane_atomic_async_check,
956 .atomic_async_update = vop_plane_atomic_async_update,
63d5e06a 957 .prepare_fb = drm_gem_fb_prepare_fb,
63ebb9fa 958};
2048e328 959
2048e328 960static const struct drm_plane_funcs vop_plane_funcs = {
63ebb9fa
MY		 961 .update_plane = drm_atomic_helper_update_plane,
962 .disable_plane = drm_atomic_helper_disable_plane,
2048e328 963 .destroy = vop_plane_destroy,
d47a7246
TF		 964 .reset = drm_atomic_helper_plane_reset,
965 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
966 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
2048e328
MY		 967};
968
2048e328
MY		 969static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
970{
971 struct vop *vop = to_vop(crtc);
972 unsigned long flags;
973
63ebb9fa 974 if (WARN_ON(!vop->is_enabled))
2048e328
MY		 975 return -EPERM;
976
977 spin_lock_irqsave(&vop->irq_lock, flags);
978
fa374107 979 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
dbb3d944 980 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
2048e328
MY		 981
982 spin_unlock_irqrestore(&vop->irq_lock, flags);
983
984 return 0;
985}
986
987static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
988{
989 struct vop *vop = to_vop(crtc);
990 unsigned long flags;
991
63ebb9fa 992 if (WARN_ON(!vop->is_enabled))
2048e328 993 return;
31e980c5 994
2048e328 995 spin_lock_irqsave(&vop->irq_lock, flags);
dbb3d944
MY		 996
997 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
998
2048e328
MY		 999 spin_unlock_irqrestore(&vop->irq_lock, flags);
1000}
1001
2048e328
MY		 1002static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1003 const struct drm_display_mode *mode,
1004 struct drm_display_mode *adjusted_mode)
1005{
b59b8de3
CZ		 1006 struct vop *vop = to_vop(crtc);
1007
b59b8de3 1008 adjusted_mode->clock =
527e4ca3
DA		 1009 DIV_ROUND_UP(clk_round_rate(vop->dclk,
1010 adjusted_mode->clock * 1000), 1000);
b59b8de3 1011
2048e328
MY		 1012 return true;
1013}
1014
0b20a0f8
LP		 1015static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
1016 struct drm_crtc_state *old_state)
2048e328
MY		 1017{
1018 struct vop *vop = to_vop(crtc);
efd11cc8 1019 const struct vop_data *vop_data = vop->data;
4e257d9e 1020 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
63ebb9fa 1021 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
2048e328
MY		 1022 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1023 u16 hdisplay = adjusted_mode->hdisplay;
1024 u16 htotal = adjusted_mode->htotal;
1025 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1026 u16 hact_end = hact_st + hdisplay;
1027 u16 vdisplay = adjusted_mode->vdisplay;
1028 u16 vtotal = adjusted_mode->vtotal;
1029 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1030 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1031 u16 vact_end = vact_st + vdisplay;
0a63bfd0 1032 uint32_t pin_pol, val;
a5c0fa44 1033 int dither_bpc = s->output_bpc ? s->output_bpc : 10;
39a9ad8f 1034 int ret;
2048e328 1035
e334d48b 1036 mutex_lock(&vop->vop_lock);
1037
893b6cad
DV		 1038 WARN_ON(vop->event);
1039
39a9ad8f
SP		 1040 ret = vop_enable(crtc);
1041 if (ret) {
e334d48b 1042 mutex_unlock(&vop->vop_lock);
39a9ad8f
SP		 1043 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
1044 return;
1045 }
1046
1a0f7ed3 1047 pin_pol = BIT(DCLK_INVERT);
d790ad03
JK		 1048 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
1049 BIT(HSYNC_POSITIVE) : 0;
1050 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ?
1051 BIT(VSYNC_POSITIVE) : 0;
9a61c54b 1052 VOP_REG_SET(vop, output, pin_pol, pin_pol);
cf6d100d 1053 VOP_REG_SET(vop, output, mipi_dual_channel_en, 0);
0a63bfd0 1054
4e257d9e
MY		 1055 switch (s->output_type) {
1056 case DRM_MODE_CONNECTOR_LVDS:
9a61c54b
M		 1057 VOP_REG_SET(vop, output, rgb_en, 1);
1058 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol);
4e257d9e
MY		 1059 break;
1060 case DRM_MODE_CONNECTOR_eDP:
9a61c54b
M		 1061 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol);
1062 VOP_REG_SET(vop, output, edp_en, 1);
4e257d9e
MY		 1063 break;
1064 case DRM_MODE_CONNECTOR_HDMIA:
9a61c54b
M		 1065 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol);
1066 VOP_REG_SET(vop, output, hdmi_en, 1);
4e257d9e
MY		 1067 break;
1068 case DRM_MODE_CONNECTOR_DSI:
9a61c54b
M		 1069 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol);
1070 VOP_REG_SET(vop, output, mipi_en, 1);
cf6d100d
HS		 1071 VOP_REG_SET(vop, output, mipi_dual_channel_en,
1072 !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL));
4e257d9e 1073 break;
1a0f7ed3
CZ		 1074 case DRM_MODE_CONNECTOR_DisplayPort:
1075 pin_pol &= ~BIT(DCLK_INVERT);
9a61c54b
M		 1076 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol);
1077 VOP_REG_SET(vop, output, dp_en, 1);
1a0f7ed3 1078 break;
4e257d9e 1079 default:
ee4d7899
SP		 1080 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
1081 s->output_type);
4e257d9e 1082 }
efd11cc8
M		 1083
1084 /*
1085 * if vop is not support RGB10 output, need force RGB10 to RGB888.
1086 */
1087 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1088 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
1089 s->output_mode = ROCKCHIP_OUT_MODE_P888;
6bda8112 1090
a5c0fa44 1091 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8)
6bda8112
MY		 1092 VOP_REG_SET(vop, common, pre_dither_down, 1);
1093 else
1094 VOP_REG_SET(vop, common, pre_dither_down, 0);
1095
a5c0fa44
UR		 1096 if (dither_bpc == 6) {
1097 VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO);
1098 VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666);
1099 VOP_REG_SET(vop, common, dither_down_en, 1);
1100 } else {
1101 VOP_REG_SET(vop, common, dither_down_en, 0);
1102 }
1103
9a61c54b 1104 VOP_REG_SET(vop, common, out_mode, s->output_mode);
2048e328 1105
9a61c54b 1106 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len);
2048e328
MY		 1107 val = hact_st << 16;
1108 val |= hact_end;
9a61c54b
M		 1109 VOP_REG_SET(vop, modeset, hact_st_end, val);
1110 VOP_REG_SET(vop, modeset, hpost_st_end, val);
2048e328 1111
9a61c54b 1112 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len);
2048e328
MY		 1113 val = vact_st << 16;
1114 val |= vact_end;
9a61c54b
M		 1115 VOP_REG_SET(vop, modeset, vact_st_end, val);
1116 VOP_REG_SET(vop, modeset, vpost_st_end, val);
2048e328 1117
9a61c54b 1118 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end);
459b086d 1119
2048e328 1120 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
ce3887ed 1121
9a61c54b 1122 VOP_REG_SET(vop, common, standby, 0);
e334d48b 1123 mutex_unlock(&vop->vop_lock);
2048e328
MY		 1124}
1125
7caecdbe
TF		 1126static bool vop_fs_irq_is_pending(struct vop *vop)
1127{
1128 return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
1129}
1130
1131static void vop_wait_for_irq_handler(struct vop *vop)
1132{
1133 bool pending;
1134 int ret;
1135
1136 /*
1137 * Spin until frame start interrupt status bit goes low, which means
1138 * that interrupt handler was invoked and cleared it. The timeout of
1139 * 10 msecs is really too long, but it is just a safety measure if
1140 * something goes really wrong. The wait will only happen in the very
1141 * unlikely case of a vblank happening exactly at the same time and
1142 * shouldn't exceed microseconds range.
1143 */
1144 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
1145 !pending, 0, 10 * 1000);
1146 if (ret)
1147 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
1148
1149 synchronize_irq(vop->irq);
1150}
1151
63ebb9fa
MY		 1152static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1153 struct drm_crtc_state *old_crtc_state)
2048e328 1154{
47a7eb45 1155 struct drm_atomic_state *old_state = old_crtc_state->state;
e741f2b1 1156 struct drm_plane_state *old_plane_state, *new_plane_state;
2048e328 1157 struct vop *vop = to_vop(crtc);
47a7eb45
TF		 1158 struct drm_plane *plane;
1159 int i;
2048e328 1160
63ebb9fa
MY		 1161 if (WARN_ON(!vop->is_enabled))
1162 return;
2048e328 1163
63ebb9fa 1164 spin_lock(&vop->reg_lock);
2048e328 1165
63ebb9fa 1166 vop_cfg_done(vop);
2048e328 1167
63ebb9fa 1168 spin_unlock(&vop->reg_lock);
7caecdbe
TF		 1169
1170 /*
1171 * There is a (rather unlikely) possiblity that a vblank interrupt
1172 * fired before we set the cfg_done bit. To avoid spuriously
1173 * signalling flip completion we need to wait for it to finish.
1174 */
1175 vop_wait_for_irq_handler(vop);
47a7eb45 1176
41ee4367
TF		 1177 spin_lock_irq(&crtc->dev->event_lock);
1178 if (crtc->state->event) {
1179 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1180 WARN_ON(vop->event);
1181
1182 vop->event = crtc->state->event;
1183 crtc->state->event = NULL;
1184 }
1185 spin_unlock_irq(&crtc->dev->event_lock);
1186
e741f2b1
ML		 1187 for_each_oldnew_plane_in_state(old_state, plane, old_plane_state,
1188 new_plane_state, i) {
47a7eb45
TF		 1189 if (!old_plane_state->fb)
1190 continue;
1191
e741f2b1 1192 if (old_plane_state->fb == new_plane_state->fb)
47a7eb45
TF		 1193 continue;
1194
adedbf03 1195 drm_framebuffer_get(old_plane_state->fb);
2d078c2d 1196 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
47a7eb45
TF		 1197 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
1198 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
47a7eb45 1199 }
2048e328
MY		 1200}
1201
63ebb9fa 1202static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
63ebb9fa
MY		 1203 .mode_fixup = vop_crtc_mode_fixup,
1204 .atomic_flush = vop_crtc_atomic_flush,
0b20a0f8 1205 .atomic_enable = vop_crtc_atomic_enable,
64581714 1206 .atomic_disable = vop_crtc_atomic_disable,
63ebb9fa
MY		 1207};
1208
2048e328
MY		 1209static void vop_crtc_destroy(struct drm_crtc *crtc)
1210{
1211 drm_crtc_cleanup(crtc);
1212}
1213
4e257d9e
MY		 1214static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1215{
1216 struct rockchip_crtc_state *rockchip_state;
1217
1218 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1219 if (!rockchip_state)
1220 return NULL;
1221
1222 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1223 return &rockchip_state->base;
1224}
1225
1226static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1227 struct drm_crtc_state *state)
1228{
1229 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1230
ec2dc6a0 1231 __drm_atomic_helper_crtc_destroy_state(&s->base);
4e257d9e
MY		 1232 kfree(s);
1233}
1234
01e2eaf4
ML		 1235static void vop_crtc_reset(struct drm_crtc *crtc)
1236{
1237 struct rockchip_crtc_state *crtc_state =
1238 kzalloc(sizeof(*crtc_state), GFP_KERNEL);
1239
1240 if (crtc->state)
1241 vop_crtc_destroy_state(crtc, crtc->state);
1242
1243 __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base);
1244}
1245
6cca3869 1246#ifdef CONFIG_DRM_ANALOGIX_DP
3190e58d
TV		 1247static struct drm_connector *vop_get_edp_connector(struct vop *vop)
1248{
3190e58d 1249 struct drm_connector *connector;
2cbeb64f 1250 struct drm_connector_list_iter conn_iter;
3190e58d 1251
2cbeb64f
GP		 1252 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter);
1253 drm_for_each_connector_iter(connector, &conn_iter) {
3190e58d 1254 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
2cbeb64f 1255 drm_connector_list_iter_end(&conn_iter);
3190e58d
TV		 1256 return connector;
1257 }
2cbeb64f
GP		 1258 }
1259 drm_connector_list_iter_end(&conn_iter);
3190e58d
TV		 1260
1261 return NULL;
1262}
1263
1264static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
c0811a7d 1265 const char *source_name)
3190e58d
TV		 1266{
1267 struct vop *vop = to_vop(crtc);
1268 struct drm_connector *connector;
1269 int ret;
1270
1271 connector = vop_get_edp_connector(vop);
1272 if (!connector)
1273 return -EINVAL;
1274
3190e58d
TV		 1275 if (source_name && strcmp(source_name, "auto") == 0)
1276 ret = analogix_dp_start_crc(connector);
1277 else if (!source_name)
1278 ret = analogix_dp_stop_crc(connector);
1279 else
1280 ret = -EINVAL;
1281
1282 return ret;
1283}
b8d913c0
MK		 1284
1285static int
1286vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1287 size_t *values_cnt)
1288{
1289 if (source_name && strcmp(source_name, "auto") != 0)
1290 return -EINVAL;
1291
1292 *values_cnt = 3;
1293 return 0;
1294}
1295
6cca3869
SP		 1296#else
1297static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
c0811a7d 1298 const char *source_name)
6cca3869
SP		 1299{
1300 return -ENODEV;
1301}
b8d913c0
MK		 1302
1303static int
1304vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1305 size_t *values_cnt)
1306{
1307 return -ENODEV;
1308}
6cca3869 1309#endif
3190e58d 1310
2048e328 1311static const struct drm_crtc_funcs vop_crtc_funcs = {
63ebb9fa
MY		 1312 .set_config = drm_atomic_helper_set_config,
1313 .page_flip = drm_atomic_helper_page_flip,
2048e328 1314 .destroy = vop_crtc_destroy,
dc0b408f 1315 .reset = vop_crtc_reset,
4e257d9e
MY		 1316 .atomic_duplicate_state = vop_crtc_duplicate_state,
1317 .atomic_destroy_state = vop_crtc_destroy_state,
c3605dfc
SG		 1318 .enable_vblank = vop_crtc_enable_vblank,
1319 .disable_vblank = vop_crtc_disable_vblank,
3190e58d 1320 .set_crc_source = vop_crtc_set_crc_source,
b8d913c0 1321 .verify_crc_source = vop_crtc_verify_crc_source,
2048e328
MY		 1322};
1323
47a7eb45
TF		 1324static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
1325{
1326 struct vop *vop = container_of(work, struct vop, fb_unref_work);
1327 struct drm_framebuffer *fb = val;
1328
1329 drm_crtc_vblank_put(&vop->crtc);
adedbf03 1330 drm_framebuffer_put(fb);
47a7eb45
TF		 1331}
1332
63ebb9fa 1333static void vop_handle_vblank(struct vop *vop)
2048e328 1334{
63ebb9fa
MY		 1335 struct drm_device *drm = vop->drm_dev;
1336 struct drm_crtc *crtc = &vop->crtc;
2048e328 1337
1c85f2fa 1338 spin_lock(&drm->event_lock);
63ebb9fa 1339 if (vop->event) {
63ebb9fa 1340 drm_crtc_send_vblank_event(crtc, vop->event);
5b680403 1341 drm_crtc_vblank_put(crtc);
646ec687 1342 vop->event = NULL;
5b680403 1343 }
1c85f2fa 1344 spin_unlock(&drm->event_lock);
893b6cad 1345
47a7eb45
TF		 1346 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
1347 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
2048e328
MY		 1348}
1349
1350static irqreturn_t vop_isr(int irq, void *data)
1351{
1352 struct vop *vop = data;
b5f7b755 1353 struct drm_crtc *crtc = &vop->crtc;
dbb3d944 1354 uint32_t active_irqs;
1067219b 1355 int ret = IRQ_NONE;
2048e328 1356
6456314f
SH		 1357 /*
1358 * The irq is shared with the iommu. If the runtime-pm state of the
1359 * vop-device is disabled the irq has to be targeted at the iommu.
1360 */
1361 if (!pm_runtime_get_if_in_use(vop->dev))
1362 return IRQ_NONE;
1363
1364 if (vop_core_clks_enable(vop)) {
1365 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n");
1366 goto out;
1367 }
1368
2048e328 1369 /*
dbb3d944 1370 * interrupt register has interrupt status, enable and clear bits, we
2048e328
MY		 1371 * must hold irq_lock to avoid a race with enable/disable_vblank().
1372 */
1c85f2fa 1373 spin_lock(&vop->irq_lock);
dbb3d944
MY		 1374
1375 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
2048e328
MY		 1376 /* Clear all active interrupt sources */
1377 if (active_irqs)
dbb3d944
MY		 1378 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1379
1c85f2fa 1380 spin_unlock(&vop->irq_lock);
2048e328
MY		 1381
1382 /* This is expected for vop iommu irqs, since the irq is shared */
1383 if (!active_irqs)
6456314f 1384 goto out_disable;
2048e328 1385
1067219b
MY		 1386 if (active_irqs & DSP_HOLD_VALID_INTR) {
1387 complete(&vop->dsp_hold_completion);
1388 active_irqs &= ~DSP_HOLD_VALID_INTR;
1389 ret = IRQ_HANDLED;
2048e328
MY		 1390 }
1391
69c34e41
YY		 1392 if (active_irqs & LINE_FLAG_INTR) {
1393 complete(&vop->line_flag_completion);
1394 active_irqs &= ~LINE_FLAG_INTR;
1395 ret = IRQ_HANDLED;
1396 }
1397
1067219b 1398 if (active_irqs & FS_INTR) {
b5f7b755 1399 drm_crtc_handle_vblank(crtc);
63ebb9fa 1400 vop_handle_vblank(vop);
1067219b 1401 active_irqs &= ~FS_INTR;
63ebb9fa 1402 ret = IRQ_HANDLED;
1067219b 1403 }
2048e328 1404
1067219b
MY		 1405 /* Unhandled irqs are spurious. */
1406 if (active_irqs)
ee4d7899
SP		 1407 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",
1408 active_irqs);
1067219b 1409
6456314f
SH		 1410out_disable:
1411 vop_core_clks_disable(vop);
1412out:
1413 pm_runtime_put(vop->dev);
1067219b 1414 return ret;
2048e328
MY		 1415}
1416
677e8bbc
DC		 1417static void vop_plane_add_properties(struct drm_plane *plane,
1418 const struct vop_win_data *win_data)
1419{
1420 unsigned int flags = 0;
1421
1422 flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0;
1423 flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0;
1424 if (flags)
1425 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
1426 DRM_MODE_ROTATE_0 | flags);
1427}
1428
2048e328
MY		 1429static int vop_create_crtc(struct vop *vop)
1430{
1431 const struct vop_data *vop_data = vop->data;
1432 struct device *dev = vop->dev;
1433 struct drm_device *drm_dev = vop->drm_dev;
328b51c0 1434 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
2048e328
MY		 1435 struct drm_crtc *crtc = &vop->crtc;
1436 struct device_node *port;
1437 int ret;
1438 int i;
1439
1440 /*
1441 * Create drm_plane for primary and cursor planes first, since we need
1442 * to pass them to drm_crtc_init_with_planes, which sets the
1443 * "possible_crtcs" to the newly initialized crtc.
1444 */
1445 for (i = 0; i < vop_data->win_size; i++) {
1446 struct vop_win *vop_win = &vop->win[i];
1447 const struct vop_win_data *win_data = vop_win->data;
1448
1449 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1450 win_data->type != DRM_PLANE_TYPE_CURSOR)
1451 continue;
1452
1453 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1454 0, &vop_plane_funcs,
1455 win_data->phy->data_formats,
1456 win_data->phy->nformats,
e6fc3b68 1457 NULL, win_data->type, NULL);
2048e328 1458 if (ret) {
ee4d7899
SP		 1459 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",
1460 ret);
2048e328
MY		 1461 goto err_cleanup_planes;
1462 }
1463
1464 plane = &vop_win->base;
63ebb9fa 1465 drm_plane_helper_add(plane, &plane_helper_funcs);
677e8bbc 1466 vop_plane_add_properties(plane, win_data);
2048e328
MY		 1467 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1468 primary = plane;
1469 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1470 cursor = plane;
1471 }
1472
1473 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
f9882876 1474 &vop_crtc_funcs, NULL);
2048e328 1475 if (ret)
328b51c0 1476 goto err_cleanup_planes;
2048e328
MY		 1477
1478 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1479
1480 /*
1481 * Create drm_planes for overlay windows with possible_crtcs restricted
1482 * to the newly created crtc.
1483 */
1484 for (i = 0; i < vop_data->win_size; i++) {
1485 struct vop_win *vop_win = &vop->win[i];
1486 const struct vop_win_data *win_data = vop_win->data;
a3e77e16 1487 unsigned long possible_crtcs = drm_crtc_mask(crtc);
2048e328
MY		 1488
1489 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1490 continue;
1491
1492 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1493 possible_crtcs,
1494 &vop_plane_funcs,
1495 win_data->phy->data_formats,
1496 win_data->phy->nformats,
e6fc3b68 1497 NULL, win_data->type, NULL);
2048e328 1498 if (ret) {
ee4d7899
SP		 1499 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
1500 ret);
2048e328
MY		 1501 goto err_cleanup_crtc;
1502 }
63ebb9fa 1503 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
677e8bbc 1504 vop_plane_add_properties(&vop_win->base, win_data);
2048e328
MY		 1505 }
1506
1507 port = of_get_child_by_name(dev->of_node, "port");
1508 if (!port) {
4bf99144
RH		 1509 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n",
1510 dev->of_node);
328b51c0 1511 ret = -ENOENT;
2048e328
MY		 1512 goto err_cleanup_crtc;
1513 }
1514
47a7eb45
TF		 1515 drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
1516 vop_fb_unref_worker);
1517
1067219b 1518 init_completion(&vop->dsp_hold_completion);
69c34e41 1519 init_completion(&vop->line_flag_completion);
2048e328 1520 crtc->port = port;
2048e328
MY		 1521
1522 return 0;
1523
1524err_cleanup_crtc:
1525 drm_crtc_cleanup(crtc);
1526err_cleanup_planes:
328b51c0
DA		 1527 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1528 head)
2048e328
MY		 1529 drm_plane_cleanup(plane);
1530 return ret;
1531}
1532
1533static void vop_destroy_crtc(struct vop *vop)
1534{
1535 struct drm_crtc *crtc = &vop->crtc;
328b51c0
DA		 1536 struct drm_device *drm_dev = vop->drm_dev;
1537 struct drm_plane *plane, *tmp;
2048e328 1538
2048e328 1539 of_node_put(crtc->port);
328b51c0
DA		 1540
1541 /*
1542 * We need to cleanup the planes now. Why?
1543 *
1544 * The planes are "&vop->win[i].base". That means the memory is
1545 * all part of the big "struct vop" chunk of memory. That memory
1546 * was devm allocated and associated with this component. We need to
1547 * free it ourselves before vop_unbind() finishes.
1548 */
1549 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1550 head)
1551 vop_plane_destroy(plane);
1552
1553 /*
1554 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1555 * references the CRTC.
1556 */
2048e328 1557 drm_crtc_cleanup(crtc);
47a7eb45 1558 drm_flip_work_cleanup(&vop->fb_unref_work);
2048e328
MY		 1559}
1560
1561static int vop_initial(struct vop *vop)
1562{
1563 const struct vop_data *vop_data = vop->data;
2048e328
MY		 1564 struct reset_control *ahb_rst;
1565 int i, ret;
1566
1567 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1568 if (IS_ERR(vop->hclk)) {
d8dd6804 1569 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n");
2048e328
MY		 1570 return PTR_ERR(vop->hclk);
1571 }
1572 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1573 if (IS_ERR(vop->aclk)) {
d8dd6804 1574 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n");
2048e328
MY		 1575 return PTR_ERR(vop->aclk);
1576 }
1577 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1578 if (IS_ERR(vop->dclk)) {
d8dd6804 1579 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n");
2048e328
MY		 1580 return PTR_ERR(vop->dclk);
1581 }
1582
5e570373
JC		 1583 ret = pm_runtime_get_sync(vop->dev);
1584 if (ret < 0) {
d8dd6804 1585 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
5e570373
JC		 1586 return ret;
1587 }
1588
2048e328
MY		 1589 ret = clk_prepare(vop->dclk);
1590 if (ret < 0) {
d8dd6804 1591 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n");
5e570373 1592 goto err_put_pm_runtime;
2048e328
MY		 1593 }
1594
d7b53fd9
SS		 1595 /* Enable both the hclk and aclk to setup the vop */
1596 ret = clk_prepare_enable(vop->hclk);
2048e328 1597 if (ret < 0) {
d8dd6804 1598 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n");
2048e328
MY		 1599 goto err_unprepare_dclk;
1600 }
1601
d7b53fd9 1602 ret = clk_prepare_enable(vop->aclk);
2048e328 1603 if (ret < 0) {
d8dd6804 1604 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n");
d7b53fd9 1605 goto err_disable_hclk;
2048e328 1606 }
d7b53fd9 1607
2048e328
MY		 1608 /*
1609 * do hclk_reset, reset all vop registers.
1610 */
1611 ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1612 if (IS_ERR(ahb_rst)) {
d8dd6804 1613 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n");
2048e328 1614 ret = PTR_ERR(ahb_rst);
d7b53fd9 1615 goto err_disable_aclk;
2048e328
MY		 1616 }
1617 reset_control_assert(ahb_rst);
1618 usleep_range(10, 20);
1619 reset_control_deassert(ahb_rst);
1620
5f9e93fe
MZ		 1621 VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1);
1622 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0);
1623
76f1416e
MZ		 1624 for (i = 0; i < vop->len; i += sizeof(u32))
1625 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i);
2048e328 1626
9a61c54b
M		 1627 VOP_REG_SET(vop, misc, global_regdone_en, 1);
1628 VOP_REG_SET(vop, common, dsp_blank, 0);
2048e328
MY		 1629
1630 for (i = 0; i < vop_data->win_size; i++) {
1631 const struct vop_win_data *win = &vop_data->win[i];
9dd2aca4 1632 int channel = i * 2 + 1;
2048e328 1633
9dd2aca4 1634 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
e9abc611 1635 vop_win_disable(vop, win);
60b7ae7f 1636 VOP_WIN_SET(vop, win, gate, 1);
2048e328
MY		 1637 }
1638
1639 vop_cfg_done(vop);
1640
1641 /*
1642 * do dclk_reset, let all config take affect.
1643 */
1644 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1645 if (IS_ERR(vop->dclk_rst)) {
d8dd6804 1646 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n");
2048e328 1647 ret = PTR_ERR(vop->dclk_rst);
d7b53fd9 1648 goto err_disable_aclk;
2048e328
MY		 1649 }
1650 reset_control_assert(vop->dclk_rst);
1651 usleep_range(10, 20);
1652 reset_control_deassert(vop->dclk_rst);
1653
1654 clk_disable(vop->hclk);
d7b53fd9 1655 clk_disable(vop->aclk);
2048e328 1656
31e980c5 1657 vop->is_enabled = false;
2048e328 1658
5e570373
JC		 1659 pm_runtime_put_sync(vop->dev);
1660
2048e328
MY		 1661 return 0;
1662
d7b53fd9
SS		 1663err_disable_aclk:
1664 clk_disable_unprepare(vop->aclk);
2048e328 1665err_disable_hclk:
d7b53fd9 1666 clk_disable_unprepare(vop->hclk);
2048e328
MY		 1667err_unprepare_dclk:
1668 clk_unprepare(vop->dclk);
5e570373
JC		 1669err_put_pm_runtime:
1670 pm_runtime_put_sync(vop->dev);
2048e328
MY		 1671 return ret;
1672}
1673
1674/*
1675 * Initialize the vop->win array elements.
1676 */
1677static void vop_win_init(struct vop *vop)
1678{
1679 const struct vop_data *vop_data = vop->data;
1680 unsigned int i;
1681
1682 for (i = 0; i < vop_data->win_size; i++) {
1683 struct vop_win *vop_win = &vop->win[i];
1684 const struct vop_win_data *win_data = &vop_data->win[i];
1685
1686 vop_win->data = win_data;
1687 vop_win->vop = vop;
ce6912b4
HS		 1688
1689 if (vop_data->win_yuv2yuv)
1690 vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i];
2048e328
MY		 1691 }
1692}
1693
69c34e41 1694/**
459b086d 1695 * rockchip_drm_wait_vact_end
69c34e41 1696 * @crtc: CRTC to enable line flag
69c34e41
YY		 1697 * @mstimeout: millisecond for timeout
1698 *
459b086d 1699 * Wait for vact_end line flag irq or timeout.
69c34e41
YY		 1700 *
1701 * Returns:
1702 * Zero on success, negative errno on failure.
1703 */
459b086d 1704int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
69c34e41
YY		 1705{
1706 struct vop *vop = to_vop(crtc);
1707 unsigned long jiffies_left;
e334d48b 1708 int ret = 0;
69c34e41
YY		 1709
1710 if (!crtc || !vop->is_enabled)
1711 return -ENODEV;
1712
e334d48b 1713 mutex_lock(&vop->vop_lock);
1714 if (mstimeout <= 0) {
1715 ret = -EINVAL;
1716 goto out;
1717 }
69c34e41 1718
e334d48b 1719 if (vop_line_flag_irq_is_enabled(vop)) {
1720 ret = -EBUSY;
1721 goto out;
1722 }
69c34e41
YY		 1723
1724 reinit_completion(&vop->line_flag_completion);
459b086d 1725 vop_line_flag_irq_enable(vop);
69c34e41
YY		 1726
1727 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
1728 msecs_to_jiffies(mstimeout));
1729 vop_line_flag_irq_disable(vop);
1730
1731 if (jiffies_left == 0) {
d8dd6804 1732 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n");
e334d48b 1733 ret = -ETIMEDOUT;
1734 goto out;
69c34e41
YY		 1735 }
1736
e334d48b 1737out:
1738 mutex_unlock(&vop->vop_lock);
1739 return ret;
69c34e41 1740}
459b086d 1741EXPORT_SYMBOL(rockchip_drm_wait_vact_end);
69c34e41 1742
2048e328
MY		 1743static int vop_bind(struct device *dev, struct device *master, void *data)
1744{
1745 struct platform_device *pdev = to_platform_device(dev);
2048e328
MY		 1746 const struct vop_data *vop_data;
1747 struct drm_device *drm_dev = data;
1748 struct vop *vop;
1749 struct resource *res;
3ea68922 1750 int ret, irq;
2048e328 1751
a67719d1 1752 vop_data = of_device_get_match_data(dev);
2048e328
MY		 1753 if (!vop_data)
1754 return -ENODEV;
1755
1756 /* Allocate vop struct and its vop_win array */
29adeb4f
GS		 1757 vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size),
1758 GFP_KERNEL);
2048e328
MY		 1759 if (!vop)
1760 return -ENOMEM;
1761
1762 vop->dev = dev;
1763 vop->data = vop_data;
1764 vop->drm_dev = drm_dev;
1765 dev_set_drvdata(dev, vop);
1766
1767 vop_win_init(vop);
1768
1769 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1770 vop->len = resource_size(res);
1771 vop->regs = devm_ioremap_resource(dev, res);
1772 if (IS_ERR(vop->regs))
1773 return PTR_ERR(vop->regs);
1774
1775 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1776 if (!vop->regsbak)
1777 return -ENOMEM;
1778
3ea68922
HS		 1779 irq = platform_get_irq(pdev, 0);
1780 if (irq < 0) {
d8dd6804 1781 DRM_DEV_ERROR(dev, "cannot find irq for vop\n");
3ea68922 1782 return irq;
2048e328 1783 }
3ea68922 1784 vop->irq = (unsigned int)irq;
2048e328
MY		 1785
1786 spin_lock_init(&vop->reg_lock);
1787 spin_lock_init(&vop->irq_lock);
e334d48b 1788 mutex_init(&vop->vop_lock);
2048e328 1789
2048e328
MY		 1790 ret = vop_create_crtc(vop);
1791 if (ret)
5f9e93fe 1792 return ret;
2048e328
MY		 1793
1794 pm_runtime_enable(&pdev->dev);
5182c1a5 1795
5e570373
JC		 1796 ret = vop_initial(vop);
1797 if (ret < 0) {
d8dd6804
HM		 1798 DRM_DEV_ERROR(&pdev->dev,
1799 "cannot initial vop dev - err %d\n", ret);
5e570373
JC		 1800 goto err_disable_pm_runtime;
1801 }
1802
5f9e93fe
MZ		 1803 ret = devm_request_irq(dev, vop->irq, vop_isr,
1804 IRQF_SHARED, dev_name(dev), vop);
1805 if (ret)
1806 goto err_disable_pm_runtime;
1807
1f0f0151
SH		 1808 if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) {
1809 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev);
1810 if (IS_ERR(vop->rgb)) {
1811 ret = PTR_ERR(vop->rgb);
1812 goto err_disable_pm_runtime;
1813 }
1814 }
1815
2048e328 1816 return 0;
8c763c9b 1817
5e570373
JC		 1818err_disable_pm_runtime:
1819 pm_runtime_disable(&pdev->dev);
1820 vop_destroy_crtc(vop);
8c763c9b 1821 return ret;
2048e328
MY		 1822}
1823
1824static void vop_unbind(struct device *dev, struct device *master, void *data)
1825{
1826 struct vop *vop = dev_get_drvdata(dev);
1827
1f0f0151
SH		 1828 if (vop->rgb)
1829 rockchip_rgb_fini(vop->rgb);
1830
2048e328
MY		 1831 pm_runtime_disable(dev);
1832 vop_destroy_crtc(vop);
ec6e7767
JC		 1833
1834 clk_unprepare(vop->aclk);
1835 clk_unprepare(vop->hclk);
1836 clk_unprepare(vop->dclk);
2048e328
MY		 1837}
1838
a67719d1 1839const struct component_ops vop_component_ops = {
2048e328
MY		 1840 .bind = vop_bind,
1841 .unbind = vop_unbind,
1842};
54255e81 1843EXPORT_SYMBOL_GPL(vop_component_ops);
Linux 6.x block layer and io_uring tree(s)