Commit | Line | Data |
---|---|---|
12b9f204 AY |
1 | /* |
2 | * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | */ | |
9 | ||
5e3bc6d1 MY |
10 | #include <linux/clk.h> |
11 | #include <linux/mfd/syscon.h> | |
12b9f204 AY |
12 | #include <linux/module.h> |
13 | #include <linux/platform_device.h> | |
bd130230 | 14 | #include <linux/phy/phy.h> |
12b9f204 | 15 | #include <linux/regmap.h> |
5e3bc6d1 | 16 | |
12b9f204 AY |
17 | #include <drm/drm_of.h> |
18 | #include <drm/drmP.h> | |
19 | #include <drm/drm_crtc_helper.h> | |
20 | #include <drm/drm_edid.h> | |
12b9f204 AY |
21 | #include <drm/bridge/dw_hdmi.h> |
22 | ||
23 | #include "rockchip_drm_drv.h" | |
24 | #include "rockchip_drm_vop.h" | |
25 | ||
6445e394 MY |
26 | #define RK3288_GRF_SOC_CON6 0x025C |
27 | #define RK3288_HDMI_LCDC_SEL BIT(4) | |
1c53ba8f HS |
28 | #define RK3328_GRF_SOC_CON2 0x0408 |
29 | ||
30 | #define RK3328_HDMI_SDAIN_MSK BIT(11) | |
31 | #define RK3328_HDMI_SCLIN_MSK BIT(10) | |
32 | #define RK3328_HDMI_HPD_IOE BIT(2) | |
33 | #define RK3328_GRF_SOC_CON3 0x040c | |
34 | /* need to be unset if hdmi or i2c should control voltage */ | |
35 | #define RK3328_HDMI_SDA5V_GRF BIT(15) | |
36 | #define RK3328_HDMI_SCL5V_GRF BIT(14) | |
37 | #define RK3328_HDMI_HPD5V_GRF BIT(13) | |
38 | #define RK3328_HDMI_CEC5V_GRF BIT(12) | |
39 | #define RK3328_GRF_SOC_CON4 0x0410 | |
40 | #define RK3328_HDMI_HPD_SARADC BIT(13) | |
41 | #define RK3328_HDMI_CEC_5V BIT(11) | |
42 | #define RK3328_HDMI_SDA_5V BIT(10) | |
43 | #define RK3328_HDMI_SCL_5V BIT(9) | |
44 | #define RK3328_HDMI_HPD_5V BIT(8) | |
45 | ||
6445e394 MY |
46 | #define RK3399_GRF_SOC_CON20 0x6250 |
47 | #define RK3399_HDMI_LCDC_SEL BIT(6) | |
48 | ||
49 | #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) | |
50 | ||
51 | /** | |
52 | * struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips | |
53 | * @lcdsel_grf_reg: grf register offset of lcdc select | |
54 | * @lcdsel_big: reg value of selecting vop big for HDMI | |
55 | * @lcdsel_lit: reg value of selecting vop little for HDMI | |
56 | */ | |
57 | struct rockchip_hdmi_chip_data { | |
96c4704f | 58 | int lcdsel_grf_reg; |
6445e394 MY |
59 | u32 lcdsel_big; |
60 | u32 lcdsel_lit; | |
61 | }; | |
12b9f204 AY |
62 | |
63 | struct rockchip_hdmi { | |
64 | struct device *dev; | |
65 | struct regmap *regmap; | |
66 | struct drm_encoder encoder; | |
6445e394 | 67 | const struct rockchip_hdmi_chip_data *chip_data; |
5e3bc6d1 | 68 | struct clk *vpll_clk; |
8814b40b | 69 | struct clk *grf_clk; |
eea034af | 70 | struct dw_hdmi *hdmi; |
bd130230 | 71 | struct phy *phy; |
12b9f204 AY |
72 | }; |
73 | ||
74 | #define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x) | |
75 | ||
76 | static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { | |
77 | { | |
78 | 27000000, { | |
79 | { 0x00b3, 0x0000}, | |
80 | { 0x2153, 0x0000}, | |
81 | { 0x40f3, 0x0000} | |
82 | }, | |
83 | }, { | |
84 | 36000000, { | |
85 | { 0x00b3, 0x0000}, | |
86 | { 0x2153, 0x0000}, | |
87 | { 0x40f3, 0x0000} | |
88 | }, | |
89 | }, { | |
90 | 40000000, { | |
91 | { 0x00b3, 0x0000}, | |
92 | { 0x2153, 0x0000}, | |
93 | { 0x40f3, 0x0000} | |
94 | }, | |
95 | }, { | |
96 | 54000000, { | |
97 | { 0x0072, 0x0001}, | |
98 | { 0x2142, 0x0001}, | |
99 | { 0x40a2, 0x0001}, | |
100 | }, | |
101 | }, { | |
102 | 65000000, { | |
103 | { 0x0072, 0x0001}, | |
104 | { 0x2142, 0x0001}, | |
105 | { 0x40a2, 0x0001}, | |
106 | }, | |
107 | }, { | |
108 | 66000000, { | |
109 | { 0x013e, 0x0003}, | |
110 | { 0x217e, 0x0002}, | |
111 | { 0x4061, 0x0002} | |
112 | }, | |
113 | }, { | |
114 | 74250000, { | |
115 | { 0x0072, 0x0001}, | |
116 | { 0x2145, 0x0002}, | |
117 | { 0x4061, 0x0002} | |
118 | }, | |
119 | }, { | |
120 | 83500000, { | |
121 | { 0x0072, 0x0001}, | |
122 | }, | |
123 | }, { | |
124 | 108000000, { | |
125 | { 0x0051, 0x0002}, | |
126 | { 0x2145, 0x0002}, | |
127 | { 0x4061, 0x0002} | |
128 | }, | |
129 | }, { | |
130 | 106500000, { | |
131 | { 0x0051, 0x0002}, | |
132 | { 0x2145, 0x0002}, | |
133 | { 0x4061, 0x0002} | |
134 | }, | |
135 | }, { | |
136 | 146250000, { | |
137 | { 0x0051, 0x0002}, | |
138 | { 0x2145, 0x0002}, | |
139 | { 0x4061, 0x0002} | |
140 | }, | |
141 | }, { | |
142 | 148500000, { | |
143 | { 0x0051, 0x0003}, | |
144 | { 0x214c, 0x0003}, | |
145 | { 0x4064, 0x0003} | |
146 | }, | |
147 | }, { | |
148 | ~0UL, { | |
149 | { 0x00a0, 0x000a }, | |
150 | { 0x2001, 0x000f }, | |
151 | { 0x4002, 0x000f }, | |
152 | }, | |
153 | } | |
154 | }; | |
155 | ||
156 | static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { | |
157 | /* pixelclk bpp8 bpp10 bpp12 */ | |
158 | { | |
159 | 40000000, { 0x0018, 0x0018, 0x0018 }, | |
160 | }, { | |
161 | 65000000, { 0x0028, 0x0028, 0x0028 }, | |
162 | }, { | |
163 | 66000000, { 0x0038, 0x0038, 0x0038 }, | |
164 | }, { | |
165 | 74250000, { 0x0028, 0x0038, 0x0038 }, | |
166 | }, { | |
167 | 83500000, { 0x0028, 0x0038, 0x0038 }, | |
168 | }, { | |
169 | 146250000, { 0x0038, 0x0038, 0x0038 }, | |
170 | }, { | |
171 | 148500000, { 0x0000, 0x0038, 0x0038 }, | |
172 | }, { | |
173 | ~0UL, { 0x0000, 0x0000, 0x0000}, | |
174 | } | |
175 | }; | |
176 | ||
034705a4 YY |
177 | static const struct dw_hdmi_phy_config rockchip_phy_config[] = { |
178 | /*pixelclk symbol term vlev*/ | |
1dbee1a3 YY |
179 | { 74250000, 0x8009, 0x0004, 0x0272}, |
180 | { 148500000, 0x802b, 0x0004, 0x028d}, | |
181 | { 297000000, 0x8039, 0x0005, 0x028d}, | |
034705a4 | 182 | { ~0UL, 0x0000, 0x0000, 0x0000} |
12b9f204 AY |
183 | }; |
184 | ||
185 | static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) | |
186 | { | |
187 | struct device_node *np = hdmi->dev->of_node; | |
188 | ||
189 | hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); | |
190 | if (IS_ERR(hdmi->regmap)) { | |
d8dd6804 | 191 | DRM_DEV_ERROR(hdmi->dev, "Unable to get rockchip,grf\n"); |
12b9f204 AY |
192 | return PTR_ERR(hdmi->regmap); |
193 | } | |
194 | ||
5e3bc6d1 MY |
195 | hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll"); |
196 | if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) { | |
197 | hdmi->vpll_clk = NULL; | |
198 | } else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) { | |
199 | return -EPROBE_DEFER; | |
200 | } else if (IS_ERR(hdmi->vpll_clk)) { | |
d8dd6804 | 201 | DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n"); |
5e3bc6d1 MY |
202 | return PTR_ERR(hdmi->vpll_clk); |
203 | } | |
204 | ||
8814b40b MY |
205 | hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf"); |
206 | if (PTR_ERR(hdmi->grf_clk) == -ENOENT) { | |
207 | hdmi->grf_clk = NULL; | |
208 | } else if (PTR_ERR(hdmi->grf_clk) == -EPROBE_DEFER) { | |
209 | return -EPROBE_DEFER; | |
210 | } else if (IS_ERR(hdmi->grf_clk)) { | |
d8dd6804 | 211 | DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n"); |
8814b40b MY |
212 | return PTR_ERR(hdmi->grf_clk); |
213 | } | |
214 | ||
12b9f204 AY |
215 | return 0; |
216 | } | |
217 | ||
218 | static enum drm_mode_status | |
219 | dw_hdmi_rockchip_mode_valid(struct drm_connector *connector, | |
b0febde7 | 220 | const struct drm_display_mode *mode) |
12b9f204 AY |
221 | { |
222 | const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg; | |
223 | int pclk = mode->clock * 1000; | |
224 | bool valid = false; | |
225 | int i; | |
226 | ||
227 | for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) { | |
228 | if (pclk == mpll_cfg[i].mpixelclock) { | |
229 | valid = true; | |
230 | break; | |
231 | } | |
232 | } | |
233 | ||
234 | return (valid) ? MODE_OK : MODE_BAD; | |
235 | } | |
236 | ||
28c508ec | 237 | static const struct drm_encoder_funcs dw_hdmi_rockchip_encoder_funcs = { |
12b9f204 AY |
238 | .destroy = drm_encoder_cleanup, |
239 | }; | |
240 | ||
241 | static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder) | |
242 | { | |
243 | } | |
244 | ||
245 | static bool | |
246 | dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder, | |
247 | const struct drm_display_mode *mode, | |
248 | struct drm_display_mode *adj_mode) | |
249 | { | |
250 | return true; | |
251 | } | |
252 | ||
253 | static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder, | |
254 | struct drm_display_mode *mode, | |
255 | struct drm_display_mode *adj_mode) | |
256 | { | |
5e3bc6d1 MY |
257 | struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); |
258 | ||
259 | clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000); | |
12b9f204 AY |
260 | } |
261 | ||
a8eef71d | 262 | static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) |
12b9f204 AY |
263 | { |
264 | struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); | |
265 | u32 val; | |
6445e394 | 266 | int ret; |
12b9f204 | 267 | |
96c4704f HS |
268 | if (hdmi->chip_data->lcdsel_grf_reg < 0) |
269 | return; | |
270 | ||
6445e394 MY |
271 | ret = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder); |
272 | if (ret) | |
273 | val = hdmi->chip_data->lcdsel_lit; | |
12b9f204 | 274 | else |
6445e394 MY |
275 | val = hdmi->chip_data->lcdsel_big; |
276 | ||
8814b40b MY |
277 | ret = clk_prepare_enable(hdmi->grf_clk); |
278 | if (ret < 0) { | |
d8dd6804 | 279 | DRM_DEV_ERROR(hdmi->dev, "failed to enable grfclk %d\n", ret); |
8814b40b MY |
280 | return; |
281 | } | |
282 | ||
6445e394 MY |
283 | ret = regmap_write(hdmi->regmap, hdmi->chip_data->lcdsel_grf_reg, val); |
284 | if (ret != 0) | |
d8dd6804 | 285 | DRM_DEV_ERROR(hdmi->dev, "Could not write to GRF: %d\n", ret); |
12b9f204 | 286 | |
8814b40b | 287 | clk_disable_unprepare(hdmi->grf_clk); |
d8dd6804 HM |
288 | DRM_DEV_DEBUG(hdmi->dev, "vop %s output to hdmi\n", |
289 | ret ? "LIT" : "BIG"); | |
12b9f204 AY |
290 | } |
291 | ||
4e257d9e MY |
292 | static int |
293 | dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder, | |
294 | struct drm_crtc_state *crtc_state, | |
295 | struct drm_connector_state *conn_state) | |
296 | { | |
297 | struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); | |
298 | ||
299 | s->output_mode = ROCKCHIP_OUT_MODE_AAAA; | |
300 | s->output_type = DRM_MODE_CONNECTOR_HDMIA; | |
301 | ||
302 | return 0; | |
303 | } | |
304 | ||
28c508ec | 305 | static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = { |
12b9f204 AY |
306 | .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup, |
307 | .mode_set = dw_hdmi_rockchip_encoder_mode_set, | |
a8eef71d | 308 | .enable = dw_hdmi_rockchip_encoder_enable, |
12b9f204 | 309 | .disable = dw_hdmi_rockchip_encoder_disable, |
4e257d9e | 310 | .atomic_check = dw_hdmi_rockchip_encoder_atomic_check, |
12b9f204 AY |
311 | }; |
312 | ||
1c53ba8f HS |
313 | static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data, |
314 | struct drm_display_mode *mode) | |
315 | { | |
316 | struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; | |
317 | ||
318 | return phy_power_on(hdmi->phy); | |
319 | } | |
320 | ||
321 | static void dw_hdmi_rockchip_genphy_disable(struct dw_hdmi *dw_hdmi, void *data) | |
322 | { | |
323 | struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; | |
324 | ||
325 | phy_power_off(hdmi->phy); | |
326 | } | |
327 | ||
328 | static enum drm_connector_status | |
329 | dw_hdmi_rk3328_read_hpd(struct dw_hdmi *dw_hdmi, void *data) | |
330 | { | |
331 | struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; | |
332 | enum drm_connector_status status; | |
333 | ||
334 | status = dw_hdmi_phy_read_hpd(dw_hdmi, data); | |
335 | ||
336 | if (status == connector_status_connected) | |
337 | regmap_write(hdmi->regmap, | |
338 | RK3328_GRF_SOC_CON4, | |
339 | HIWORD_UPDATE(RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V, | |
340 | RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V)); | |
341 | else | |
342 | regmap_write(hdmi->regmap, | |
343 | RK3328_GRF_SOC_CON4, | |
344 | HIWORD_UPDATE(0, RK3328_HDMI_SDA_5V | | |
345 | RK3328_HDMI_SCL_5V)); | |
346 | return status; | |
347 | } | |
348 | ||
349 | static void dw_hdmi_rk3328_setup_hpd(struct dw_hdmi *dw_hdmi, void *data) | |
350 | { | |
351 | struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; | |
352 | ||
353 | dw_hdmi_phy_setup_hpd(dw_hdmi, data); | |
354 | ||
355 | /* Enable and map pins to 3V grf-controlled io-voltage */ | |
356 | regmap_write(hdmi->regmap, | |
357 | RK3328_GRF_SOC_CON4, | |
358 | HIWORD_UPDATE(0, RK3328_HDMI_HPD_SARADC | RK3328_HDMI_CEC_5V | | |
359 | RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V | | |
360 | RK3328_HDMI_HPD_5V)); | |
361 | regmap_write(hdmi->regmap, | |
362 | RK3328_GRF_SOC_CON3, | |
363 | HIWORD_UPDATE(0, RK3328_HDMI_SDA5V_GRF | RK3328_HDMI_SCL5V_GRF | | |
364 | RK3328_HDMI_HPD5V_GRF | | |
365 | RK3328_HDMI_CEC5V_GRF)); | |
366 | regmap_write(hdmi->regmap, | |
367 | RK3328_GRF_SOC_CON2, | |
368 | HIWORD_UPDATE(RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK, | |
369 | RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK | | |
370 | RK3328_HDMI_HPD_IOE)); | |
371 | } | |
372 | ||
6445e394 MY |
373 | static struct rockchip_hdmi_chip_data rk3288_chip_data = { |
374 | .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, | |
375 | .lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL), | |
376 | .lcdsel_lit = HIWORD_UPDATE(RK3288_HDMI_LCDC_SEL, RK3288_HDMI_LCDC_SEL), | |
377 | }; | |
378 | ||
379 | static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = { | |
12b9f204 AY |
380 | .mode_valid = dw_hdmi_rockchip_mode_valid, |
381 | .mpll_cfg = rockchip_mpll_cfg, | |
382 | .cur_ctr = rockchip_cur_ctr, | |
034705a4 | 383 | .phy_config = rockchip_phy_config, |
6445e394 MY |
384 | .phy_data = &rk3288_chip_data, |
385 | }; | |
386 | ||
1c53ba8f HS |
387 | static const struct dw_hdmi_phy_ops rk3328_hdmi_phy_ops = { |
388 | .init = dw_hdmi_rockchip_genphy_init, | |
389 | .disable = dw_hdmi_rockchip_genphy_disable, | |
390 | .read_hpd = dw_hdmi_rk3328_read_hpd, | |
391 | .update_hpd = dw_hdmi_phy_update_hpd, | |
392 | .setup_hpd = dw_hdmi_rk3328_setup_hpd, | |
393 | }; | |
394 | ||
395 | static struct rockchip_hdmi_chip_data rk3328_chip_data = { | |
396 | .lcdsel_grf_reg = -1, | |
397 | }; | |
398 | ||
399 | static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { | |
400 | .mode_valid = dw_hdmi_rockchip_mode_valid, | |
401 | .mpll_cfg = rockchip_mpll_cfg, | |
402 | .cur_ctr = rockchip_cur_ctr, | |
403 | .phy_config = rockchip_phy_config, | |
404 | .phy_data = &rk3328_chip_data, | |
405 | .phy_ops = &rk3328_hdmi_phy_ops, | |
406 | .phy_name = "inno_dw_hdmi_phy2", | |
407 | .phy_force_vendor = true, | |
408 | }; | |
409 | ||
6445e394 MY |
410 | static struct rockchip_hdmi_chip_data rk3399_chip_data = { |
411 | .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, | |
412 | .lcdsel_big = HIWORD_UPDATE(0, RK3399_HDMI_LCDC_SEL), | |
413 | .lcdsel_lit = HIWORD_UPDATE(RK3399_HDMI_LCDC_SEL, RK3399_HDMI_LCDC_SEL), | |
414 | }; | |
415 | ||
416 | static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = { | |
417 | .mode_valid = dw_hdmi_rockchip_mode_valid, | |
418 | .mpll_cfg = rockchip_mpll_cfg, | |
419 | .cur_ctr = rockchip_cur_ctr, | |
420 | .phy_config = rockchip_phy_config, | |
421 | .phy_data = &rk3399_chip_data, | |
12b9f204 AY |
422 | }; |
423 | ||
424 | static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = { | |
425 | { .compatible = "rockchip,rk3288-dw-hdmi", | |
6445e394 MY |
426 | .data = &rk3288_hdmi_drv_data |
427 | }, | |
1c53ba8f HS |
428 | { .compatible = "rockchip,rk3328-dw-hdmi", |
429 | .data = &rk3328_hdmi_drv_data | |
430 | }, | |
6445e394 MY |
431 | { .compatible = "rockchip,rk3399-dw-hdmi", |
432 | .data = &rk3399_hdmi_drv_data | |
12b9f204 AY |
433 | }, |
434 | {}, | |
435 | }; | |
436 | MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids); | |
437 | ||
438 | static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, | |
439 | void *data) | |
440 | { | |
441 | struct platform_device *pdev = to_platform_device(dev); | |
5c3f3d22 | 442 | struct dw_hdmi_plat_data *plat_data; |
12b9f204 AY |
443 | const struct of_device_id *match; |
444 | struct drm_device *drm = data; | |
445 | struct drm_encoder *encoder; | |
446 | struct rockchip_hdmi *hdmi; | |
12b9f204 AY |
447 | int ret; |
448 | ||
449 | if (!pdev->dev.of_node) | |
450 | return -ENODEV; | |
451 | ||
452 | hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); | |
453 | if (!hdmi) | |
454 | return -ENOMEM; | |
455 | ||
456 | match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node); | |
5c3f3d22 HS |
457 | plat_data = devm_kmemdup(&pdev->dev, match->data, |
458 | sizeof(*plat_data), GFP_KERNEL); | |
459 | if (!plat_data) | |
460 | return -ENOMEM; | |
461 | ||
12b9f204 | 462 | hdmi->dev = &pdev->dev; |
6445e394 | 463 | hdmi->chip_data = plat_data->phy_data; |
5c3f3d22 | 464 | plat_data->phy_data = hdmi; |
12b9f204 AY |
465 | encoder = &hdmi->encoder; |
466 | ||
12b9f204 AY |
467 | encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); |
468 | /* | |
469 | * If we failed to find the CRTC(s) which this encoder is | |
470 | * supposed to be connected to, it's because the CRTC has | |
471 | * not been registered yet. Defer probing, and hope that | |
472 | * the required CRTC is added later. | |
473 | */ | |
474 | if (encoder->possible_crtcs == 0) | |
475 | return -EPROBE_DEFER; | |
476 | ||
477 | ret = rockchip_hdmi_parse_dt(hdmi); | |
478 | if (ret) { | |
d8dd6804 | 479 | DRM_DEV_ERROR(hdmi->dev, "Unable to parse OF data\n"); |
12b9f204 AY |
480 | return ret; |
481 | } | |
482 | ||
8ba905f1 JC |
483 | ret = clk_prepare_enable(hdmi->vpll_clk); |
484 | if (ret) { | |
485 | DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n", | |
486 | ret); | |
487 | return ret; | |
488 | } | |
489 | ||
bd130230 HS |
490 | hdmi->phy = devm_phy_optional_get(dev, "hdmi"); |
491 | if (IS_ERR(hdmi->phy)) { | |
492 | ret = PTR_ERR(hdmi->phy); | |
493 | if (ret != -EPROBE_DEFER) | |
494 | DRM_DEV_ERROR(hdmi->dev, "failed to get phy\n"); | |
495 | return ret; | |
496 | } | |
497 | ||
12b9f204 AY |
498 | drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs); |
499 | drm_encoder_init(drm, encoder, &dw_hdmi_rockchip_encoder_funcs, | |
13a3d91f | 500 | DRM_MODE_ENCODER_TMDS, NULL); |
12b9f204 | 501 | |
eea034af JS |
502 | platform_set_drvdata(pdev, hdmi); |
503 | ||
504 | hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data); | |
948cf427 DA |
505 | |
506 | /* | |
507 | * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(), | |
508 | * which would have called the encoder cleanup. Do it manually. | |
509 | */ | |
eea034af JS |
510 | if (IS_ERR(hdmi->hdmi)) { |
511 | ret = PTR_ERR(hdmi->hdmi); | |
948cf427 | 512 | drm_encoder_cleanup(encoder); |
8ba905f1 | 513 | clk_disable_unprepare(hdmi->vpll_clk); |
eea034af | 514 | } |
948cf427 DA |
515 | |
516 | return ret; | |
12b9f204 AY |
517 | } |
518 | ||
519 | static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master, | |
520 | void *data) | |
521 | { | |
eea034af JS |
522 | struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); |
523 | ||
524 | dw_hdmi_unbind(hdmi->hdmi); | |
8ba905f1 | 525 | clk_disable_unprepare(hdmi->vpll_clk); |
12b9f204 AY |
526 | } |
527 | ||
528 | static const struct component_ops dw_hdmi_rockchip_ops = { | |
529 | .bind = dw_hdmi_rockchip_bind, | |
530 | .unbind = dw_hdmi_rockchip_unbind, | |
531 | }; | |
532 | ||
533 | static int dw_hdmi_rockchip_probe(struct platform_device *pdev) | |
534 | { | |
535 | return component_add(&pdev->dev, &dw_hdmi_rockchip_ops); | |
536 | } | |
537 | ||
538 | static int dw_hdmi_rockchip_remove(struct platform_device *pdev) | |
539 | { | |
540 | component_del(&pdev->dev, &dw_hdmi_rockchip_ops); | |
541 | ||
542 | return 0; | |
543 | } | |
544 | ||
8820b68b | 545 | struct platform_driver dw_hdmi_rockchip_pltfm_driver = { |
12b9f204 AY |
546 | .probe = dw_hdmi_rockchip_probe, |
547 | .remove = dw_hdmi_rockchip_remove, | |
548 | .driver = { | |
549 | .name = "dwhdmi-rockchip", | |
550 | .of_match_table = dw_hdmi_rockchip_dt_ids, | |
551 | }, | |
552 | }; |