[linux-2.6-block.git] / drivers / gpu / drm / rockchip / analogix_dp-rockchip.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Rockchip SoC DP (Display Port) interface driver.
 *
 * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
 * Author: Andy Yan <andy.yan@rock-chips.com>
 *         Yakir Yang <ykk@rock-chips.com>
 *         Jeff Chen <jeff.chen@rock-chips.com>
 */

#include <linux/component.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_graph.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/clk.h>

#include <video/of_videomode.h>
#include <video/videomode.h>

#include <drm/display/drm_dp_helper.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/bridge/analogix_dp.h>
#include <drm/drm_of.h>
#include <drm/drm_panel.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_simple_kms_helper.h>

#include "rockchip_drm_drv.h"

#define RK3288_GRF_SOC_CON6		0x25c
#define RK3288_EDP_LCDC_SEL		BIT(5)
#define RK3399_GRF_SOC_CON20		0x6250
#define RK3399_EDP_LCDC_SEL		BIT(5)

#define HIWORD_UPDATE(val, mask)	(val | (mask) << 16)

#define PSR_WAIT_LINE_FLAG_TIMEOUT_MS	100

/**
 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
 * @lcdsel_grf_reg: grf register offset of lcdc select
 * @lcdsel_big: reg value of selecting vop big for eDP
 * @lcdsel_lit: reg value of selecting vop little for eDP
 * @chip_type: specific chip type
 */
struct rockchip_dp_chip_data {
	u32	lcdsel_grf_reg;
	u32	lcdsel_big;
	u32	lcdsel_lit;
	u32	chip_type;
};

struct rockchip_dp_device {
	struct drm_device        *drm_dev;
	struct device            *dev;
	struct rockchip_encoder  encoder;
	struct drm_display_mode  mode;

	struct clk               *pclk;
	struct clk               *grfclk;
	struct regmap            *grf;
	struct reset_control     *rst;

	const struct rockchip_dp_chip_data *data;

	struct analogix_dp_device *adp;
	struct analogix_dp_plat_data plat_data;
};

static struct rockchip_dp_device *encoder_to_dp(struct drm_encoder *encoder)
{
	struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);

	return container_of(rkencoder, struct rockchip_dp_device, encoder);
}

static struct rockchip_dp_device *pdata_encoder_to_dp(struct analogix_dp_plat_data *plat_data)
{
	return container_of(plat_data, struct rockchip_dp_device, plat_data);
}

static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
{
	reset_control_assert(dp->rst);
	usleep_range(10, 20);
	reset_control_deassert(dp->rst);

	return 0;
}

static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
{
	struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data);
	int ret;

	ret = clk_prepare_enable(dp->pclk);
	if (ret < 0) {
		DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret);
		return ret;
	}

	ret = rockchip_dp_pre_init(dp);
	if (ret < 0) {
		DRM_DEV_ERROR(dp->dev, "failed to dp pre init %d\n", ret);
		clk_disable_unprepare(dp->pclk);
		return ret;
	}

	return ret;
}

static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
{
	struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data);

	clk_disable_unprepare(dp->pclk);

	return 0;
}

static int rockchip_dp_get_modes(struct analogix_dp_plat_data *plat_data,
				 struct drm_connector *connector)
{
	struct drm_display_info *di = &connector->display_info;
	/* VOP couldn't output YUV video format for eDP rightly */
	u32 mask = DRM_COLOR_FORMAT_YCBCR444 | DRM_COLOR_FORMAT_YCBCR422;

	if ((di->color_formats & mask)) {
		DRM_DEBUG_KMS("Swapping display color format from YUV to RGB\n");
		di->color_formats &= ~mask;
		di->color_formats |= DRM_COLOR_FORMAT_RGB444;
		di->bpc = 8;
	}

	return 0;
}

static bool
rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
				   const struct drm_display_mode *mode,
				   struct drm_display_mode *adjusted_mode)
{
	/* do nothing */
	return true;
}

static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
					     struct drm_display_mode *mode,
					     struct drm_display_mode *adjusted)
{
	/* do nothing */
}

static
struct drm_crtc *rockchip_dp_drm_get_new_crtc(struct drm_encoder *encoder,
					      struct drm_atomic_state *state)
{
	struct drm_connector *connector;
	struct drm_connector_state *conn_state;

	connector = drm_atomic_get_new_connector_for_encoder(state, encoder);
	if (!connector)
		return NULL;

	conn_state = drm_atomic_get_new_connector_state(state, connector);
	if (!conn_state)
		return NULL;

	return conn_state->crtc;
}

static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder,
					   struct drm_atomic_state *state)
{
	struct rockchip_dp_device *dp = encoder_to_dp(encoder);
	struct drm_crtc *crtc;
	struct drm_crtc_state *old_crtc_state;
	int ret;
	u32 val;

	crtc = rockchip_dp_drm_get_new_crtc(encoder, state);
	if (!crtc)
		return;

	old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
	/* Coming back from self refresh, nothing to do */
	if (old_crtc_state && old_crtc_state->self_refresh_active)
		return;

	ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);
	if (ret < 0)
		return;

	if (ret)
		val = dp->data->lcdsel_lit;
	else
		val = dp->data->lcdsel_big;

	DRM_DEV_DEBUG(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");

	ret = clk_prepare_enable(dp->grfclk);
	if (ret < 0) {
		DRM_DEV_ERROR(dp->dev, "failed to enable grfclk %d\n", ret);
		return;
	}

	ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
	if (ret != 0)
		DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret);

	clk_disable_unprepare(dp->grfclk);
}

static void rockchip_dp_drm_encoder_disable(struct drm_encoder *encoder,
					    struct drm_atomic_state *state)
{
	struct rockchip_dp_device *dp = encoder_to_dp(encoder);
	struct drm_crtc *crtc;
	struct drm_crtc_state *new_crtc_state = NULL;
	int ret;

	crtc = rockchip_dp_drm_get_new_crtc(encoder, state);
	/* No crtc means we're doing a full shutdown */
	if (!crtc)
		return;

	new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
	/* If we're not entering self-refresh, no need to wait for vact */
	if (!new_crtc_state || !new_crtc_state->self_refresh_active)
		return;

	ret = rockchip_drm_wait_vact_end(crtc, PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
	if (ret)
		DRM_DEV_ERROR(dp->dev, "line flag irq timed out\n");
}

static int
rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder,
				      struct drm_crtc_state *crtc_state,
				      struct drm_connector_state *conn_state)
{
	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
	struct drm_display_info *di = &conn_state->connector->display_info;

	/*
	 * The hardware IC designed that VOP must output the RGB10 video
	 * format to eDP controller, and if eDP panel only support RGB8,
	 * then eDP controller should cut down the video data, not via VOP
	 * controller, that's why we need to hardcode the VOP output mode
	 * to RGA10 here.
	 */

	s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
	s->output_type = DRM_MODE_CONNECTOR_eDP;
	s->output_bpc = di->bpc;

	return 0;
}

static const struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
	.mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
	.mode_set = rockchip_dp_drm_encoder_mode_set,
	.atomic_enable = rockchip_dp_drm_encoder_enable,
	.atomic_disable = rockchip_dp_drm_encoder_disable,
	.atomic_check = rockchip_dp_drm_encoder_atomic_check,
};

static int rockchip_dp_of_probe(struct rockchip_dp_device *dp)
{
	struct device *dev = dp->dev;
	struct device_node *np = dev->of_node;

	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
	if (IS_ERR(dp->grf)) {
		DRM_DEV_ERROR(dev, "failed to get rockchip,grf property\n");
		return PTR_ERR(dp->grf);
	}

	dp->grfclk = devm_clk_get(dev, "grf");
	if (PTR_ERR(dp->grfclk) == -ENOENT) {
		dp->grfclk = NULL;
	} else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) {
		return -EPROBE_DEFER;
	} else if (IS_ERR(dp->grfclk)) {
		DRM_DEV_ERROR(dev, "failed to get grf clock\n");
		return PTR_ERR(dp->grfclk);
	}

	dp->pclk = devm_clk_get(dev, "pclk");
	if (IS_ERR(dp->pclk)) {
		DRM_DEV_ERROR(dev, "failed to get pclk property\n");
		return PTR_ERR(dp->pclk);
	}

	dp->rst = devm_reset_control_get(dev, "dp");
	if (IS_ERR(dp->rst)) {
		DRM_DEV_ERROR(dev, "failed to get dp reset control\n");
		return PTR_ERR(dp->rst);
	}

	return 0;
}

static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
{
	struct drm_encoder *encoder = &dp->encoder.encoder;
	struct drm_device *drm_dev = dp->drm_dev;
	struct device *dev = dp->dev;
	int ret;

	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
							     dev->of_node);
	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);

	ret = drm_simple_encoder_init(drm_dev, encoder,
				      DRM_MODE_ENCODER_TMDS);
	if (ret) {
		DRM_ERROR("failed to initialize encoder with drm\n");
		return ret;
	}

	drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);

	return 0;
}

static int rockchip_dp_bind(struct device *dev, struct device *master,
			    void *data)
{
	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
	struct drm_device *drm_dev = data;
	int ret;

	dp->drm_dev = drm_dev;

	ret = rockchip_dp_drm_create_encoder(dp);
	if (ret) {
		DRM_ERROR("failed to create drm encoder\n");
		return ret;
	}

	rockchip_drm_encoder_set_crtc_endpoint_id(&dp->encoder,
						  dev->of_node, 0, 0);

	dp->plat_data.encoder = &dp->encoder.encoder;

	ret = analogix_dp_bind(dp->adp, drm_dev);
	if (ret)
		goto err_cleanup_encoder;

	return 0;
err_cleanup_encoder:
	dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder);
	return ret;
}

static void rockchip_dp_unbind(struct device *dev, struct device *master,
			       void *data)
{
	struct rockchip_dp_device *dp = dev_get_drvdata(dev);

	analogix_dp_unbind(dp->adp);
	dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder);
}

static const struct component_ops rockchip_dp_component_ops = {
	.bind = rockchip_dp_bind,
	.unbind = rockchip_dp_unbind,
};

static int rockchip_dp_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	const struct rockchip_dp_chip_data *dp_data;
	struct drm_panel *panel = NULL;
	struct rockchip_dp_device *dp;
	int ret;

	dp_data = of_device_get_match_data(dev);
	if (!dp_data)
		return -ENODEV;

	ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, NULL);
	if (ret < 0)
		return ret;

	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
	if (!dp)
		return -ENOMEM;

	dp->dev = dev;
	dp->adp = ERR_PTR(-ENODEV);
	dp->data = dp_data;
	dp->plat_data.panel = panel;
	dp->plat_data.dev_type = dp->data->chip_type;
	dp->plat_data.power_on = rockchip_dp_poweron;
	dp->plat_data.power_off = rockchip_dp_powerdown;
	dp->plat_data.get_modes = rockchip_dp_get_modes;

	ret = rockchip_dp_of_probe(dp);
	if (ret < 0)
		return ret;

	platform_set_drvdata(pdev, dp);

	dp->adp = analogix_dp_probe(dev, &dp->plat_data);
	if (IS_ERR(dp->adp))
		return PTR_ERR(dp->adp);

	ret = component_add(dev, &rockchip_dp_component_ops);
	if (ret)
		return ret;

	return 0;
}

static void rockchip_dp_remove(struct platform_device *pdev)
{
	component_del(&pdev->dev, &rockchip_dp_component_ops);
}

static int rockchip_dp_suspend(struct device *dev)
{
	struct rockchip_dp_device *dp = dev_get_drvdata(dev);

	if (IS_ERR(dp->adp))
		return 0;

	return analogix_dp_suspend(dp->adp);
}

static int rockchip_dp_resume(struct device *dev)
{
	struct rockchip_dp_device *dp = dev_get_drvdata(dev);

	if (IS_ERR(dp->adp))
		return 0;

	return analogix_dp_resume(dp->adp);
}

static DEFINE_RUNTIME_DEV_PM_OPS(rockchip_dp_pm_ops, rockchip_dp_suspend,
		rockchip_dp_resume, NULL);

static const struct rockchip_dp_chip_data rk3399_edp = {
	.lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
	.lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
	.lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL),
	.chip_type = RK3399_EDP,
};

static const struct rockchip_dp_chip_data rk3288_dp = {
	.lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
	.lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
	.lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL),
	.chip_type = RK3288_DP,
};

static const struct of_device_id rockchip_dp_dt_ids[] = {
	{.compatible = "rockchip,rk3288-dp", .data = &rk3288_dp },
	{.compatible = "rockchip,rk3399-edp", .data = &rk3399_edp },
	{}
};
MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);

struct platform_driver rockchip_dp_driver = {
	.probe = rockchip_dp_probe,
	.remove_new = rockchip_dp_remove,
	.driver = {
		   .name = "rockchip-dp",
		   .pm = pm_ptr(&rockchip_dp_pm_ops),
		   .of_match_table = rockchip_dp_dt_ids,
	},
};
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
9e32e16e YY	2	/*
	3	* Rockchip SoC DP (Display Port) interface driver.
	4	*
	5	* Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
	6	* Author: Andy Yan <andy.yan@rock-chips.com>
	7	* Yakir Yang <ykk@rock-chips.com>
	8	* Jeff Chen <jeff.chen@rock-chips.com>
9e32e16e YY	9	*/
	10
	11	#include <linux/component.h>
	12	#include <linux/mfd/syscon.h>
722d4f06	13	#include <linux/of.h>
9e32e16e	14	#include <linux/of_graph.h>
722d4f06	15	#include <linux/platform_device.h>
c91b5bd7	16	#include <linux/pm_runtime.h>
9e32e16e YY	17	#include <linux/regmap.h>
	18	#include <linux/reset.h>
	19	#include <linux/clk.h>
	20
9e32e16e YY	21	#include <video/of_videomode.h>
	22	#include <video/videomode.h>
	23
da68386d	24	#include <drm/display/drm_dp_helper.h>
6c836d96 SP	25	#include <drm/drm_atomic.h>
6c836d96 SP	26	#include <drm/drm_atomic_helper.h>
9e32e16e	27	#include <drm/bridge/analogix_dp.h>
c2156ccd SR	28	#include <drm/drm_of.h>
	29	#include <drm/drm_panel.h>
	30	#include <drm/drm_probe_helper.h>
0dbd7354	31	#include <drm/drm_simple_kms_helper.h>
9e32e16e YY	32
9e32e16e YY	33	#include "rockchip_drm_drv.h"
9e32e16e	34
d9c900b0 YY	35	#define RK3288_GRF_SOC_CON6 0x25c
d9c900b0 YY	36	#define RK3288_EDP_LCDC_SEL BIT(5)
82872e42 YY	37	#define RK3399_GRF_SOC_CON20 0x6250
82872e42 YY	38	#define RK3399_EDP_LCDC_SEL BIT(5)
d9c900b0 YY	39
	40	#define HIWORD_UPDATE(val, mask) (val \| (mask) << 16)
	41
8f0ac5c4 YY	42	#define PSR_WAIT_LINE_FLAG_TIMEOUT_MS 100
8f0ac5c4 YY	43
d9c900b0 YY	44	/**
	45	* struct rockchip_dp_chip_data - splite the grf setting of kind of chips
	46	* @lcdsel_grf_reg: grf register offset of lcdc select
	47	* @lcdsel_big: reg value of selecting vop big for eDP
	48	* @lcdsel_lit: reg value of selecting vop little for eDP
	49	* @chip_type: specific chip type
	50	*/
	51	struct rockchip_dp_chip_data {
	52	u32 lcdsel_grf_reg;
	53	u32 lcdsel_big;
	54	u32 lcdsel_lit;
	55	u32 chip_type;
	56	};
9e32e16e YY	57
	58	struct rockchip_dp_device {
	59	struct drm_device *drm_dev;
	60	struct device *dev;
540b8f27	61	struct rockchip_encoder encoder;
9e32e16e YY	62	struct drm_display_mode mode;
	63
	64	struct clk *pclk;
dc1c93be	65	struct clk *grfclk;
9e32e16e YY	66	struct regmap *grf;
	67	struct reset_control *rst;
	68
d9c900b0 YY	69	const struct rockchip_dp_chip_data *data;
d9c900b0 YY	70
6b2d8fd9	71	struct analogix_dp_device *adp;
9e32e16e YY	72	struct analogix_dp_plat_data plat_data;
	73	};
	74
540b8f27 SH	75	static struct rockchip_dp_device encoder_to_dp(struct drm_encoder encoder)
	76	{
	77	struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
	78
	79	return container_of(rkencoder, struct rockchip_dp_device, encoder);
	80	}
	81
	82	static struct rockchip_dp_device pdata_encoder_to_dp(struct analogix_dp_plat_data plat_data)
	83	{
	84	return container_of(plat_data, struct rockchip_dp_device, plat_data);
	85	}
	86
9e32e16e YY	87	static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
	88	{
	89	reset_control_assert(dp->rst);
	90	usleep_range(10, 20);
	91	reset_control_deassert(dp->rst);
	92
	93	return 0;
	94	}
	95
6d4618ad	96	static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
9e32e16e	97	{
540b8f27	98	struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data);
9e32e16e YY	99	int ret;
	100
	101	ret = clk_prepare_enable(dp->pclk);
	102	if (ret < 0) {
d8dd6804	103	DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret);
9e32e16e YY	104	return ret;
	105	}
	106
	107	ret = rockchip_dp_pre_init(dp);
	108	if (ret < 0) {
d8dd6804	109	DRM_DEV_ERROR(dp->dev, "failed to dp pre init %d\n", ret);
3694c5c3	110	clk_disable_unprepare(dp->pclk);
9e32e16e YY	111	return ret;
	112	}
	113
7bb3bb4d DA	114	return ret;
	115	}
	116
9e32e16e YY	117	static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
9e32e16e YY	118	{
540b8f27	119	struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data);
9e32e16e YY	120
	121	clk_disable_unprepare(dp->pclk);
	122
	123	return 0;
	124	}
	125
db8a9aed YY	126	static int rockchip_dp_get_modes(struct analogix_dp_plat_data *plat_data,
	127	struct drm_connector *connector)
	128	{
	129	struct drm_display_info *di = &connector->display_info;
	130	/* VOP couldn't output YUV video format for eDP rightly */
c03d0b52	131	u32 mask = DRM_COLOR_FORMAT_YCBCR444 \| DRM_COLOR_FORMAT_YCBCR422;
db8a9aed YY	132
	133	if ((di->color_formats & mask)) {
	134	DRM_DEBUG_KMS("Swapping display color format from YUV to RGB\n");
	135	di->color_formats &= ~mask;
	136	di->color_formats \|= DRM_COLOR_FORMAT_RGB444;
	137	di->bpc = 8;
	138	}
	139
	140	return 0;
	141	}
	142
9e32e16e YY	143	static bool
	144	rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
	145	const struct drm_display_mode *mode,
	146	struct drm_display_mode *adjusted_mode)
	147	{
	148	/* do nothing */
	149	return true;
	150	}
	151
	152	static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
	153	struct drm_display_mode *mode,
	154	struct drm_display_mode *adjusted)
	155	{
	156	/* do nothing */
	157	}
	158
6c836d96 SP	159	static
	160	struct drm_crtc rockchip_dp_drm_get_new_crtc(struct drm_encoder encoder,
	161	struct drm_atomic_state *state)
	162	{
	163	struct drm_connector *connector;
	164	struct drm_connector_state *conn_state;
	165
	166	connector = drm_atomic_get_new_connector_for_encoder(state, encoder);
	167	if (!connector)
	168	return NULL;
	169
	170	conn_state = drm_atomic_get_new_connector_state(state, connector);
	171	if (!conn_state)
	172	return NULL;
	173
	174	return conn_state->crtc;
	175	}
	176
	177	static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder,
	178	struct drm_atomic_state *state)
9e32e16e	179	{
540b8f27	180	struct rockchip_dp_device *dp = encoder_to_dp(encoder);
6c836d96 SP	181	struct drm_crtc *crtc;
6c836d96 SP	182	struct drm_crtc_state *old_crtc_state;
9e32e16e YY	183	int ret;
	184	u32 val;
	185
6c836d96 SP	186	crtc = rockchip_dp_drm_get_new_crtc(encoder, state);
	187	if (!crtc)
	188	return;
	189
	190	old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
	191	/* Coming back from self refresh, nothing to do */
	192	if (old_crtc_state && old_crtc_state->self_refresh_active)
	193	return;
	194
9e32e16e YY	195	ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);
	196	if (ret < 0)
	197	return;
	198
	199	if (ret)
d9c900b0	200	val = dp->data->lcdsel_lit;
9e32e16e	201	else
d9c900b0	202	val = dp->data->lcdsel_big;
9e32e16e	203
d8dd6804	204	DRM_DEV_DEBUG(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
9e32e16e	205
dc1c93be YY	206	ret = clk_prepare_enable(dp->grfclk);
dc1c93be YY	207	if (ret < 0) {
d8dd6804	208	DRM_DEV_ERROR(dp->dev, "failed to enable grfclk %d\n", ret);
9e32e16e YY	209	return;
9e32e16e YY	210	}
dc1c93be YY	211
	212	ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
	213	if (ret != 0)
d8dd6804	214	DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret);
dc1c93be YY	215
dc1c93be YY	216	clk_disable_unprepare(dp->grfclk);
9e32e16e YY	217	}
9e32e16e YY	218
6c836d96 SP	219	static void rockchip_dp_drm_encoder_disable(struct drm_encoder *encoder,
6c836d96 SP	220	struct drm_atomic_state *state)
9e32e16e	221	{
540b8f27	222	struct rockchip_dp_device *dp = encoder_to_dp(encoder);
6c836d96 SP	223	struct drm_crtc *crtc;
	224	struct drm_crtc_state *new_crtc_state = NULL;
	225	int ret;
	226
	227	crtc = rockchip_dp_drm_get_new_crtc(encoder, state);
	228	/* No crtc means we're doing a full shutdown */
	229	if (!crtc)
	230	return;
	231
	232	new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
	233	/* If we're not entering self-refresh, no need to wait for vact */
	234	if (!new_crtc_state \|\| !new_crtc_state->self_refresh_active)
	235	return;
	236
	237	ret = rockchip_drm_wait_vact_end(crtc, PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
	238	if (ret)
	239	DRM_DEV_ERROR(dp->dev, "line flag irq timed out\n");
9e32e16e YY	240	}
9e32e16e YY	241
4e257d9e MY	242	static int
	243	rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder,
	244	struct drm_crtc_state *crtc_state,
	245	struct drm_connector_state *conn_state)
	246	{
	247	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
6bda8112	248	struct drm_display_info *di = &conn_state->connector->display_info;
4e257d9e MY	249
4e257d9e MY	250	/*
d698f0eb YY	251	* The hardware IC designed that VOP must output the RGB10 video
	252	* format to eDP controller, and if eDP panel only support RGB8,
	253	* then eDP controller should cut down the video data, not via VOP
	254	* controller, that's why we need to hardcode the VOP output mode
	255	* to RGA10 here.
4e257d9e	256	*/
82872e42	257
4e257d9e MY	258	s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
4e257d9e MY	259	s->output_type = DRM_MODE_CONNECTOR_eDP;
6bda8112	260	s->output_bpc = di->bpc;
4e257d9e MY	261
	262	return 0;
	263	}
	264
7af62003	265	static const struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
9e32e16e YY	266	.mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
9e32e16e YY	267	.mode_set = rockchip_dp_drm_encoder_mode_set,
6c836d96 SP	268	.atomic_enable = rockchip_dp_drm_encoder_enable,
6c836d96 SP	269	.atomic_disable = rockchip_dp_drm_encoder_disable,
4e257d9e	270	.atomic_check = rockchip_dp_drm_encoder_atomic_check,
9e32e16e YY	271	};
9e32e16e YY	272
102712a3	273	static int rockchip_dp_of_probe(struct rockchip_dp_device *dp)
9e32e16e YY	274	{
	275	struct device *dev = dp->dev;
	276	struct device_node *np = dev->of_node;
9e32e16e YY	277
	278	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
	279	if (IS_ERR(dp->grf)) {
d8dd6804	280	DRM_DEV_ERROR(dev, "failed to get rockchip,grf property\n");
9e32e16e YY	281	return PTR_ERR(dp->grf);
	282	}
	283
dc1c93be YY	284	dp->grfclk = devm_clk_get(dev, "grf");
	285	if (PTR_ERR(dp->grfclk) == -ENOENT) {
	286	dp->grfclk = NULL;
	287	} else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) {
	288	return -EPROBE_DEFER;
	289	} else if (IS_ERR(dp->grfclk)) {
d8dd6804	290	DRM_DEV_ERROR(dev, "failed to get grf clock\n");
dc1c93be YY	291	return PTR_ERR(dp->grfclk);
	292	}
	293
9e32e16e YY	294	dp->pclk = devm_clk_get(dev, "pclk");
9e32e16e YY	295	if (IS_ERR(dp->pclk)) {
d8dd6804	296	DRM_DEV_ERROR(dev, "failed to get pclk property\n");
9e32e16e YY	297	return PTR_ERR(dp->pclk);
	298	}
	299
	300	dp->rst = devm_reset_control_get(dev, "dp");
	301	if (IS_ERR(dp->rst)) {
d8dd6804	302	DRM_DEV_ERROR(dev, "failed to get dp reset control\n");
9e32e16e YY	303	return PTR_ERR(dp->rst);
	304	}
	305
9e32e16e YY	306	return 0;
	307	}
	308
	309	static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
	310	{
540b8f27	311	struct drm_encoder *encoder = &dp->encoder.encoder;
9e32e16e YY	312	struct drm_device *drm_dev = dp->drm_dev;
	313	struct device *dev = dp->dev;
	314	int ret;
	315
	316	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
	317	dev->of_node);
	318	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
	319
0dbd7354 TZ	320	ret = drm_simple_encoder_init(drm_dev, encoder,
0dbd7354 TZ	321	DRM_MODE_ENCODER_TMDS);
9e32e16e YY	322	if (ret) {
	323	DRM_ERROR("failed to initialize encoder with drm\n");
	324	return ret;
	325	}
	326
	327	drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);
	328
	329	return 0;
	330	}
	331
	332	static int rockchip_dp_bind(struct device dev, struct device master,
	333	void *data)
	334	{
	335	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
	336	struct drm_device *drm_dev = data;
	337	int ret;
	338
9e32e16e YY	339	dp->drm_dev = drm_dev;
	340
	341	ret = rockchip_dp_drm_create_encoder(dp);
	342	if (ret) {
	343	DRM_ERROR("failed to create drm encoder\n");
	344	return ret;
	345	}
	346
bb056046 LS	347	rockchip_drm_encoder_set_crtc_endpoint_id(&dp->encoder,
	348	dev->of_node, 0, 0);
	349
540b8f27	350	dp->plat_data.encoder = &dp->encoder.encoder;
9e32e16e	351
152cce00 MS	352	ret = analogix_dp_bind(dp->adp, drm_dev);
152cce00 MS	353	if (ret)
6c836d96	354	goto err_cleanup_encoder;
6b2d8fd9 JC	355
6b2d8fd9 JC	356	return 0;
c8c04514	357	err_cleanup_encoder:
540b8f27	358	dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder);
c8c04514	359	return ret;
9e32e16e YY	360	}
	361
	362	static void rockchip_dp_unbind(struct device dev, struct device master,
	363	void *data)
	364	{
8f0ac5c4 YY	365	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
8f0ac5c4 YY	366
6b2d8fd9	367	analogix_dp_unbind(dp->adp);
540b8f27	368	dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder);
9e32e16e YY	369	}
	370
	371	static const struct component_ops rockchip_dp_component_ops = {
	372	.bind = rockchip_dp_bind,
	373	.unbind = rockchip_dp_unbind,
	374	};
	375
	376	static int rockchip_dp_probe(struct platform_device *pdev)
	377	{
	378	struct device *dev = &pdev->dev;
152cce00	379	const struct rockchip_dp_chip_data *dp_data;
eb87c91c	380	struct drm_panel *panel = NULL;
9e32e16e	381	struct rockchip_dp_device *dp;
ebc94461	382	int ret;
9e32e16e	383
152cce00 MS	384	dp_data = of_device_get_match_data(dev);
	385	if (!dp_data)
	386	return -ENODEV;
	387
ebc94461	388	ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, NULL);
102712a3	389	if (ret < 0)
ebc94461	390	return ret;
9e32e16e	391
9e32e16e YY	392	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
	393	if (!dp)
	394	return -ENOMEM;
	395
	396	dp->dev = dev;
a4169609	397	dp->adp = ERR_PTR(-ENODEV);
152cce00	398	dp->data = dp_data;
9e32e16e	399	dp->plat_data.panel = panel;
152cce00	400	dp->plat_data.dev_type = dp->data->chip_type;
6d4618ad	401	dp->plat_data.power_on = rockchip_dp_poweron;
152cce00 MS	402	dp->plat_data.power_off = rockchip_dp_powerdown;
152cce00 MS	403	dp->plat_data.get_modes = rockchip_dp_get_modes;
9e32e16e	404
102712a3 JC	405	ret = rockchip_dp_of_probe(dp);
	406	if (ret < 0)
	407	return ret;
	408
9e32e16e YY	409	platform_set_drvdata(pdev, dp);
9e32e16e YY	410
152cce00 MS	411	dp->adp = analogix_dp_probe(dev, &dp->plat_data);
	412	if (IS_ERR(dp->adp))
	413	return PTR_ERR(dp->adp);
	414
50743768 CJ	415	ret = component_add(dev, &rockchip_dp_component_ops);
50743768 CJ	416	if (ret)
e7514df0	417	return ret;
50743768 CJ	418
50743768 CJ	419	return 0;
9e32e16e YY	420	}
9e32e16e YY	421
3c855610	422	static void rockchip_dp_remove(struct platform_device *pdev)
9e32e16e YY	423	{
9e32e16e YY	424	component_del(&pdev->dev, &rockchip_dp_component_ops);
9e32e16e YY	425	}
9e32e16e YY	426
6b2d8fd9 JC	427	static int rockchip_dp_suspend(struct device *dev)
	428	{
	429	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
	430
a4169609 TF	431	if (IS_ERR(dp->adp))
	432	return 0;
	433
6b2d8fd9 JC	434	return analogix_dp_suspend(dp->adp);
	435	}
	436
	437	static int rockchip_dp_resume(struct device *dev)
	438	{
	439	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
	440
a4169609 TF	441	if (IS_ERR(dp->adp))
	442	return 0;
	443
6b2d8fd9 JC	444	return analogix_dp_resume(dp->adp);
6b2d8fd9 JC	445	}
6b2d8fd9	446
c91b5bd7 LS	447	static DEFINE_RUNTIME_DEV_PM_OPS(rockchip_dp_pm_ops, rockchip_dp_suspend,
c91b5bd7 LS	448	rockchip_dp_resume, NULL);
9e32e16e	449
82872e42 YY	450	static const struct rockchip_dp_chip_data rk3399_edp = {
	451	.lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
	452	.lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
	453	.lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL),
	454	.chip_type = RK3399_EDP,
	455	};
	456
d9c900b0 YY	457	static const struct rockchip_dp_chip_data rk3288_dp = {
	458	.lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
	459	.lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
	460	.lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL),
	461	.chip_type = RK3288_DP,
	462	};
	463
9e32e16e	464	static const struct of_device_id rockchip_dp_dt_ids[] = {
d9c900b0	465	{.compatible = "rockchip,rk3288-dp", .data = &rk3288_dp },
82872e42	466	{.compatible = "rockchip,rk3399-edp", .data = &rk3399_edp },
9e32e16e YY	467	{}
	468	};
	469	MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);
	470
8820b68b	471	struct platform_driver rockchip_dp_driver = {
9e32e16e	472	.probe = rockchip_dp_probe,
3c855610	473	.remove_new = rockchip_dp_remove,
9e32e16e YY	474	.driver = {
9e32e16e YY	475	.name = "rockchip-dp",
c91b5bd7	476	.pm = pm_ptr(&rockchip_dp_pm_ops),
f7fc7a79	477	.of_match_table = rockchip_dp_dt_ids,
9e32e16e YY	478	},
9e32e16e YY	479	};