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drm/radeon/dpm: remove local sumo_get_xclk()
[linux-2.6-block.git] / drivers / gpu / drm / radeon / sumo_dpm.c
CommitLineData
80ea2c12
AD		 1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "drmP.h"
25#include "radeon.h"
26#include "sumod.h"
27#include "r600_dpm.h"
28#include "cypress_dpm.h"
29#include "sumo_dpm.h"
80ea2c12
AD		 30
31#define SUMO_MAX_DEEPSLEEP_DIVIDER_ID 5
32#define SUMO_MINIMUM_ENGINE_CLOCK 800
33#define BOOST_DPM_LEVEL 7
34
35static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] =
36{
37 SUMO_UTC_DFLT_00,
38 SUMO_UTC_DFLT_01,
39 SUMO_UTC_DFLT_02,
40 SUMO_UTC_DFLT_03,
41 SUMO_UTC_DFLT_04,
42 SUMO_UTC_DFLT_05,
43 SUMO_UTC_DFLT_06,
44 SUMO_UTC_DFLT_07,
45 SUMO_UTC_DFLT_08,
46 SUMO_UTC_DFLT_09,
47 SUMO_UTC_DFLT_10,
48 SUMO_UTC_DFLT_11,
49 SUMO_UTC_DFLT_12,
50 SUMO_UTC_DFLT_13,
51 SUMO_UTC_DFLT_14,
52};
53
54static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] =
55{
56 SUMO_DTC_DFLT_00,
57 SUMO_DTC_DFLT_01,
58 SUMO_DTC_DFLT_02,
59 SUMO_DTC_DFLT_03,
60 SUMO_DTC_DFLT_04,
61 SUMO_DTC_DFLT_05,
62 SUMO_DTC_DFLT_06,
63 SUMO_DTC_DFLT_07,
64 SUMO_DTC_DFLT_08,
65 SUMO_DTC_DFLT_09,
66 SUMO_DTC_DFLT_10,
67 SUMO_DTC_DFLT_11,
68 SUMO_DTC_DFLT_12,
69 SUMO_DTC_DFLT_13,
70 SUMO_DTC_DFLT_14,
71};
72
73struct sumo_ps *sumo_get_ps(struct radeon_ps *rps)
74{
75 struct sumo_ps *ps = rps->ps_priv;
76
77 return ps;
78}
79
80struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev)
81{
82 struct sumo_power_info *pi = rdev->pm.dpm.priv;
83
84 return pi;
85}
86
80ea2c12
AD		 87static void sumo_gfx_clockgating_enable(struct radeon_device *rdev, bool enable)
88{
89 if (enable)
90 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
91 else {
92 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
93 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
94 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
95 RREG32(GB_ADDR_CONFIG);
96 }
97}
98
99#define CGCG_CGTT_LOCAL0_MASK 0xE5BFFFFF
100#define CGCG_CGTT_LOCAL1_MASK 0xEFFF07FF
101
102static void sumo_mg_clockgating_enable(struct radeon_device *rdev, bool enable)
103{
104 u32 local0;
105 u32 local1;
106
107 local0 = RREG32(CG_CGTT_LOCAL_0);
108 local1 = RREG32(CG_CGTT_LOCAL_1);
109
110 if (enable) {
111 WREG32(CG_CGTT_LOCAL_0, (0 & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) );
112 WREG32(CG_CGTT_LOCAL_1, (0 & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) );
113 } else {
114 WREG32(CG_CGTT_LOCAL_0, (0xFFFFFFFF & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) );
115 WREG32(CG_CGTT_LOCAL_1, (0xFFFFCFFF & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) );
116 }
117}
118
119static void sumo_program_git(struct radeon_device *rdev)
120{
121 u32 p, u;
9d45ad5a 122 u32 xclk = radeon_get_xclk(rdev);
80ea2c12
AD		 123
124 r600_calculate_u_and_p(SUMO_GICST_DFLT,
125 xclk, 16, &p, &u);
126
127 WREG32_P(CG_GIT, CG_GICST(p), ~CG_GICST_MASK);
128}
129
130static void sumo_program_grsd(struct radeon_device *rdev)
131{
132 u32 p, u;
9d45ad5a 133 u32 xclk = radeon_get_xclk(rdev);
80ea2c12
AD		 134 u32 grs = 256 * 25 / 100;
135
136 r600_calculate_u_and_p(1, xclk, 14, &p, &u);
137
138 WREG32(CG_GCOOR, PHC(grs) | SDC(p) | SU(u));
139}
140
d70229f7 141void sumo_gfx_clockgating_initialize(struct radeon_device *rdev)
80ea2c12
AD		 142{
143 sumo_program_git(rdev);
144 sumo_program_grsd(rdev);
145}
146
147static void sumo_gfx_powergating_initialize(struct radeon_device *rdev)
148{
149 u32 rcu_pwr_gating_cntl;
150 u32 p, u;
151 u32 p_c, p_p, d_p;
152 u32 r_t, i_t;
9d45ad5a 153 u32 xclk = radeon_get_xclk(rdev);
80ea2c12
AD		 154
155 if (rdev->family == CHIP_PALM) {
156 p_c = 4;
157 d_p = 10;
158 r_t = 10;
159 i_t = 4;
160 p_p = 50 + 1000/200 + 6 * 32;
161 } else {
162 p_c = 16;
163 d_p = 50;
164 r_t = 50;
165 i_t = 50;
166 p_p = 113;
167 }
168
169 WREG32(CG_SCRATCH2, 0x01B60A17);
170
171 r600_calculate_u_and_p(SUMO_GFXPOWERGATINGT_DFLT,
172 xclk, 16, &p, &u);
173
174 WREG32_P(CG_PWR_GATING_CNTL, PGP(p) | PGU(u),
175 ~(PGP_MASK | PGU_MASK));
176
177 r600_calculate_u_and_p(SUMO_VOLTAGEDROPT_DFLT,
178 xclk, 16, &p, &u);
179
180 WREG32_P(CG_CG_VOLTAGE_CNTL, PGP(p) | PGU(u),
181 ~(PGP_MASK | PGU_MASK));
182
183 if (rdev->family == CHIP_PALM) {
184 WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x10103210);
185 WREG32_RCU(RCU_PWR_GATING_SEQ1, 0x10101010);
186 } else {
187 WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x76543210);
188 WREG32_RCU(RCU_PWR_GATING_SEQ1, 0xFEDCBA98);
189 }
190
191 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
192 rcu_pwr_gating_cntl &=
193 ~(RSVD_MASK | PCV_MASK | PGS_MASK);
194 rcu_pwr_gating_cntl |= PCV(p_c) | PGS(1) | PWR_GATING_EN;
195 if (rdev->family == CHIP_PALM) {
196 rcu_pwr_gating_cntl &= ~PCP_MASK;
197 rcu_pwr_gating_cntl |= PCP(0x77);
198 }
199 WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
200
201 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
202 rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
203 rcu_pwr_gating_cntl |= MPPU(p_p) | MPPD(50);
204 WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
205
206 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
207 rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
208 rcu_pwr_gating_cntl |= DPPU(d_p) | DPPD(50);
209 WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
210
211 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_4);
212 rcu_pwr_gating_cntl &= ~(RT_MASK | IT_MASK);
213 rcu_pwr_gating_cntl |= RT(r_t) | IT(i_t);
214 WREG32_RCU(RCU_PWR_GATING_CNTL_4, rcu_pwr_gating_cntl);
215
216 if (rdev->family == CHIP_PALM)
217 WREG32_RCU(RCU_PWR_GATING_CNTL_5, 0xA02);
218
219 sumo_smu_pg_init(rdev);
220
221 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
222 rcu_pwr_gating_cntl &=
223 ~(RSVD_MASK | PCV_MASK | PGS_MASK);
224 rcu_pwr_gating_cntl |= PCV(p_c) | PGS(4) | PWR_GATING_EN;
225 if (rdev->family == CHIP_PALM) {
226 rcu_pwr_gating_cntl &= ~PCP_MASK;
227 rcu_pwr_gating_cntl |= PCP(0x77);
228 }
229 WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
230
231 if (rdev->family == CHIP_PALM) {
232 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
233 rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
234 rcu_pwr_gating_cntl |= MPPU(113) | MPPD(50);
235 WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
236
237 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
238 rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
239 rcu_pwr_gating_cntl |= DPPU(16) | DPPD(50);
240 WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
241 }
242
243 sumo_smu_pg_init(rdev);
244
245 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
246 rcu_pwr_gating_cntl &=
247 ~(RSVD_MASK | PCV_MASK | PGS_MASK);
248 rcu_pwr_gating_cntl |= PGS(5) | PWR_GATING_EN;
249
250 if (rdev->family == CHIP_PALM) {
251 rcu_pwr_gating_cntl |= PCV(4);
252 rcu_pwr_gating_cntl &= ~PCP_MASK;
253 rcu_pwr_gating_cntl |= PCP(0x77);
254 } else
255 rcu_pwr_gating_cntl |= PCV(11);
256 WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
257
258 if (rdev->family == CHIP_PALM) {
259 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
260 rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
261 rcu_pwr_gating_cntl |= MPPU(113) | MPPD(50);
262 WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
263
264 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
265 rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
266 rcu_pwr_gating_cntl |= DPPU(22) | DPPD(50);
267 WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
268 }
269
270 sumo_smu_pg_init(rdev);
271}
272
273static void sumo_gfx_powergating_enable(struct radeon_device *rdev, bool enable)
274{
275 if (enable)
276 WREG32_P(CG_PWR_GATING_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN);
277 else {
278 WREG32_P(CG_PWR_GATING_CNTL, 0, ~DYN_PWR_DOWN_EN);
279 RREG32(GB_ADDR_CONFIG);
280 }
281}
282
283static int sumo_enable_clock_power_gating(struct radeon_device *rdev)
284{
285 struct sumo_power_info *pi = sumo_get_pi(rdev);
286
287 if (pi->enable_gfx_clock_gating)
288 sumo_gfx_clockgating_initialize(rdev);
289 if (pi->enable_gfx_power_gating)
290 sumo_gfx_powergating_initialize(rdev);
291 if (pi->enable_mg_clock_gating)
292 sumo_mg_clockgating_enable(rdev, true);
293 if (pi->enable_gfx_clock_gating)
294 sumo_gfx_clockgating_enable(rdev, true);
295 if (pi->enable_gfx_power_gating)
296 sumo_gfx_powergating_enable(rdev, true);
297
298 return 0;
299}
300
301static void sumo_disable_clock_power_gating(struct radeon_device *rdev)
302{
303 struct sumo_power_info *pi = sumo_get_pi(rdev);
304
305 if (pi->enable_gfx_clock_gating)
306 sumo_gfx_clockgating_enable(rdev, false);
307 if (pi->enable_gfx_power_gating)
308 sumo_gfx_powergating_enable(rdev, false);
309 if (pi->enable_mg_clock_gating)
310 sumo_mg_clockgating_enable(rdev, false);
311}
312
313static void sumo_calculate_bsp(struct radeon_device *rdev,
314 u32 high_clk)
315{
316 struct sumo_power_info *pi = sumo_get_pi(rdev);
9d45ad5a 317 u32 xclk = radeon_get_xclk(rdev);
80ea2c12
AD		 318
319 pi->pasi = 65535 * 100 / high_clk;
320 pi->asi = 65535 * 100 / high_clk;
321
322 r600_calculate_u_and_p(pi->asi,
323 xclk, 16, &pi->bsp, &pi->bsu);
324
325 r600_calculate_u_and_p(pi->pasi,
326 xclk, 16, &pi->pbsp, &pi->pbsu);
327
328 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
329 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
330}
331
332static void sumo_init_bsp(struct radeon_device *rdev)
333{
334 struct sumo_power_info *pi = sumo_get_pi(rdev);
335
336 WREG32(CG_BSP_0, pi->psp);
337}
338
339
34936f55
AD		 340static void sumo_program_bsp(struct radeon_device *rdev,
341 struct radeon_ps *rps)
80ea2c12
AD		 342{
343 struct sumo_power_info *pi = sumo_get_pi(rdev);
34936f55 344 struct sumo_ps *ps = sumo_get_ps(rps);
80ea2c12
AD		 345 u32 i;
346 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk;
347
348 if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
349 highest_engine_clock = pi->boost_pl.sclk;
350
351 sumo_calculate_bsp(rdev, highest_engine_clock);
352
353 for (i = 0; i < ps->num_levels - 1; i++)
354 WREG32(CG_BSP_0 + (i * 4), pi->dsp);
355
356 WREG32(CG_BSP_0 + (i * 4), pi->psp);
357
358 if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
359 WREG32(CG_BSP_0 + (BOOST_DPM_LEVEL * 4), pi->psp);
360}
361
362static void sumo_write_at(struct radeon_device *rdev,
363 u32 index, u32 value)
364{
365 if (index == 0)
366 WREG32(CG_AT_0, value);
367 else if (index == 1)
368 WREG32(CG_AT_1, value);
369 else if (index == 2)
370 WREG32(CG_AT_2, value);
371 else if (index == 3)
372 WREG32(CG_AT_3, value);
373 else if (index == 4)
374 WREG32(CG_AT_4, value);
375 else if (index == 5)
376 WREG32(CG_AT_5, value);
377 else if (index == 6)
378 WREG32(CG_AT_6, value);
379 else if (index == 7)
380 WREG32(CG_AT_7, value);
381}
382
34936f55
AD		 383static void sumo_program_at(struct radeon_device *rdev,
384 struct radeon_ps *rps)
80ea2c12
AD		 385{
386 struct sumo_power_info *pi = sumo_get_pi(rdev);
34936f55 387 struct sumo_ps *ps = sumo_get_ps(rps);
80ea2c12
AD		 388 u32 asi;
389 u32 i;
390 u32 m_a;
391 u32 a_t;
392 u32 r[SUMO_MAX_HARDWARE_POWERLEVELS];
393 u32 l[SUMO_MAX_HARDWARE_POWERLEVELS];
394
395 r[0] = SUMO_R_DFLT0;
396 r[1] = SUMO_R_DFLT1;
397 r[2] = SUMO_R_DFLT2;
398 r[3] = SUMO_R_DFLT3;
399 r[4] = SUMO_R_DFLT4;
400
401 l[0] = SUMO_L_DFLT0;
402 l[1] = SUMO_L_DFLT1;
403 l[2] = SUMO_L_DFLT2;
404 l[3] = SUMO_L_DFLT3;
405 l[4] = SUMO_L_DFLT4;
406
407 for (i = 0; i < ps->num_levels; i++) {
408 asi = (i == ps->num_levels - 1) ? pi->pasi : pi->asi;
409
410 m_a = asi * ps->levels[i].sclk / 100;
411
412 a_t = CG_R(m_a * r[i] / 100) | CG_L(m_a * l[i] / 100);
413
414 sumo_write_at(rdev, i, a_t);
415 }
416
417 if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) {
418 asi = pi->pasi;
419
420 m_a = asi * pi->boost_pl.sclk / 100;
421
422 a_t = CG_R(m_a * r[ps->num_levels - 1] / 100) |
423 CG_L(m_a * l[ps->num_levels - 1] / 100);
424
425 sumo_write_at(rdev, BOOST_DPM_LEVEL, a_t);
426 }
427}
428
429static void sumo_program_tp(struct radeon_device *rdev)
430{
431 int i;
432 enum r600_td td = R600_TD_DFLT;
433
434 for (i = 0; i < SUMO_PM_NUMBER_OF_TC; i++) {
435 WREG32_P(CG_FFCT_0 + (i * 4), UTC_0(sumo_utc[i]), ~UTC_0_MASK);
436 WREG32_P(CG_FFCT_0 + (i * 4), DTC_0(sumo_dtc[i]), ~DTC_0_MASK);
437 }
438
439 if (td == R600_TD_AUTO)
440 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
441 else
442 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
443
444 if (td == R600_TD_UP)
445 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
446
447 if (td == R600_TD_DOWN)
448 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
449}
450
d70229f7 451void sumo_program_vc(struct radeon_device *rdev, u32 vrc)
80ea2c12 452{
d70229f7 453 WREG32(CG_FTV, vrc);
80ea2c12
AD		 454}
455
d70229f7 456void sumo_clear_vc(struct radeon_device *rdev)
80ea2c12
AD		 457{
458 WREG32(CG_FTV, 0);
459}
460
d70229f7 461void sumo_program_sstp(struct radeon_device *rdev)
80ea2c12
AD		 462{
463 u32 p, u;
9d45ad5a 464 u32 xclk = radeon_get_xclk(rdev);
80ea2c12
AD		 465
466 r600_calculate_u_and_p(SUMO_SST_DFLT,
467 xclk, 16, &p, &u);
468
469 WREG32(CG_SSP, SSTU(u) | SST(p));
470}
471
472static void sumo_set_divider_value(struct radeon_device *rdev,
473 u32 index, u32 divider)
474{
475 u32 reg_index = index / 4;
476 u32 field_index = index % 4;
477
478 if (field_index == 0)
479 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
480 SCLK_FSTATE_0_DIV(divider), ~SCLK_FSTATE_0_DIV_MASK);
481 else if (field_index == 1)
482 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
483 SCLK_FSTATE_1_DIV(divider), ~SCLK_FSTATE_1_DIV_MASK);
484 else if (field_index == 2)
485 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
486 SCLK_FSTATE_2_DIV(divider), ~SCLK_FSTATE_2_DIV_MASK);
487 else if (field_index == 3)
488 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
489 SCLK_FSTATE_3_DIV(divider), ~SCLK_FSTATE_3_DIV_MASK);
490}
491
492static void sumo_set_ds_dividers(struct radeon_device *rdev,
493 u32 index, u32 divider)
494{
495 struct sumo_power_info *pi = sumo_get_pi(rdev);
496
497 if (pi->enable_sclk_ds) {
498 u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_6);
499
500 dpm_ctrl &= ~(0x7 << (index * 3));
501 dpm_ctrl |= (divider << (index * 3));
502 WREG32(CG_SCLK_DPM_CTRL_6, dpm_ctrl);
503 }
504}
505
506static void sumo_set_ss_dividers(struct radeon_device *rdev,
507 u32 index, u32 divider)
508{
509 struct sumo_power_info *pi = sumo_get_pi(rdev);
510
511 if (pi->enable_sclk_ds) {
512 u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_11);
513
514 dpm_ctrl &= ~(0x7 << (index * 3));
515 dpm_ctrl |= (divider << (index * 3));
516 WREG32(CG_SCLK_DPM_CTRL_11, dpm_ctrl);
517 }
518}
519
520static void sumo_set_vid(struct radeon_device *rdev, u32 index, u32 vid)
521{
522 u32 voltage_cntl = RREG32(CG_DPM_VOLTAGE_CNTL);
523
524 voltage_cntl &= ~(DPM_STATE0_LEVEL_MASK << (index * 2));
525 voltage_cntl |= (vid << (DPM_STATE0_LEVEL_SHIFT + index * 2));
526 WREG32(CG_DPM_VOLTAGE_CNTL, voltage_cntl);
527}
528
529static void sumo_set_allos_gnb_slow(struct radeon_device *rdev, u32 index, u32 gnb_slow)
530{
531 struct sumo_power_info *pi = sumo_get_pi(rdev);
532 u32 temp = gnb_slow;
533 u32 cg_sclk_dpm_ctrl_3;
534
535 if (pi->driver_nbps_policy_disable)
536 temp = 1;
537
538 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);
539 cg_sclk_dpm_ctrl_3 &= ~(GNB_SLOW_FSTATE_0_MASK << index);
540 cg_sclk_dpm_ctrl_3 |= (temp << (GNB_SLOW_FSTATE_0_SHIFT + index));
541
542 WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3);
543}
544
545static void sumo_program_power_level(struct radeon_device *rdev,
546 struct sumo_pl *pl, u32 index)
547{
548 struct sumo_power_info *pi = sumo_get_pi(rdev);
549 int ret;
550 struct atom_clock_dividers dividers;
551 u32 ds_en = RREG32(DEEP_SLEEP_CNTL) & ENABLE_DS;
552
553 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
554 pl->sclk, false, &dividers);
555 if (ret)
556 return;
557
558 sumo_set_divider_value(rdev, index, dividers.post_div);
559
560 sumo_set_vid(rdev, index, pl->vddc_index);
561
562 if (pl->ss_divider_index == 0 || pl->ds_divider_index == 0) {
563 if (ds_en)
564 WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS);
565 } else {
566 sumo_set_ss_dividers(rdev, index, pl->ss_divider_index);
567 sumo_set_ds_dividers(rdev, index, pl->ds_divider_index);
568
569 if (!ds_en)
570 WREG32_P(DEEP_SLEEP_CNTL, ENABLE_DS, ~ENABLE_DS);
571 }
572
573 sumo_set_allos_gnb_slow(rdev, index, pl->allow_gnb_slow);
574
575 if (pi->enable_boost)
576 sumo_set_tdp_limit(rdev, index, pl->sclk_dpm_tdp_limit);
577}
578
579static void sumo_power_level_enable(struct radeon_device *rdev, u32 index, bool enable)
580{
581 u32 reg_index = index / 4;
582 u32 field_index = index % 4;
583
584 if (field_index == 0)
585 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
586 enable ? SCLK_FSTATE_0_VLD : 0, ~SCLK_FSTATE_0_VLD);
587 else if (field_index == 1)
588 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
589 enable ? SCLK_FSTATE_1_VLD : 0, ~SCLK_FSTATE_1_VLD);
590 else if (field_index == 2)
591 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
592 enable ? SCLK_FSTATE_2_VLD : 0, ~SCLK_FSTATE_2_VLD);
593 else if (field_index == 3)
594 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
595 enable ? SCLK_FSTATE_3_VLD : 0, ~SCLK_FSTATE_3_VLD);
596}
597
598static bool sumo_dpm_enabled(struct radeon_device *rdev)
599{
600 if (RREG32(CG_SCLK_DPM_CTRL_3) & DPM_SCLK_ENABLE)
601 return true;
602 else
603 return false;
604}
605
606static void sumo_start_dpm(struct radeon_device *rdev)
607{
608 WREG32_P(CG_SCLK_DPM_CTRL_3, DPM_SCLK_ENABLE, ~DPM_SCLK_ENABLE);
609}
610
611static void sumo_stop_dpm(struct radeon_device *rdev)
612{
613 WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~DPM_SCLK_ENABLE);
614}
615
616static void sumo_set_forced_mode(struct radeon_device *rdev, bool enable)
617{
618 if (enable)
619 WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE_EN, ~FORCE_SCLK_STATE_EN);
620 else
621 WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_SCLK_STATE_EN);
622}
623
624static void sumo_set_forced_mode_enabled(struct radeon_device *rdev)
625{
626 int i;
627
628 sumo_set_forced_mode(rdev, true);
629 for (i = 0; i < rdev->usec_timeout; i++) {
630 if (RREG32(CG_SCLK_STATUS) & SCLK_OVERCLK_DETECT)
631 break;
632 udelay(1);
633 }
634}
635
636static void sumo_wait_for_level_0(struct radeon_device *rdev)
637{
638 int i;
639
640 for (i = 0; i < rdev->usec_timeout; i++) {
641 if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) == 0)
642 break;
643 udelay(1);
644 }
645 for (i = 0; i < rdev->usec_timeout; i++) {
646 if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) == 0)
647 break;
648 udelay(1);
649 }
650}
651
652static void sumo_set_forced_mode_disabled(struct radeon_device *rdev)
653{
654 sumo_set_forced_mode(rdev, false);
655}
656
657static void sumo_enable_power_level_0(struct radeon_device *rdev)
658{
659 sumo_power_level_enable(rdev, 0, true);
660}
661
34936f55
AD		 662static void sumo_patch_boost_state(struct radeon_device *rdev,
663 struct radeon_ps *rps)
80ea2c12
AD		 664{
665 struct sumo_power_info *pi = sumo_get_pi(rdev);
34936f55 666 struct sumo_ps *new_ps = sumo_get_ps(rps);
80ea2c12
AD		 667
668 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) {
669 pi->boost_pl = new_ps->levels[new_ps->num_levels - 1];
670 pi->boost_pl.sclk = pi->sys_info.boost_sclk;
671 pi->boost_pl.vddc_index = pi->sys_info.boost_vid_2bit;
672 pi->boost_pl.sclk_dpm_tdp_limit = pi->sys_info.sclk_dpm_tdp_limit_boost;
673 }
674}
675
34936f55
AD		 676static void sumo_pre_notify_alt_vddnb_change(struct radeon_device *rdev,
677 struct radeon_ps *new_rps,
678 struct radeon_ps *old_rps)
80ea2c12 679{
34936f55
AD		 680 struct sumo_ps *new_ps = sumo_get_ps(new_rps);
681 struct sumo_ps *old_ps = sumo_get_ps(old_rps);
80ea2c12
AD		 682 u32 nbps1_old = 0;
683 u32 nbps1_new = 0;
684
685 if (old_ps != NULL)
686 nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;
687
688 nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;
689
690 if (nbps1_old == 1 && nbps1_new == 0)
691 sumo_smu_notify_alt_vddnb_change(rdev, 0, 0);
692}
693
34936f55
AD		 694static void sumo_post_notify_alt_vddnb_change(struct radeon_device *rdev,
695 struct radeon_ps *new_rps,
696 struct radeon_ps *old_rps)
80ea2c12 697{
34936f55
AD		 698 struct sumo_ps *new_ps = sumo_get_ps(new_rps);
699 struct sumo_ps *old_ps = sumo_get_ps(old_rps);
80ea2c12
AD		 700 u32 nbps1_old = 0;
701 u32 nbps1_new = 0;
702
703 if (old_ps != NULL)
704 nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0;
705
706 nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0;
707
708 if (nbps1_old == 0 && nbps1_new == 1)
709 sumo_smu_notify_alt_vddnb_change(rdev, 1, 1);
710}
711
34936f55
AD		 712static void sumo_enable_boost(struct radeon_device *rdev,
713 struct radeon_ps *rps,
714 bool enable)
80ea2c12 715{
34936f55 716 struct sumo_ps *new_ps = sumo_get_ps(rps);
80ea2c12
AD		 717
718 if (enable) {
719 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
720 sumo_boost_state_enable(rdev, true);
721 } else
722 sumo_boost_state_enable(rdev, false);
723}
724
80ea2c12
AD		 725static void sumo_set_forced_level(struct radeon_device *rdev, u32 index)
726{
727 WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE(index), ~FORCE_SCLK_STATE_MASK);
728}
729
730static void sumo_set_forced_level_0(struct radeon_device *rdev)
731{
732 sumo_set_forced_level(rdev, 0);
733}
734
34936f55
AD		 735static void sumo_program_wl(struct radeon_device *rdev,
736 struct radeon_ps *rps)
80ea2c12 737{
34936f55 738 struct sumo_ps *new_ps = sumo_get_ps(rps);
80ea2c12
AD		 739 u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);
740
741 dpm_ctrl4 &= 0xFFFFFF00;
742 dpm_ctrl4 |= (1 << (new_ps->num_levels - 1));
743
744 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
745 dpm_ctrl4 |= (1 << BOOST_DPM_LEVEL);
746
747 WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4);
748}
749
34936f55
AD		 750static void sumo_program_power_levels_0_to_n(struct radeon_device *rdev,
751 struct radeon_ps *new_rps,
752 struct radeon_ps *old_rps)
80ea2c12
AD		 753{
754 struct sumo_power_info *pi = sumo_get_pi(rdev);
34936f55
AD		 755 struct sumo_ps *new_ps = sumo_get_ps(new_rps);
756 struct sumo_ps *old_ps = sumo_get_ps(old_rps);
80ea2c12
AD		 757 u32 i;
758 u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels;
759
760 for (i = 0; i < new_ps->num_levels; i++) {
761 sumo_program_power_level(rdev, &new_ps->levels[i], i);
762 sumo_power_level_enable(rdev, i, true);
763 }
764
765 for (i = new_ps->num_levels; i < n_current_state_levels; i++)
766 sumo_power_level_enable(rdev, i, false);
767
768 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
769 sumo_program_power_level(rdev, &pi->boost_pl, BOOST_DPM_LEVEL);
770}
771
772static void sumo_enable_acpi_pm(struct radeon_device *rdev)
773{
774 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
775}
776
777static void sumo_program_power_level_enter_state(struct radeon_device *rdev)
778{
779 WREG32_P(CG_SCLK_DPM_CTRL_5, SCLK_FSTATE_BOOTUP(0), ~SCLK_FSTATE_BOOTUP_MASK);
780}
781
782static void sumo_program_acpi_power_level(struct radeon_device *rdev)
783{
784 struct sumo_power_info *pi = sumo_get_pi(rdev);
785 struct atom_clock_dividers dividers;
786 int ret;
787
788 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
789 pi->acpi_pl.sclk,
790 false, &dividers);
791 if (ret)
792 return;
793
794 WREG32_P(CG_ACPI_CNTL, SCLK_ACPI_DIV(dividers.post_div), ~SCLK_ACPI_DIV_MASK);
795 WREG32_P(CG_ACPI_VOLTAGE_CNTL, 0, ~ACPI_VOLTAGE_EN);
796}
797
798static void sumo_program_bootup_state(struct radeon_device *rdev)
799{
800 struct sumo_power_info *pi = sumo_get_pi(rdev);
801 u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);
802 u32 i;
803
804 sumo_program_power_level(rdev, &pi->boot_pl, 0);
805
806 dpm_ctrl4 &= 0xFFFFFF00;
807 WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4);
808
809 for (i = 1; i < 8; i++)
810 sumo_power_level_enable(rdev, i, false);
811}
812
34936f55
AD		 813static void sumo_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
814 struct radeon_ps *new_rps,
815 struct radeon_ps *old_rps)
06793dfb 816{
34936f55
AD		 817 struct sumo_ps *new_ps = sumo_get_ps(new_rps);
818 struct sumo_ps *current_ps = sumo_get_ps(old_rps);
06793dfb 819
34936f55
AD		 820 if ((new_rps->vclk == old_rps->vclk) &&
821 (new_rps->dclk == old_rps->dclk))
06793dfb
AD		 822 return;
823
824 if (new_ps->levels[new_ps->num_levels - 1].sclk >=
825 current_ps->levels[current_ps->num_levels - 1].sclk)
826 return;
827
34936f55 828 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
06793dfb
AD		 829}
830
34936f55
AD		 831static void sumo_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
832 struct radeon_ps *new_rps,
833 struct radeon_ps *old_rps)
06793dfb 834{
34936f55
AD		 835 struct sumo_ps *new_ps = sumo_get_ps(new_rps);
836 struct sumo_ps *current_ps = sumo_get_ps(old_rps);
06793dfb 837
34936f55
AD		 838 if ((new_rps->vclk == old_rps->vclk) &&
839 (new_rps->dclk == old_rps->dclk))
06793dfb
AD		 840 return;
841
842 if (new_ps->levels[new_ps->num_levels - 1].sclk <
843 current_ps->levels[current_ps->num_levels - 1].sclk)
844 return;
845
34936f55 846 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
06793dfb
AD		 847}
848
d70229f7 849void sumo_take_smu_control(struct radeon_device *rdev, bool enable)
80ea2c12 850{
65676d06
AD		 851/* This bit selects who handles display phy powergating.
852 * Clear the bit to let atom handle it.
853 * Set it to let the driver handle it.
854 * For now we just let atom handle it.
855 */
856#if 0
80ea2c12
AD		 857 u32 v = RREG32(DOUT_SCRATCH3);
858
859 if (enable)
860 v |= 0x4;
861 else
862 v &= 0xFFFFFFFB;
863
864 WREG32(DOUT_SCRATCH3, v);
65676d06 865#endif
80ea2c12
AD		 866}
867
868static void sumo_enable_sclk_ds(struct radeon_device *rdev, bool enable)
869{
870 if (enable) {
871 u32 deep_sleep_cntl = RREG32(DEEP_SLEEP_CNTL);
872 u32 deep_sleep_cntl2 = RREG32(DEEP_SLEEP_CNTL2);
873 u32 t = 1;
874
875 deep_sleep_cntl &= ~R_DIS;
876 deep_sleep_cntl &= ~HS_MASK;
877 deep_sleep_cntl |= HS(t > 4095 ? 4095 : t);
878
879 deep_sleep_cntl2 |= LB_UFP_EN;
880 deep_sleep_cntl2 &= INOUT_C_MASK;
881 deep_sleep_cntl2 |= INOUT_C(0xf);
882
883 WREG32(DEEP_SLEEP_CNTL2, deep_sleep_cntl2);
884 WREG32(DEEP_SLEEP_CNTL, deep_sleep_cntl);
885 } else
886 WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS);
887}
888
889static void sumo_program_bootup_at(struct radeon_device *rdev)
890{
891 WREG32_P(CG_AT_0, CG_R(0xffff), ~CG_R_MASK);
892 WREG32_P(CG_AT_0, CG_L(0), ~CG_L_MASK);
893}
894
895static void sumo_reset_am(struct radeon_device *rdev)
896{
897 WREG32_P(SCLK_PWRMGT_CNTL, FIR_RESET, ~FIR_RESET);
898}
899
900static void sumo_start_am(struct radeon_device *rdev)
901{
902 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_RESET);
903}
904
905static void sumo_program_ttp(struct radeon_device *rdev)
906{
9d45ad5a 907 u32 xclk = radeon_get_xclk(rdev);
80ea2c12
AD		 908 u32 p, u;
909 u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5);
910
911 r600_calculate_u_and_p(1000,
912 xclk, 16, &p, &u);
913
914 cg_sclk_dpm_ctrl_5 &= ~(TT_TP_MASK | TT_TU_MASK);
915 cg_sclk_dpm_ctrl_5 |= TT_TP(p) | TT_TU(u);
916
917 WREG32(CG_SCLK_DPM_CTRL_5, cg_sclk_dpm_ctrl_5);
918}
919
920static void sumo_program_ttt(struct radeon_device *rdev)
921{
922 u32 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);
923 struct sumo_power_info *pi = sumo_get_pi(rdev);
924
925 cg_sclk_dpm_ctrl_3 &= ~(GNB_TT_MASK | GNB_THERMTHRO_MASK);
926 cg_sclk_dpm_ctrl_3 |= GNB_TT(pi->thermal_auto_throttling + 49);
927
928 WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3);
929}
930
931
932static void sumo_enable_voltage_scaling(struct radeon_device *rdev, bool enable)
933{
934 if (enable) {
935 WREG32_P(CG_DPM_VOLTAGE_CNTL, DPM_VOLTAGE_EN, ~DPM_VOLTAGE_EN);
936 WREG32_P(CG_CG_VOLTAGE_CNTL, 0, ~CG_VOLTAGE_EN);
937 } else {
938 WREG32_P(CG_CG_VOLTAGE_CNTL, CG_VOLTAGE_EN, ~CG_VOLTAGE_EN);
939 WREG32_P(CG_DPM_VOLTAGE_CNTL, 0, ~DPM_VOLTAGE_EN);
940 }
941}
942
943static void sumo_override_cnb_thermal_events(struct radeon_device *rdev)
944{
945 WREG32_P(CG_SCLK_DPM_CTRL_3, CNB_THERMTHRO_MASK_SCLK,
946 ~CNB_THERMTHRO_MASK_SCLK);
947}
948
949static void sumo_program_dc_hto(struct radeon_device *rdev)
950{
951 u32 cg_sclk_dpm_ctrl_4 = RREG32(CG_SCLK_DPM_CTRL_4);
952 u32 p, u;
9d45ad5a 953 u32 xclk = radeon_get_xclk(rdev);
80ea2c12
AD		 954
955 r600_calculate_u_and_p(100000,
956 xclk, 14, &p, &u);
957
958 cg_sclk_dpm_ctrl_4 &= ~(DC_HDC_MASK | DC_HU_MASK);
959 cg_sclk_dpm_ctrl_4 |= DC_HDC(p) | DC_HU(u);
960
961 WREG32(CG_SCLK_DPM_CTRL_4, cg_sclk_dpm_ctrl_4);
962}
963
34936f55
AD		 964static void sumo_force_nbp_state(struct radeon_device *rdev,
965 struct radeon_ps *rps)
80ea2c12
AD		 966{
967 struct sumo_power_info *pi = sumo_get_pi(rdev);
34936f55 968 struct sumo_ps *new_ps = sumo_get_ps(rps);
80ea2c12
AD		 969
970 if (!pi->driver_nbps_policy_disable) {
971 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)
972 WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_NB_PSTATE_1, ~FORCE_NB_PSTATE_1);
973 else
974 WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_NB_PSTATE_1);
975 }
976}
977
d70229f7 978u32 sumo_get_sleep_divider_from_id(u32 id)
80ea2c12
AD		 979{
980 return 1 << id;
981}
982
d70229f7
AD		 983u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
984 u32 sclk,
985 u32 min_sclk_in_sr)
80ea2c12
AD		 986{
987 struct sumo_power_info *pi = sumo_get_pi(rdev);
988 u32 i;
989 u32 temp;
990 u32 min = (min_sclk_in_sr > SUMO_MINIMUM_ENGINE_CLOCK) ?
991 min_sclk_in_sr : SUMO_MINIMUM_ENGINE_CLOCK;
992
993 if (sclk < min)
994 return 0;
995
996 if (!pi->enable_sclk_ds)
997 return 0;
998
999 for (i = SUMO_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
1000 temp = sclk / sumo_get_sleep_divider_from_id(i);
1001
1002 if (temp >= min || i == 0)
1003 break;
1004 }
1005 return i;
1006}
1007
1008static u32 sumo_get_valid_engine_clock(struct radeon_device *rdev,
1009 u32 lower_limit)
1010{
1011 struct sumo_power_info *pi = sumo_get_pi(rdev);
1012 u32 i;
1013
1014 for (i = 0; i < pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries; i++) {
1015 if (pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency >= lower_limit)
1016 return pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency;
1017 }
1018
1019 return pi->sys_info.sclk_voltage_mapping_table.entries[pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1].sclk_frequency;
1020}
1021
1022static void sumo_patch_thermal_state(struct radeon_device *rdev,
1023 struct sumo_ps *ps,
1024 struct sumo_ps *current_ps)
1025{
1026 struct sumo_power_info *pi = sumo_get_pi(rdev);
1027 u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
1028 u32 current_vddc;
1029 u32 current_sclk;
1030 u32 current_index = 0;
1031
1032 if (current_ps) {
1033 current_vddc = current_ps->levels[current_index].vddc_index;
1034 current_sclk = current_ps->levels[current_index].sclk;
1035 } else {
1036 current_vddc = pi->boot_pl.vddc_index;
1037 current_sclk = pi->boot_pl.sclk;
1038 }
1039
1040 ps->levels[0].vddc_index = current_vddc;
1041
1042 if (ps->levels[0].sclk > current_sclk)
1043 ps->levels[0].sclk = current_sclk;
1044
1045 ps->levels[0].ss_divider_index =
1046 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, sclk_in_sr);
1047
1048 ps->levels[0].ds_divider_index =
1049 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, SUMO_MINIMUM_ENGINE_CLOCK);
1050
1051 if (ps->levels[0].ds_divider_index > ps->levels[0].ss_divider_index + 1)
1052 ps->levels[0].ds_divider_index = ps->levels[0].ss_divider_index + 1;
1053
1054 if (ps->levels[0].ss_divider_index == ps->levels[0].ds_divider_index) {
1055 if (ps->levels[0].ss_divider_index > 1)
1056 ps->levels[0].ss_divider_index = ps->levels[0].ss_divider_index - 1;
1057 }
1058
1059 if (ps->levels[0].ss_divider_index == 0)
1060 ps->levels[0].ds_divider_index = 0;
1061
1062 if (ps->levels[0].ds_divider_index == 0)
1063 ps->levels[0].ss_divider_index = 0;
1064}
1065
34936f55
AD		 1066static void sumo_apply_state_adjust_rules(struct radeon_device *rdev,
1067 struct radeon_ps *new_rps,
1068 struct radeon_ps *old_rps)
80ea2c12 1069{
34936f55
AD		 1070 struct sumo_ps *ps = sumo_get_ps(new_rps);
1071 struct sumo_ps *current_ps = sumo_get_ps(old_rps);
80ea2c12
AD		 1072 struct sumo_power_info *pi = sumo_get_pi(rdev);
1073 u32 min_voltage = 0; /* ??? */
1074 u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */
1075 u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
1076 u32 i;
1077
34936f55 1078 if (new_rps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
80ea2c12
AD		 1079 return sumo_patch_thermal_state(rdev, ps, current_ps);
1080
1081 if (pi->enable_boost) {
34936f55 1082 if (new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE)
80ea2c12
AD		 1083 ps->flags |= SUMO_POWERSTATE_FLAGS_BOOST_STATE;
1084 }
1085
34936f55
AD		 1086 if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) ||
1087 (new_rps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) ||
1088 (new_rps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE))
80ea2c12
AD		 1089 ps->flags |= SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE;
1090
1091 for (i = 0; i < ps->num_levels; i++) {
1092 if (ps->levels[i].vddc_index < min_voltage)
1093 ps->levels[i].vddc_index = min_voltage;
1094
1095 if (ps->levels[i].sclk < min_sclk)
1096 ps->levels[i].sclk =
1097 sumo_get_valid_engine_clock(rdev, min_sclk);
1098
1099 ps->levels[i].ss_divider_index =
1100 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, sclk_in_sr);
1101
1102 ps->levels[i].ds_divider_index =
1103 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, SUMO_MINIMUM_ENGINE_CLOCK);
1104
1105 if (ps->levels[i].ds_divider_index > ps->levels[i].ss_divider_index + 1)
1106 ps->levels[i].ds_divider_index = ps->levels[i].ss_divider_index + 1;
1107
1108 if (ps->levels[i].ss_divider_index == ps->levels[i].ds_divider_index) {
1109 if (ps->levels[i].ss_divider_index > 1)
1110 ps->levels[i].ss_divider_index = ps->levels[i].ss_divider_index - 1;
1111 }
1112
1113 if (ps->levels[i].ss_divider_index == 0)
1114 ps->levels[i].ds_divider_index = 0;
1115
1116 if (ps->levels[i].ds_divider_index == 0)
1117 ps->levels[i].ss_divider_index = 0;
1118
1119 if (ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)
1120 ps->levels[i].allow_gnb_slow = 1;
34936f55
AD		 1121 else if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) ||
1122 (new_rps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC))
80ea2c12
AD		 1123 ps->levels[i].allow_gnb_slow = 0;
1124 else if (i == ps->num_levels - 1)
1125 ps->levels[i].allow_gnb_slow = 0;
1126 else
1127 ps->levels[i].allow_gnb_slow = 1;
1128 }
1129}
1130
1131static void sumo_cleanup_asic(struct radeon_device *rdev)
1132{
1133 sumo_take_smu_control(rdev, false);
1134}
1135
06793dfb
AD		 1136static void sumo_uvd_init(struct radeon_device *rdev)
1137{
1138 u32 tmp;
1139
1140 tmp = RREG32(CG_VCLK_CNTL);
1141 tmp &= ~VCLK_DIR_CNTL_EN;
1142 WREG32(CG_VCLK_CNTL, tmp);
1143
1144 tmp = RREG32(CG_DCLK_CNTL);
1145 tmp &= ~DCLK_DIR_CNTL_EN;
1146 WREG32(CG_DCLK_CNTL, tmp);
1147
1148 /* 100 Mhz */
1149 radeon_set_uvd_clocks(rdev, 10000, 10000);
1150}
1151
80ea2c12
AD		 1152static int sumo_set_thermal_temperature_range(struct radeon_device *rdev,
1153 int min_temp, int max_temp)
1154{
1155 int low_temp = 0 * 1000;
1156 int high_temp = 255 * 1000;
1157
1158 if (low_temp < min_temp)
1159 low_temp = min_temp;
1160 if (high_temp > max_temp)
1161 high_temp = max_temp;
1162 if (high_temp < low_temp) {
1163 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
1164 return -EINVAL;
1165 }
1166
1167 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(49 + (high_temp / 1000)), ~DIG_THERM_INTH_MASK);
1168 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(49 + (low_temp / 1000)), ~DIG_THERM_INTL_MASK);
1169
1170 rdev->pm.dpm.thermal.min_temp = low_temp;
1171 rdev->pm.dpm.thermal.max_temp = high_temp;
1172
1173 return 0;
1174}
1175
422a56bc
AD		 1176static void sumo_update_current_ps(struct radeon_device *rdev,
1177 struct radeon_ps *rps)
1178{
1179 struct sumo_ps *new_ps = sumo_get_ps(rps);
1180 struct sumo_power_info *pi = sumo_get_pi(rdev);
1181
1182 pi->current_rps = *rps;
1183 pi->current_ps = *new_ps;
1184 pi->current_rps.ps_priv = &pi->current_ps;
1185}
1186
1187static void sumo_update_requested_ps(struct radeon_device *rdev,
1188 struct radeon_ps *rps)
1189{
1190 struct sumo_ps *new_ps = sumo_get_ps(rps);
1191 struct sumo_power_info *pi = sumo_get_pi(rdev);
1192
1193 pi->requested_rps = *rps;
1194 pi->requested_ps = *new_ps;
1195 pi->requested_rps.ps_priv = &pi->requested_ps;
1196}
1197
80ea2c12
AD		 1198int sumo_dpm_enable(struct radeon_device *rdev)
1199{
1200 struct sumo_power_info *pi = sumo_get_pi(rdev);
1201
1202 if (sumo_dpm_enabled(rdev))
1203 return -EINVAL;
1204
1205 sumo_enable_clock_power_gating(rdev);
1206 sumo_program_bootup_state(rdev);
1207 sumo_init_bsp(rdev);
1208 sumo_reset_am(rdev);
1209 sumo_program_tp(rdev);
1210 sumo_program_bootup_at(rdev);
1211 sumo_start_am(rdev);
1212 if (pi->enable_auto_thermal_throttling) {
1213 sumo_program_ttp(rdev);
1214 sumo_program_ttt(rdev);
1215 }
1216 sumo_program_dc_hto(rdev);
1217 sumo_program_power_level_enter_state(rdev);
1218 sumo_enable_voltage_scaling(rdev, true);
1219 sumo_program_sstp(rdev);
d70229f7 1220 sumo_program_vc(rdev, SUMO_VRC_DFLT);
80ea2c12
AD		 1221 sumo_override_cnb_thermal_events(rdev);
1222 sumo_start_dpm(rdev);
1223 sumo_wait_for_level_0(rdev);
1224 if (pi->enable_sclk_ds)
1225 sumo_enable_sclk_ds(rdev, true);
1226 if (pi->enable_boost)
1227 sumo_enable_boost_timer(rdev);
1228
1229 if (rdev->irq.installed &&
1230 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1231 sumo_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1232 rdev->irq.dpm_thermal = true;
1233 radeon_irq_set(rdev);
1234 }
1235
422a56bc
AD		 1236 sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1237
80ea2c12
AD		 1238 return 0;
1239}
1240
1241void sumo_dpm_disable(struct radeon_device *rdev)
1242{
1243 struct sumo_power_info *pi = sumo_get_pi(rdev);
1244
1245 if (!sumo_dpm_enabled(rdev))
1246 return;
1247 sumo_disable_clock_power_gating(rdev);
1248 if (pi->enable_sclk_ds)
1249 sumo_enable_sclk_ds(rdev, false);
1250 sumo_clear_vc(rdev);
1251 sumo_wait_for_level_0(rdev);
1252 sumo_stop_dpm(rdev);
1253 sumo_enable_voltage_scaling(rdev, false);
1254
1255 if (rdev->irq.installed &&
1256 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1257 rdev->irq.dpm_thermal = false;
1258 radeon_irq_set(rdev);
1259 }
422a56bc
AD		 1260
1261 sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
80ea2c12
AD		 1262}
1263
422a56bc 1264int sumo_dpm_pre_set_power_state(struct radeon_device *rdev)
80ea2c12
AD		 1265{
1266 struct sumo_power_info *pi = sumo_get_pi(rdev);
422a56bc
AD		 1267 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
1268 struct radeon_ps *new_ps = &requested_ps;
1269
1270 sumo_update_requested_ps(rdev, new_ps);
80ea2c12
AD		 1271
1272 if (pi->enable_dynamic_patch_ps)
422a56bc
AD		 1273 sumo_apply_state_adjust_rules(rdev,
1274 &pi->requested_rps,
1275 &pi->current_rps);
1276
1277 return 0;
1278}
1279
1280int sumo_dpm_set_power_state(struct radeon_device *rdev)
1281{
1282 struct sumo_power_info *pi = sumo_get_pi(rdev);
1283 struct radeon_ps *new_ps = &pi->requested_rps;
1284 struct radeon_ps *old_ps = &pi->current_rps;
1285
06793dfb 1286 if (pi->enable_dpm)
34936f55 1287 sumo_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
80ea2c12 1288 if (pi->enable_boost) {
34936f55
AD		 1289 sumo_enable_boost(rdev, new_ps, false);
1290 sumo_patch_boost_state(rdev, new_ps);
80ea2c12
AD		 1291 }
1292 if (pi->enable_dpm) {
34936f55 1293 sumo_pre_notify_alt_vddnb_change(rdev, new_ps, old_ps);
80ea2c12
AD		 1294 sumo_enable_power_level_0(rdev);
1295 sumo_set_forced_level_0(rdev);
1296 sumo_set_forced_mode_enabled(rdev);
1297 sumo_wait_for_level_0(rdev);
34936f55
AD		 1298 sumo_program_power_levels_0_to_n(rdev, new_ps, old_ps);
1299 sumo_program_wl(rdev, new_ps);
1300 sumo_program_bsp(rdev, new_ps);
1301 sumo_program_at(rdev, new_ps);
1302 sumo_force_nbp_state(rdev, new_ps);
80ea2c12
AD		 1303 sumo_set_forced_mode_disabled(rdev);
1304 sumo_set_forced_mode_enabled(rdev);
1305 sumo_set_forced_mode_disabled(rdev);
34936f55 1306 sumo_post_notify_alt_vddnb_change(rdev, new_ps, old_ps);
80ea2c12
AD		 1307 }
1308 if (pi->enable_boost)
34936f55 1309 sumo_enable_boost(rdev, new_ps, true);
06793dfb 1310 if (pi->enable_dpm)
34936f55 1311 sumo_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
80ea2c12
AD		 1312
1313 return 0;
1314}
1315
422a56bc
AD		 1316void sumo_dpm_post_set_power_state(struct radeon_device *rdev)
1317{
1318 struct sumo_power_info *pi = sumo_get_pi(rdev);
1319 struct radeon_ps *new_ps = &pi->requested_rps;
1320
1321 sumo_update_current_ps(rdev, new_ps);
1322}
1323
80ea2c12
AD		 1324void sumo_dpm_reset_asic(struct radeon_device *rdev)
1325{
1326 sumo_program_bootup_state(rdev);
1327 sumo_enable_power_level_0(rdev);
1328 sumo_set_forced_level_0(rdev);
1329 sumo_set_forced_mode_enabled(rdev);
1330 sumo_wait_for_level_0(rdev);
1331 sumo_set_forced_mode_disabled(rdev);
1332 sumo_set_forced_mode_enabled(rdev);
1333 sumo_set_forced_mode_disabled(rdev);
1334}
1335
1336void sumo_dpm_setup_asic(struct radeon_device *rdev)
1337{
1338 struct sumo_power_info *pi = sumo_get_pi(rdev);
1339
1340 sumo_initialize_m3_arb(rdev);
1341 pi->fw_version = sumo_get_running_fw_version(rdev);
1342 DRM_INFO("Found smc ucode version: 0x%08x\n", pi->fw_version);
1343 sumo_program_acpi_power_level(rdev);
1344 sumo_enable_acpi_pm(rdev);
1345 sumo_take_smu_control(rdev, true);
06793dfb 1346 sumo_uvd_init(rdev);
80ea2c12
AD		 1347}
1348
1349void sumo_dpm_display_configuration_changed(struct radeon_device *rdev)
1350{
1351
1352}
1353
1354union power_info {
1355 struct _ATOM_POWERPLAY_INFO info;
1356 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1357 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1358 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1359 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1360 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1361};
1362
1363union pplib_clock_info {
1364 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1365 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1366 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1367 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1368};
1369
1370union pplib_power_state {
1371 struct _ATOM_PPLIB_STATE v1;
1372 struct _ATOM_PPLIB_STATE_V2 v2;
1373};
1374
1375static void sumo_patch_boot_state(struct radeon_device *rdev,
1376 struct sumo_ps *ps)
1377{
1378 struct sumo_power_info *pi = sumo_get_pi(rdev);
1379
1380 ps->num_levels = 1;
1381 ps->flags = 0;
1382 ps->levels[0] = pi->boot_pl;
1383}
1384
1385static void sumo_parse_pplib_non_clock_info(struct radeon_device *rdev,
1386 struct radeon_ps *rps,
1387 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
1388 u8 table_rev)
1389{
1390 struct sumo_ps *ps = sumo_get_ps(rps);
1391
1392 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1393 rps->class = le16_to_cpu(non_clock_info->usClassification);
1394 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
1395
1396 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
1397 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
1398 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
1399 } else {
1400 rps->vclk = 0;
1401 rps->dclk = 0;
1402 }
1403
1404 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1405 rdev->pm.dpm.boot_ps = rps;
1406 sumo_patch_boot_state(rdev, ps);
1407 }
1408 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
1409 rdev->pm.dpm.uvd_ps = rps;
1410}
1411
1412static void sumo_parse_pplib_clock_info(struct radeon_device *rdev,
1413 struct radeon_ps *rps, int index,
1414 union pplib_clock_info *clock_info)
1415{
1416 struct sumo_power_info *pi = sumo_get_pi(rdev);
1417 struct sumo_ps *ps = sumo_get_ps(rps);
1418 struct sumo_pl *pl = &ps->levels[index];
1419 u32 sclk;
1420
1421 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
1422 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
1423 pl->sclk = sclk;
1424 pl->vddc_index = clock_info->sumo.vddcIndex;
1425 pl->sclk_dpm_tdp_limit = clock_info->sumo.tdpLimit;
1426
1427 ps->num_levels = index + 1;
1428
1429 if (pi->enable_sclk_ds) {
1430 pl->ds_divider_index = 5;
1431 pl->ss_divider_index = 4;
1432 }
1433}
1434
1435static int sumo_parse_power_table(struct radeon_device *rdev)
1436{
1437 struct radeon_mode_info *mode_info = &rdev->mode_info;
1438 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1439 union pplib_power_state *power_state;
1440 int i, j, k, non_clock_array_index, clock_array_index;
1441 union pplib_clock_info *clock_info;
1442 struct _StateArray *state_array;
1443 struct _ClockInfoArray *clock_info_array;
1444 struct _NonClockInfoArray *non_clock_info_array;
1445 union power_info *power_info;
1446 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1447 u16 data_offset;
1448 u8 frev, crev;
1449 u8 *power_state_offset;
1450 struct sumo_ps *ps;
1451
1452 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1453 &frev, &crev, &data_offset))
1454 return -EINVAL;
1455 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1456
1457 state_array = (struct _StateArray *)
1458 (mode_info->atom_context->bios + data_offset +
1459 le16_to_cpu(power_info->pplib.usStateArrayOffset));
1460 clock_info_array = (struct _ClockInfoArray *)
1461 (mode_info->atom_context->bios + data_offset +
1462 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
1463 non_clock_info_array = (struct _NonClockInfoArray *)
1464 (mode_info->atom_context->bios + data_offset +
1465 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
1466
1467 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
1468 state_array->ucNumEntries, GFP_KERNEL);
1469 if (!rdev->pm.dpm.ps)
1470 return -ENOMEM;
1471 power_state_offset = (u8 *)state_array->states;
1472 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
1473 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
1474 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
1475 for (i = 0; i < state_array->ucNumEntries; i++) {
1476 power_state = (union pplib_power_state *)power_state_offset;
1477 non_clock_array_index = power_state->v2.nonClockInfoIndex;
1478 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1479 &non_clock_info_array->nonClockInfo[non_clock_array_index];
1480 if (!rdev->pm.power_state[i].clock_info)
1481 return -EINVAL;
1482 ps = kzalloc(sizeof(struct sumo_ps), GFP_KERNEL);
1483 if (ps == NULL) {
1484 kfree(rdev->pm.dpm.ps);
1485 return -ENOMEM;
1486 }
1487 rdev->pm.dpm.ps[i].ps_priv = ps;
1488 k = 0;
1489 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
1490 clock_array_index = power_state->v2.clockInfoIndex[j];
1491 if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
1492 break;
1493 clock_info = (union pplib_clock_info *)
1494 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
1495 sumo_parse_pplib_clock_info(rdev,
1496 &rdev->pm.dpm.ps[i], k,
1497 clock_info);
1498 k++;
1499 }
1500 sumo_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
1501 non_clock_info,
1502 non_clock_info_array->ucEntrySize);
1503 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
1504 }
1505 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
1506 return 0;
1507}
1508
d70229f7
AD		 1509u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev,
1510 struct sumo_vid_mapping_table *vid_mapping_table,
1511 u32 vid_2bit)
80ea2c12 1512{
80ea2c12
AD		 1513 u32 i;
1514
d70229f7
AD		 1515 for (i = 0; i < vid_mapping_table->num_entries; i++) {
1516 if (vid_mapping_table->entries[i].vid_2bit == vid_2bit)
1517 return vid_mapping_table->entries[i].vid_7bit;
80ea2c12
AD		 1518 }
1519
d70229f7 1520 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit;
80ea2c12
AD		 1521}
1522
1523static u16 sumo_convert_voltage_index_to_value(struct radeon_device *rdev,
1524 u32 vid_2bit)
1525{
d70229f7
AD		 1526 struct sumo_power_info *pi = sumo_get_pi(rdev);
1527 u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid_2bit);
80ea2c12
AD		 1528
1529 if (vid_7bit > 0x7C)
1530 return 0;
1531
1532 return (15500 - vid_7bit * 125 + 5) / 10;
1533}
1534
1535static void sumo_construct_display_voltage_mapping_table(struct radeon_device *rdev,
d70229f7 1536 struct sumo_disp_clock_voltage_mapping_table *disp_clk_voltage_mapping_table,
80ea2c12
AD		 1537 ATOM_CLK_VOLT_CAPABILITY *table)
1538{
80ea2c12
AD		 1539 u32 i;
1540
1541 for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
1542 if (table[i].ulMaximumSupportedCLK == 0)
1543 break;
1544
d70229f7 1545 disp_clk_voltage_mapping_table->display_clock_frequency[i] =
80ea2c12
AD		 1546 table[i].ulMaximumSupportedCLK;
1547 }
1548
d70229f7 1549 disp_clk_voltage_mapping_table->num_max_voltage_levels = i;
80ea2c12 1550
d70229f7
AD		 1551 if (disp_clk_voltage_mapping_table->num_max_voltage_levels == 0) {
1552 disp_clk_voltage_mapping_table->display_clock_frequency[0] = 80000;
1553 disp_clk_voltage_mapping_table->num_max_voltage_levels = 1;
80ea2c12
AD		 1554 }
1555}
1556
d70229f7
AD		 1557void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev,
1558 struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table,
1559 ATOM_AVAILABLE_SCLK_LIST *table)
80ea2c12 1560{
80ea2c12
AD		 1561 u32 i;
1562 u32 n = 0;
1563 u32 prev_sclk = 0;
1564
1565 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
1566 if (table[i].ulSupportedSCLK > prev_sclk) {
d70229f7 1567 sclk_voltage_mapping_table->entries[n].sclk_frequency =
80ea2c12 1568 table[i].ulSupportedSCLK;
d70229f7 1569 sclk_voltage_mapping_table->entries[n].vid_2bit =
80ea2c12
AD		 1570 table[i].usVoltageIndex;
1571 prev_sclk = table[i].ulSupportedSCLK;
1572 n++;
1573 }
1574 }
1575
d70229f7 1576 sclk_voltage_mapping_table->num_max_dpm_entries = n;
80ea2c12
AD		 1577}
1578
d70229f7
AD		 1579void sumo_construct_vid_mapping_table(struct radeon_device *rdev,
1580 struct sumo_vid_mapping_table *vid_mapping_table,
1581 ATOM_AVAILABLE_SCLK_LIST *table)
80ea2c12 1582{
80ea2c12
AD		 1583 u32 i, j;
1584
1585 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
1586 if (table[i].ulSupportedSCLK != 0) {
d70229f7 1587 vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit =
80ea2c12 1588 table[i].usVoltageID;
d70229f7 1589 vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit =
80ea2c12
AD		 1590 table[i].usVoltageIndex;
1591 }
1592 }
1593
1594 for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
d70229f7 1595 if (vid_mapping_table->entries[i].vid_7bit == 0) {
80ea2c12 1596 for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) {
d70229f7
AD		 1597 if (vid_mapping_table->entries[j].vid_7bit != 0) {
1598 vid_mapping_table->entries[i] =
1599 vid_mapping_table->entries[j];
1600 vid_mapping_table->entries[j].vid_7bit = 0;
80ea2c12
AD		 1601 break;
1602 }
1603 }
1604
1605 if (j == SUMO_MAX_NUMBER_VOLTAGES)
1606 break;
1607 }
1608 }
1609
d70229f7 1610 vid_mapping_table->num_entries = i;
80ea2c12
AD		 1611}
1612
1613union igp_info {
1614 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1615 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1616 struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5;
1617 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1618};
1619
1620static int sumo_parse_sys_info_table(struct radeon_device *rdev)
1621{
1622 struct sumo_power_info *pi = sumo_get_pi(rdev);
1623 struct radeon_mode_info *mode_info = &rdev->mode_info;
1624 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1625 union igp_info *igp_info;
1626 u8 frev, crev;
1627 u16 data_offset;
1628 int i;
1629
1630 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1631 &frev, &crev, &data_offset)) {
1632 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1633 data_offset);
1634
1635 if (crev != 6) {
1636 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1637 return -EINVAL;
1638 }
1639 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_6.ulBootUpEngineClock);
1640 pi->sys_info.min_sclk = le32_to_cpu(igp_info->info_6.ulMinEngineClock);
1641 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_6.ulBootUpUMAClock);
1642 pi->sys_info.bootup_nb_voltage_index =
1643 le16_to_cpu(igp_info->info_6.usBootUpNBVoltage);
1644 if (igp_info->info_6.ucHtcTmpLmt == 0)
1645 pi->sys_info.htc_tmp_lmt = 203;
1646 else
1647 pi->sys_info.htc_tmp_lmt = igp_info->info_6.ucHtcTmpLmt;
1648 if (igp_info->info_6.ucHtcHystLmt == 0)
1649 pi->sys_info.htc_hyst_lmt = 5;
1650 else
1651 pi->sys_info.htc_hyst_lmt = igp_info->info_6.ucHtcHystLmt;
1652 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
1653 DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
1654 }
1655 for (i = 0; i < NUMBER_OF_M3ARB_PARAM_SETS; i++) {
1656 pi->sys_info.csr_m3_arb_cntl_default[i] =
1657 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_DEFAULT[i]);
1658 pi->sys_info.csr_m3_arb_cntl_uvd[i] =
1659 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_UVD[i]);
1660 pi->sys_info.csr_m3_arb_cntl_fs3d[i] =
1661 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_FS3D[i]);
1662 }
1663 pi->sys_info.sclk_dpm_boost_margin =
1664 le32_to_cpu(igp_info->info_6.SclkDpmBoostMargin);
1665 pi->sys_info.sclk_dpm_throttle_margin =
1666 le32_to_cpu(igp_info->info_6.SclkDpmThrottleMargin);
1667 pi->sys_info.sclk_dpm_tdp_limit_pg =
1668 le16_to_cpu(igp_info->info_6.SclkDpmTdpLimitPG);
1669 pi->sys_info.gnb_tdp_limit = le16_to_cpu(igp_info->info_6.GnbTdpLimit);
1670 pi->sys_info.sclk_dpm_tdp_limit_boost =
1671 le16_to_cpu(igp_info->info_6.SclkDpmTdpLimitBoost);
1672 pi->sys_info.boost_sclk = le32_to_cpu(igp_info->info_6.ulBoostEngineCLock);
1673 pi->sys_info.boost_vid_2bit = igp_info->info_6.ulBoostVid_2bit;
1674 if (igp_info->info_6.EnableBoost)
1675 pi->sys_info.enable_boost = true;
1676 else
1677 pi->sys_info.enable_boost = false;
1678 sumo_construct_display_voltage_mapping_table(rdev,
d70229f7 1679 &pi->sys_info.disp_clk_voltage_mapping_table,
80ea2c12
AD		 1680 igp_info->info_6.sDISPCLK_Voltage);
1681 sumo_construct_sclk_voltage_mapping_table(rdev,
d70229f7 1682 &pi->sys_info.sclk_voltage_mapping_table,
80ea2c12 1683 igp_info->info_6.sAvail_SCLK);
d70229f7
AD		 1684 sumo_construct_vid_mapping_table(rdev, &pi->sys_info.vid_mapping_table,
1685 igp_info->info_6.sAvail_SCLK);
80ea2c12
AD		 1686
1687 }
1688 return 0;
1689}
1690
1691static void sumo_construct_boot_and_acpi_state(struct radeon_device *rdev)
1692{
1693 struct sumo_power_info *pi = sumo_get_pi(rdev);
1694
1695 pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
1696 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
1697 pi->boot_pl.ds_divider_index = 0;
1698 pi->boot_pl.ss_divider_index = 0;
1699 pi->boot_pl.allow_gnb_slow = 1;
1700 pi->acpi_pl = pi->boot_pl;
1701 pi->current_ps.num_levels = 1;
1702 pi->current_ps.levels[0] = pi->boot_pl;
1703}
1704
1705int sumo_dpm_init(struct radeon_device *rdev)
1706{
1707 struct sumo_power_info *pi;
1708 u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT;
1709 int ret;
1710
1711 pi = kzalloc(sizeof(struct sumo_power_info), GFP_KERNEL);
1712 if (pi == NULL)
1713 return -ENOMEM;
1714 rdev->pm.dpm.priv = pi;
1715
1716 pi->driver_nbps_policy_disable = false;
1717 if ((rdev->family == CHIP_PALM) && (hw_rev < 3))
1718 pi->disable_gfx_power_gating_in_uvd = true;
1719 else
1720 pi->disable_gfx_power_gating_in_uvd = false;
1721 pi->enable_alt_vddnb = true;
1722 pi->enable_sclk_ds = true;
1723 pi->enable_dynamic_m3_arbiter = false;
1724 pi->enable_dynamic_patch_ps = true;
1725 pi->enable_gfx_power_gating = true;
1726 pi->enable_gfx_clock_gating = true;
1727 pi->enable_mg_clock_gating = true;
1728 pi->enable_auto_thermal_throttling = true;
1729
1730 ret = sumo_parse_sys_info_table(rdev);
1731 if (ret)
1732 return ret;
1733
1734 sumo_construct_boot_and_acpi_state(rdev);
1735
1736 ret = sumo_parse_power_table(rdev);
1737 if (ret)
1738 return ret;
1739
1740 pi->pasi = CYPRESS_HASI_DFLT;
1741 pi->asi = RV770_ASI_DFLT;
1742 pi->thermal_auto_throttling = pi->sys_info.htc_tmp_lmt;
1743 pi->enable_boost = pi->sys_info.enable_boost;
1744 pi->enable_dpm = true;
1745
1746 return 0;
1747}
1748
1749void sumo_dpm_print_power_state(struct radeon_device *rdev,
1750 struct radeon_ps *rps)
1751{
1752 int i;
1753 struct sumo_ps *ps = sumo_get_ps(rps);
1754
1755 r600_dpm_print_class_info(rps->class, rps->class2);
1756 r600_dpm_print_cap_info(rps->caps);
1757 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1758 for (i = 0; i < ps->num_levels; i++) {
1759 struct sumo_pl *pl = &ps->levels[i];
1760 printk("\t\tpower level %d sclk: %u vddc: %u\n",
1761 i, pl->sclk,
1762 sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1763 }
1764 r600_dpm_print_ps_status(rdev, rps);
1765}
1766
1767void sumo_dpm_fini(struct radeon_device *rdev)
1768{
1769 int i;
1770
1771 sumo_cleanup_asic(rdev); /* ??? */
1772
1773 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1774 kfree(rdev->pm.dpm.ps[i].ps_priv);
1775 }
1776 kfree(rdev->pm.dpm.ps);
1777 kfree(rdev->pm.dpm.priv);
1778}
1779
1780u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low)
1781{
422a56bc
AD		 1782 struct sumo_power_info *pi = sumo_get_pi(rdev);
1783 struct sumo_ps *requested_state = sumo_get_ps(&pi->requested_rps);
80ea2c12
AD		 1784
1785 if (low)
1786 return requested_state->levels[0].sclk;
1787 else
1788 return requested_state->levels[requested_state->num_levels - 1].sclk;
1789}
1790
1791u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low)
1792{
1793 struct sumo_power_info *pi = sumo_get_pi(rdev);
1794
1795 return pi->sys_info.bootup_uma_clk;
1796}
Linux 6.x block layer and io_uring tree(s)