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80ea2c12 AD |
1 | /* |
2 | * Copyright 2012 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | ||
24 | #include "drmP.h" | |
25 | #include "radeon.h" | |
26 | #include "sumod.h" | |
27 | #include "r600_dpm.h" | |
28 | #include "cypress_dpm.h" | |
29 | #include "sumo_dpm.h" | |
30 | #include "atom.h" | |
31 | ||
32 | #define SUMO_MAX_DEEPSLEEP_DIVIDER_ID 5 | |
33 | #define SUMO_MINIMUM_ENGINE_CLOCK 800 | |
34 | #define BOOST_DPM_LEVEL 7 | |
35 | ||
36 | static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] = | |
37 | { | |
38 | SUMO_UTC_DFLT_00, | |
39 | SUMO_UTC_DFLT_01, | |
40 | SUMO_UTC_DFLT_02, | |
41 | SUMO_UTC_DFLT_03, | |
42 | SUMO_UTC_DFLT_04, | |
43 | SUMO_UTC_DFLT_05, | |
44 | SUMO_UTC_DFLT_06, | |
45 | SUMO_UTC_DFLT_07, | |
46 | SUMO_UTC_DFLT_08, | |
47 | SUMO_UTC_DFLT_09, | |
48 | SUMO_UTC_DFLT_10, | |
49 | SUMO_UTC_DFLT_11, | |
50 | SUMO_UTC_DFLT_12, | |
51 | SUMO_UTC_DFLT_13, | |
52 | SUMO_UTC_DFLT_14, | |
53 | }; | |
54 | ||
55 | static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] = | |
56 | { | |
57 | SUMO_DTC_DFLT_00, | |
58 | SUMO_DTC_DFLT_01, | |
59 | SUMO_DTC_DFLT_02, | |
60 | SUMO_DTC_DFLT_03, | |
61 | SUMO_DTC_DFLT_04, | |
62 | SUMO_DTC_DFLT_05, | |
63 | SUMO_DTC_DFLT_06, | |
64 | SUMO_DTC_DFLT_07, | |
65 | SUMO_DTC_DFLT_08, | |
66 | SUMO_DTC_DFLT_09, | |
67 | SUMO_DTC_DFLT_10, | |
68 | SUMO_DTC_DFLT_11, | |
69 | SUMO_DTC_DFLT_12, | |
70 | SUMO_DTC_DFLT_13, | |
71 | SUMO_DTC_DFLT_14, | |
72 | }; | |
73 | ||
74 | struct sumo_ps *sumo_get_ps(struct radeon_ps *rps) | |
75 | { | |
76 | struct sumo_ps *ps = rps->ps_priv; | |
77 | ||
78 | return ps; | |
79 | } | |
80 | ||
81 | struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev) | |
82 | { | |
83 | struct sumo_power_info *pi = rdev->pm.dpm.priv; | |
84 | ||
85 | return pi; | |
86 | } | |
87 | ||
88 | u32 sumo_get_xclk(struct radeon_device *rdev) | |
89 | { | |
90 | return rdev->clock.spll.reference_freq; | |
91 | } | |
92 | ||
93 | static void sumo_gfx_clockgating_enable(struct radeon_device *rdev, bool enable) | |
94 | { | |
95 | if (enable) | |
96 | WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); | |
97 | else { | |
98 | WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); | |
99 | WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); | |
100 | WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); | |
101 | RREG32(GB_ADDR_CONFIG); | |
102 | } | |
103 | } | |
104 | ||
105 | #define CGCG_CGTT_LOCAL0_MASK 0xE5BFFFFF | |
106 | #define CGCG_CGTT_LOCAL1_MASK 0xEFFF07FF | |
107 | ||
108 | static void sumo_mg_clockgating_enable(struct radeon_device *rdev, bool enable) | |
109 | { | |
110 | u32 local0; | |
111 | u32 local1; | |
112 | ||
113 | local0 = RREG32(CG_CGTT_LOCAL_0); | |
114 | local1 = RREG32(CG_CGTT_LOCAL_1); | |
115 | ||
116 | if (enable) { | |
117 | WREG32(CG_CGTT_LOCAL_0, (0 & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) ); | |
118 | WREG32(CG_CGTT_LOCAL_1, (0 & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) ); | |
119 | } else { | |
120 | WREG32(CG_CGTT_LOCAL_0, (0xFFFFFFFF & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) ); | |
121 | WREG32(CG_CGTT_LOCAL_1, (0xFFFFCFFF & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) ); | |
122 | } | |
123 | } | |
124 | ||
125 | static void sumo_program_git(struct radeon_device *rdev) | |
126 | { | |
127 | u32 p, u; | |
128 | u32 xclk = sumo_get_xclk(rdev); | |
129 | ||
130 | r600_calculate_u_and_p(SUMO_GICST_DFLT, | |
131 | xclk, 16, &p, &u); | |
132 | ||
133 | WREG32_P(CG_GIT, CG_GICST(p), ~CG_GICST_MASK); | |
134 | } | |
135 | ||
136 | static void sumo_program_grsd(struct radeon_device *rdev) | |
137 | { | |
138 | u32 p, u; | |
139 | u32 xclk = sumo_get_xclk(rdev); | |
140 | u32 grs = 256 * 25 / 100; | |
141 | ||
142 | r600_calculate_u_and_p(1, xclk, 14, &p, &u); | |
143 | ||
144 | WREG32(CG_GCOOR, PHC(grs) | SDC(p) | SU(u)); | |
145 | } | |
146 | ||
147 | static void sumo_gfx_clockgating_initialize(struct radeon_device *rdev) | |
148 | { | |
149 | sumo_program_git(rdev); | |
150 | sumo_program_grsd(rdev); | |
151 | } | |
152 | ||
153 | static void sumo_gfx_powergating_initialize(struct radeon_device *rdev) | |
154 | { | |
155 | u32 rcu_pwr_gating_cntl; | |
156 | u32 p, u; | |
157 | u32 p_c, p_p, d_p; | |
158 | u32 r_t, i_t; | |
159 | u32 xclk = sumo_get_xclk(rdev); | |
160 | ||
161 | if (rdev->family == CHIP_PALM) { | |
162 | p_c = 4; | |
163 | d_p = 10; | |
164 | r_t = 10; | |
165 | i_t = 4; | |
166 | p_p = 50 + 1000/200 + 6 * 32; | |
167 | } else { | |
168 | p_c = 16; | |
169 | d_p = 50; | |
170 | r_t = 50; | |
171 | i_t = 50; | |
172 | p_p = 113; | |
173 | } | |
174 | ||
175 | WREG32(CG_SCRATCH2, 0x01B60A17); | |
176 | ||
177 | r600_calculate_u_and_p(SUMO_GFXPOWERGATINGT_DFLT, | |
178 | xclk, 16, &p, &u); | |
179 | ||
180 | WREG32_P(CG_PWR_GATING_CNTL, PGP(p) | PGU(u), | |
181 | ~(PGP_MASK | PGU_MASK)); | |
182 | ||
183 | r600_calculate_u_and_p(SUMO_VOLTAGEDROPT_DFLT, | |
184 | xclk, 16, &p, &u); | |
185 | ||
186 | WREG32_P(CG_CG_VOLTAGE_CNTL, PGP(p) | PGU(u), | |
187 | ~(PGP_MASK | PGU_MASK)); | |
188 | ||
189 | if (rdev->family == CHIP_PALM) { | |
190 | WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x10103210); | |
191 | WREG32_RCU(RCU_PWR_GATING_SEQ1, 0x10101010); | |
192 | } else { | |
193 | WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x76543210); | |
194 | WREG32_RCU(RCU_PWR_GATING_SEQ1, 0xFEDCBA98); | |
195 | } | |
196 | ||
197 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL); | |
198 | rcu_pwr_gating_cntl &= | |
199 | ~(RSVD_MASK | PCV_MASK | PGS_MASK); | |
200 | rcu_pwr_gating_cntl |= PCV(p_c) | PGS(1) | PWR_GATING_EN; | |
201 | if (rdev->family == CHIP_PALM) { | |
202 | rcu_pwr_gating_cntl &= ~PCP_MASK; | |
203 | rcu_pwr_gating_cntl |= PCP(0x77); | |
204 | } | |
205 | WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl); | |
206 | ||
207 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2); | |
208 | rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK); | |
209 | rcu_pwr_gating_cntl |= MPPU(p_p) | MPPD(50); | |
210 | WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl); | |
211 | ||
212 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3); | |
213 | rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK); | |
214 | rcu_pwr_gating_cntl |= DPPU(d_p) | DPPD(50); | |
215 | WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl); | |
216 | ||
217 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_4); | |
218 | rcu_pwr_gating_cntl &= ~(RT_MASK | IT_MASK); | |
219 | rcu_pwr_gating_cntl |= RT(r_t) | IT(i_t); | |
220 | WREG32_RCU(RCU_PWR_GATING_CNTL_4, rcu_pwr_gating_cntl); | |
221 | ||
222 | if (rdev->family == CHIP_PALM) | |
223 | WREG32_RCU(RCU_PWR_GATING_CNTL_5, 0xA02); | |
224 | ||
225 | sumo_smu_pg_init(rdev); | |
226 | ||
227 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL); | |
228 | rcu_pwr_gating_cntl &= | |
229 | ~(RSVD_MASK | PCV_MASK | PGS_MASK); | |
230 | rcu_pwr_gating_cntl |= PCV(p_c) | PGS(4) | PWR_GATING_EN; | |
231 | if (rdev->family == CHIP_PALM) { | |
232 | rcu_pwr_gating_cntl &= ~PCP_MASK; | |
233 | rcu_pwr_gating_cntl |= PCP(0x77); | |
234 | } | |
235 | WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl); | |
236 | ||
237 | if (rdev->family == CHIP_PALM) { | |
238 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2); | |
239 | rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK); | |
240 | rcu_pwr_gating_cntl |= MPPU(113) | MPPD(50); | |
241 | WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl); | |
242 | ||
243 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3); | |
244 | rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK); | |
245 | rcu_pwr_gating_cntl |= DPPU(16) | DPPD(50); | |
246 | WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl); | |
247 | } | |
248 | ||
249 | sumo_smu_pg_init(rdev); | |
250 | ||
251 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL); | |
252 | rcu_pwr_gating_cntl &= | |
253 | ~(RSVD_MASK | PCV_MASK | PGS_MASK); | |
254 | rcu_pwr_gating_cntl |= PGS(5) | PWR_GATING_EN; | |
255 | ||
256 | if (rdev->family == CHIP_PALM) { | |
257 | rcu_pwr_gating_cntl |= PCV(4); | |
258 | rcu_pwr_gating_cntl &= ~PCP_MASK; | |
259 | rcu_pwr_gating_cntl |= PCP(0x77); | |
260 | } else | |
261 | rcu_pwr_gating_cntl |= PCV(11); | |
262 | WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl); | |
263 | ||
264 | if (rdev->family == CHIP_PALM) { | |
265 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2); | |
266 | rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK); | |
267 | rcu_pwr_gating_cntl |= MPPU(113) | MPPD(50); | |
268 | WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl); | |
269 | ||
270 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3); | |
271 | rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK); | |
272 | rcu_pwr_gating_cntl |= DPPU(22) | DPPD(50); | |
273 | WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl); | |
274 | } | |
275 | ||
276 | sumo_smu_pg_init(rdev); | |
277 | } | |
278 | ||
279 | static void sumo_gfx_powergating_enable(struct radeon_device *rdev, bool enable) | |
280 | { | |
281 | if (enable) | |
282 | WREG32_P(CG_PWR_GATING_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN); | |
283 | else { | |
284 | WREG32_P(CG_PWR_GATING_CNTL, 0, ~DYN_PWR_DOWN_EN); | |
285 | RREG32(GB_ADDR_CONFIG); | |
286 | } | |
287 | } | |
288 | ||
289 | static int sumo_enable_clock_power_gating(struct radeon_device *rdev) | |
290 | { | |
291 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
292 | ||
293 | if (pi->enable_gfx_clock_gating) | |
294 | sumo_gfx_clockgating_initialize(rdev); | |
295 | if (pi->enable_gfx_power_gating) | |
296 | sumo_gfx_powergating_initialize(rdev); | |
297 | if (pi->enable_mg_clock_gating) | |
298 | sumo_mg_clockgating_enable(rdev, true); | |
299 | if (pi->enable_gfx_clock_gating) | |
300 | sumo_gfx_clockgating_enable(rdev, true); | |
301 | if (pi->enable_gfx_power_gating) | |
302 | sumo_gfx_powergating_enable(rdev, true); | |
303 | ||
304 | return 0; | |
305 | } | |
306 | ||
307 | static void sumo_disable_clock_power_gating(struct radeon_device *rdev) | |
308 | { | |
309 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
310 | ||
311 | if (pi->enable_gfx_clock_gating) | |
312 | sumo_gfx_clockgating_enable(rdev, false); | |
313 | if (pi->enable_gfx_power_gating) | |
314 | sumo_gfx_powergating_enable(rdev, false); | |
315 | if (pi->enable_mg_clock_gating) | |
316 | sumo_mg_clockgating_enable(rdev, false); | |
317 | } | |
318 | ||
319 | static void sumo_calculate_bsp(struct radeon_device *rdev, | |
320 | u32 high_clk) | |
321 | { | |
322 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
323 | u32 xclk = sumo_get_xclk(rdev); | |
324 | ||
325 | pi->pasi = 65535 * 100 / high_clk; | |
326 | pi->asi = 65535 * 100 / high_clk; | |
327 | ||
328 | r600_calculate_u_and_p(pi->asi, | |
329 | xclk, 16, &pi->bsp, &pi->bsu); | |
330 | ||
331 | r600_calculate_u_and_p(pi->pasi, | |
332 | xclk, 16, &pi->pbsp, &pi->pbsu); | |
333 | ||
334 | pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); | |
335 | pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); | |
336 | } | |
337 | ||
338 | static void sumo_init_bsp(struct radeon_device *rdev) | |
339 | { | |
340 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
341 | ||
342 | WREG32(CG_BSP_0, pi->psp); | |
343 | } | |
344 | ||
345 | ||
346 | static void sumo_program_bsp(struct radeon_device *rdev) | |
347 | { | |
348 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
349 | struct sumo_ps *ps = sumo_get_ps(rdev->pm.dpm.requested_ps); | |
350 | u32 i; | |
351 | u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk; | |
352 | ||
353 | if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) | |
354 | highest_engine_clock = pi->boost_pl.sclk; | |
355 | ||
356 | sumo_calculate_bsp(rdev, highest_engine_clock); | |
357 | ||
358 | for (i = 0; i < ps->num_levels - 1; i++) | |
359 | WREG32(CG_BSP_0 + (i * 4), pi->dsp); | |
360 | ||
361 | WREG32(CG_BSP_0 + (i * 4), pi->psp); | |
362 | ||
363 | if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) | |
364 | WREG32(CG_BSP_0 + (BOOST_DPM_LEVEL * 4), pi->psp); | |
365 | } | |
366 | ||
367 | static void sumo_write_at(struct radeon_device *rdev, | |
368 | u32 index, u32 value) | |
369 | { | |
370 | if (index == 0) | |
371 | WREG32(CG_AT_0, value); | |
372 | else if (index == 1) | |
373 | WREG32(CG_AT_1, value); | |
374 | else if (index == 2) | |
375 | WREG32(CG_AT_2, value); | |
376 | else if (index == 3) | |
377 | WREG32(CG_AT_3, value); | |
378 | else if (index == 4) | |
379 | WREG32(CG_AT_4, value); | |
380 | else if (index == 5) | |
381 | WREG32(CG_AT_5, value); | |
382 | else if (index == 6) | |
383 | WREG32(CG_AT_6, value); | |
384 | else if (index == 7) | |
385 | WREG32(CG_AT_7, value); | |
386 | } | |
387 | ||
388 | static void sumo_program_at(struct radeon_device *rdev) | |
389 | { | |
390 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
391 | struct sumo_ps *ps = sumo_get_ps(rdev->pm.dpm.requested_ps); | |
392 | u32 asi; | |
393 | u32 i; | |
394 | u32 m_a; | |
395 | u32 a_t; | |
396 | u32 r[SUMO_MAX_HARDWARE_POWERLEVELS]; | |
397 | u32 l[SUMO_MAX_HARDWARE_POWERLEVELS]; | |
398 | ||
399 | r[0] = SUMO_R_DFLT0; | |
400 | r[1] = SUMO_R_DFLT1; | |
401 | r[2] = SUMO_R_DFLT2; | |
402 | r[3] = SUMO_R_DFLT3; | |
403 | r[4] = SUMO_R_DFLT4; | |
404 | ||
405 | l[0] = SUMO_L_DFLT0; | |
406 | l[1] = SUMO_L_DFLT1; | |
407 | l[2] = SUMO_L_DFLT2; | |
408 | l[3] = SUMO_L_DFLT3; | |
409 | l[4] = SUMO_L_DFLT4; | |
410 | ||
411 | for (i = 0; i < ps->num_levels; i++) { | |
412 | asi = (i == ps->num_levels - 1) ? pi->pasi : pi->asi; | |
413 | ||
414 | m_a = asi * ps->levels[i].sclk / 100; | |
415 | ||
416 | a_t = CG_R(m_a * r[i] / 100) | CG_L(m_a * l[i] / 100); | |
417 | ||
418 | sumo_write_at(rdev, i, a_t); | |
419 | } | |
420 | ||
421 | if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) { | |
422 | asi = pi->pasi; | |
423 | ||
424 | m_a = asi * pi->boost_pl.sclk / 100; | |
425 | ||
426 | a_t = CG_R(m_a * r[ps->num_levels - 1] / 100) | | |
427 | CG_L(m_a * l[ps->num_levels - 1] / 100); | |
428 | ||
429 | sumo_write_at(rdev, BOOST_DPM_LEVEL, a_t); | |
430 | } | |
431 | } | |
432 | ||
433 | static void sumo_program_tp(struct radeon_device *rdev) | |
434 | { | |
435 | int i; | |
436 | enum r600_td td = R600_TD_DFLT; | |
437 | ||
438 | for (i = 0; i < SUMO_PM_NUMBER_OF_TC; i++) { | |
439 | WREG32_P(CG_FFCT_0 + (i * 4), UTC_0(sumo_utc[i]), ~UTC_0_MASK); | |
440 | WREG32_P(CG_FFCT_0 + (i * 4), DTC_0(sumo_dtc[i]), ~DTC_0_MASK); | |
441 | } | |
442 | ||
443 | if (td == R600_TD_AUTO) | |
444 | WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); | |
445 | else | |
446 | WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); | |
447 | ||
448 | if (td == R600_TD_UP) | |
449 | WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); | |
450 | ||
451 | if (td == R600_TD_DOWN) | |
452 | WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); | |
453 | } | |
454 | ||
455 | static void sumo_program_vc(struct radeon_device *rdev) | |
456 | { | |
457 | WREG32(CG_FTV, SUMO_VRC_DFLT); | |
458 | } | |
459 | ||
460 | static void sumo_clear_vc(struct radeon_device *rdev) | |
461 | { | |
462 | WREG32(CG_FTV, 0); | |
463 | } | |
464 | ||
465 | static void sumo_program_sstp(struct radeon_device *rdev) | |
466 | { | |
467 | u32 p, u; | |
468 | u32 xclk = sumo_get_xclk(rdev); | |
469 | ||
470 | r600_calculate_u_and_p(SUMO_SST_DFLT, | |
471 | xclk, 16, &p, &u); | |
472 | ||
473 | WREG32(CG_SSP, SSTU(u) | SST(p)); | |
474 | } | |
475 | ||
476 | static void sumo_set_divider_value(struct radeon_device *rdev, | |
477 | u32 index, u32 divider) | |
478 | { | |
479 | u32 reg_index = index / 4; | |
480 | u32 field_index = index % 4; | |
481 | ||
482 | if (field_index == 0) | |
483 | WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), | |
484 | SCLK_FSTATE_0_DIV(divider), ~SCLK_FSTATE_0_DIV_MASK); | |
485 | else if (field_index == 1) | |
486 | WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), | |
487 | SCLK_FSTATE_1_DIV(divider), ~SCLK_FSTATE_1_DIV_MASK); | |
488 | else if (field_index == 2) | |
489 | WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), | |
490 | SCLK_FSTATE_2_DIV(divider), ~SCLK_FSTATE_2_DIV_MASK); | |
491 | else if (field_index == 3) | |
492 | WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), | |
493 | SCLK_FSTATE_3_DIV(divider), ~SCLK_FSTATE_3_DIV_MASK); | |
494 | } | |
495 | ||
496 | static void sumo_set_ds_dividers(struct radeon_device *rdev, | |
497 | u32 index, u32 divider) | |
498 | { | |
499 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
500 | ||
501 | if (pi->enable_sclk_ds) { | |
502 | u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_6); | |
503 | ||
504 | dpm_ctrl &= ~(0x7 << (index * 3)); | |
505 | dpm_ctrl |= (divider << (index * 3)); | |
506 | WREG32(CG_SCLK_DPM_CTRL_6, dpm_ctrl); | |
507 | } | |
508 | } | |
509 | ||
510 | static void sumo_set_ss_dividers(struct radeon_device *rdev, | |
511 | u32 index, u32 divider) | |
512 | { | |
513 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
514 | ||
515 | if (pi->enable_sclk_ds) { | |
516 | u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_11); | |
517 | ||
518 | dpm_ctrl &= ~(0x7 << (index * 3)); | |
519 | dpm_ctrl |= (divider << (index * 3)); | |
520 | WREG32(CG_SCLK_DPM_CTRL_11, dpm_ctrl); | |
521 | } | |
522 | } | |
523 | ||
524 | static void sumo_set_vid(struct radeon_device *rdev, u32 index, u32 vid) | |
525 | { | |
526 | u32 voltage_cntl = RREG32(CG_DPM_VOLTAGE_CNTL); | |
527 | ||
528 | voltage_cntl &= ~(DPM_STATE0_LEVEL_MASK << (index * 2)); | |
529 | voltage_cntl |= (vid << (DPM_STATE0_LEVEL_SHIFT + index * 2)); | |
530 | WREG32(CG_DPM_VOLTAGE_CNTL, voltage_cntl); | |
531 | } | |
532 | ||
533 | static void sumo_set_allos_gnb_slow(struct radeon_device *rdev, u32 index, u32 gnb_slow) | |
534 | { | |
535 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
536 | u32 temp = gnb_slow; | |
537 | u32 cg_sclk_dpm_ctrl_3; | |
538 | ||
539 | if (pi->driver_nbps_policy_disable) | |
540 | temp = 1; | |
541 | ||
542 | cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3); | |
543 | cg_sclk_dpm_ctrl_3 &= ~(GNB_SLOW_FSTATE_0_MASK << index); | |
544 | cg_sclk_dpm_ctrl_3 |= (temp << (GNB_SLOW_FSTATE_0_SHIFT + index)); | |
545 | ||
546 | WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3); | |
547 | } | |
548 | ||
549 | static void sumo_program_power_level(struct radeon_device *rdev, | |
550 | struct sumo_pl *pl, u32 index) | |
551 | { | |
552 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
553 | int ret; | |
554 | struct atom_clock_dividers dividers; | |
555 | u32 ds_en = RREG32(DEEP_SLEEP_CNTL) & ENABLE_DS; | |
556 | ||
557 | ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, | |
558 | pl->sclk, false, ÷rs); | |
559 | if (ret) | |
560 | return; | |
561 | ||
562 | sumo_set_divider_value(rdev, index, dividers.post_div); | |
563 | ||
564 | sumo_set_vid(rdev, index, pl->vddc_index); | |
565 | ||
566 | if (pl->ss_divider_index == 0 || pl->ds_divider_index == 0) { | |
567 | if (ds_en) | |
568 | WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS); | |
569 | } else { | |
570 | sumo_set_ss_dividers(rdev, index, pl->ss_divider_index); | |
571 | sumo_set_ds_dividers(rdev, index, pl->ds_divider_index); | |
572 | ||
573 | if (!ds_en) | |
574 | WREG32_P(DEEP_SLEEP_CNTL, ENABLE_DS, ~ENABLE_DS); | |
575 | } | |
576 | ||
577 | sumo_set_allos_gnb_slow(rdev, index, pl->allow_gnb_slow); | |
578 | ||
579 | if (pi->enable_boost) | |
580 | sumo_set_tdp_limit(rdev, index, pl->sclk_dpm_tdp_limit); | |
581 | } | |
582 | ||
583 | static void sumo_power_level_enable(struct radeon_device *rdev, u32 index, bool enable) | |
584 | { | |
585 | u32 reg_index = index / 4; | |
586 | u32 field_index = index % 4; | |
587 | ||
588 | if (field_index == 0) | |
589 | WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), | |
590 | enable ? SCLK_FSTATE_0_VLD : 0, ~SCLK_FSTATE_0_VLD); | |
591 | else if (field_index == 1) | |
592 | WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), | |
593 | enable ? SCLK_FSTATE_1_VLD : 0, ~SCLK_FSTATE_1_VLD); | |
594 | else if (field_index == 2) | |
595 | WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), | |
596 | enable ? SCLK_FSTATE_2_VLD : 0, ~SCLK_FSTATE_2_VLD); | |
597 | else if (field_index == 3) | |
598 | WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), | |
599 | enable ? SCLK_FSTATE_3_VLD : 0, ~SCLK_FSTATE_3_VLD); | |
600 | } | |
601 | ||
602 | static bool sumo_dpm_enabled(struct radeon_device *rdev) | |
603 | { | |
604 | if (RREG32(CG_SCLK_DPM_CTRL_3) & DPM_SCLK_ENABLE) | |
605 | return true; | |
606 | else | |
607 | return false; | |
608 | } | |
609 | ||
610 | static void sumo_start_dpm(struct radeon_device *rdev) | |
611 | { | |
612 | WREG32_P(CG_SCLK_DPM_CTRL_3, DPM_SCLK_ENABLE, ~DPM_SCLK_ENABLE); | |
613 | } | |
614 | ||
615 | static void sumo_stop_dpm(struct radeon_device *rdev) | |
616 | { | |
617 | WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~DPM_SCLK_ENABLE); | |
618 | } | |
619 | ||
620 | static void sumo_set_forced_mode(struct radeon_device *rdev, bool enable) | |
621 | { | |
622 | if (enable) | |
623 | WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE_EN, ~FORCE_SCLK_STATE_EN); | |
624 | else | |
625 | WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_SCLK_STATE_EN); | |
626 | } | |
627 | ||
628 | static void sumo_set_forced_mode_enabled(struct radeon_device *rdev) | |
629 | { | |
630 | int i; | |
631 | ||
632 | sumo_set_forced_mode(rdev, true); | |
633 | for (i = 0; i < rdev->usec_timeout; i++) { | |
634 | if (RREG32(CG_SCLK_STATUS) & SCLK_OVERCLK_DETECT) | |
635 | break; | |
636 | udelay(1); | |
637 | } | |
638 | } | |
639 | ||
640 | static void sumo_wait_for_level_0(struct radeon_device *rdev) | |
641 | { | |
642 | int i; | |
643 | ||
644 | for (i = 0; i < rdev->usec_timeout; i++) { | |
645 | if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) == 0) | |
646 | break; | |
647 | udelay(1); | |
648 | } | |
649 | for (i = 0; i < rdev->usec_timeout; i++) { | |
650 | if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) == 0) | |
651 | break; | |
652 | udelay(1); | |
653 | } | |
654 | } | |
655 | ||
656 | static void sumo_set_forced_mode_disabled(struct radeon_device *rdev) | |
657 | { | |
658 | sumo_set_forced_mode(rdev, false); | |
659 | } | |
660 | ||
661 | static void sumo_enable_power_level_0(struct radeon_device *rdev) | |
662 | { | |
663 | sumo_power_level_enable(rdev, 0, true); | |
664 | } | |
665 | ||
666 | static void sumo_patch_boost_state(struct radeon_device *rdev) | |
667 | { | |
668 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
669 | struct sumo_ps *new_ps = sumo_get_ps(rdev->pm.dpm.requested_ps); | |
670 | ||
671 | if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) { | |
672 | pi->boost_pl = new_ps->levels[new_ps->num_levels - 1]; | |
673 | pi->boost_pl.sclk = pi->sys_info.boost_sclk; | |
674 | pi->boost_pl.vddc_index = pi->sys_info.boost_vid_2bit; | |
675 | pi->boost_pl.sclk_dpm_tdp_limit = pi->sys_info.sclk_dpm_tdp_limit_boost; | |
676 | } | |
677 | } | |
678 | ||
679 | static void sumo_pre_notify_alt_vddnb_change(struct radeon_device *rdev) | |
680 | { | |
681 | struct sumo_ps *new_ps = sumo_get_ps(rdev->pm.dpm.requested_ps); | |
682 | struct sumo_ps *old_ps = sumo_get_ps(rdev->pm.dpm.current_ps); | |
683 | u32 nbps1_old = 0; | |
684 | u32 nbps1_new = 0; | |
685 | ||
686 | if (old_ps != NULL) | |
687 | nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0; | |
688 | ||
689 | nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0; | |
690 | ||
691 | if (nbps1_old == 1 && nbps1_new == 0) | |
692 | sumo_smu_notify_alt_vddnb_change(rdev, 0, 0); | |
693 | } | |
694 | ||
695 | static void sumo_post_notify_alt_vddnb_change(struct radeon_device *rdev) | |
696 | { | |
697 | struct sumo_ps *new_ps = sumo_get_ps(rdev->pm.dpm.requested_ps); | |
698 | struct sumo_ps *old_ps = sumo_get_ps(rdev->pm.dpm.current_ps); | |
699 | u32 nbps1_old = 0; | |
700 | u32 nbps1_new = 0; | |
701 | ||
702 | if (old_ps != NULL) | |
703 | nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0; | |
704 | ||
705 | nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0; | |
706 | ||
707 | if (nbps1_old == 0 && nbps1_new == 1) | |
708 | sumo_smu_notify_alt_vddnb_change(rdev, 1, 1); | |
709 | } | |
710 | ||
711 | static void sumo_enable_boost(struct radeon_device *rdev, bool enable) | |
712 | { | |
713 | struct sumo_ps *new_ps = sumo_get_ps(rdev->pm.dpm.requested_ps); | |
714 | ||
715 | if (enable) { | |
716 | if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) | |
717 | sumo_boost_state_enable(rdev, true); | |
718 | } else | |
719 | sumo_boost_state_enable(rdev, false); | |
720 | } | |
721 | ||
722 | static void sumo_update_current_power_levels(struct radeon_device *rdev) | |
723 | { | |
724 | struct sumo_ps *new_ps = sumo_get_ps(rdev->pm.dpm.requested_ps); | |
725 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
726 | ||
727 | pi->current_ps = *new_ps; | |
728 | } | |
729 | ||
730 | static void sumo_set_forced_level(struct radeon_device *rdev, u32 index) | |
731 | { | |
732 | WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE(index), ~FORCE_SCLK_STATE_MASK); | |
733 | } | |
734 | ||
735 | static void sumo_set_forced_level_0(struct radeon_device *rdev) | |
736 | { | |
737 | sumo_set_forced_level(rdev, 0); | |
738 | } | |
739 | ||
740 | static void sumo_program_wl(struct radeon_device *rdev) | |
741 | { | |
742 | struct sumo_ps *new_ps = sumo_get_ps(rdev->pm.dpm.requested_ps); | |
743 | u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4); | |
744 | ||
745 | dpm_ctrl4 &= 0xFFFFFF00; | |
746 | dpm_ctrl4 |= (1 << (new_ps->num_levels - 1)); | |
747 | ||
748 | if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) | |
749 | dpm_ctrl4 |= (1 << BOOST_DPM_LEVEL); | |
750 | ||
751 | WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4); | |
752 | } | |
753 | ||
754 | static void sumo_program_power_levels_0_to_n(struct radeon_device *rdev) | |
755 | { | |
756 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
757 | struct sumo_ps *new_ps = sumo_get_ps(rdev->pm.dpm.requested_ps); | |
758 | struct sumo_ps *old_ps = sumo_get_ps(rdev->pm.dpm.current_ps); | |
759 | u32 i; | |
760 | u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels; | |
761 | ||
762 | for (i = 0; i < new_ps->num_levels; i++) { | |
763 | sumo_program_power_level(rdev, &new_ps->levels[i], i); | |
764 | sumo_power_level_enable(rdev, i, true); | |
765 | } | |
766 | ||
767 | for (i = new_ps->num_levels; i < n_current_state_levels; i++) | |
768 | sumo_power_level_enable(rdev, i, false); | |
769 | ||
770 | if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) | |
771 | sumo_program_power_level(rdev, &pi->boost_pl, BOOST_DPM_LEVEL); | |
772 | } | |
773 | ||
774 | static void sumo_enable_acpi_pm(struct radeon_device *rdev) | |
775 | { | |
776 | WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); | |
777 | } | |
778 | ||
779 | static void sumo_program_power_level_enter_state(struct radeon_device *rdev) | |
780 | { | |
781 | WREG32_P(CG_SCLK_DPM_CTRL_5, SCLK_FSTATE_BOOTUP(0), ~SCLK_FSTATE_BOOTUP_MASK); | |
782 | } | |
783 | ||
784 | static void sumo_program_acpi_power_level(struct radeon_device *rdev) | |
785 | { | |
786 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
787 | struct atom_clock_dividers dividers; | |
788 | int ret; | |
789 | ||
790 | ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, | |
791 | pi->acpi_pl.sclk, | |
792 | false, ÷rs); | |
793 | if (ret) | |
794 | return; | |
795 | ||
796 | WREG32_P(CG_ACPI_CNTL, SCLK_ACPI_DIV(dividers.post_div), ~SCLK_ACPI_DIV_MASK); | |
797 | WREG32_P(CG_ACPI_VOLTAGE_CNTL, 0, ~ACPI_VOLTAGE_EN); | |
798 | } | |
799 | ||
800 | static void sumo_program_bootup_state(struct radeon_device *rdev) | |
801 | { | |
802 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
803 | u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4); | |
804 | u32 i; | |
805 | ||
806 | sumo_program_power_level(rdev, &pi->boot_pl, 0); | |
807 | ||
808 | dpm_ctrl4 &= 0xFFFFFF00; | |
809 | WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4); | |
810 | ||
811 | for (i = 1; i < 8; i++) | |
812 | sumo_power_level_enable(rdev, i, false); | |
813 | } | |
814 | ||
815 | static void sumo_take_smu_control(struct radeon_device *rdev, bool enable) | |
816 | { | |
817 | u32 v = RREG32(DOUT_SCRATCH3); | |
818 | ||
819 | if (enable) | |
820 | v |= 0x4; | |
821 | else | |
822 | v &= 0xFFFFFFFB; | |
823 | ||
824 | WREG32(DOUT_SCRATCH3, v); | |
825 | } | |
826 | ||
827 | static void sumo_enable_sclk_ds(struct radeon_device *rdev, bool enable) | |
828 | { | |
829 | if (enable) { | |
830 | u32 deep_sleep_cntl = RREG32(DEEP_SLEEP_CNTL); | |
831 | u32 deep_sleep_cntl2 = RREG32(DEEP_SLEEP_CNTL2); | |
832 | u32 t = 1; | |
833 | ||
834 | deep_sleep_cntl &= ~R_DIS; | |
835 | deep_sleep_cntl &= ~HS_MASK; | |
836 | deep_sleep_cntl |= HS(t > 4095 ? 4095 : t); | |
837 | ||
838 | deep_sleep_cntl2 |= LB_UFP_EN; | |
839 | deep_sleep_cntl2 &= INOUT_C_MASK; | |
840 | deep_sleep_cntl2 |= INOUT_C(0xf); | |
841 | ||
842 | WREG32(DEEP_SLEEP_CNTL2, deep_sleep_cntl2); | |
843 | WREG32(DEEP_SLEEP_CNTL, deep_sleep_cntl); | |
844 | } else | |
845 | WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS); | |
846 | } | |
847 | ||
848 | static void sumo_program_bootup_at(struct radeon_device *rdev) | |
849 | { | |
850 | WREG32_P(CG_AT_0, CG_R(0xffff), ~CG_R_MASK); | |
851 | WREG32_P(CG_AT_0, CG_L(0), ~CG_L_MASK); | |
852 | } | |
853 | ||
854 | static void sumo_reset_am(struct radeon_device *rdev) | |
855 | { | |
856 | WREG32_P(SCLK_PWRMGT_CNTL, FIR_RESET, ~FIR_RESET); | |
857 | } | |
858 | ||
859 | static void sumo_start_am(struct radeon_device *rdev) | |
860 | { | |
861 | WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_RESET); | |
862 | } | |
863 | ||
864 | static void sumo_program_ttp(struct radeon_device *rdev) | |
865 | { | |
866 | u32 xclk = sumo_get_xclk(rdev); | |
867 | u32 p, u; | |
868 | u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5); | |
869 | ||
870 | r600_calculate_u_and_p(1000, | |
871 | xclk, 16, &p, &u); | |
872 | ||
873 | cg_sclk_dpm_ctrl_5 &= ~(TT_TP_MASK | TT_TU_MASK); | |
874 | cg_sclk_dpm_ctrl_5 |= TT_TP(p) | TT_TU(u); | |
875 | ||
876 | WREG32(CG_SCLK_DPM_CTRL_5, cg_sclk_dpm_ctrl_5); | |
877 | } | |
878 | ||
879 | static void sumo_program_ttt(struct radeon_device *rdev) | |
880 | { | |
881 | u32 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3); | |
882 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
883 | ||
884 | cg_sclk_dpm_ctrl_3 &= ~(GNB_TT_MASK | GNB_THERMTHRO_MASK); | |
885 | cg_sclk_dpm_ctrl_3 |= GNB_TT(pi->thermal_auto_throttling + 49); | |
886 | ||
887 | WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3); | |
888 | } | |
889 | ||
890 | ||
891 | static void sumo_enable_voltage_scaling(struct radeon_device *rdev, bool enable) | |
892 | { | |
893 | if (enable) { | |
894 | WREG32_P(CG_DPM_VOLTAGE_CNTL, DPM_VOLTAGE_EN, ~DPM_VOLTAGE_EN); | |
895 | WREG32_P(CG_CG_VOLTAGE_CNTL, 0, ~CG_VOLTAGE_EN); | |
896 | } else { | |
897 | WREG32_P(CG_CG_VOLTAGE_CNTL, CG_VOLTAGE_EN, ~CG_VOLTAGE_EN); | |
898 | WREG32_P(CG_DPM_VOLTAGE_CNTL, 0, ~DPM_VOLTAGE_EN); | |
899 | } | |
900 | } | |
901 | ||
902 | static void sumo_override_cnb_thermal_events(struct radeon_device *rdev) | |
903 | { | |
904 | WREG32_P(CG_SCLK_DPM_CTRL_3, CNB_THERMTHRO_MASK_SCLK, | |
905 | ~CNB_THERMTHRO_MASK_SCLK); | |
906 | } | |
907 | ||
908 | static void sumo_program_dc_hto(struct radeon_device *rdev) | |
909 | { | |
910 | u32 cg_sclk_dpm_ctrl_4 = RREG32(CG_SCLK_DPM_CTRL_4); | |
911 | u32 p, u; | |
912 | u32 xclk = sumo_get_xclk(rdev); | |
913 | ||
914 | r600_calculate_u_and_p(100000, | |
915 | xclk, 14, &p, &u); | |
916 | ||
917 | cg_sclk_dpm_ctrl_4 &= ~(DC_HDC_MASK | DC_HU_MASK); | |
918 | cg_sclk_dpm_ctrl_4 |= DC_HDC(p) | DC_HU(u); | |
919 | ||
920 | WREG32(CG_SCLK_DPM_CTRL_4, cg_sclk_dpm_ctrl_4); | |
921 | } | |
922 | ||
923 | static void sumo_force_nbp_state(struct radeon_device *rdev) | |
924 | { | |
925 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
926 | struct sumo_ps *new_ps = sumo_get_ps(rdev->pm.dpm.requested_ps); | |
927 | ||
928 | if (!pi->driver_nbps_policy_disable) { | |
929 | if (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) | |
930 | WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_NB_PSTATE_1, ~FORCE_NB_PSTATE_1); | |
931 | else | |
932 | WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_NB_PSTATE_1); | |
933 | } | |
934 | } | |
935 | ||
936 | static u32 sumo_get_sleep_divider_from_id(u32 id) | |
937 | { | |
938 | return 1 << id; | |
939 | } | |
940 | ||
941 | static u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev, | |
942 | u32 sclk, | |
943 | u32 min_sclk_in_sr) | |
944 | { | |
945 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
946 | u32 i; | |
947 | u32 temp; | |
948 | u32 min = (min_sclk_in_sr > SUMO_MINIMUM_ENGINE_CLOCK) ? | |
949 | min_sclk_in_sr : SUMO_MINIMUM_ENGINE_CLOCK; | |
950 | ||
951 | if (sclk < min) | |
952 | return 0; | |
953 | ||
954 | if (!pi->enable_sclk_ds) | |
955 | return 0; | |
956 | ||
957 | for (i = SUMO_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { | |
958 | temp = sclk / sumo_get_sleep_divider_from_id(i); | |
959 | ||
960 | if (temp >= min || i == 0) | |
961 | break; | |
962 | } | |
963 | return i; | |
964 | } | |
965 | ||
966 | static u32 sumo_get_valid_engine_clock(struct radeon_device *rdev, | |
967 | u32 lower_limit) | |
968 | { | |
969 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
970 | u32 i; | |
971 | ||
972 | for (i = 0; i < pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries; i++) { | |
973 | if (pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency >= lower_limit) | |
974 | return pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency; | |
975 | } | |
976 | ||
977 | return pi->sys_info.sclk_voltage_mapping_table.entries[pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1].sclk_frequency; | |
978 | } | |
979 | ||
980 | static void sumo_patch_thermal_state(struct radeon_device *rdev, | |
981 | struct sumo_ps *ps, | |
982 | struct sumo_ps *current_ps) | |
983 | { | |
984 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
985 | u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */ | |
986 | u32 current_vddc; | |
987 | u32 current_sclk; | |
988 | u32 current_index = 0; | |
989 | ||
990 | if (current_ps) { | |
991 | current_vddc = current_ps->levels[current_index].vddc_index; | |
992 | current_sclk = current_ps->levels[current_index].sclk; | |
993 | } else { | |
994 | current_vddc = pi->boot_pl.vddc_index; | |
995 | current_sclk = pi->boot_pl.sclk; | |
996 | } | |
997 | ||
998 | ps->levels[0].vddc_index = current_vddc; | |
999 | ||
1000 | if (ps->levels[0].sclk > current_sclk) | |
1001 | ps->levels[0].sclk = current_sclk; | |
1002 | ||
1003 | ps->levels[0].ss_divider_index = | |
1004 | sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, sclk_in_sr); | |
1005 | ||
1006 | ps->levels[0].ds_divider_index = | |
1007 | sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, SUMO_MINIMUM_ENGINE_CLOCK); | |
1008 | ||
1009 | if (ps->levels[0].ds_divider_index > ps->levels[0].ss_divider_index + 1) | |
1010 | ps->levels[0].ds_divider_index = ps->levels[0].ss_divider_index + 1; | |
1011 | ||
1012 | if (ps->levels[0].ss_divider_index == ps->levels[0].ds_divider_index) { | |
1013 | if (ps->levels[0].ss_divider_index > 1) | |
1014 | ps->levels[0].ss_divider_index = ps->levels[0].ss_divider_index - 1; | |
1015 | } | |
1016 | ||
1017 | if (ps->levels[0].ss_divider_index == 0) | |
1018 | ps->levels[0].ds_divider_index = 0; | |
1019 | ||
1020 | if (ps->levels[0].ds_divider_index == 0) | |
1021 | ps->levels[0].ss_divider_index = 0; | |
1022 | } | |
1023 | ||
1024 | static void sumo_apply_state_adjust_rules(struct radeon_device *rdev) | |
1025 | { | |
1026 | struct radeon_ps *rps = rdev->pm.dpm.requested_ps; | |
1027 | struct sumo_ps *ps = sumo_get_ps(rps); | |
1028 | struct sumo_ps *current_ps = sumo_get_ps(rdev->pm.dpm.current_ps); | |
1029 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
1030 | u32 min_voltage = 0; /* ??? */ | |
1031 | u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */ | |
1032 | u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */ | |
1033 | u32 i; | |
1034 | ||
1035 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL) | |
1036 | return sumo_patch_thermal_state(rdev, ps, current_ps); | |
1037 | ||
1038 | if (pi->enable_boost) { | |
1039 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) | |
1040 | ps->flags |= SUMO_POWERSTATE_FLAGS_BOOST_STATE; | |
1041 | } | |
1042 | ||
1043 | if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) || | |
1044 | (rps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) || | |
1045 | (rps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)) | |
1046 | ps->flags |= SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE; | |
1047 | ||
1048 | for (i = 0; i < ps->num_levels; i++) { | |
1049 | if (ps->levels[i].vddc_index < min_voltage) | |
1050 | ps->levels[i].vddc_index = min_voltage; | |
1051 | ||
1052 | if (ps->levels[i].sclk < min_sclk) | |
1053 | ps->levels[i].sclk = | |
1054 | sumo_get_valid_engine_clock(rdev, min_sclk); | |
1055 | ||
1056 | ps->levels[i].ss_divider_index = | |
1057 | sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, sclk_in_sr); | |
1058 | ||
1059 | ps->levels[i].ds_divider_index = | |
1060 | sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, SUMO_MINIMUM_ENGINE_CLOCK); | |
1061 | ||
1062 | if (ps->levels[i].ds_divider_index > ps->levels[i].ss_divider_index + 1) | |
1063 | ps->levels[i].ds_divider_index = ps->levels[i].ss_divider_index + 1; | |
1064 | ||
1065 | if (ps->levels[i].ss_divider_index == ps->levels[i].ds_divider_index) { | |
1066 | if (ps->levels[i].ss_divider_index > 1) | |
1067 | ps->levels[i].ss_divider_index = ps->levels[i].ss_divider_index - 1; | |
1068 | } | |
1069 | ||
1070 | if (ps->levels[i].ss_divider_index == 0) | |
1071 | ps->levels[i].ds_divider_index = 0; | |
1072 | ||
1073 | if (ps->levels[i].ds_divider_index == 0) | |
1074 | ps->levels[i].ss_divider_index = 0; | |
1075 | ||
1076 | if (ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) | |
1077 | ps->levels[i].allow_gnb_slow = 1; | |
1078 | else if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) || | |
1079 | (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)) | |
1080 | ps->levels[i].allow_gnb_slow = 0; | |
1081 | else if (i == ps->num_levels - 1) | |
1082 | ps->levels[i].allow_gnb_slow = 0; | |
1083 | else | |
1084 | ps->levels[i].allow_gnb_slow = 1; | |
1085 | } | |
1086 | } | |
1087 | ||
1088 | static void sumo_cleanup_asic(struct radeon_device *rdev) | |
1089 | { | |
1090 | sumo_take_smu_control(rdev, false); | |
1091 | } | |
1092 | ||
1093 | static int sumo_set_thermal_temperature_range(struct radeon_device *rdev, | |
1094 | int min_temp, int max_temp) | |
1095 | { | |
1096 | int low_temp = 0 * 1000; | |
1097 | int high_temp = 255 * 1000; | |
1098 | ||
1099 | if (low_temp < min_temp) | |
1100 | low_temp = min_temp; | |
1101 | if (high_temp > max_temp) | |
1102 | high_temp = max_temp; | |
1103 | if (high_temp < low_temp) { | |
1104 | DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); | |
1105 | return -EINVAL; | |
1106 | } | |
1107 | ||
1108 | WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(49 + (high_temp / 1000)), ~DIG_THERM_INTH_MASK); | |
1109 | WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(49 + (low_temp / 1000)), ~DIG_THERM_INTL_MASK); | |
1110 | ||
1111 | rdev->pm.dpm.thermal.min_temp = low_temp; | |
1112 | rdev->pm.dpm.thermal.max_temp = high_temp; | |
1113 | ||
1114 | return 0; | |
1115 | } | |
1116 | ||
1117 | int sumo_dpm_enable(struct radeon_device *rdev) | |
1118 | { | |
1119 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
1120 | ||
1121 | if (sumo_dpm_enabled(rdev)) | |
1122 | return -EINVAL; | |
1123 | ||
1124 | sumo_enable_clock_power_gating(rdev); | |
1125 | sumo_program_bootup_state(rdev); | |
1126 | sumo_init_bsp(rdev); | |
1127 | sumo_reset_am(rdev); | |
1128 | sumo_program_tp(rdev); | |
1129 | sumo_program_bootup_at(rdev); | |
1130 | sumo_start_am(rdev); | |
1131 | if (pi->enable_auto_thermal_throttling) { | |
1132 | sumo_program_ttp(rdev); | |
1133 | sumo_program_ttt(rdev); | |
1134 | } | |
1135 | sumo_program_dc_hto(rdev); | |
1136 | sumo_program_power_level_enter_state(rdev); | |
1137 | sumo_enable_voltage_scaling(rdev, true); | |
1138 | sumo_program_sstp(rdev); | |
1139 | sumo_program_vc(rdev); | |
1140 | sumo_override_cnb_thermal_events(rdev); | |
1141 | sumo_start_dpm(rdev); | |
1142 | sumo_wait_for_level_0(rdev); | |
1143 | if (pi->enable_sclk_ds) | |
1144 | sumo_enable_sclk_ds(rdev, true); | |
1145 | if (pi->enable_boost) | |
1146 | sumo_enable_boost_timer(rdev); | |
1147 | ||
1148 | if (rdev->irq.installed && | |
1149 | r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { | |
1150 | sumo_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); | |
1151 | rdev->irq.dpm_thermal = true; | |
1152 | radeon_irq_set(rdev); | |
1153 | } | |
1154 | ||
1155 | return 0; | |
1156 | } | |
1157 | ||
1158 | void sumo_dpm_disable(struct radeon_device *rdev) | |
1159 | { | |
1160 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
1161 | ||
1162 | if (!sumo_dpm_enabled(rdev)) | |
1163 | return; | |
1164 | sumo_disable_clock_power_gating(rdev); | |
1165 | if (pi->enable_sclk_ds) | |
1166 | sumo_enable_sclk_ds(rdev, false); | |
1167 | sumo_clear_vc(rdev); | |
1168 | sumo_wait_for_level_0(rdev); | |
1169 | sumo_stop_dpm(rdev); | |
1170 | sumo_enable_voltage_scaling(rdev, false); | |
1171 | ||
1172 | if (rdev->irq.installed && | |
1173 | r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { | |
1174 | rdev->irq.dpm_thermal = false; | |
1175 | radeon_irq_set(rdev); | |
1176 | } | |
1177 | } | |
1178 | ||
1179 | int sumo_dpm_set_power_state(struct radeon_device *rdev) | |
1180 | { | |
1181 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
1182 | ||
1183 | if (pi->enable_dynamic_patch_ps) | |
1184 | sumo_apply_state_adjust_rules(rdev); | |
1185 | sumo_update_current_power_levels(rdev); | |
1186 | if (pi->enable_boost) { | |
1187 | sumo_enable_boost(rdev, false); | |
1188 | sumo_patch_boost_state(rdev); | |
1189 | } | |
1190 | if (pi->enable_dpm) { | |
1191 | sumo_pre_notify_alt_vddnb_change(rdev); | |
1192 | sumo_enable_power_level_0(rdev); | |
1193 | sumo_set_forced_level_0(rdev); | |
1194 | sumo_set_forced_mode_enabled(rdev); | |
1195 | sumo_wait_for_level_0(rdev); | |
1196 | sumo_program_power_levels_0_to_n(rdev); | |
1197 | sumo_program_wl(rdev); | |
1198 | sumo_program_bsp(rdev); | |
1199 | sumo_program_at(rdev); | |
1200 | sumo_force_nbp_state(rdev); | |
1201 | sumo_set_forced_mode_disabled(rdev); | |
1202 | sumo_set_forced_mode_enabled(rdev); | |
1203 | sumo_set_forced_mode_disabled(rdev); | |
1204 | sumo_post_notify_alt_vddnb_change(rdev); | |
1205 | } | |
1206 | if (pi->enable_boost) | |
1207 | sumo_enable_boost(rdev, true); | |
1208 | ||
1209 | return 0; | |
1210 | } | |
1211 | ||
1212 | void sumo_dpm_reset_asic(struct radeon_device *rdev) | |
1213 | { | |
1214 | sumo_program_bootup_state(rdev); | |
1215 | sumo_enable_power_level_0(rdev); | |
1216 | sumo_set_forced_level_0(rdev); | |
1217 | sumo_set_forced_mode_enabled(rdev); | |
1218 | sumo_wait_for_level_0(rdev); | |
1219 | sumo_set_forced_mode_disabled(rdev); | |
1220 | sumo_set_forced_mode_enabled(rdev); | |
1221 | sumo_set_forced_mode_disabled(rdev); | |
1222 | } | |
1223 | ||
1224 | void sumo_dpm_setup_asic(struct radeon_device *rdev) | |
1225 | { | |
1226 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
1227 | ||
1228 | sumo_initialize_m3_arb(rdev); | |
1229 | pi->fw_version = sumo_get_running_fw_version(rdev); | |
1230 | DRM_INFO("Found smc ucode version: 0x%08x\n", pi->fw_version); | |
1231 | sumo_program_acpi_power_level(rdev); | |
1232 | sumo_enable_acpi_pm(rdev); | |
1233 | sumo_take_smu_control(rdev, true); | |
1234 | } | |
1235 | ||
1236 | void sumo_dpm_display_configuration_changed(struct radeon_device *rdev) | |
1237 | { | |
1238 | ||
1239 | } | |
1240 | ||
1241 | union power_info { | |
1242 | struct _ATOM_POWERPLAY_INFO info; | |
1243 | struct _ATOM_POWERPLAY_INFO_V2 info_2; | |
1244 | struct _ATOM_POWERPLAY_INFO_V3 info_3; | |
1245 | struct _ATOM_PPLIB_POWERPLAYTABLE pplib; | |
1246 | struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; | |
1247 | struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; | |
1248 | }; | |
1249 | ||
1250 | union pplib_clock_info { | |
1251 | struct _ATOM_PPLIB_R600_CLOCK_INFO r600; | |
1252 | struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; | |
1253 | struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; | |
1254 | struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; | |
1255 | }; | |
1256 | ||
1257 | union pplib_power_state { | |
1258 | struct _ATOM_PPLIB_STATE v1; | |
1259 | struct _ATOM_PPLIB_STATE_V2 v2; | |
1260 | }; | |
1261 | ||
1262 | static void sumo_patch_boot_state(struct radeon_device *rdev, | |
1263 | struct sumo_ps *ps) | |
1264 | { | |
1265 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
1266 | ||
1267 | ps->num_levels = 1; | |
1268 | ps->flags = 0; | |
1269 | ps->levels[0] = pi->boot_pl; | |
1270 | } | |
1271 | ||
1272 | static void sumo_parse_pplib_non_clock_info(struct radeon_device *rdev, | |
1273 | struct radeon_ps *rps, | |
1274 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, | |
1275 | u8 table_rev) | |
1276 | { | |
1277 | struct sumo_ps *ps = sumo_get_ps(rps); | |
1278 | ||
1279 | rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); | |
1280 | rps->class = le16_to_cpu(non_clock_info->usClassification); | |
1281 | rps->class2 = le16_to_cpu(non_clock_info->usClassification2); | |
1282 | ||
1283 | if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { | |
1284 | rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); | |
1285 | rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); | |
1286 | } else { | |
1287 | rps->vclk = 0; | |
1288 | rps->dclk = 0; | |
1289 | } | |
1290 | ||
1291 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { | |
1292 | rdev->pm.dpm.boot_ps = rps; | |
1293 | sumo_patch_boot_state(rdev, ps); | |
1294 | } | |
1295 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) | |
1296 | rdev->pm.dpm.uvd_ps = rps; | |
1297 | } | |
1298 | ||
1299 | static void sumo_parse_pplib_clock_info(struct radeon_device *rdev, | |
1300 | struct radeon_ps *rps, int index, | |
1301 | union pplib_clock_info *clock_info) | |
1302 | { | |
1303 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
1304 | struct sumo_ps *ps = sumo_get_ps(rps); | |
1305 | struct sumo_pl *pl = &ps->levels[index]; | |
1306 | u32 sclk; | |
1307 | ||
1308 | sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); | |
1309 | sclk |= clock_info->sumo.ucEngineClockHigh << 16; | |
1310 | pl->sclk = sclk; | |
1311 | pl->vddc_index = clock_info->sumo.vddcIndex; | |
1312 | pl->sclk_dpm_tdp_limit = clock_info->sumo.tdpLimit; | |
1313 | ||
1314 | ps->num_levels = index + 1; | |
1315 | ||
1316 | if (pi->enable_sclk_ds) { | |
1317 | pl->ds_divider_index = 5; | |
1318 | pl->ss_divider_index = 4; | |
1319 | } | |
1320 | } | |
1321 | ||
1322 | static int sumo_parse_power_table(struct radeon_device *rdev) | |
1323 | { | |
1324 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1325 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; | |
1326 | union pplib_power_state *power_state; | |
1327 | int i, j, k, non_clock_array_index, clock_array_index; | |
1328 | union pplib_clock_info *clock_info; | |
1329 | struct _StateArray *state_array; | |
1330 | struct _ClockInfoArray *clock_info_array; | |
1331 | struct _NonClockInfoArray *non_clock_info_array; | |
1332 | union power_info *power_info; | |
1333 | int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); | |
1334 | u16 data_offset; | |
1335 | u8 frev, crev; | |
1336 | u8 *power_state_offset; | |
1337 | struct sumo_ps *ps; | |
1338 | ||
1339 | if (!atom_parse_data_header(mode_info->atom_context, index, NULL, | |
1340 | &frev, &crev, &data_offset)) | |
1341 | return -EINVAL; | |
1342 | power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); | |
1343 | ||
1344 | state_array = (struct _StateArray *) | |
1345 | (mode_info->atom_context->bios + data_offset + | |
1346 | le16_to_cpu(power_info->pplib.usStateArrayOffset)); | |
1347 | clock_info_array = (struct _ClockInfoArray *) | |
1348 | (mode_info->atom_context->bios + data_offset + | |
1349 | le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); | |
1350 | non_clock_info_array = (struct _NonClockInfoArray *) | |
1351 | (mode_info->atom_context->bios + data_offset + | |
1352 | le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); | |
1353 | ||
1354 | rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * | |
1355 | state_array->ucNumEntries, GFP_KERNEL); | |
1356 | if (!rdev->pm.dpm.ps) | |
1357 | return -ENOMEM; | |
1358 | power_state_offset = (u8 *)state_array->states; | |
1359 | rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); | |
1360 | rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); | |
1361 | rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); | |
1362 | for (i = 0; i < state_array->ucNumEntries; i++) { | |
1363 | power_state = (union pplib_power_state *)power_state_offset; | |
1364 | non_clock_array_index = power_state->v2.nonClockInfoIndex; | |
1365 | non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) | |
1366 | &non_clock_info_array->nonClockInfo[non_clock_array_index]; | |
1367 | if (!rdev->pm.power_state[i].clock_info) | |
1368 | return -EINVAL; | |
1369 | ps = kzalloc(sizeof(struct sumo_ps), GFP_KERNEL); | |
1370 | if (ps == NULL) { | |
1371 | kfree(rdev->pm.dpm.ps); | |
1372 | return -ENOMEM; | |
1373 | } | |
1374 | rdev->pm.dpm.ps[i].ps_priv = ps; | |
1375 | k = 0; | |
1376 | for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { | |
1377 | clock_array_index = power_state->v2.clockInfoIndex[j]; | |
1378 | if (k >= SUMO_MAX_HARDWARE_POWERLEVELS) | |
1379 | break; | |
1380 | clock_info = (union pplib_clock_info *) | |
1381 | &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; | |
1382 | sumo_parse_pplib_clock_info(rdev, | |
1383 | &rdev->pm.dpm.ps[i], k, | |
1384 | clock_info); | |
1385 | k++; | |
1386 | } | |
1387 | sumo_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], | |
1388 | non_clock_info, | |
1389 | non_clock_info_array->ucEntrySize); | |
1390 | power_state_offset += 2 + power_state->v2.ucNumDPMLevels; | |
1391 | } | |
1392 | rdev->pm.dpm.num_ps = state_array->ucNumEntries; | |
1393 | return 0; | |
1394 | } | |
1395 | ||
1396 | static u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev, u32 vid_2bit) | |
1397 | { | |
1398 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
1399 | u32 i; | |
1400 | ||
1401 | for (i = 0; i < pi->sys_info.vid_mapping_table.num_entries; i++) { | |
1402 | if (pi->sys_info.vid_mapping_table.entries[i].vid_2bit == vid_2bit) | |
1403 | return pi->sys_info.vid_mapping_table.entries[i].vid_7bit; | |
1404 | } | |
1405 | ||
1406 | return pi->sys_info.vid_mapping_table.entries[pi->sys_info.vid_mapping_table.num_entries - 1].vid_7bit; | |
1407 | } | |
1408 | ||
1409 | static u16 sumo_convert_voltage_index_to_value(struct radeon_device *rdev, | |
1410 | u32 vid_2bit) | |
1411 | { | |
1412 | u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, vid_2bit); | |
1413 | ||
1414 | if (vid_7bit > 0x7C) | |
1415 | return 0; | |
1416 | ||
1417 | return (15500 - vid_7bit * 125 + 5) / 10; | |
1418 | } | |
1419 | ||
1420 | static void sumo_construct_display_voltage_mapping_table(struct radeon_device *rdev, | |
1421 | ATOM_CLK_VOLT_CAPABILITY *table) | |
1422 | { | |
1423 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
1424 | u32 i; | |
1425 | ||
1426 | for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) { | |
1427 | if (table[i].ulMaximumSupportedCLK == 0) | |
1428 | break; | |
1429 | ||
1430 | pi->sys_info.disp_clk_voltage_mapping_table.display_clock_frequency[i] = | |
1431 | table[i].ulMaximumSupportedCLK; | |
1432 | } | |
1433 | ||
1434 | pi->sys_info.disp_clk_voltage_mapping_table.num_max_voltage_levels = i; | |
1435 | ||
1436 | if (pi->sys_info.disp_clk_voltage_mapping_table.num_max_voltage_levels == 0) { | |
1437 | pi->sys_info.disp_clk_voltage_mapping_table.display_clock_frequency[0] = 80000; | |
1438 | pi->sys_info.disp_clk_voltage_mapping_table.num_max_voltage_levels = 1; | |
1439 | } | |
1440 | } | |
1441 | ||
1442 | static void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev, | |
1443 | ATOM_AVAILABLE_SCLK_LIST *table) | |
1444 | { | |
1445 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
1446 | u32 i; | |
1447 | u32 n = 0; | |
1448 | u32 prev_sclk = 0; | |
1449 | ||
1450 | for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) { | |
1451 | if (table[i].ulSupportedSCLK > prev_sclk) { | |
1452 | pi->sys_info.sclk_voltage_mapping_table.entries[n].sclk_frequency = | |
1453 | table[i].ulSupportedSCLK; | |
1454 | pi->sys_info.sclk_voltage_mapping_table.entries[n].vid_2bit = | |
1455 | table[i].usVoltageIndex; | |
1456 | prev_sclk = table[i].ulSupportedSCLK; | |
1457 | n++; | |
1458 | } | |
1459 | } | |
1460 | ||
1461 | pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries = n; | |
1462 | } | |
1463 | ||
1464 | static void sumo_construct_vid_mapping_table(struct radeon_device *rdev, | |
1465 | ATOM_AVAILABLE_SCLK_LIST *table) | |
1466 | { | |
1467 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
1468 | u32 i, j; | |
1469 | ||
1470 | for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) { | |
1471 | if (table[i].ulSupportedSCLK != 0) { | |
1472 | pi->sys_info.vid_mapping_table.entries[table[i].usVoltageIndex].vid_7bit = | |
1473 | table[i].usVoltageID; | |
1474 | pi->sys_info.vid_mapping_table.entries[table[i].usVoltageIndex].vid_2bit = | |
1475 | table[i].usVoltageIndex; | |
1476 | } | |
1477 | } | |
1478 | ||
1479 | for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) { | |
1480 | if (pi->sys_info.vid_mapping_table.entries[i].vid_7bit == 0) { | |
1481 | for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) { | |
1482 | if (pi->sys_info.vid_mapping_table.entries[j].vid_7bit != 0) { | |
1483 | pi->sys_info.vid_mapping_table.entries[i] = | |
1484 | pi->sys_info.vid_mapping_table.entries[j]; | |
1485 | pi->sys_info.vid_mapping_table.entries[j].vid_7bit = 0; | |
1486 | break; | |
1487 | } | |
1488 | } | |
1489 | ||
1490 | if (j == SUMO_MAX_NUMBER_VOLTAGES) | |
1491 | break; | |
1492 | } | |
1493 | } | |
1494 | ||
1495 | pi->sys_info.vid_mapping_table.num_entries = i; | |
1496 | } | |
1497 | ||
1498 | union igp_info { | |
1499 | struct _ATOM_INTEGRATED_SYSTEM_INFO info; | |
1500 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; | |
1501 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5; | |
1502 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; | |
1503 | }; | |
1504 | ||
1505 | static int sumo_parse_sys_info_table(struct radeon_device *rdev) | |
1506 | { | |
1507 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
1508 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1509 | int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); | |
1510 | union igp_info *igp_info; | |
1511 | u8 frev, crev; | |
1512 | u16 data_offset; | |
1513 | int i; | |
1514 | ||
1515 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, | |
1516 | &frev, &crev, &data_offset)) { | |
1517 | igp_info = (union igp_info *)(mode_info->atom_context->bios + | |
1518 | data_offset); | |
1519 | ||
1520 | if (crev != 6) { | |
1521 | DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); | |
1522 | return -EINVAL; | |
1523 | } | |
1524 | pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_6.ulBootUpEngineClock); | |
1525 | pi->sys_info.min_sclk = le32_to_cpu(igp_info->info_6.ulMinEngineClock); | |
1526 | pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_6.ulBootUpUMAClock); | |
1527 | pi->sys_info.bootup_nb_voltage_index = | |
1528 | le16_to_cpu(igp_info->info_6.usBootUpNBVoltage); | |
1529 | if (igp_info->info_6.ucHtcTmpLmt == 0) | |
1530 | pi->sys_info.htc_tmp_lmt = 203; | |
1531 | else | |
1532 | pi->sys_info.htc_tmp_lmt = igp_info->info_6.ucHtcTmpLmt; | |
1533 | if (igp_info->info_6.ucHtcHystLmt == 0) | |
1534 | pi->sys_info.htc_hyst_lmt = 5; | |
1535 | else | |
1536 | pi->sys_info.htc_hyst_lmt = igp_info->info_6.ucHtcHystLmt; | |
1537 | if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) { | |
1538 | DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n"); | |
1539 | } | |
1540 | for (i = 0; i < NUMBER_OF_M3ARB_PARAM_SETS; i++) { | |
1541 | pi->sys_info.csr_m3_arb_cntl_default[i] = | |
1542 | le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_DEFAULT[i]); | |
1543 | pi->sys_info.csr_m3_arb_cntl_uvd[i] = | |
1544 | le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_UVD[i]); | |
1545 | pi->sys_info.csr_m3_arb_cntl_fs3d[i] = | |
1546 | le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_FS3D[i]); | |
1547 | } | |
1548 | pi->sys_info.sclk_dpm_boost_margin = | |
1549 | le32_to_cpu(igp_info->info_6.SclkDpmBoostMargin); | |
1550 | pi->sys_info.sclk_dpm_throttle_margin = | |
1551 | le32_to_cpu(igp_info->info_6.SclkDpmThrottleMargin); | |
1552 | pi->sys_info.sclk_dpm_tdp_limit_pg = | |
1553 | le16_to_cpu(igp_info->info_6.SclkDpmTdpLimitPG); | |
1554 | pi->sys_info.gnb_tdp_limit = le16_to_cpu(igp_info->info_6.GnbTdpLimit); | |
1555 | pi->sys_info.sclk_dpm_tdp_limit_boost = | |
1556 | le16_to_cpu(igp_info->info_6.SclkDpmTdpLimitBoost); | |
1557 | pi->sys_info.boost_sclk = le32_to_cpu(igp_info->info_6.ulBoostEngineCLock); | |
1558 | pi->sys_info.boost_vid_2bit = igp_info->info_6.ulBoostVid_2bit; | |
1559 | if (igp_info->info_6.EnableBoost) | |
1560 | pi->sys_info.enable_boost = true; | |
1561 | else | |
1562 | pi->sys_info.enable_boost = false; | |
1563 | sumo_construct_display_voltage_mapping_table(rdev, | |
1564 | igp_info->info_6.sDISPCLK_Voltage); | |
1565 | sumo_construct_sclk_voltage_mapping_table(rdev, | |
1566 | igp_info->info_6.sAvail_SCLK); | |
1567 | sumo_construct_vid_mapping_table(rdev, igp_info->info_6.sAvail_SCLK); | |
1568 | ||
1569 | } | |
1570 | return 0; | |
1571 | } | |
1572 | ||
1573 | static void sumo_construct_boot_and_acpi_state(struct radeon_device *rdev) | |
1574 | { | |
1575 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
1576 | ||
1577 | pi->boot_pl.sclk = pi->sys_info.bootup_sclk; | |
1578 | pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index; | |
1579 | pi->boot_pl.ds_divider_index = 0; | |
1580 | pi->boot_pl.ss_divider_index = 0; | |
1581 | pi->boot_pl.allow_gnb_slow = 1; | |
1582 | pi->acpi_pl = pi->boot_pl; | |
1583 | pi->current_ps.num_levels = 1; | |
1584 | pi->current_ps.levels[0] = pi->boot_pl; | |
1585 | } | |
1586 | ||
1587 | int sumo_dpm_init(struct radeon_device *rdev) | |
1588 | { | |
1589 | struct sumo_power_info *pi; | |
1590 | u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT; | |
1591 | int ret; | |
1592 | ||
1593 | pi = kzalloc(sizeof(struct sumo_power_info), GFP_KERNEL); | |
1594 | if (pi == NULL) | |
1595 | return -ENOMEM; | |
1596 | rdev->pm.dpm.priv = pi; | |
1597 | ||
1598 | pi->driver_nbps_policy_disable = false; | |
1599 | if ((rdev->family == CHIP_PALM) && (hw_rev < 3)) | |
1600 | pi->disable_gfx_power_gating_in_uvd = true; | |
1601 | else | |
1602 | pi->disable_gfx_power_gating_in_uvd = false; | |
1603 | pi->enable_alt_vddnb = true; | |
1604 | pi->enable_sclk_ds = true; | |
1605 | pi->enable_dynamic_m3_arbiter = false; | |
1606 | pi->enable_dynamic_patch_ps = true; | |
1607 | pi->enable_gfx_power_gating = true; | |
1608 | pi->enable_gfx_clock_gating = true; | |
1609 | pi->enable_mg_clock_gating = true; | |
1610 | pi->enable_auto_thermal_throttling = true; | |
1611 | ||
1612 | ret = sumo_parse_sys_info_table(rdev); | |
1613 | if (ret) | |
1614 | return ret; | |
1615 | ||
1616 | sumo_construct_boot_and_acpi_state(rdev); | |
1617 | ||
1618 | ret = sumo_parse_power_table(rdev); | |
1619 | if (ret) | |
1620 | return ret; | |
1621 | ||
1622 | pi->pasi = CYPRESS_HASI_DFLT; | |
1623 | pi->asi = RV770_ASI_DFLT; | |
1624 | pi->thermal_auto_throttling = pi->sys_info.htc_tmp_lmt; | |
1625 | pi->enable_boost = pi->sys_info.enable_boost; | |
1626 | pi->enable_dpm = true; | |
1627 | ||
1628 | return 0; | |
1629 | } | |
1630 | ||
1631 | void sumo_dpm_print_power_state(struct radeon_device *rdev, | |
1632 | struct radeon_ps *rps) | |
1633 | { | |
1634 | int i; | |
1635 | struct sumo_ps *ps = sumo_get_ps(rps); | |
1636 | ||
1637 | r600_dpm_print_class_info(rps->class, rps->class2); | |
1638 | r600_dpm_print_cap_info(rps->caps); | |
1639 | printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); | |
1640 | for (i = 0; i < ps->num_levels; i++) { | |
1641 | struct sumo_pl *pl = &ps->levels[i]; | |
1642 | printk("\t\tpower level %d sclk: %u vddc: %u\n", | |
1643 | i, pl->sclk, | |
1644 | sumo_convert_voltage_index_to_value(rdev, pl->vddc_index)); | |
1645 | } | |
1646 | r600_dpm_print_ps_status(rdev, rps); | |
1647 | } | |
1648 | ||
1649 | void sumo_dpm_fini(struct radeon_device *rdev) | |
1650 | { | |
1651 | int i; | |
1652 | ||
1653 | sumo_cleanup_asic(rdev); /* ??? */ | |
1654 | ||
1655 | for (i = 0; i < rdev->pm.dpm.num_ps; i++) { | |
1656 | kfree(rdev->pm.dpm.ps[i].ps_priv); | |
1657 | } | |
1658 | kfree(rdev->pm.dpm.ps); | |
1659 | kfree(rdev->pm.dpm.priv); | |
1660 | } | |
1661 | ||
1662 | u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low) | |
1663 | { | |
1664 | struct sumo_ps *requested_state = sumo_get_ps(rdev->pm.dpm.requested_ps); | |
1665 | ||
1666 | if (low) | |
1667 | return requested_state->levels[0].sclk; | |
1668 | else | |
1669 | return requested_state->levels[requested_state->num_levels - 1].sclk; | |
1670 | } | |
1671 | ||
1672 | u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low) | |
1673 | { | |
1674 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
1675 | ||
1676 | return pi->sys_info.bootup_uma_clk; | |
1677 | } |